Display panel and display device

Abstract

A display panel comprises a main display area and a functional device area, and the main display area at least partially surrounds the functional device area. The display panel comprises a plurality of first pixel circuits and a plurality of redundant pixel circuits, and the plurality of first pixel circuits are located in the main display area; the plurality of redundant pixel circuits are adjacent to a plurality of first pixel circuits which are arranged on the edge, close to the functional device area, of the main display area. The display panel comprises an active layer and an anode layer which are sequentially arranged in the direction perpendicular to the substrate and away from the substrate. The anode layer comprises a plurality of first anodes located in the main display area, and each first anode is electrically connected with one first pixel circuit; the redundant pixel circuit at least comprises a redundant active layer pattern located on the active layer, and the redundant pixel circuit is electrically insulated from the anode layer.

Description

[0001] This divisional application is filed based on the patent application with the filing date of April 29, 2021, application number 202180000993.0, and invention title "Display Panel, Manufacturing Method Thereof, and Display Device". Technical Field

[0002] The present disclosure relates to the field of display technologies, and particularly to a display panel and a display device. Background Art

[0003] An organic light-emitting diode (OLED) display panel includes a plurality of sub-pixels. Each sub-pixel includes a pixel circuit and a light-emitting device stacked on a substrate. The pixel circuit includes an active layer pattern. Due to the influence of the manufacturing process, during the manufacturing process of the pixel circuit, the uniformity of the pixel circuits in the edge region of the display panel near the under-screen camera is poor, resulting in the problem that the threshold voltage (Vth) of the pixel circuits in this region is prone to shift, and further resulting in abnormal light emission of the sub-pixels (such as dark spots, bright spots, or different colors).

[0004] Disclosure Content

[0005] On the one hand, a display panel is provided. It includes a main display area and a functional device area, and at least part of the main display area surrounds the functional device area. The display panel includes a plurality of first pixel circuits and a plurality of redundant pixel circuits. The plurality of first pixel circuits are located in the main display area; the plurality of redundant pixel circuits are adjacent to a plurality of first pixel circuits arranged at the edge of the main display area close to the functional device area. The display panel includes an active layer and an anode layer arranged in sequence along a direction perpendicular to the substrate and away from the substrate; the anode layer includes a plurality of first anodes located in the main display area, and each first anode is electrically connected to a first pixel circuit; the redundant pixel circuit at least includes a redundant active layer pattern located in the active layer, and the redundant pixel circuit is electrically insulated from the anode layer.

[0006] In some embodiments, any row of first pixel circuits is arranged in a first direction, and any column of first pixel circuits is arranged in a second direction, and the first direction intersects with the second direction. At least two redundant pixel circuits arranged in the first direction are provided at the edge of any row of first pixel circuits close to the functional device area that intersects with the boundary of the functional device area; at least two redundant pixel circuits arranged in the second direction are provided at the edge of any column of first pixel circuits close to the functional device area that intersects with the boundary of the functional device area.

[0007] In some embodiments, 2 to 4 redundant pixel circuits arranged in a first direction are provided at the edge of any row of first pixel circuits intersecting the functional device region, close to the functional device region; 2 to 4 redundant pixel circuits arranged in a second direction are provided at the edge of any column of first pixel circuits intersecting the functional device region, close to the functional device region.

[0008] In some embodiments, the edge of the main display region close to the functional device region, and / or

[0009] Alternatively, the edge of the functional device region close to the main display region is a transition region, and the plurality of redundant pixel circuits are located in the transition region. The transition region at least includes a first straight extension segment and two second straight extension segments; the first straight extension segment is located at one edge of the transition region in the second direction, and at least two rows of redundant pixel circuits are provided on the first straight extension segment; the two second straight extension segments are respectively located at the two edges of the transition region in the first direction, and at least two columns of redundant pixel circuits are provided on each second straight extension segment.

[0010] In some embodiments, the transition region further includes four broken-line extension segments; each segment is provided with multiple rows of redundant pixel circuits, and the multiple rows of redundant pixel circuits located in different segments are staggered in the first direction, and the first straight extension segment and the second straight extension segment are connected by the broken-line extension segments.

[0011] In some embodiments, the transition region is an annular shape with one side open, and the opening is located at the edge of the transition region opposite to the first straight segment. Alternatively, the transition region further includes a third straight extension segment, the third straight extension segment is located at the edge of the transition region opposite to the first straight segment, and the third straight extension segment includes at least two rows of redundant pixel circuits; the transition region is a closed annular shape.

[0012] In some embodiments, the pattern formed by arranging the plurality of redundant pixel circuits is symmetric with respect to a straight line in the first direction of the transition region; and / or, the pattern formed by arranging the plurality of redundant pixel circuits is symmetric with respect to a straight line in the second direction of the transition region.

[0013] In some embodiments, the first pixel circuit includes a plurality of first thin-film transistors and a first storage capacitor; the active layer further includes a first active layer pattern of the plurality of first thin-film transistors. The display panel further includes a first gate conductive layer, a second gate conductive layer, and a source-drain conductive layer. The first gate conductive layer is disposed between the active layer and the anode layer and includes a first gate pattern of the plurality of first pixel circuits. The first gate pattern includes gates of the plurality of first thin-film transistors, a first electrode plate of the first storage capacitor, a scan line, and a light-emitting signal line. The second gate conductive layer is disposed between the first gate conductive layer and the anode layer and includes a second gate pattern of the plurality of first pixel circuits. The second gate pattern includes a second electrode plate of the first storage capacitor, a first initialization power supply line, and a second initialization power supply line. The source-drain conductive layer is disposed between the second gate conductive layer and the anode layer and includes a source-drain conductive pattern of the plurality of first pixel circuits. The source-drain conductive pattern includes source and drain electrodes of the plurality of first thin-film transistors, a data line, and a voltage signal line.

[0014] In some embodiments, the orthographic projections of all patterns of the first gate conductive layer, all patterns of the second gate conductive layer, and all patterns of the source-drain conductive layer on the substrate are separated from the orthographic projection of the redundant active layer pattern on the substrate.

[0015] In some embodiments, the display panel further includes a first gate insulating layer, a second gate insulating layer, and an interlayer insulating layer. The first gate insulating layer is disposed between the active layer and the first gate conductive layer; the second gate insulating layer is disposed between the first gate conductive layer and the second gate conductive layer; the interlayer insulating layer is disposed between the second gate conductive layer and the source-drain conductive layer. The first gate insulating layer, the second gate insulating layer, and the interlayer insulating layer all cover the redundant active layer pattern; and a plurality of vias are provided in the first gate insulating layer, the second gate insulating layer, and the interlayer insulating layer. The vias pass through the interlayer insulating layer, the second gate insulating layer, and the first gate insulating layer, and the orthographic projection of the vias on the substrate is located within the orthographic projection range of the redundant active layer pattern on the substrate.

[0016] In some embodiments, the display panel further includes a passivation layer. The passivation layer is disposed between the source-drain conductive layer and the anode layer and covers the redundant active layer pattern. The materials of the passivation layer are filled in the plurality of vias.

[0017] In some embodiments, the redundant pixel circuit includes a plurality of redundant thin film transistors and redundant storage capacitors. The first gate conductive layer further includes a first redundant gate pattern of the plurality of redundant pixel circuits, and the first redundant gate pattern includes gates of the plurality of redundant thin film transistors and a first electrode plate of the redundant storage capacitor. The second gate conductive layer further includes a second redundant gate pattern of the plurality of redundant pixel circuits, and the second redundant gate pattern includes a second electrode plate of the redundant storage capacitor. The source-drain conductive layer further includes a redundant source-drain conductive pattern of the plurality of redundant pixel circuits, and the redundant source-drain conductive pattern includes sources and drains of the plurality of redundant thin film transistors, data lines, and voltage signal lines; the redundant source-drain conductive pattern is electrically insulated from the anode layer.

[0018] In some embodiments, in two redundant pixel circuits adjacent in a first direction, the redundant active layer patterns are separated from each other, the first redundant gate patterns are connected, and the second redundant gate patterns are connected; the first direction is the row direction in which the plurality of first pixel circuits are arranged. In two redundant pixel circuits adjacent in a second direction, the redundant active layer patterns are separated from each other, and the redundant source-drain conductive patterns are connected; the second direction is the column direction in which the plurality of first pixel circuits are arranged.

[0019] In some embodiments, the display panel further includes a plurality of second pixel circuits, and the plurality of second pixel circuits are disposed in a region of the display panel other than the functional device region. The anode layer further includes a plurality of second anodes, the plurality of second anodes are located in the functional device region, and each second anode is electrically connected to a second pixel circuit.

[0020] In some embodiments, the display panel further includes a transfer conductive layer, the transfer conductive layer is located between the film layer where the plurality of first pixel circuits and the plurality of second pixel circuits are located and the anode layer, and includes a plurality of separated transfer blocks; the plurality of transfer blocks include a first transfer block electrically connected to the first pixel circuit and a second transfer block electrically connected to the second pixel circuit. A positive projection of the first transfer block on the substrate covers a first connection node of the first pixel circuit electrically connected thereto and is electrically connected to the first connection node; the first connection node is a node in the first pixel circuit configured to be electrically connected to the first anode; a positive projection of the second transfer block on the substrate covers a second connection node of the second pixel circuit electrically connected thereto and is electrically connected to the second connection node; the second connection node is a node in the second pixel circuit configured to be electrically connected to the second anode.

[0021] In some embodiments, the plurality of first pixel circuits and the plurality of second pixel circuits are both located in the main display area. The plurality of second pixel circuits are arranged in multiple rows and multiple columns, and a plurality of first pixel circuits are provided between two adjacent second pixel circuits in the same row.

[0022] In some embodiments, the display panel further includes a border area surrounding the main display area. The plurality of second pixel circuits are located in the border area.

[0023] In some embodiments, the display panel further includes at least one connection layer; the at least one connection layer is located between the transfer conductive layer and the anode layer; the connection layer includes a plurality of connection lines, one end of each connection line is electrically connected to the second pixel circuit through a second transfer block, and the other end of the connection line is electrically connected to the second anode.

[0024] On the other hand, a display device is further provided, and the display device includes the display panel described in any of the above embodiments.

[0025] On yet another aspect, a method for manufacturing a display panel is further provided. The display panel includes a main display area and a functional device area, and the main display area at least partially surrounds the functional device area; the display panel includes a plurality of first pixel circuits and a plurality of redundant pixel circuits. The plurality of first pixel circuits are located in the main display area, and the plurality of redundant pixel circuits are adjacent to the first pixel circuits in the main display area close to the functional device area. The manufacturing method includes: fabricating an active layer on a substrate; fabricating an anode layer on a side of the active layer away from the substrate. Wherein, the active layer includes a first active layer pattern of the plurality of first pixel circuits and a redundant active layer pattern of the plurality of redundant pixel circuits; the anode layer includes a plurality of first anodes located in the main display area, and each first anode is electrically connected to a first pixel circuit; the plurality of redundant pixel circuits are electrically insulated from the anode layer.

[0026] In some embodiments, the first pixel circuit includes a plurality of first thin film transistors and a first storage capacitor. Between fabricating the active layer on the substrate and fabricating the anode layer on a side of the active layer away from the substrate, the method further includes: fabricating a first gate conductive layer on a side of the active layer away from the substrate; fabricating a second gate conductive layer on a side of the first gate conductive layer away from the substrate; fabricating a source-drain conductive layer on a side of the second gate conductive layer away from the substrate. The first gate conductive layer includes a first gate pattern of the plurality of first pixel circuits, and the first gate pattern includes gates of the plurality of first thin film transistors, a first electrode plate of the first storage capacitor, a scanning line, and a light emitting signal line; the second gate conductive layer includes a second gate pattern of the plurality of first pixel circuits, and the second gate pattern includes a second electrode plate of the first storage capacitor, a first initialization power supply line, and a second initialization power supply line; the source-drain conductive layer includes a source-drain conductive pattern of the plurality of first pixel circuits, and the source-drain conductive pattern includes sources and drains of the plurality of first thin film transistors, a data line, and a voltage signal line.

[0027] The orthographic projections of all the patterns of the first gate conductive layer, all the patterns of the second gate conductive layer, and all the patterns of the source-drain conductive layer on the substrate are all separated from the orthographic projection of the redundant active layer on the substrate. Alternatively, the redundant pixel circuit includes a plurality of redundant thin-film transistors and a redundant storage capacitor; the first gate conductive layer further includes a first redundant gate pattern of the plurality of redundant pixel circuits, the first redundant gate pattern includes the gates of the plurality of redundant thin-film transistors and the first electrode plate of the redundant storage capacitor; the second gate conductive layer further includes a second redundant gate pattern of the plurality of redundant pixel circuits, the second redundant gate pattern includes the second electrode plate of the redundant storage capacitor; the source-drain conductive layer further includes a redundant source-drain conductive pattern of the plurality of redundant pixel circuits, the redundant source-drain conductive pattern includes the sources and drains of the plurality of redundant thin-film transistors; and the redundant source-drain conductive pattern is electrically insulated from the anode layer. Description of the Drawings

[0028] In order to more clearly illustrate the technical solutions in the present disclosure, the drawings required for use in some embodiments of the present disclosure will be briefly introduced below. Obviously, the drawings in the following description are only the drawings of some embodiments of the present disclosure. For those of ordinary skill in the art, other drawings can also be obtained based on these drawings. In addition, the drawings in the following description can be regarded as schematic diagrams and do not limit the actual sizes of the products, the actual processes of the methods, the actual timings of the signals, etc. involved in the embodiments of the present disclosure.

[0029] Figure 1 It is a structural diagram of a display panel according to some embodiments;

[0030] Figure 2 It is a structural diagram of the pixel arrangement in the boundary region between the main display area and the functional device setting area in the display panel;

[0031] Figure 3A It is a structural diagram of a transition region according to some embodiments;

[0032] Figure 3B It is another structural diagram of a transition region according to some embodiments;

[0033] Figure 3C It is yet another structural diagram of a transition region according to some embodiments;

[0034] Figure 3D It is yet another structural diagram of a transition region according to some embodiments;

[0035] Figure 3E It is yet another structural diagram of a transition region according to some embodiments;

[0036] Figure 4A structural diagram of a redundant pixel circuit according to some embodiments;

[0037] Figure 5A is Figure 4 A cross-sectional view of A′-A′ and A″-A″ in

[0038] Figure 5B is Figure 4 Another cross-sectional view of A′-A′ and A″-A″ in

[0039] Figure 6 Another structural diagram of a redundant pixel circuit according to some embodiments;

[0040] Figure 7 is Figure 6 A cross-sectional view of B′-B′ and B″-B″ in

[0041] Figure 8 A structural diagram of a first pixel circuit according to some embodiments;

[0042] Figure 9 A structural diagram of a second pixel circuit disposed in a main display area according to some embodiments;

[0043] Figure 10 A structural diagram of a second pixel circuit disposed in a border area according to some embodiments. Detailed implementation manners

[0044] Next, in conjunction with the accompanying drawings, the technical solutions in some embodiments of the present disclosure will be clearly and completely described. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, rather than all of the embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by those of ordinary skill in the art belong to the scope of protection of the present disclosure.

[0045] Unless the context otherwise requires, throughout the specification and claims, the term "comprise" and its other forms such as the third-person singular form "comprises" and the present participle form "comprising" are interpreted as open, inclusive meanings, that is, "including, but not limited to". In the description of the specification, terms such as "some embodiments", "exemplary embodiments", "example" or "some examples" are intended to indicate that specific features, structures, materials or characteristics related to the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representations of the above terms do not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0046] Hereinafter, the terms "first" and "second" are for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the embodiments of the present disclosure, unless otherwise specified, the meaning of "a plurality" is two or more.

[0047] When describing some embodiments, expressions such as "connected" and "electrically connected" and their derivatives may be used. For example, when describing some embodiments, the term "connected" may be used to indicate that two or more components have direct physical contact or electrical contact with each other. The embodiments disclosed herein are not necessarily limited to the content herein.

[0048] "A and / or B" includes the following three combinations: only A, only B, and the combination of A and B.

[0049] The use of "configured to" herein means open and inclusive language, which does not exclude devices that are suitable for or configured to perform additional tasks or steps.

[0050] Exemplary embodiments are described herein with reference to cross-sectional views and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are contemplated. Therefore, the exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include deviations in shape due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device, and are not intended to limit the scope of the exemplary embodiments.

[0051] In this article, the expression "same-layer arrangement" is used, which means that a film layer with a specific pattern is formed by a single patterning process using the same mask. Depending on the specific pattern, a single patterning process may include multiple exposure, development or etching processes, and the specific pattern in the formed layer structure may be continuous or discontinuous, and these specific patterns may also be at different heights or have different thicknesses.

[0052] Some embodiments of the present disclosure provide a display device 1000, referring to Figure 1 The display device 1000 can be a television, a computer, a laptop computer, a mobile phone, a tablet computer, a personal digital assistant (PDA), a car computer, etc.

[0053] The display device 1000 adopts a technology of setting functional components on the back side of the screen (the side away from the light-emitting surface of the screen), and the functional components are, for example, a front camera component, an under-screen fingerprint component, a 3D face recognition component, an iris recognition component, a proximity sensor, and other components that can realize specific functions. For example, when a front camera component is set on the back side of the screen, the display device 1000 adopts the under-screen camera technology.

[0054] See also Figure 1 The display device 1000 includes a display panel 100. In some embodiments, the display panel 100 may be an organic light-emitting diode (OLED) display panel.

[0055] The display panel 100 includes a main display area 101, a functional device area 102, and a frame area 104 surrounding the main display 101. The functional device is arranged on the back side of the functional device area 102, and the functional device needs to receive light from the outside when working. In order to improve the sensitivity of the functional device, it is necessary to ensure that the functional device can receive a sufficient amount of light, and the light transmittance of the functional device area 102 needs to be improved.

[0056] Referring to Figure 2 , the display panel 100 includes a plurality of sub-pixels 110. The sub-pixel 110 includes a pixel circuit 20 disposed on a substrate 120, and an anode 32 disposed on a side of the film layer where the pixel circuit 20 is located away from the substrate 120. Among them, the anode 32 includes a first anode 321 located in the main display area 101 and a second anode 322 disposed in the functional device area 102.

[0057] Referring to Figure 2 , in order to improve the light transmittance of the functional device area 102, the pixel circuit 20 connected to the second anode 322 is disposed in an area of the display panel 100 other than the functional device area 102; that is, the functional device area 102 does not have a pixel circuit 20, and only the second anode 322 is retained. During the manufacturing process of the pixel circuit, the uniformity of the pixel circuit 20 in the edge area of the display panel near the under-screen camera is poor, resulting in a problem of Vth shift in the pixel circuit in this area, and further causing abnormal light emission of the sub-pixel 110 where the pixel circuit 20 is located (such as dark spots, bright spots, etc.); that is, the uniformity of the pixel circuit 20 included in the sub-pixel 110 near the edge of the main display area 101 close to the functional device area 102 is poor, resulting in a problem that the sub-pixel 110 near the edge of the main display area 101 close to the functional device area 102 may have abnormal light emission.

[0058] Some embodiments of the present disclosure provide a display panel 100. Referring to Figure 1 , it includes a main display area 101 and a functional device area 102, and the main display area 101 at least partially surrounds the functional device area 102. Exemplarily, referring to Figure 3A and Figure 3B , a part of the boundary of the functional device area 102 coincides with a part of the border area 104, and the main display area 101 partially surrounds the functional device area 102; referring to Figure 3C , the boundary of the functional device area 102 is separated from the border area 104, and the main display area 101 surrounds the functional device area 102.

[0059] Referring to Figure 3A , Figure 3B , Figure 3C and Figure 3D , the display panel 100 includes a plurality of first pixel circuits 210 and a plurality of redundant pixel circuits 220. The plurality of first pixel circuits 210 are located in the main display area 101; the plurality of redundant pixel circuits 220 are adjacent to the plurality of first pixel circuits 210 disposed at the edge of the main display area 101 close to the functional device area 102. That is, on a side of the first pixel circuit 210 located at the edge of the main display area 101 close to the functional device area 102 and close to the functional device area 102, a redundant pixel circuit 220 adjacent to the first pixel circuit 210 is provided.

[0060] Referring to Figure 4 and Figure 5A , the display panel 100 includes an active layer 310 and an anode layer 320 that are sequentially disposed along a direction perpendicular to and away from the substrate 120. The anode layer 320 includes a plurality of first anodes 321 located in the main display area 101, and each first anode 321 is electrically connected to a first pixel circuit 210. The first pixel circuit 210 is electrically connected to the first anode 321 and is configured to transmit a driving current to the first anode 321 to control the light-emitting device 30 where the first anode 321 is located to emit light.

[0061] The redundant pixel circuit 220 includes at least a redundant active layer pattern 311 located in the active layer 310, and the redundant pixel circuit 220 is electrically insulated from the anode layer 320. Due to the influence of the manufacturing process, during the manufacturing process of the pixel circuit, the uniformity of the pixel circuits in the edge area of the display panel close to the under-screen camera is poor, and the problem of poor uniformity mainly appears in the active layer 310. Therefore, the redundant pixel circuit 220 includes at least a redundant active layer pattern 311 located in the active layer 310.

[0062] The display panel 100 provided by the embodiments of the present disclosure, referring to Figures 3A to 3E , on one side of the first pixel circuit 210 close to the functional device area 102 at the edge of the main display area 101 close to the functional device area 102, a redundant pixel circuit 220 adjacent to the first pixel circuit 210 is provided; and, referring to Figure 4 and Figure 6 , the redundant pixel circuit 220 includes a redundant active layer pattern 311 located in the active layer 310. The edge of the active layer 310 close to the functional device area 102 is transferred from the first active layer pattern 312 of the first pixel circuit 210 to the redundant active layer pattern 311 of the redundant pixel circuit 220; thereby avoiding the problem of poor uniformity of the first pixel circuit 210 and enabling the sub-pixels 20 at the edge of the main display area 101 close to the functional device area 102 to emit light normally. Moreover, the redundant pixel circuit 220 is electrically insulated from the anode layer 320, that is, the redundant pixel circuit 220 does not control any sub-pixel 20 to emit light. Even if the redundant active layer pattern 311 of the redundant pixel circuit 220 has a problem of poor uniformity, it will not affect the light emission of any sub-pixel 20.

[0063] In some embodiments, referring to Figure 3A , a plurality of first pixel circuits 210 are arranged in multiple rows and multiple columns. Any row of first pixel circuits 210 is arranged along a first direction M1 ( Figure 3A the horizontal direction in Figure 3A ), and any column of first pixel circuits 210 is arranged along a second direction M2 ( the vertical direction in ). The first direction M1 intersects the second direction M2.

[0064] At the edge of any row of the first pixel circuits 210 intersecting the boundary of the functional device area 102, which is close to the functional device area 102, at least two redundant pixel circuits 220 arranged along the first direction are provided. At the edge of any column of the first pixel circuits 210 intersecting the boundary of the functional device area 102, which is close to the functional device area 102, redundant pixel circuits arranged along the second direction are provided. That is, for each first pixel circuit 210 at the edge of the main display area 101 close to the functional device area 102, at least two redundant pixel circuits 220 adjacent to the first pixel circuit 210 are provided on the side close to the functional device area 102 along the first direction M1 or the second direction M2; so as to ensure that the areas with poor uniformity that may appear on the active layer 310 completely fall on the redundant active layer patterns 311 of the redundant pixel circuits 220, which is beneficial to improving the yield of the display panel 100.

[0065] For the first pixel circuits 210 in the edge area of the main display area 101 close to the functional device area 102, the more the number of redundant pixel circuits 220 provided on the side close to the functional device area 102, the larger the area occupied by the redundant pixel circuits 220, and more redundant pixel circuits 220 will be located at the edge of the functional device area 102, resulting in a decrease in the light transmittance at the edge of the functional device area 102 and affecting the operation of the functional device. Or, the opening of the functional device area 102 needs to be made larger to avoid the redundant pixel circuits 220 affecting the light collection of the functional device, which is not conducive to the arrangement of the pixel circuits 20 included in the sub-pixels 120 located in the functional device area 102.

[0066] Therefore, at the edge of any row of the first pixel circuits 210 intersecting the functional device area 102, which is close to the functional device area 102, 2 to 4 redundant pixel circuits 220 arranged along the first direction are provided; similarly, at the edge of any column of the first pixel circuits 210 intersecting the functional device area 102, which is close to the functional device area 102, 2 to 4 redundant pixel circuits arranged along the second direction are provided. It is possible to minimize the influence of the redundant pixel circuits on the light transmittance of the functional device area 102 on the premise of ensuring that there are no problems with poor uniformity in the first pixel circuits 210 at the edge of the main display area 01 close to the functional device area 102.

[0067] Exemplarily, refer to Figure 3A, the functional device area 102 is located in the middle of the display panel 100 along the first direction. Any row of the first pixel circuits 210 that intersects with the boundary of the functional device area 102 is divided into two parts by the functional device area 102. Among them, at least two redundant pixel circuits 220 adjacent to the first pixel circuit 210 are provided on the right side of the rightmost first pixel circuit 210 in the Nth row of the first pixel circuits 210 on the left side of the functional device area 102. For example, two, three, or four redundant pixel circuits 220 can be provided.

[0068] At least two redundant pixel circuits 220 adjacent to the first pixel circuit 210 are provided on the left side of the leftmost first pixel circuit 210 in the Mth row of the first pixel circuits 210 on the right side of the functional device area 102; at least two redundant pixel circuits 220 adjacent to the first pixel circuit 210 are provided on the upper side of the uppermost first pixel circuit 210 in the Oth column of the first pixel circuits 210 on the lower side of the functional device area 102; at least two redundant pixel circuits 220 adjacent to the first pixel circuit 210 are provided on the lower side of the lowermost first pixel circuit 210 in the Pth column of the first pixel circuits 210 on the upper side of the functional device area 102. Among them, the first pixel circuits 210 in the Nth row and the Mth row intersect with the boundary of the functional device area 102, and the first pixel circuits 210 in the Oth column and the Pth column intersect with the boundary of the functional device area 102.

[0069] Exemplarily, refer to Figure 3A , four redundant pixel circuits 220 arranged along the first direction M1 are provided on the edge of any row of the first pixel circuits 210 that intersects with the functional device area 102 and is close to the functional device area 102; two redundant pixel circuits 220 arranged along the second direction M2 are provided on the edge of any column of the first pixel circuits 210 that intersects with the functional device area 102 and is close to the functional device area 102.

[0070] Exemplarily, refer to Figure 3C , two redundant pixel circuits 220 arranged along the first direction M1 are provided on the edge of any row of the first pixel circuits 210 that intersects with the functional device area 102 and is close to the functional device area 102; two redundant pixel circuits 220 arranged along the second direction M2 are provided on the edge of any column of the first pixel circuits 210 that intersects with the functional device area 102 and is close to the functional device area 102.

[0071] In some embodiments, the region where the redundant pixel circuit 220 is located is defined as the transition region 103. The transition region 103 includes the edge of the main display region 101 close to the functional device region 102, and / or, the edge of the functional device region 102 close to the main display region 101 is the transition region 103; that is, the transition region 103 may include part of the main display region 101 and / or part of the functional device region 102. Exemplarily, the transition region 103 may be entirely located in the functional device region 102; or, a part of the transition region 102 is located in the functional device region 102 and a part is located in the main display region 101; or, the transition region 102 is entirely located in the main display region 101. It should be understood that the region where the first anode 321 is located is the main display region; the region where the second anode 321 is located is the functional device region 102; the region where the redundant pixel circuit 220 is located is the transition region 103.

[0072] According to the differences in the shapes of the functional devices, the shape of the boundary of the functional device region 102 may be different, and thus, the shape of the transition region 103 may also be different. Exemplarily, the boundary of the functional device region 102 may be rectangular or approximately rectangular, circular or approximately circular, etc., which are not specifically limited herein.

[0073] Multiple first pixel circuits 210 are arranged in multiple rows and multiple columns, and the boundary of the functional device region 102 is formed by alternately connecting the boundaries of multiple first pixel circuits 210 arranged along the first direction M1 (the row direction in which the multiple first pixel circuits 210 are arranged), and the boundaries of multiple first pixel circuits 210 arranged along the second direction M2 (the row direction in which the multiple first pixel circuits 210 are arranged). Refer to Figure 3B , when a part of the boundary of the functional device region 102 coincides with a part of the border region 104, the boundary of the functional device region 102 includes at least one straight line segment extending along the first direction M1, and two straight line segments extending along the second direction M2.

[0074] Corresponding to the boundary of the functional device region 102, the transition region 103 includes at least a first straight line extension segment 1031 and two second straight line extension segments 1032; the first straight line extension segment 1031 is located at one edge of the transition region 103 in the second direction M2, and the two second straight line extension segments 1032 are respectively located at the two edges of the transition region 103 in the first direction M1.

[0075] Exemplarily, refer to Figure 3B , the boundary of the functional device region 102 is rectangular, and one boundary of the functional device region 102 in the second direction M2 ( Figure 3B the upper boundary of the functional device region 102 inFigure 3B the lower boundary of the middle transition region 103), and the two second straight line extension segments 1032 respectively form two boundaries of the transition region 103 in the first direction ( Figure 3B the left and right boundaries of the middle transition region 103).

[0076] At least two rows of redundant pixel circuits 220 are provided on the first straight line extension segment 1031 (at the edge of any column of first pixel circuits 210 intersecting the boundary of the functional device region 102 and close to the functional device region 102, at least two redundant pixel circuits 220 arranged along the second direction M2 are provided); that is, in at least one row of first pixel circuits 210 that coincides with a part of the boundary of the functional device region 102, in the part that coincides with the boundary of the functional device region 102, at least two rows of redundant pixel circuits 220 are provided on the side close to the functional device region 102.

[0077] At least two columns of redundant pixel circuits 220 are provided on each second straight line extension segment 1302 (at the edge of any row of first pixel circuits 210 intersecting the boundary of the functional device region 102 and close to the functional device region 102, at least two redundant pixel circuits 220 arranged along the first direction M1 are provided); that is, in at least one column of first pixel circuits 210 that coincides with a part of the boundary of the functional device region 102, in the part that coincides with the part of the boundary of the functional device region 102, at least two columns of redundant pixel circuits 220 are provided on the side close to the functional device region 102.

[0078] In some embodiments, referring to Figure 3A and Figure 3C , the transition region 103 further includes four polyline extension segments 1033; each polyline extension segment 1033 includes a plurality of sequentially connected line segments 10331, and each line segment 10331 is provided with multiple rows of redundant pixel circuits 220, and the multiple rows of redundant pixel circuits 220 located in different line segments 10331 are staggered in the first direction M1; the first straight line extension segment 1031 and the second straight line extension segment 1032 are connected by the polyline extension segment 1033.

[0079] Exemplarily, the boundary shape of the functional device region 102 is approximately circular, and at the corners of the boundary of the functional device region 102, there are polyline segments formed by alternately connecting a plurality of straight line segments extending along the first direction M1 and a plurality of straight line segments extending along the second direction M2. Corresponding to the polyline segments of the boundary of the functional device region 102, the transition region 103 includes polyline extension segments 1033, and the polyline extension segments 1033 of the transition region 103 are provided at positions corresponding to the polyline segments of the boundary of the functional device region 102.

[0080] The position of the functional device area 102 on the display panel 100 is not unique. According to the different positions of the functional device area 102 on the display panel 100, the shape of the transition area 103 may also be different. For example, the functional device area 102 can be set in the middle upper position of the display panel 100 (as Figure 3A shown), or set on the upper left or right side of the display panel 100, or can also be set in the middle position of the lower part of the display panel 100; the functional device area 102 can be completely surrounded by the main display area 101 (as Figure 3C shown), and part of the boundary of the functional device area 102 can also coincide with part of the boundary of the border area 104, that is, the main display area 101 partially surrounds the functional device area 102 (as Figure 3A shown).

[0081] Refer to Figure 3A , when the upper boundary of the functional device area 102 coincides with part of the boundary of the border area 104, the transition area 103 is an annular shape with an opening 1035 on one side (the upper side), and the opening 1035 is located at the edge of the transition area 103 opposite to the first straight line segment 1031.

[0082] The transition area 103 can only include the first straight line extension segment 1031 and two second straight line extension segments 1032 (as Figure 3B shown); or, the transition area 103 further includes two broken line extension segments 1033 or four broken line extension segments 1033 (as Figure 3A shown). The transition area 103 can also include other extension segments, which will not be listed one by one here.

[0083] Refer to Figure 3C , when all the boundaries of the functional device area 102 are located within the main display area 101, the transition area 103 further includes a third straight line extension segment 1034. The third straight line extension segment 1034 is located at the edge of the transition area 103 opposite to the first straight line segment 1031, and the third straight line extension segment 1034 includes at least two rows of redundant pixel circuits 220; the transition area 103 is a closed ring shape. The first straight line extension segment 1301 and the third straight line extension segment 1034 respectively constitute two boundaries of the transition area 103 in the first direction M1 ( Figure 3C in, the upper and lower boundaries of the transition area 103).

[0084] Exemplarily, the transition area 103 can include the first straight line extension segment 1031, two second straight line extension segments 1032 and the third straight line extension segment 1034; or, the transition area 103 can also include two broken line extension segments 1303 or four broken line extension segments 1033. The transition area 103 can also include other extension segments, which will not be listed one by one here.

[0085] In some embodiments, refer to Figure 3DAlternatively, at least two redundant pixel circuits 220 arranged along the first direction M1 may be provided only at the edge of any row of first pixel circuits 210 that intersects the boundary of the functional device area 102 and is close to the functional device area 102. Alternatively, see Figure 3E At least two redundant pixel circuits 220 arranged along the second direction M2 are provided only on the edge of any column of first pixel circuits 210 close to the functional device area 102 that intersects with the boundary of the functional device area 102 .

[0086] In some embodiments, see Figure 3C The pattern formed by arranging the plurality of redundant pixel circuits 220 is symmetrical with respect to a straight line L2 along the first direction M1 of the transition region 103. And / or, refer to Figure 3A , Figure 3B and Figure 3C , see Figure 3C The pattern formed by arranging the plurality of redundant pixel circuits 220 is symmetrical with respect to a straight line L1 along the second direction M2 of the transition region 103. The plurality of redundant pixel circuits 220 are symmetrical with respect to a straight line L2 along the first direction M1 of the transition region 103, and / or are symmetrical with respect to a straight line L1 along the second direction M2 of the transition region 103, which is beneficial to improving the uniformity of the redundant active layer pattern 311 of the redundant pixel circuits 220 and improving the uniformity of the entire active layer 310.

[0087] In some embodiments, see Figure 4 and Figure 5A The first pixel circuit 210 includes a plurality of first thin film transistors (TFT) 211 and a first storage capacitor 212; Figure 5A The section A′-A′ is a cross-sectional view of a first thin film transistor 211 and a first storage capacitor 212 in the first pixel circuit 210. The first thin film transistor 211 may be a P-type transistor or an N-type transistor, which is not specifically limited herein.

[0088] The active layer 310 includes a plurality of first active layer patterns 312 of the first thin film transistors 211 , and each of the first pixel circuits 210 includes a first active layer pattern 312 located in the active layer 310 .

[0089] See also Figure 4 , Figure 5A and Figure 8 The display panel 100 further includes a first gate conductive layer 330 , a second gate conductive layer 340 , and a source-drain conductive layer 350 .

[0090] The first gate conductive layer 330 is disposed between the active layer 310 and the anode layer 320, and includes first gate patterns 331 of a plurality of first pixel circuits 210. The first gate patterns 331 include gates G1 of a plurality of first thin film transistors 211, first plates C11 of first storage capacitors 212, scan lines GL, and light emitting signal lines EM.

[0091] The second gate conductive layer 340 is disposed between the first gate conductive layer 330 and the anode layer 320, and includes second gate patterns 341 of a plurality of first pixel circuits 210. The second gate patterns 341 include second plates C12 of first storage capacitors 212, first initialization power supply lines Vint1, and second initialization power supply lines Vint2.

[0092] The source-drain conductive layer 350 is disposed between the second gate conductive layer 340 and the anode layer 320, and includes source-drain conductive patterns 351 of a plurality of first pixel circuits 210. The source-drain conductive patterns 351 include sources S1 and drains D1 of a plurality of first thin film transistors 30, data lines DATA, and voltage signal lines VDD. The first active layer pattern 312, the first gate pattern 331, the second gate pattern 341, and the source-drain conductive pattern 351 together constitute the first pixel circuit 210.

[0093] The display panel 100 further includes a first gate insulating layer 360 disposed between the active layer 310 and the first gate conductive layer 330; a second gate insulating layer 370 disposed between the first gate conductive layer 330 and the second gate conductive layer 340; an interlayer insulating layer 380 disposed between the second gate conductive layer 340 and the source-drain conductive layer 350; and a passivation layer 390 and a planarization layer 420 disposed between the source-drain conductive layer 350 and the anode layer 320. Among them, the first gate insulating layer 360, the second gate insulating layer 370, the interlayer insulating layer 380, the passivation layer 390, and the planarization layer 420 are all integral layer structures and all cover the redundant active layer pattern 311. At least one insulating layer is disposed between two adjacent conductive layers to prevent the patterns on the two adjacent conductive layers from overlapping.

[0094] The redundant pixel circuit 220 may only include the redundant active layer pattern 311; or, the redundant pixel circuit 220 may include the redundant active layer pattern 311, the redundant first gate pattern 332, the redundant second gate pattern 342, and the redundant source-drain conductive layer pattern 352 that are sequentially stacked on the substrate 120.

[0095] Refer to Figure 6 、 Figure 7 and Figure 8, when the redundant pixel circuit 220 only includes the redundant active layer pattern 311, the orthographic projections of all patterns of the first gate conductive layer 330, all patterns of the second gate conductive layer 340, and all patterns of the source-drain conductive layer 350 on the substrate 120 are all separated from the orthographic projection of the redundant active layer pattern 311 on the substrate 120; that is, there are no conductive patterns of the first gate conductive layer 330, the second gate conductive layer 340, and the source-drain conductive layer 350 above the redundant active layer pattern 311. In this way, the structure of the redundant pixel circuit 210 is simple, and the patterns of the first gate conductive layer 330, the second gate conductive layer 340, and the source-drain conductive layer 350 are simple, which is beneficial to improving the manufacturing efficiency of the display panel 100.

[0096] Refer to Figure 7 , a plurality of vias 361 are provided in the first gate insulating layer 360, the second gate insulating layer 370, and the interlayer insulating layer 380. The plurality of vias 361 penetrate through the first gate insulating layer 360, the second gate insulating layer 370, and the interlayer insulating layer 380, and the orthographic projection of the via 361 on the substrate 120 is located within the orthographic projection range of the redundant active layer pattern 311 on the substrate 120; so that the structure of the redundant active layer pattern 311 of the redundant pixel circuit 210 is consistent with the structure of the first active layer pattern 312 of the first pixel circuit 210, which is beneficial to improving the uniformity of the edge of the active layer 310 close to the functional device area 102 and reducing the possibility of poor uniformity of the first active layer pattern 312.

[0097] Since the redundant pixel circuit 220 only includes the redundant active layer pattern 311, and a passivation layer 390 is provided on the side of the interlayer insulating layer 380 away from the redundant active layer pattern 311, according to the manufacturing process of the display panel 100, therefore, after forming the via 361, it is necessary to fabricate the source-drain conductive layer 350 and the passivation layer 390; the inside of the via of the first pixel circuit 210 is filled with the source-drain conductive layer 350; the inside of the via 361 of the redundant pixel circuit 220 is filled with the material of the passivation layer 390.

[0098] Refer to Figure 4 、 Figure 5A and Figure 8 , when the redundant pixel circuit 220 includes a plurality of redundant thin film transistors 221 and redundant storage capacitors 222, that is, the redundant pixel circuit 220 includes a redundant active layer pattern 311, a redundant first gate pattern 332, a redundant second gate pattern 342, and a redundant source-drain conductive layer pattern 352 that are sequentially stacked on the substrate 120. Among them, Figure 8FIG. 0 is a structural diagram of the first pixel circuit 210. When the redundant pixel circuit 220 includes a plurality of redundant thin film transistors 221 and redundant storage capacitors 222, the structure of the redundant pixel circuit 220 is the same as that of the first pixel circuit 210. Therefore, the conductive layer patterns of each layer of the redundant pixel circuit 220 can refer to the corresponding conductive layer patterns of the first pixel circuit 210.

[0099] The first gate conductive layer 330 further includes first redundant gate patterns 332 of a plurality of redundant pixel circuits 220. The first redundant gate patterns 332 include gates G2 of a plurality of redundant thin film transistors 221 and first plates C21 of redundant storage capacitors 222; and the first redundant gate patterns 332 are disposed on the same layer as the first gate pattern 331.

[0100] The second gate conductive layer 340 further includes second redundant gate patterns 342 of a plurality of redundant pixel circuits 220. The second redundant gate patterns 342 include second plates C22 of redundant storage capacitors 222; and the second redundant gate patterns 342 are disposed on the same layer as the second gate pattern 341.

[0101] The source-drain conductive layer 350 further includes redundant source-drain conductive patterns 352 of a plurality of redundant pixel circuits 220. The redundant source-drain conductive patterns 352 include sources S2 and drains D2 of a plurality of redundant thin film transistors 221; the redundant source-drain conductive patterns 352 are electrically insulated from the anode layer 320, and the redundant source-drain conductive patterns 352 are disposed on the same layer as the source-drain conductive pattern 351.

[0102] The redundant pixel circuit 220 includes a plurality of redundant thin film transistors 221 and redundant storage capacitors 222. The redundant pixel circuit 220 has the same structure as the first pixel circuit 210 (however, the redundant pixel circuit 220 is not electrically connected to the anode layer 320, and the first pixel circuit 210 is electrically connected to the first anode 321 of the anode layer 320); it is possible to improve the uniformity of the first gate pattern 331, the second gate pattern 341, and the source-drain conductive pattern 351 of a plurality of first pixel circuits 210 at the edge of the main display area 101 close to the functional device area 102, make the uniformity of a plurality of first pixel circuits 210 at the edge of the main display area 101 close to the functional device area 102 better, and further reduce the probability of Vth shift occurring in the first pixel circuits 210 at the edge of the main display area 101 close to the functional device area 102, so that the light-emitting devices 30 at the edge of the main display area 101 close to the functional device area 102 emit light normally.

[0103] In some embodiments, among two adjacent redundant pixel circuits 220 along the first direction M1, the redundant active layer patterns 311 are separated from each other (see Figure 6), the first redundant gate pattern 332 is connected (the scanning line GL and the light-emitting signal line EM are connected), and the second redundant gate pattern 342 is connected (the first initialization power supply line Vint1 and the second initialization power supply line Vint2 are connected). Among two redundant pixel circuits 220 adjacent along the second direction M2, the redundant active layer patterns 311 are separated from each other (refer to Figure 6 ), and the redundant source-drain conductive pattern 352 is connected (the data line DATA and the voltage signal line VDD are connected). That is, when the redundant pixel circuit 220 includes a plurality of redundant thin-film transistors 221 and a redundant storage capacitor 222, the redundant active layer patterns 351 of two redundant pixel circuits 220 adjacent along the first direction are separated from each other, and the first redundant gate pattern 332 and the second redundant gate pattern 342 are connected; the redundant active layer patterns 311 of two redundant pixel circuits 220 adjacent along the second direction M2 are separated from each other, and the redundant source-drain conductive pattern is connected.

[0104] It should be understood that when the redundant pixel circuit 220 only includes the redundant active layer pattern 311 disposed on the active layer 310, the redundant active layer patterns 311 of two redundant pixel circuits 220 adjacent along the first direction M1 are separated from each other; the redundant active layer patterns 311 of two redundant pixel circuits 220 adjacent along the second direction M2 are separated from each other.

[0105] In some embodiments, refer to Figure 9 or Figure 10 , the anode layer 320 further includes a plurality of second anodes 322, and the plurality of second anodes 322 are located in the functional device area 102. The display panel 100 further includes a plurality of second pixel circuits 230, and each second anode 322 is electrically connected to a second pixel circuit 230; the plurality of second pixel circuits 230 are disposed in the area of the display panel 100 other than the functional device area 102. The structure of the second pixel circuit 203 may be the same as the structure of the first pixel circuit 210; disposing the second pixel circuit 230 in the area of the display panel 100 other than the functional device area 102 is beneficial to improving the light transmittance of the functional device area 102, so that when the functional device works, the functional device can collect sufficient light.

[0106] In some embodiments, refer to Figure 5A , Figure 9 and Figure 10; The display panel 100 further includes a transfer conductive layer 410. The first pixel circuit 210 and the second pixel circuit 230 are electrically connected to the first anode 321 or the second anode 322 through the transfer conductive layer 410. The transfer conductive layer 410 is located between the film layer where the plurality of first pixel circuits 210 and the plurality of second pixel circuits 230 are located and the anode layer 320, and is also located between the passivation layer 390 and the anode layer 320. The transfer conductive layer 410 can reduce the depth of a single via when the source-drain conductive layer 350 is connected to the anode layer 320, improve the connection stability between the pixel circuit 20 and the light-emitting device 30 indirectly, and at the same time reduce the process difficulty in the process of fabricating the via.

[0107] The transfer conductive layer 410 includes a plurality of mutually separated transfer blocks 411. The plurality of transfer blocks 411 include a first transfer block 4111 electrically connected to the first pixel circuit 210 and a second transfer block 4112 electrically connected to the second pixel circuit 230.

[0108] The orthographic projection of the first transfer block 4111 on the substrate 120 covers the first connection node N1 of the first pixel circuit 210 electrically connected thereto, thereby shielding the connection layer 430 on the side of the first transfer block 4111 away from the substrate 120 and reducing or eliminating the influence of the connection layer 430 on the first connection node N1.

[0109] The first transfer block 4111 is electrically connected to the first connection node N1, and the first anode 321 is electrically connected to the first transfer block 4111; so that the first anode 321 is electrically connected to the first pixel circuit 210 through the first transfer block 4111. Among them, the first connection node N1 is the node in the first pixel circuit 210 configured to be connected to the first anode 321.

[0110] The orthographic projection of the second transfer block 4112 on the substrate 120 covers the second connection node N2 of the second pixel circuit 230 electrically connected thereto, thereby shielding the connection layer 430 on the side of the second transfer block 4112 away from the substrate 120 and reducing or eliminating the influence of the connection layer 430 on the second connection node N2. The second transfer block 4112 is electrically connected to the second connection node N2, and the second anode 322 is electrically connected to the second transfer block 4112; so that the second anode 322 is electrically connected to the second pixel circuit 230 through the second transfer block 4112. Among them, the second connection node N2 is the node in the second pixel circuit 230 configured to be electrically connected to the second anode 322.

[0111] In some embodiments, the display panel 100 further includes a border area 104 surrounding the main display area 101. The second pixel circuit 230 can be disposed in the main display area 101 (as Figure 9 shown) or disposed in the border area 104 (as Figure 10 shown).

[0112] Referring to Figure 9 , when the second pixel circuit 230 is disposed in the main display area 101, a plurality of first pixel circuits 210 and a plurality of second pixel circuits 230 are both located in the main display area 101. The plurality of second pixel circuits 230 are arranged in multiple rows and multiple columns, and a plurality of first pixel circuits 210 are provided between two adjacent second pixel circuits 230 in the same row. That is, multiple columns of second pixel circuits 230 are inserted into the gaps between multiple columns of first pixel circuits 210 at intervals. The second pixel circuit 230 is disposed in the main display area 101, which is beneficial to reducing the width of the border area 104 and improving the screen-to-body ratio of the display panel 100.

[0113] Referring to Figure 10 , disposing the second pixel circuit 230 in the border area 104 is beneficial to improving the pixel density of the main display area 101 of the display panel 100. Exemplarily, in some display panels 100 with a high pixel density (Pixels Per Inch; abbreviated as PPI), the pixel density is large. Correspondingly, the density of the first pixel circuits 210 is large, and the available gap between the first pixel circuits 210 is very small, and it is not easy for the second pixel circuit 230 to be inserted into the interval between the first pixel circuits 210. Therefore, disposing the second pixel circuit 230 in the border area 104 is beneficial to improving the pixel density of the main display area 101 of the display panel 100 and is beneficial to manufacturing a display panel 100 with a high PPI.

[0114] The second anode 322 is located in the functional device area 102, while the second pixel circuit 230 is disposed in the area of the display panel 100 other than the functional device area 102; that is, the orthographic projection of the second pixel circuit 230 on the substrate 120 does not overlap with the orthographic projection of the second anode 322 on the substrate, and the second anode 322 and the second pixel circuit 230 cannot be directly electrically connected through a via.

[0115] Therefore, referring to Figure 9 and Figure 10 , the display panel 100 further includes at least one connection layer 430, and at least one connection layer 430 is located between the transfer conductive layer 410 and the anode layer 320; the connection layer 430 includes a plurality of connection lines 431, one end of the connection line 431 is electrically connected to the second pixel circuit 230 through the second transfer block 4112, and the other end of the connection line 431 is electrically connected to the second anode 322.

[0116] To improve the light transmittance of the functional device area 102, the connection lines 431 of the connection layer 430 can be made of a transparent conductive material, such as Indium Tin Oxides (abbreviated as ITO).

[0117] Since the number of the second anodes 322 in the functional device region 102 is plural, a plurality of connection lines 431 are required to connect the plurality of second anodes 322 and the plurality of second pixel circuits 230. The plurality of connection lines 431 may be disposed in the same connection layer 430 or may be disposed in different connection layers 430 to provide sufficient routing space for the plurality of connection lines 431; wherein, when the number of the connection layers 430 is greater than two, at least one insulating layer 440 is disposed between any two adjacent connection layers 430.

[0118] Exemplarily, referring to Figure 5B and Figure 7 , the number of the connection layers 430 is three; along a direction perpendicular to the substrate 120 and pointing from the substrate 120 to the anode layer 320, the three connection layers 430 are a first connection layer 4301, a second connection layer 4302, and a third connection layer 4303 in sequence. An insulating layer 441 is disposed between the first connection layer 4301 and the second connection layer 4302, and an insulating layer 442 is disposed between the second connection layer 4302 and the third connection layer 4303; and an insulating layer 443 is disposed between the transfer conductive layer 410 and the first connection layer 4301, and an insulating layer 444 is disposed between the third connection layer 4303 and the anode layer 320.

[0119] Referring to Figure 5A and Figure 5B , when the display panel 100 includes multiple connection layers 430, for the second pixel circuit 230 and the second anode 322 that need to be electrically connected through the connection line 431, in addition to setting the connection line 431 in one of the connection layers 430, a third transfer block 432 also needs to be disposed on other connection layers 430 except the connection layer 430 where the connection line 431 is located. The second anode 322 is electrically connected to the connection line 431 through the third transfer block 422, and / or the connection line 431 is electrically connected to the second transfer block 412 through the third transfer block 422.

[0120] In some embodiments, since the number of the second anodes 322 is large, the second anodes 322 at different positions may be electrically connected to the second pixel circuit 230 through the connection lines 431 of different connection layers 430. Exemplarily, the second anodes of different sub-pixels 120 of the same pixel unit (at least including a red sub-pixel, a green sub-pixel, and a blue sub-pixel) are electrically connected to the second pixel circuit 230 through the connection lines 431 of different layers; or, two adjacent second anodes 322 are electrically connected to the second pixel circuit 230 through the connection lines 431 of different layers, and so on, which will not be listed one by one here.

[0121] Exemplarily, referring to 5A, the second anode 322 is electrically connected to the second pixel circuit 230 through the connection line 431 in the third connection layer 4303; referring to Figure 5B, the second anode 322 is electrically connected to the second pixel circuit 230 through a connection line 431 in the first connection layer 4301. Among them, in Figure 5B it can be considered that Figure 4 the second anode 322 intercepted by A''-A'' in is the second anode 322 located in the central region of the functional device area 102. In this way, there is no redundant pixel circuit on the side of the second anode 322 close to the substrate 110.

[0122] In some quantities, referring to FIG. 5 and Figure 7 , the display panel 100 further includes a pixel defining layer 450 disposed on the side of the anode layer 320 away from the substrate 120. The pixel defining layer 450 includes a plurality of opening regions 451, and one first anode 321 or one second anode 321 corresponds to one opening region 451.

[0123] A light-emitting functional layer 460 is disposed in the opening region 451. Exemplarily, the light-emitting functional layer 460 includes one or more of an electron transporting layer (abbreviated as ETL), an electron injection layer (abbreviated as EIL), a hole transporting layer (abbreviated as HTL), and a hole injection layer (abbreviated as HIL).

[0124] The display panel 100 further includes a cathode conductive layer 470 disposed on the side of the pixel defining layer 450 and the light-emitting functional layer away from the substrate 120, and a packaging layer 480 disposed on the side of the cathode conductive layer 470 away from the substrate 120.

[0125] Some embodiments of the present disclosure further provide a manufacturing method of a display panel 100. The display panel 100 includes a main display area 101 and a functional device area 102. The main display area 101 at least partially surrounds the functional device area 102; the display panel 100 includes a plurality of first pixel circuits 210 and a plurality of redundant pixel circuits 220. The plurality of first pixel circuits 210 are located in the main display area 101, and the plurality of redundant pixel circuits 220 are adjacent to the first pixel circuits 210 in the main display area 101 close to the functional device area 102.

[0126] The above manufacturing method includes:

[0127] S10, fabricating an active layer 310 on the substrate 120.

[0128] The active layer 310 includes a first active layer pattern 312 of a plurality of first pixel circuits 210 and a redundant active layer pattern 311 of a plurality of redundant pixel circuits 220.

[0129] S20, fabricate an anode layer 320 on the side of the active layer 310 away from the substrate 120.

[0130] The anode layer 320 includes a plurality of first anodes 321 located in the main display area 101, each first anode 321 being electrically connected to a first pixel circuit 210; a plurality of redundant pixel circuits 220 are electrically insulated from the anode layer 320.

[0131] For the display panel 100 obtained by the above fabrication method, on the side of the first pixel circuit 210 close to the functional device area 102 at the edge of the main display area 101 close to the functional device area 102, there is a redundant pixel circuit 220 adjacent to the first pixel circuit 210, and the redundant pixel circuit 220 includes a redundant active layer pattern 311 located in the active layer 310, thereby avoiding the problem of poor uniformity of the first active layer pattern 312 of the first pixel circuit 210, enabling the sub-pixel 120 where the first anode 321 is located at the edge of the main display area 101 close to the functional device area 102 to emit light normally.

[0132] In some embodiments, the first pixel circuit 210 includes a plurality of first thin film transistors 211 and a first storage capacitor 212. Between S10 of fabricating the active layer 310 on the substrate 120 and S20 of fabricating the anode layer 320 on the side of the active layer 310 away from the substrate 120, the above fabrication method further includes:

[0133] S11, fabricate a first gate conductive layer 330 on the side of the active layer 310 away from the substrate 120.

[0134] The first gate conductive layer 330 includes first gate patterns 331 of a plurality of first pixel circuits 210, and the first gate patterns 331 include gates G1 of a plurality of first thin film transistors 211, a first electrode plate C11 of the first storage capacitor 212, a scanning line GL, and a light emitting signal line EM.

[0135] S12, fabricate a second gate conductive layer 340 on the side of the first gate conductive layer 330 away from the substrate 120.

[0136] The second gate conductive layer 340 includes second gate patterns 341 of a plurality of first pixel circuits 210, and the second gate patterns 341 include a second electrode plate C12 of the first storage capacitor 212, a first initialization power supply line Vint1, and a second initialization power supply line Vint2.

[0137] S13, fabricate a source-drain conductive layer 350 on the side of the second gate conductive layer 340 away from the substrate 120.

[0138] The source-drain conductive layer 350 includes source-drain conductive patterns 351 of a plurality of first pixel circuits 210. The source-drain conductive patterns 351 include source electrodes S1 and drain electrodes D1 of a plurality of first thin-film transistors 30, data lines DATA, and voltage signal lines VDD.

[0139] The first active layer pattern 312, the first gate pattern 331, the second gate pattern 341, and the source-drain conductive pattern 351 together constitute the first pixel circuit 210.

[0140] In some embodiments, the redundant pixel circuit 220 may only include a redundant active layer pattern 311, or may further include a redundant active layer pattern 311, a redundant first gate pattern 332, a redundant second gate pattern 342, and a redundant source-drain conductive layer pattern 352 that are sequentially stacked on the substrate 120.

[0141] In the case where the redundant pixel circuit 220 only includes the redundant active layer pattern 311, the orthographic projections of all patterns of the first gate conductive layer 330, all patterns of the second gate conductive layer 340, and all patterns of the source-drain conductive layer 350 on the substrate 120 are all separated from the orthographic projection of the redundant active layer pattern 311 on the substrate 120.

[0142] In the case where the redundant pixel circuit 220 includes a plurality of redundant thin-film transistors 221 and a redundant storage capacitor 222; that is, the redundant pixel circuit 220 further includes a redundant active layer pattern 311, a redundant first gate pattern 332, a redundant second gate pattern 342, and a redundant source-drain conductive layer pattern 352 that are sequentially stacked on the substrate 120.

[0143] The first gate conductive layer 330 further includes first redundant gate patterns 332 of a plurality of redundant pixel circuits 220. The redundant gate patterns 332 include gates G2 of a plurality of redundant thin-film transistors 221 and first electrode plates C21 of the redundant storage capacitor 222; the first redundant gate patterns 332 are provided on the same layer as the first gate pattern 331.

[0144] The second gate conductive layer 340 further includes second redundant gate patterns 342 of a plurality of redundant pixel circuits 220. The second redundant gate patterns 342 include second electrode plates C22 of the redundant storage capacitor 222; the second redundant gate patterns 342 are provided on the same layer as the second gate pattern 341.

[0145] The source-drain conductive layer 350 further includes redundant source-drain conductive patterns 352 of a plurality of redundant pixel circuits 220. The redundant source-drain conductive patterns 352 include source electrodes S2 and drain electrodes D2 of a plurality of redundant thin-film transistors 221; the redundant source-drain conductive patterns 352 are electrically insulated from the anode layer 320, and the redundant source-drain conductive patterns 352 are provided on the same layer as the source-drain conductive patterns 351.

[0146] The structure of the redundant pixel circuit 220 is the same as that of the first pixel circuit 210. However, the redundant pixel circuit 220 is electrically insulated from the anode layer 320 and does not control the light emission of any light-emitting device 30; the first pixel circuit 210 is electrically connected to the first anode 321 and is used to control the light emission of the light-emitting device 30 where the first anode 321 is located. The redundant pixel circuit 220 can improve the uniformity of the first pixel circuit 210, avoid the problem of Vth shift in the first pixel circuit 210, and thus solve the problem of abnormal display of the light-emitting device 30 connected to the first pixel circuit 210 located at the edge of the main display area 101 close to the functional device area 102.

[0147] As described above, the above is only the specific implementation manner of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present disclosure, thinking of changes or substitutions, should be covered within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A display panel, characterized in that, it includes a main display area and a functional device area, and at least part of the main display area surrounds the functional device area; the display panel includes a plurality of first pixel circuits and a plurality of redundant pixel circuits, and the plurality of first pixel circuits are located in the main display area; the display panel includes an active layer and an anode layer sequentially arranged along a direction perpendicular to the substrate and away from the substrate; the anode layer includes a plurality of first anodes located in the main display area, and each first anode is electrically connected to a first pixel circuit; the plurality of redundant pixel circuits are adjacent to a plurality of first pixel circuits arranged at the edge of the main display area close to the functional device area; the redundant pixel circuit at least includes a redundant active layer pattern located in the active layer, and the redundant pixel circuit is electrically insulated from the anode layer.

2. The display panel according to claim 1, characterized in that, the plurality of redundant pixel circuits are located in a transition area; the transition area includes: a first straight extension segment located at one edge of the transition area in the second direction, and at least two rows of redundant pixel circuits are arranged on the first straight extension segment; two second straight extension segments respectively located at two edges of the transition area in the first direction, and at least two columns of redundant pixel circuits are arranged on each second straight extension segment.

3. The display panel according to claim 2, characterized in that, the pattern formed by arranging the plurality of redundant pixel circuits is symmetric with respect to a straight line along the first direction of the transition area; and / or, the pattern formed by arranging the plurality of redundant pixel circuits is symmetric with respect to a straight line along the second direction of the transition area.

4. The display panel according to any one of claims 1 to 3, characterized in that, the first pixel circuit includes a plurality of first thin film transistors and a first storage capacitor; the active layer further includes a first active layer pattern of the plurality of first thin film transistors; the display panel further includes: a first gate conductive layer disposed between the active layer and the anode layer, including a first gate pattern of the plurality of first pixel circuits, and the first gate pattern includes gates of the plurality of first thin film transistors, a first electrode plate of the first storage capacitor, a scan line, and a light emitting signal line; a second gate conductive layer disposed between the first gate conductive layer and the anode layer, including a second gate pattern of the plurality of first pixel circuits, and the second gate pattern includes a second electrode plate of the first storage capacitor, a first initialization power supply line, and a second initialization power supply line; a source-drain conductive layer disposed between the second gate conductive layer and the anode layer, including a source-drain conductive pattern of the plurality of first pixel circuits, and the source-drain conductive pattern includes sources and drains of the plurality of first thin film transistors, a data line, and a voltage signal line.

5. The display panel according to claim 4, characterized in that, the display panel further includes: a first gate insulating layer disposed between the active layer and the first gate conductive layer; a second gate insulating layer disposed between the first gate conductive layer and the second gate conductive layer; an interlayer insulating layer disposed between the second gate conductive layer and the source-drain conductive layer; Wherein, the first gate insulating layer, the second gate insulating layer, and the interlayer insulating layer all cover the redundant active layer pattern; Multiple vias are provided in the first gate insulating layer, the second gate insulating layer, and the interlayer insulating layer. The vias penetrate through the interlayer insulating layer, the second gate insulating layer, and the first gate insulating layer, and the orthographic projection of the vias on the substrate is located within the orthographic projection range of the redundant active layer pattern on the substrate.

6. The display panel according to claim 5, wherein, the display panel further includes: a passivation layer, disposed between the source-drain conductive layer and the anode layer, and covering the redundant active layer pattern; the material of the passivation layer is filled in the vias.

7. The display panel according to claim 4, wherein, the redundant pixel circuit includes multiple redundant thin film transistors and redundant storage capacitors; the first gate conductive layer further includes a first redundant gate pattern of the multiple redundant pixel circuits. The first redundant gate pattern includes the gates of the multiple redundant thin film transistors and the first electrode plate of the redundant storage capacitor; the second gate conductive layer further includes a second redundant gate pattern of the multiple redundant pixel circuits. The second redundant gate pattern includes the second electrode plate of the redundant storage capacitor; the source-drain conductive layer further includes a redundant source-drain conductive pattern of the multiple redundant pixel circuits. The redundant source-drain conductive pattern includes the sources and drains of the multiple redundant thin film transistors; the redundant source-drain conductive pattern is electrically insulated from the anode layer.

8. The display panel according to claim 7, wherein, in two adjacent redundant pixel circuits along a first direction, the redundant active layer patterns are separated from each other, the first redundant gate patterns are connected, and the second redundant gate patterns are connected; the first direction is the row direction in which the multiple first pixel circuits are arranged; in two adjacent redundant pixel circuits along a second direction, the redundant active layer patterns are separated from each other, and the redundant source-drain conductive patterns are connected; the second direction is the column direction in which the multiple first pixel circuits are arranged.

9. The display panel according to claim 1, wherein, the display panel further includes: multiple second pixel circuits, disposed in the area of the display panel other than the functional device area; the anode layer further includes: multiple second anodes, located in the functional device area, and each second anode is electrically connected to a second pixel circuit.

10. The display panel according to claim 9, wherein, the display panel further includes: a transfer conductive layer, located between the film layer where the multiple first pixel circuits and the multiple second pixel circuits are located and the anode layer, and including multiple separated transfer blocks; the multiple transfer blocks include a first transfer block electrically connected to the first pixel circuit and a second transfer block electrically connected to the second pixel circuit; the orthographic projection of the first transfer block on the substrate covers the first connection node of the first pixel circuit electrically connected thereto, and is electrically connected to the first connection node; the first connection node is the node in the first pixel circuit configured to be electrically connected to the first anode; The orthographic projection of the second adapter block on the substrate covers the second connection node of the second pixel circuit electrically connected thereto and is electrically connected to the second connection node; the second connection node is a node in the second pixel circuit configured to be electrically connected to the second anode.

11. The display panel according to claim 10, It is characterized in that The plurality of first pixel circuits and the plurality of second pixel circuits are both located in the main display area; The plurality of second pixel circuits are arranged in a plurality of rows and a plurality of columns, and a plurality of first pixel circuits are arranged between two adjacent second pixel circuits in the same row.

12. The display panel according to claim 10 or 11, It is characterized in that The display panel further includes: At least one connection layer is located between the switching conductive layer and the anode layer; the connection layer includes a plurality of connection lines, one end of the connection line is electrically connected to the second pixel circuit through a second switching block, and the other end of the connection line is electrically connected to the second anode.

13. A display device, It is characterized in that The invention comprises the display panel according to any one of claims 1 to 12.

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