Display substrate and display device

Abstract

The display substrate comprises a substrate, a plurality of sub-pixels and a plurality of first power lines located in a display area, and M first voltage power supply groups located in a first frame area. The plurality of sub-pixels are divided into N sub-pixel groups, each sub-pixel group comprises a plurality of sub-pixels emitting light of the same color, different sub-pixel groups are configured to emit light of different colors, and each first power line is connected with the plurality of sub-pixels emitting light of the same color. The M first voltage power supply groups are configured to provide different first voltage signals; each first voltage power supply group is configured to provide a first voltage signal for the pixel circuit in at least one sub-pixel group through at least one first power line, M and N are integers larger than 1, and M is smaller than or equal to N.

Description

Technical Field

[0001] This application relates to, but is not limited to, display technologies, and particularly to a display substrate and a display device. Background Art

[0002] Organic Light Emitting Diode (OLED) and Quantum-dot Light Emitting Diode (QLED) are active light-emitting display devices, which have the advantages of self-luminescence, wide viewing angle, high contrast ratio, low power consumption, extremely high response speed, light weight, flexibility, and low cost. Summary of the Invention

[0003] The following is an overview of the subject matter described in detail in this application. This overview is not intended to limit the scope of protection of the claims.

[0004] Embodiments of the present disclosure provide a display substrate and a display device.

[0005] On the one hand, an embodiment of the present disclosure provides a display substrate, including: a substrate, a plurality of sub-pixels, a plurality of first power supply lines, and M first voltage supply groups. The substrate includes: a display area and a first border area located on one side of the display area. The plurality of sub-pixels and the plurality of first power supply lines are located in the display area. The plurality of sub-pixels are divided into N sub-pixel groups, and each sub-pixel group includes a plurality of sub-pixels that emit light of the same color. Different sub-pixel groups are configured to emit light of different colors. At least one sub-pixel among the plurality of sub-pixels includes: a pixel circuit and a light-emitting element connected to the pixel circuit. Each first power supply line is connected to the pixel circuits of the plurality of sub-pixels that emit light of the same color. The M first voltage supply groups are located in the first border area, and the M first voltage supply groups are configured to provide different first voltage signals; each first voltage supply group is configured to supply a first voltage signal to the pixel circuits in at least one sub-pixel group through at least one first power supply line, where M and N are both integers greater than 1, and M is less than or equal to N.

[0006] In some exemplary embodiments, the first border area includes: a first fan-out area and a first signal access area sequentially arranged along a direction away from the display area. Each first voltage supply group at least includes: at least one first power supply line located in the first fan-out area and at least one first voltage contact pad located in the first signal access area; the at least one first power supply line is connected to the at least one first voltage contact pad.

[0007] In some exemplary embodiments, the first border region further includes: a second fan-out region and a bending region. The second fan-out region and the bending region are located on a side of the first fan-out region close to the display region, and the bending region connects the first fan-out region and the second fan-out region. Each first voltage power supply group further includes: at least one second power supply line located in the second fan-out region, and at least one first power supply bending line located in the bending region; the at least one second power supply line is connected to a plurality of first power supply lines transmitting the same first voltage signal, and the at least one first power supply bending line connects the at least one first power supply line and the at least one second power supply line.

[0008] In some exemplary embodiments, the second power supply line extends at least along a first direction, the first power supply bending line extends at least along a second direction, the first power supply line extends at least along the second direction, and the first direction intersects the second direction; the at least one first power supply line is symmetrically arranged about a median line of the first border region along the first direction.

[0009] In some exemplary embodiments, the second power supply line is connected to a plurality of first power supply lines through a first type of voltage transfer electrode, and the at least one first power supply bending line is connected to the second power supply line and a plurality of first power supply lines through a second type of voltage transfer electrode; the first type of voltage transfer electrode and the second type of voltage transfer electrode are of the same layer structure.

[0010] In some exemplary embodiments, the distance between the orthographic projections of the first power supply lines of at least two of the M first voltage power supply groups on the substrate is greater than 0, and the first power supply line includes at least two interconnected traces.

[0011] In some exemplary embodiments, in a direction perpendicular to the display substrate, the display substrate includes: a first semiconductor layer, a first gate metal layer, a second gate metal layer, a second semiconductor layer, a third gate metal layer, a first source-drain metal layer, a second source-drain metal layer, and a third source-drain metal layer disposed on the substrate. The first power supply line of at least one of the M first voltage power supply groups includes traces located in at least two of the first source-drain metal layer, the second source-drain metal layer, and the third source-drain metal layer.

[0012] In some exemplary embodiments, the first power supply lines of different first voltage power supply groups are located in different conductive layers, and the orthographic projections of the first power supply lines of at least two first voltage power supply groups partially overlap on the substrate.

[0013] In some exemplary embodiments, the line widths of the line segments of the first power supply lines of the M first voltage power supply groups in the same extension direction are the same.

[0014] In some exemplary embodiments, the line widths of line segments of the first power supply lines of at least two adjacent first voltage power supply groups in the same extension direction are different.

[0015] In some exemplary embodiments, the N sub-pixel groups include: a first sub-pixel group that emits a first color light, a second sub-pixel group that emits a second color light, and a third sub-pixel group that emits a third color light. The M first voltage power supply groups include: a first first voltage power supply group that provides a first type of first voltage signal, a second first voltage power supply group that provides a second type of first voltage signal, and a third first voltage power supply group that provides a third type of first voltage signal. The first first voltage power supply group is configured to provide the first type of first voltage signal to the first sub-pixel group; the second first voltage power supply group is configured to provide the second type of first voltage signal to the second sub-pixel group; the third first voltage power supply group is configured to provide the third type of first voltage signal to the third sub-pixel group.

[0016] In some exemplary embodiments, the first color light is blue light, the second color light is red light, and the third color light is green light; the first type of first voltage signal is greater than the second type of first voltage signal, and the second type of first voltage signal is greater than the third type of first voltage signal.

[0017] In some exemplary embodiments, the display substrate further includes: a bottom shielding layer, and the bottom shielding layer is connected to the first first voltage power supply group.

[0018] In some exemplary embodiments, the first border region includes: a first fan-out region and a first signal access region that are sequentially arranged along a direction away from the display region. Each first voltage power supply group includes at least: at least one first power supply line located in the first fan-out region and at least one first voltage contact pad located in the first signal access region; the at least one first power supply line is connected to the at least one first voltage contact pad. The average line width of the first power supply lines of the first first voltage power supply group is greater than the average line width of the first power supply lines of the second first voltage power supply group; the average line width of the first power supply lines of the second first voltage power supply group is greater than the average line width of the first power supply lines of the third first voltage power supply group.

[0019] In some exemplary embodiments, the first border region includes: a first fan-out region and a first signal access region sequentially arranged along a direction away from the display region. Each first voltage supply group includes at least: at least one first power supply line located in the first fan-out region and at least one first voltage contact pad located in the first signal access region; the at least one first power supply line is connected to the at least one first voltage contact pad. The first power supply lines of the first first voltage supply group, the first power supply lines of the second first voltage supply group, and the first power supply lines of the third first voltage supply group are single-layer traces and partially overlap in the orthographic projection on the substrate.

[0020] In some exemplary embodiments, in a direction perpendicular to the display substrate, the display substrate at least includes: a first source-drain metal layer, a second source-drain metal layer, and a third source-drain metal layer disposed on the substrate. The first power supply lines of the first first voltage supply group are located in the first source-drain metal layer, the first power supply lines of the second first voltage supply group are located in the second source-drain metal layer, and the first power supply lines of the third first voltage supply group are located in the third source-drain metal layer.

[0021] In some exemplary embodiments, the display substrate further includes: L second voltage supply groups located in the first border region, the L second voltage supply groups are configured to provide different second voltage signals, and each second voltage supply group is configured to provide a second voltage signal to the light-emitting elements in at least one sub-pixel group, where L is an integer greater than 1 and less than or equal to N; the second voltage signal is different from the first voltage signal.

[0022] In some exemplary embodiments, the N sub-pixel groups include: a first sub-pixel group that emits first-color light, a second sub-pixel group that emits second-color light, and a third sub-pixel group that emits third-color light. The L second voltage supply groups include: a first second voltage supply group that provides a first type of second voltage signal, a second second voltage supply group that provides a second type of second voltage signal, and a third second voltage supply group that provides a third type of second voltage signal. The first second voltage supply group is configured to provide a first type of second voltage signal to the first sub-pixel group; the second second voltage supply group is configured to provide a second type of second voltage signal to the second sub-pixel group; the third second voltage supply group is configured to provide a third type of second voltage signal to the third sub-pixel group.

[0023] In some exemplary embodiments, the first-color light is blue light, the second-color light is red light, and the third-color light is green light; the first type of second voltage signal is less than the second type of second voltage signal, and the second type of second voltage signal is less than the third type of second voltage signal.

[0024] In some exemplary embodiments, the light-emitting element includes an anode and a cathode; cathodes of a plurality of light-emitting elements that emit light of the same color are interconnected and connected to a second voltage supply group through at least a third-type voltage transfer electrode.

[0025] On the other hand, this embodiment provides a display device including the display substrate as described above.

[0026] On the other hand, this embodiment provides a display substrate including: a substrate, a plurality of sub-pixels, a plurality of second power supply lines, and L second voltage supply groups. The substrate includes a display area and a first border area on one side of the display area. The plurality of sub-pixels and the plurality of second power supply lines are located in the display area. The plurality of sub-pixels are divided into N sub-pixel groups, each sub-pixel group includes a plurality of sub-pixels that emit light of the same color, different sub-pixel groups are configured to emit light of different colors, and at least one sub-pixel of the plurality of sub-pixels includes: a pixel circuit and a light-emitting element connected to the pixel circuit. Each second power supply line is connected to the light-emitting elements of a plurality of sub-pixels that emit light of the same color. The L second voltage supply groups are located in the first border area, the L second voltage supply groups are configured to provide different second voltage signals, and each second voltage supply group is configured to provide a second voltage signal to the light-emitting elements in at least one sub-pixel group through at least one second power supply line; wherein, both L and N are integers greater than 1, and L is less than or equal to N.

[0027] In some exemplary embodiments, the N sub-pixel groups include: a first sub-pixel group that emits first-color light, a second sub-pixel group that emits second-color light, and a third sub-pixel group that emits third-color light. The L second voltage supply groups include: a first second voltage supply group that provides a first type of second voltage signal, a second second voltage supply group that provides a second type of second voltage signal, and a third second voltage supply group that provides a third type of second voltage signal. The first second voltage supply group is configured to provide the first type of second voltage signal to the first sub-pixel group. The second second voltage supply group is configured to provide the second type of second voltage signal to the second sub-pixel group. The third second voltage supply group is configured to provide the third type of second voltage signal to the third sub-pixel group.

[0028] In some exemplary embodiments, the first-color light is blue light, the second-color light is red light, and the third-color light is green light; the first type of second voltage signal is less than the second type of second voltage signal, and the second type of second voltage signal is less than the third type of second voltage signal.

[0029] Other aspects can be understood after reading and understanding the drawings and the detailed description. Description of the Drawings

[0030] The accompanying drawings are used to provide an understanding of the technical solutions of the present application and form a part of the specification. Together with the embodiments of the present application, they are used to explain the technical solutions of the present application and do not constitute a limitation to the technical solutions of the present application.

[0031] Figure 1 Schematic diagram of a display substrate according to at least one embodiment of the present disclosure;

[0032] Figure 2 Equivalent circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0033] Figure 3 is Figure 2 Timing diagram of the operation of the provided pixel circuit;

[0034] Figure 4 Schematic diagram of the transmission of the first voltage signal according to at least one embodiment of the present disclosure;

[0035] Figure 5 Schematic diagram of the wiring in the first border area according to at least one embodiment of the present disclosure;

[0036] Figure 6 is Figure 5 Partial enlarged schematic diagram of area C1 in

[0037] Figure 7 is Figure 6 Partial schematic diagram of the display substrate after forming the shielding layer in

[0038] Figure 8 is Figure 6 Partial schematic diagram of the display substrate after forming the first semiconductor layer in

[0039] Fig.9A is Figure 6 Partial schematic diagram of the display substrate after forming the first conductive layer in

[0040] Fig. 9B is Fig.9A Schematic diagram of the first conductive layer in

[0041] Fig. 10A is Figure 6 Partial schematic diagram of the display substrate after forming the second conductive layer in

[0042] Fig. 10B is Fig. 10A Schematic diagram of the second conductive layer in

[0043] Fig.11 is Figure 6 Partial schematic diagram of the display substrate after forming the second semiconductor layer in

[0044] Fig. 12A is Figure 6 Partial schematic diagram of the display substrate after forming the third conductive layer;

[0045] Fig. 12B For Fig. 12A Schematic diagram of the third conductive layer in;

[0046] Fig.13 For Figure 6 Partial schematic diagram of the display substrate after forming the sixth insulating layer;

[0047] Fig.14A For Figure 6 Partial schematic diagram of the display substrate after forming the fourth conductive layer;

[0048] Fig. 14B For Fig.14A Schematic diagram of the fourth conductive layer in;

[0049] Fig.15 For Figure 6 Partial schematic diagram of the display substrate after forming the eighth insulating layer;

[0050] Fig.16A For Figure 6 Partial schematic diagram of the display substrate after forming the fifth conductive layer;

[0051] Fig. 16B For Fig.16A Schematic diagram of the fifth conductive layer in;

[0052] Fig.17 For Figure 6 Partial schematic diagram of the display substrate after forming the ninth insulating layer;

[0053] Fig.18A For Figure 6 Partial schematic diagram of the display substrate after forming the sixth conductive layer;

[0054] Fig.18B For Fig.18A Schematic diagram of the sixth conductive layer in;

[0055] Fig.19 For Figure 6 Schematic diagram of the anode layer in;

[0056] Fig. 20A For Figure 5 Partial enlarged schematic diagram of region C2 in;

[0057] Fig. 20B For Fig. 20A Schematic diagram of the fourth conductive layer in;

[0058] Fig. 20C For Fig. 20A Schematic diagram after forming the eighth insulating layer;

[0059] Fig.20D Schematic diagram of the fifth conductive layer in Fig. 20A ;

[0060] Fig.21A Schematic diagram of the partial magnification of region C2 in Figure 5 ;

[0061] Fig.21B Schematic diagram of the fourth conductive layer in Fig.21A ;

[0062] Fig. 21C Schematic diagram after forming the eighth insulating layer in Fig.21A ;

[0063] Fig.21D Schematic diagram of the fifth conductive layer in Fig.21A ;

[0064] Fig.22A Schematic diagram of the partial magnification of region C2 in Figure 5 ;

[0065] Fig. 22B Schematic diagram of the fourth conductive layer in Fig.22A ;

[0066] Fig. 22C Schematic diagram after forming the eighth insulating layer in Fig.22A ;

[0067] Fig.22D Schematic diagram of the fifth conductive layer in Fig.22A ;

[0068] Fig.23A Schematic diagram of the partial magnification of region C3 in Figure 5 ;

[0069] Fig. 23B Schematic diagram of the fourth conductive layer in Fig.23A ;

[0070] Fig.23C Schematic diagram after forming the eighth insulating layer in Fig.23A ;

[0071] Fig.23D Schematic diagram of the fifth conductive layer in Fig.23A ;

[0072] Fig.23E Schematic diagram after forming the ninth insulating layer in Fig.23A ;

[0073] Fig.23F Schematic diagram of the sixth conductive layer in Fig.23A ;

[0074] Fig.24A is Figure 5 a partial enlarged schematic view of region C4 in

[0075] Fig. 24B is Fig.24A a schematic view of the fourth conductive layer in

[0076] Fig.24C is Fig.24A a schematic view after the eighth insulating layer is formed in

[0077] Fig.24D is Fig.24A a schematic view of the fifth conductive layer in

[0078] Fig.24E is Fig.24A a schematic view of the sixth conductive layer in

[0079] Fig.25 is Fig.24A a partial enlarged schematic view of region C5 in

[0080] Fig.26 is another wiring schematic view of the first border region of at least one embodiment of the present disclosure;

[0081] Fig. 27 is Fig.26 a partial enlarged schematic view of region C6 in

[0082] Fig.28 is another wiring schematic view of the first border region of at least one embodiment of the present disclosure;

[0083] Fig.29 is Fig.28 a partial enlarged schematic view of region C7 in

[0084] Fig. 30A is Fig.28 a partial enlarged schematic view of region C8 in

[0085] Fig. 30B is Fig. 30A a schematic view of the fourth conductive layer and the fifth conductive layer in

[0086] Fig. 30C is Fig. 30A a schematic view of the fifth conductive layer in

[0087] Fig.31A is Fig.28 a partial enlarged schematic view of region C9 in

[0088] Fig.31B is Fig.31A a schematic view of the fourth conductive layer and the fifth conductive layer in

[0089] Fig.31C is Fig.31A a schematic diagram of the fifth conductive layer in

[0090] Fig.32 a schematic diagram of the transmission of the second voltage signal in at least one embodiment of the present disclosure;

[0091] Fig.33 a schematic diagram of the routing in the first border region in at least one embodiment of the present disclosure;

[0092] Fig.34A is Fig.33 a partial enlarged schematic diagram of region C10 in

[0093] Fig.34B is Fig.34A a schematic diagram of the fourth conductive layer in

[0094] Fig.34C is Fig.34A a schematic diagram after forming the fifth conductive layer in

[0095] Fig.34D is Fig.34A a schematic diagram after forming the anode layer in

[0096] Fig.35 a schematic diagram of a display device in at least one embodiment of the present disclosure. Detailed Embodiments

[0097] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. The embodiments can be implemented in multiple different forms. It is easy for those of ordinary skill in the art to understand the fact that the forms and contents can be transformed into other forms without departing from the spirit and scope of the present disclosure. Therefore, the present disclosure should not be construed as being limited only to the contents described in the following embodiments. Without conflict, the embodiments and features in the embodiments of the present disclosure can be combined arbitrarily with each other.

[0098] In the drawings, sometimes for clarity, the size, thickness of a layer, or region of one or more constituent elements is exaggerated. Therefore, one aspect of the present disclosure is not necessarily limited to this size, and the shape and size of one or more components in the drawings do not reflect the true scale. In addition, the drawings schematically show ideal examples, and one aspect of the present disclosure is not limited to the shapes or values shown in the drawings.

[0099] The ordinal numbers such as "first", "second", "third", etc. in this specification are set to avoid confusion of constituent elements, rather than to limit the quantity. "Multiple" in the present disclosure means two or more quantities.

[0100] In this specification, for convenience, terms indicating orientation or positional relationships such as "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. are used to describe the positional relationships of the components with reference to the accompanying drawings. This is only for the convenience of describing this specification and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation on the present disclosure. The positional relationships of the components are appropriately changed according to the directions describing the components. Therefore, it is not limited to the terms described in the specification and can be appropriately replaced according to the circumstances.

[0101] In this specification, unless otherwise clearly defined and limited, the terms "mounted", "connected", "coupled" shall be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate member, or the internal communication of two elements. For those of ordinary skill in the art, the meanings of the above terms in the present disclosure can be understood according to the circumstances.

[0102] In this specification, "electrically connected" includes the case where components are connected together through an element having a certain electrical function. There is no particular limitation on the "element having a certain electrical function" as long as it can transmit electrical signals between the components to be connected. Examples of the "element having a certain electrical function" include not only electrodes and wirings, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.

[0103] In this specification, a transistor refers to an element having at least three terminals: a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain) and the source electrode (source electrode terminal, source region, or source), and current can flow through the drain electrode, the channel region, and the source electrode. In this specification, the channel region refers to the region where current mainly flows.

[0104] In this specification, the first pole can be the drain electrode and the second pole can be the source electrode, or the first pole can be the source electrode and the second pole can be the drain electrode. In the case of using transistors with opposite polarities or when the current direction changes during circuit operation, etc., the functions of the "source electrode" and "drain electrode" are sometimes interchanged. Therefore, in this specification, the "source electrode" and "drain electrode" can be interchanged. In addition, the gate can also be referred to as the control electrode.

[0105] In this specification, "parallel" means a state where the angle formed by two straight lines is more than -10° and less than 10°. Therefore, it also includes the state where the angle is more than -5° and less than 5°. In addition, "perpendicular" means a state where the angle formed by two straight lines is more than 80° and less than 100°. Therefore, it also includes the state where the angle is more than 85° and less than 95°.

[0106] In this specification, shapes such as circles, ellipses, triangles, rectangles, trapezoids, pentagons, or hexagons are not strictly defined and can be approximate circles, approximate ellipses, approximate triangles, approximate rectangles, approximate trapezoids, approximate pentagons, or approximate hexagons, etc. There can be some small deformations caused by tolerances, such as chamfers, arc edges, and deformations.

[0107] "About" and "substantially" in this disclosure mean that the boundaries are not strictly defined and situations within the process and measurement errors are allowed. In this disclosure, "the same" includes both exactly the same and substantially the same situations. "Substantially the same" means that the numerical difference is within 10%.

[0108] In this specification, A extending along the B direction means that A can include a main body part and a secondary part connected to the main body part. The main body part is a line, line segment, or strip-shaped body, the main body part extends along the B direction, and the length of the main body part extending along the B direction is greater than the length of the secondary part extending along other directions. When it is said that "A extends along the B direction" in this specification, it always means that "the main body part of A extends along the B direction".

[0109] When it is said in this specification that "A and B are of the same layer structure" or "A and B are arranged on the same layer", it means that A and B are formed simultaneously through the same lithography process, or the distances from the surfaces of A and B close to the substrate side to the substrate are basically the same, or the surfaces of A and B close to the substrate side are in direct contact with the same film layer. "The same layer" does not always mean that the thickness or height of the layer is the same in the cross-sectional view. The "thickness" of the film layer is the dimension of the film layer in the direction perpendicular to the display substrate. "The orthographic projection of A contains the orthographic projection of B" means that the orthographic projection of B falls within the orthographic projection range of A, or the orthographic projection of A covers the orthographic projection of B.

[0110] With the development of display technology, how to save the power consumption of the display substrate is an issue that needs to be considered.

[0111] This embodiment provides a display substrate and a display device, which can save the overall power consumption of the display substrate.

[0112] This embodiment provides a display substrate, including: a substrate, a plurality of sub-pixels, a plurality of first power lines, and M first voltage supply groups. The substrate includes: a display area and a first border area located on one side of the display area. The plurality of sub-pixels and the plurality of first power lines are located in the display area. The plurality of sub-pixels are divided into N sub-pixel groups. Each sub-pixel group includes a plurality of sub-pixels that emit light of the same color. Different sub-pixel groups are configured to emit light of different colors. At least one sub-pixel includes: a pixel circuit and a light-emitting element connected to the pixel circuit. Each first power line is connected to the pixel circuits of a plurality of sub-pixels that emit light of the same color. The M first voltage supply groups are located in the first border area. The M first voltage supply groups are configured to provide different first voltage signals. Each first voltage supply group is configured to supply a first voltage signal to the pixel circuits in at least one sub-pixel group through at least one first power line. Wherein, both M and N are integers greater than 1, and M is less than or equal to N.

[0113] In some examples, the number of sub-pixel groups may be the same as the number of first voltage supply groups, that is, M may be equal to N. Each first voltage supply group may supply a first voltage signal to one sub-pixel group. Wherein, different sub-pixel groups receive different first voltage signals. In other examples, M may be less than N, and at least one first voltage supply group may supply first voltage signals to at least two sub-pixel groups. Wherein, the first voltage signals received by at least two sub-pixel groups may be the same. For example, one of the M first voltage supply groups may be configured to supply the same first voltage signal to the pixel circuits in two sub-pixel groups. This embodiment does not limit this.

[0114] In some examples, each of the M first voltage supply groups may be configured to provide a first voltage signal different from that of the remaining first voltage supply groups. In other words, the M first voltage supply groups may provide M different first voltage signals. In other examples, at least two of the M first voltage supply groups may be configured to provide different first voltage signals. For example, the M first voltage supply groups may be configured to provide M - 1 different first voltage signals. Two of the M first voltage supply groups may provide the same first voltage signal, and the remaining first voltage supply groups may be configured to provide different first voltage signals. This embodiment does not limit this.

[0115] In some examples, multiple pixel circuits in a sub-pixel group can be connected to multiple first power supply lines, and a first voltage supply group can be configured to supply a first voltage signal to the pixel circuits in the sub-pixel group through the multiple first power supply lines. In other examples, multiple pixel circuits in a sub-pixel group can be connected to one first power supply line, and a first voltage supply group can be configured to supply a first voltage signal to the pixel circuits in the sub-pixel group through one first power supply line. This embodiment does not limit this.

[0116] In some examples, the pixel circuit of a sub-pixel can at least include: a driving transistor, a first light-emitting control transistor, and a storage capacitor. The first pole of the first light-emitting control transistor can be connected to the first power supply line, and the second pole can be connected to the first pole of the driving transistor. The first electrode of the storage capacitor can be connected to the gate of the driving transistor, and the second electrode can be connected to the first power supply line. The first power supply line can be electrically connected to the first poles of the first light-emitting control transistors and the second electrodes of the storage capacitors of the pixel circuits of multiple sub-pixels that emit the same color of light.

[0117] For the display substrate provided in this embodiment, by grouping to supply the first voltage signal to the sub-pixels, different sub-pixel groups in the display area can receive different first voltage signals, which is beneficial to reducing the power consumption of the display substrate.

[0118] In some exemplary embodiments, the first border area can include: a first fan-out area and a first signal access area arranged in sequence along the direction away from the display area. Each first voltage supply group can at least include: at least one first power supply line located in the first fan-out area and at least one first voltage contact pad located in the first signal access area; at least one first power supply line is connected to at least one first voltage contact pad. In some examples, the first border area can further include: a second fan-out area and a bending area. The second fan-out area and the bending area can be located on the side of the first fan-out area close to the display area, and the bending area connects the first fan-out area and the second fan-out area; each first voltage supply group can further include: at least one second power supply line located in the second fan-out area and at least one first power supply bending line located in the bending area. At least one second power supply line is connected to multiple first power supply lines that transmit the same first voltage signal, and at least one first power supply bending line connects at least one first power supply line and at least one second power supply line. This example can set the routing layout of the first voltage supply group according to the structure of the first border area, which is beneficial to the routing space layout.

[0119] In some exemplary embodiments, the second power supply line may extend at least along a first direction, the first power supply bending line may extend at least along a second direction, and the first power line may extend at least along the second direction, wherein the first direction intersects the second direction. At least one first power supply line may be symmetrically arranged about the midline of the first border region along the first direction. The wiring arrangement in this example is conducive to saving layout space.

[0120] In some exemplary embodiments, the second power supply line may be connected to a plurality of first power lines through a first type of voltage transfer electrode, at least one first power supply bending line may be connected to the second power supply line and a plurality of first power lines through a second type of voltage transfer electrode, and the first type of voltage transfer electrode and the second type of voltage transfer electrode may be of the same-layer structure. The wiring connection method of the first voltage power supply group in this example can advantageously save layout space and is conducive to the uniform design of the film layer pattern.

[0121] In some exemplary embodiments, the distance between the positive projections of the first power supply lines of at least two of the M first voltage power supply groups on the substrate may be greater than 0. In other words, the positive projections of the first power supply lines of at least two first voltage power supply groups on the substrate may not overlap. The first power supply line may include at least two interconnected traces. For example, the first power supply line may be a double-layer trace structure or a triple-layer trace structure. For example, in a direction perpendicular to the display substrate, the display substrate may include: a first semiconductor layer, a first gate metal layer, a second gate metal layer, a second semiconductor layer, a third gate metal layer, a first source-drain metal layer, a second source-drain metal layer, and a third source-drain metal layer provided on the substrate; the first power supply line of at least one first voltage power supply group may include sub-traces located in at least two of the first source-drain metal layer, the second source-drain metal layer, and the third source-drain metal layer. For example, the first power supply lines of multiple first voltage power supply groups may all include double-layer traces or may all include triple-layer traces. Another example is that the first power supply line of at least one first voltage power supply group may include triple-layer traces, and the first power supply lines of the remaining first voltage power supply groups may include double-layer traces to meet the voltage drop requirements of different first power supply lines. The multi-layer trace design of the first power supply line in this example can reduce the voltage drop of the first power supply line.

[0122] In some exemplary embodiments, the first power supply lines of different first voltage power supply groups may be located in different conductive layers, and the positive projections of the first power supply lines of at least two first voltage power supply groups on the substrate may partially overlap. For example, the first power supply line of at least one first voltage power supply group may be located in the first source-drain metal layer, the second source-drain metal layer, or the third source-drain metal layer. The first power supply lines of multiple first voltage power supply groups in this example may adopt single-layer traces, thereby reducing hole digging and overlapping and simplifying the manufacturing process.

[0123] In some exemplary embodiments, the line widths of the line segments of the first power supply lines of the M first voltage power supply groups in the same extension direction may be the same. By setting the first power supply lines of multiple first voltage power supply groups to have an equal-width design, this example not only helps to reduce the impedance of the first power supply lines, but also helps to optimize the routing layout space.

[0124] In some exemplary embodiments, the line widths of the line segments of the first power supply lines of at least two adjacent first voltage power supply groups in the same extension direction may be different. By setting the first power supply lines of multiple first voltage power supply groups to have a non-equal-width design, this example can adjust the voltage drops of different first power supply lines according to requirements to meet the differential design of different first power supply lines.

[0125] In some exemplary embodiments, the N sub-pixel groups may include: a first sub-pixel group that emits a first color light, a second sub-pixel group that emits a second color light, and a third sub-pixel group that emits a third color light. The M first voltage power supply groups may include: a first first voltage power supply group that provides a first type of first voltage signal, a second first voltage power supply group that provides a second type of first voltage signal, and a third first voltage power supply group that provides a third type of first voltage signal. The first first voltage power supply group is configured to provide the first type of first voltage signal to the first sub-pixel group. The second first voltage power supply group is configured to provide the second type of first voltage signal to the second sub-pixel group. The third first voltage power supply group is configured to provide the third type of first voltage signal to the third sub-pixel group. In this example, M may be equal to N, and both are three. In some examples, the first color light may be blue light (B), the second color light may be red light (R), and the third color light may be green light (G); the first type of first voltage signal may be greater than the second type of first voltage signal, and the second type of first voltage signal may be greater than the third type of first voltage signal. However, this embodiment is not limited thereto. In other examples, the number of sub-pixel groups may be three, and the number of first voltage power supply groups may be two. The first first voltage power supply group may be configured to provide the first type of first voltage signal to the first sub-pixel group (e.g., including blue sub-pixels), and the second first voltage power supply group may be configured to provide the second type of first voltage signal to the second sub-pixel group (e.g., including red sub-pixels) and the third sub-pixel group (e.g., including green sub-pixels). This example can achieve RGB brightness grouping control through the grouping design of the first voltage signal, thereby achieving the purpose of power consumption saving of the first voltage signal.

[0126] In some exemplary embodiments, the display substrate may further include: a bottom shielding layer, and the bottom shielding layer may be connected to the first first voltage power supply group. By setting the first first voltage power supply line group to be connected to the bottom shielding layer, this example can reduce the impedance of the first first voltage power supply group.

[0127] In some exemplary embodiments, the average line width of the first power supply lines of the first first-voltage power supply group may be greater than the average line width of the first power supply lines of the second first-voltage power supply group, and the average line width of the first power supply lines of the second first-voltage power supply group may be greater than the average line width of the first power supply lines of the third first-voltage power supply group. The average line width of the first power supply lines in this example refers to the average of the line widths of multiple line segments of the first power supply lines. In some examples, the first power supply lines of each first-voltage power supply group may adopt a non-uniform line width design. By setting the average line widths of the first power supply lines of multiple first-voltage power supply groups in this example, the differential design requirements of different first power supply lines can be met.

[0128] In some exemplary embodiments, the display substrate may further include: L second-voltage power supply groups located in the first border area. The L second-voltage power supply groups may be configured to provide different second-voltage signals. Each second-voltage power supply group may be configured to provide a second-voltage signal to the light-emitting elements in at least one sub-pixel group. Here, L is an integer greater than 1 and less than or equal to N. The second-voltage signal is different from the first-voltage signal. For example, the second-voltage signal may be less than the first-voltage signal. In some examples, the turn-on voltages of sub-pixels emitting different colors of light are different. By grouping and designing the second-voltage signals, precise control of the brightness of sub-pixels emitting different colors of light can be achieved, thereby achieving the purpose of reducing power consumption.

[0129] In some examples, the number of sub-pixel groups may be the same as the number of second-voltage power supply groups, that is, L may be equal to N. Each second-voltage power supply group may provide a second-voltage signal to one sub-pixel group. Among them, different sub-pixel groups receive different second-voltage signals. In other examples, L may be less than N, and at least one second-voltage power supply group may provide a first-voltage signal to at least two sub-pixel groups. Among them, the second-voltage signals received by at least two sub-pixel groups may be the same. For example, one of the L second-voltage power supply groups may be configured to provide the same second-voltage signal to two sub-pixel groups. However, this embodiment is not limited thereto.

[0130] In some examples, each of the L second-voltage power supply groups may be configured to provide a second-voltage signal different from that of the remaining second-voltage power supply groups. In other words, the L second-voltage power supply groups may provide L different second-voltage signals. In other examples, at least two of the L second-voltage power supply groups may be configured to provide different second-voltage signals. For example, the L second-voltage power supply groups may be configured to provide L - 1 different second-voltage signals, two of the L second-voltage power supply groups may provide the same second-voltage signal, and the remaining second-voltage power supply groups may be configured to provide different second-voltage signals. This embodiment is not limited thereto.

[0131] In some examples, the display area may include a plurality of second power supply lines, and each second power supply line may be connected to a light-emitting element of a plurality of sub-pixels that emit light of the same color. For example, the light-emitting element of the sub-pixel may include an anode and a cathode. The cathode of the light-emitting element may be connected to the second power supply line.

[0132] In some examples, a plurality of light-emitting elements in a sub-pixel group may be connected to a plurality of second power supply lines, and a second voltage supply group may be configured to supply a second voltage signal to the light-emitting elements in the sub-pixel group through the plurality of second power supply lines. In other examples, a plurality of light-emitting elements in a sub-pixel group may be connected to one second power supply line, and a second voltage supply group may be configured to supply a second voltage signal to the light-emitting elements in the sub-pixel group through the one second power supply line. This embodiment does not limit this.

[0133] The display substrate of this embodiment will be illustrated by some examples below. In the following exemplary embodiments, the display substrate is taken as an OLED display substrate for illustration. Among them, since the number of partial types of traces in the display area and the first border area is usually large, only several or a whole is schematically shown for a certain type of trace in the drawings, and the number of a certain type of trace is not limited.

[0134] Figure 1 Schematic diagram of a display substrate according to at least one embodiment of the present disclosure. In some examples, as Figure 1 shown, the display substrate of this example may include: a display area AA, and a border area located around the display area AA. The border area may include: a first border area B1 located on one side of the display area AA, and a second border area B2 located on the remaining sides of the display area AA. After the first border area B1 and the second border area B2 are connected, they can surround the display area AA. In some examples, the first border area B1 may be the lower border of the display substrate, and the second border area B2 may include the upper border, left border, and right border of the display substrate. However, this embodiment does not limit this.

[0135] In some examples, as Figure 1 shown, the display area AA may include: a plurality of sub-pixels PX that make up a pixel array. The plurality of sub-pixels PX may be configured to display dynamic pictures or still images, and the display area AA may be referred to as an effective area. In some examples, the display substrate may adopt a flexible substrate, so the display substrate may be deformable, such as curling, bending, folding, or rolling up.

[0136] In some examples, as Figure 1As shown, the display area AA may further include: a plurality of gate lines GL and a plurality of data lines DL. The gate lines GL may extend along the first direction X, and the data lines DL may extend along the second direction Y. The first direction X and the second direction Y may intersect. For example, the first direction X may be perpendicular to the second direction Y. The orthographic projections of the plurality of gate lines GL and the plurality of data lines DL on the substrate may intersect to form a plurality of sub-pixel regions, and one sub-pixel PX is disposed in each sub-pixel region. The plurality of data lines DL are electrically connected to the plurality of sub-pixels PX, and the plurality of data lines DL may be configured to provide data signals to the plurality of sub-pixels PX. The plurality of gate lines GL are electrically connected to the plurality of sub-pixels PX, and the plurality of gate lines GL may be configured to provide scan signals to the plurality of sub-pixels PX.

[0137] In some examples, a pixel unit may include four sub-pixels. The four sub-pixels may include a red (R) sub-pixel, a blue (B) sub-pixel, and two green (G) sub-pixels. Alternatively, a pixel unit may include three sub-pixels, which are a red (R) sub-pixel, a green (G) sub-pixel, and a blue (B) sub-pixel respectively. However, this embodiment is not limited thereto. In other examples, a pixel unit may include four sub-pixels, which are a red sub-pixel, a green sub-pixel, a blue sub-pixel, and a white sub-pixel respectively.

[0138] In some examples, at least one sub-pixel may include a pixel circuit and a light-emitting element. The pixel circuit may be configured to drive the connected light-emitting element. For example, the pixel circuit may be configured to provide a driving current to drive the light-emitting element to emit light. The pixel circuit may include a plurality of transistors and at least one capacitor. For example, the pixel circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, or 8T1C structure. Among them, T in the above circuit structure refers to a thin-film transistor, C refers to a capacitor, the number in front of T represents the number of thin-film transistors in the circuit, and the number in front of C represents the number of capacitors in the circuit.

[0139] In some examples, the light-emitting element may be any one of a light-emitting diode (LED), an organic light-emitting diode (OLED), a quantum dot light-emitting diode (QLED), a micro-LED (including: mini-LED or micro-LED), etc. For example, the light-emitting element may be an OLED, and the light-emitting element can emit red light, green light, blue light, or white light, etc. under the drive of its corresponding pixel circuit. The color of the light emitted by the light-emitting element can be determined as needed. In some examples, the light-emitting element may include: an anode, a cathode, and an organic light-emitting layer located between the anode and the cathode. The anode of the light-emitting element can be electrically connected to the corresponding pixel circuit. However, this embodiment is not limited thereto.

[0140] In some examples, the shape of the light-emitting element may be rectangular, diamond-shaped, pentagonal, or hexagonal. When a pixel unit includes three sub-pixels, the light-emitting elements of the three sub-pixels can be arranged in a horizontal side-by-side, vertical side-by-side, or triangular pattern. When a pixel unit includes four sub-pixels, the light-emitting elements of the four sub-pixels can be arranged in a horizontal side-by-side, vertical side-by-side, or square pattern. However, this embodiment is not limited thereto.

[0141] Figure 2 is an equivalent circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure. The pixel circuit of this example is described by taking an 8T1C structure as an example. In some examples, as Figure 2 shown, the pixel circuit of this example may include eight transistors (i.e., a first transistor T1 to an eighth transistor T8) and a storage capacitor Cst. The first transistor T1 may also be referred to as a first reset transistor, the second transistor T2 may also be referred to as a threshold compensation transistor, the third transistor T3 may also be referred to as a driving transistor, the fourth transistor T4 may also be referred to as a data writing transistor, the fifth transistor T5 may also be referred to as a first light-emitting control transistor, the sixth transistor T6 may also be referred to as a second light-emitting control transistor, the seventh transistor T7 may also be referred to as a second reset transistor, and the eighth transistor T8 may also be referred to as a third reset transistor. The light-emitting element EL may include an anode, a cathode, and an organic light-emitting layer provided between the anode and the cathode.

[0142] In some examples, the first transistor T1, the third transistor T3 to the eighth transistor T8 may be of the first type of transistor. For example, they may be P-type transistors. The second transistor T2 may be of the second type of transistor. For example, it may be an N-type transistor. However, this embodiment is not limited thereto. For example, multiple transistors of the pixel circuit may all be P-type transistors, or may all be N-type transistors. Using transistors of the same type in the pixel circuit can simplify the process flow, reduce the process difficulty of the display substrate, and improve the yield of the product.

[0143] In some examples, the first type of transistor of the pixel circuit (for example, including the first transistor T1, the third transistor T3 to the eighth transistor T8) may adopt a low-temperature polysilicon thin-film transistor, and the second type of transistor of the pixel circuit (for example, including the second transistor T2) may adopt an oxide thin-film transistor. The active layer of the low-temperature polysilicon thin-film transistor uses low-temperature polysilicon (LTPS, Low Temperature Poly-Silicon), and the active layer of the oxide thin-film transistor uses an oxide semiconductor (Oxide). The low-temperature polysilicon thin-film transistor has advantages such as high mobility and fast charging, and the oxide thin-film transistor has advantages such as low leakage current. Integrating the low-temperature polysilicon thin-film transistor and the oxide thin-film transistor on a display substrate to form a low-temperature polycrystalline oxide (LTPS+Oxide) display substrate can utilize the advantages of both, can achieve low-frequency driving, can reduce power consumption, and can improve the display quality.

[0144] In some examples, as Figure 2 shown, the pixel circuit may be electrically connected to the first scan line GL1, the second scan line GL2, the data line DL, the first power supply line VDD, the second power supply line VSS, the emission control line EML, the first initial signal line INIT1, the second initial signal line INIT2, the third initial signal line INIT3, the first reset control line RST1, and the second reset control line RST2. The first power supply line VDD may be configured to provide a constant first voltage signal Vdd to the pixel circuit. The second power supply line VSS may be configured to provide a constant second voltage signal Vss to the pixel circuit, and the first voltage signal Vdd may be greater than the second voltage signal Vss. The first scan line GL1 may be configured to provide a first scan signal SCAN1 to the pixel circuit. The second scan line GL2 may be configured to provide a second scan signal SCAN2 to the pixel circuit. The data line DL may be configured to provide a data signal to the pixel circuit. The emission control line EML may be configured to provide an emission control signal EM to the pixel circuit. The first reset control line RST1 may be configured to provide a first reset control signal RESET1 to the pixel circuit. The second reset control line may be configured to provide a second reset control signal RESET2 to the pixel circuit.

[0145] In some examples, such as Figure 2 shown, the gate of the third transistor T3 is electrically connected to the first node N1, the first pole of the third transistor T3 is electrically connected to the second node N2, and the second pole of the third transistor T3 is electrically connected to the third node N3. The gate of the fourth transistor T4 is electrically connected to the first scan line GL1, the first pole of the fourth transistor T4 is electrically connected to the data line DL, and the second pole of the fourth transistor T4 is electrically connected to the second node N2. The gate of the second transistor T2 is electrically connected to the second scan line GL2, the second pole of the second transistor T2 is electrically connected to the first node N1, and the first pole of the second transistor T2 is electrically connected to the third node N3. The gate of the fifth transistor T5 is electrically connected to the emission control line EML, the first pole of the fifth transistor T5 is electrically connected to the first power supply line VDD, and the second pole of the fifth transistor T5 is electrically connected to the second node N2. The gate of the sixth transistor T6 is electrically connected to the emission control line EML, the first pole of the sixth transistor T6 is electrically connected to the third node N3, and the second pole of the sixth transistor T6 is electrically connected to the fourth node N4. The gate of the first transistor T1 is electrically connected to the first reset control line RST1, the first pole of the first transistor T1 is electrically connected to the first initial signal line INIT1, and the second pole of the first transistor T1 is electrically connected to the third node N3. The first transistor T1 can be configured to reset the third node N3. The gate of the seventh transistor T7 is electrically connected to the second reset control line RST2, the first pole of the seventh transistor T7 is electrically connected to the second initial signal line INIT2, and the second pole of the seventh transistor T7 is electrically connected to the fourth node N4. The seventh transistor T7 can be configured to reset the fourth node N4. The gate of the eighth transistor T8 is electrically connected to the second reset control line RST2, the first pole of the eighth transistor T8 is electrically connected to the third initial signal line INIT3, and the second pole of the eighth transistor T8 is electrically connected to the second node N2. The eighth transistor T8 can be configured to reset the second node N2. The first electrode of the storage capacitor Cst is electrically connected to the first node N1, and the second electrode of the storage capacitor Cst is electrically connected to the first power supply line VDD. The anode of the light-emitting element EL can be electrically connected to the fourth node N4, and the cathode of the light-emitting element EL can be electrically connected to the second power supply line VSS.

[0146] In this example, the first node N1 is the connection point of the storage capacitor Cst, the second transistor T2, and the third transistor T3. The second node N2 is the connection point of the fifth transistor T5, the fourth transistor T4, the eighth transistor T8, and the third transistor T3. The third node N3 is the connection point of the first transistor T1, the third transistor T3, the second transistor T2, and the sixth transistor T6. The fourth node N4 is the connection point of the sixth transistor T6, the seventh transistor T7, and the light-emitting element EL.

[0147] Figure 3 For Figure 2The operating timing diagram of the provided pixel circuit is as follows. Refer to Figure 3 for Figure 2 the operating process of the pixel circuit shown. Among them, the first transistor T1, the third transistor T3 to the eighth transistor T8 of the pixel circuit are P-type transistors, and the second transistor T2 is an N-type transistor.

[0148] In some examples, such as Figure 2 and Figure 3 shown, during one frame display period, the operating process of the pixel circuit can at least include: a first stage S11, a second stage S12, a third stage S13, and a fourth stage S14.

[0149] The first stage S11 is called the first reset stage. The second reset control signal RESET2 provided by the second reset control line RST2 is a low-level signal, turning on the seventh transistor T7 and the eighth transistor T8; the second scan signal SCAN2 provided by the second scan line GL2 is a high-level signal, turning on the second transistor T2. When the eighth transistor T8 is turned on, the third initial signal provided by the third initial signal line INIT3 is provided to the second node N2. When the seventh transistor T7 is turned on, the second initial signal provided by the second initial signal line INIT2 is provided to the fourth node N4 to initialize the fourth node N4. The first scan signal SCAN1 provided by the first scan line GL1 is a high-level signal, the first reset control signal RESET1 provided by the first reset control line RST1 is a high-level signal, and the emission control signal EM provided by the emission control line EML is a high-level signal, turning off the fourth transistor T4, the first transistor T1, the fifth transistor T5, and the sixth transistor T6. The light-emitting element EL does not emit light in this stage.

[0150] The second stage S12 is called the second reset stage. The first reset control signal RESET1 provided by the first reset control line RST1 is a low-level signal, turning on the first transistor T1; the second scan signal SCAN2 provided by the second scan line GL2 is a high-level signal, turning on the second transistor T2. When the first transistor T1 and the second transistor T2 are turned on, the first initial signal provided by the first initial signal line INIT1 is provided to the first node N1 to initialize the first node N1. The second reset control signal RESET2 provided by the second reset control line RST2 is a high-level signal, the first scan signal SCAN1 provided by the first scan line GL1 is a high-level signal, and the emission control signal EM provided by the emission control line EML is a high-level signal, turning off the seventh transistor T7, the eighth transistor T8, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6. The light-emitting element EL does not emit light in this stage.

[0151] The third stage S13 is called the data writing stage or the threshold compensation stage. The first scan signal SCAN1 provided by the first scan line GL1 is a low-level signal, and the fourth transistor T4 is turned on; the second scan signal SCAN2 provided by the second scan line GL2 is a high-level signal, and the second transistor T2 is turned on. At this stage, the first electrode of the storage capacitor Cst is at a low level, and the third transistor T3 is turned on. The second transistor T2, the fourth transistor T4, and the third transistor T3 are turned on, so that the data voltage Vdata output by the data line DL is provided to the first node N1 through the second node N2, the turned-on third transistor T3, the third node N3, and the turned-on second transistor T2, and the difference between the data voltage Vdata output by the data line DL and the threshold voltage of the third transistor T3 is charged into the storage capacitor Cst. The voltage of the first electrode (i.e., the first node N1) of the storage capacitor Cst is Vdata - |Vth|, where Vdata is the data voltage output by the data line DL, and Vth is the threshold voltage of the third transistor T3. The first reset control signal RESET1 provided by the first reset control line RST1 is a high-level signal, the second reset control signal RESET2 provided by the second reset control line RST2 is a high-level signal, and the emission control signal EM provided by the emission control line EML is a high-level signal, so that the first transistor T1, the seventh transistor T7, the eighth transistor T8, the fifth transistor T5, and the sixth transistor T6 are turned off.

[0152] In the fourth stage S14, the emission control signal EM provided by the emission control line EML can be switched from a high-level signal to a low-level signal, so that the fifth transistor T5 and the sixth transistor T6 are turned on. The second scan signal SCAN2 provided by the second scan line GL2 is a low-level signal, so that the second transistor T2 is turned off. The first scan signal SCAN1 provided by the first scan line GL1, the first reset control signal RESET1 provided by the first reset control line RST1, and the second reset control signal RESET2 provided by the second reset control line RST2 are high-level signals, so that the fourth transistor T4, the first transistor T1, the seventh transistor T7, and the eighth transistor T8 are turned off. The first voltage signal Vdd output by the first power supply line VDD can provide a driving voltage to the anode of the light-emitting element EL through the turned-on fifth transistor T5, the third transistor T3, and the sixth transistor T6, driving the light-emitting element EL to emit light.

[0153] During the driving process of the pixel circuit, the driving current flowing through the third transistor T3 is determined by the voltage difference between its gate and the first pole. Since the voltage of the first node N1 is Vdata - |Vth|, the driving current of the third transistor T3 is:

[0154] I = K × (Vgs - Vth) 2 = K × [(Vdd - Vdata + |Vth|) - Vth]2 = K × [Vdd - Vdata] 2 ;

[0155] Wherein, I is the driving current flowing through the third transistor T3, which is also the driving current for driving the light-emitting element, K is a constant, Vgs is the voltage difference between the gate and the first pole of the third transistor T3, Vth is the threshold voltage of the third transistor T3, Vdata is the data voltage output by the data line DL, and Vdd is the first voltage signal output by the first power supply line VDD.

[0156] It can be seen from the above formula that the current flowing through the light-emitting element has nothing to do with the threshold voltage of the third transistor T3. Therefore, the pixel circuit of this embodiment can better compensate for the threshold voltage of the third transistor T3. Moreover, the pixel circuit provided in this embodiment can improve the display defect caused by low frequency and improve the display effect of the light-emitting element.

[0157] In some examples, the data voltage ranges (Data Range) required for sub-pixels emitting different colors of light are different. Moreover, according to the above calculation formula of the driving current, the driving current of the sub-pixel is related to the data voltage and the first voltage signal. Therefore, the requirements for the first voltage signal of sub-pixels emitting different colors of light (such as including red sub-pixels, blue sub-pixels, and green sub-pixels) are different. This embodiment can group-design the first voltage signal to provide the first voltage signal that meets the actual requirements for sub-pixels emitting different colors of light respectively, so as to achieve the purpose of saving power.

[0158] In some examples, as Figure 1 shown, the first border area B1 may include: a second fan-out area B11, a bending area B12, a first fan-out area B13, a second signal access area B14, and a first signal access area B15 arranged in sequence along the direction away from the display area AA. The second fan-out area B11 may communicate with the second border area B2 and be located on one side of the display area AA. The bending area B12 may communicate with the second fan-out area B11 and the first fan-out area B13 and be located on the side of the second fan-out area B11 away from the display area AA. The bending area B12 may bend the first fan-out area B13, the first signal access area B15, and the second signal access area B14 to the back of the display area AA. The bending area B12 may include multiple bending connection lines to realize the connection between the signal traces transmitting the same signal in the second fan-out area B11 and the first fan-out area B13. The first fan-out area B13 may be located on the side of the bending area B12 away from the display area AA.

[0159] In some examples, as Figure 1As shown, the second signal access area B14 may be located on a side of the first fan-out area B13 away from the display area AA. The second signal access area B14 may be configured to set a driving chip (IC, Integrated Circuit). For example, the driving chip set in the second signal access area B14 may be a touch and display driver integration (TDDI) chip. The second signal access area B14 may also be referred to as a driving chip setting area. The driving chip may be configured to generate data signals required for driving sub-pixels.

[0160] In some examples, as Figure 1 shown, the first signal access area B15 may be located on a side of the second signal access area B14 away from the display area AA. The first signal access area B15 may be provided with a plurality of contact pads, and the plurality of contact pads may be configured to bind a flexible printed circuit (FPC), such that a plurality of signal lines (such as a power line, a control signal line, etc.) are connected to an external control device through the plurality of contact pads. The first signal access area B15 may also be referred to as a circuit binding area.

[0161] Figure 4 This is a schematic diagram of the transmission of the first voltage signal according to at least one embodiment of the present disclosure. In some examples, the display area AA may include a plurality of sub-pixels and a plurality of first power lines. The plurality of sub-pixels in the display area AA may be divided into N sub-pixel groups, and each sub-pixel group may include a plurality of sub-pixels that emit light of the same color. Different sub-pixel groups may be configured to emit light of different colors. In this example, it is illustrated by taking the plurality of sub-pixels in the display area AA being divided into three sub-pixel groups as an example. The display area AA may include: a first sub-pixel group P1, a second sub-pixel group P2, and a third sub-pixel group P3. The first sub-pixel group P1 may include a plurality of sub-pixels PX1 that emit a first color of light, the second sub-pixel group P2 may include a plurality of sub-pixels PX2 that emit a second color of light, and the third sub-pixel group P3 may include a plurality of sub-pixels PX3 that emit a third color of light. For example, the first color of light may be blue light, the second color of light may be red light, and the third color of light may be green light; in other words, the first sub-pixel group P1 may be a blue sub-pixel group, the second sub-pixel group P2 may be a red sub-pixel group, and the third sub-pixel group P3 may be a green sub-pixel group. This embodiment is not limited thereto.

[0162] In some examples, a sub-pixel may include: a pixel circuit and a connected light-emitting element. Figure 4 In, the pixel circuit of the sub-pixels in the display area AA is used as an example for illustration, and the light-emitting elements of the sub-pixels are omitted. As Figure 4As shown, multiple pixel circuits in the display area AA can be arranged in an array of multiple rows and multiple columns. One row of pixel circuits can include multiple pixel circuits arranged along the first direction X, and one column of pixel circuits can include multiple pixel circuits arranged along the second direction Y. The first sub-pixel group P1 can include multiple columns of pixel circuits, and each column of pixel circuits can include multiple pixel circuits PX1-1; the second sub-pixel group P2 can include multiple columns of pixel circuits, and each column of pixel circuits can include multiple pixel circuits PX2-1; the third sub-pixel group P3 can include multiple columns of pixel circuits, and each column of pixel circuits can include multiple pixel circuits PX3-1.

[0163] In some examples, as Figure 4 shown, multiple first power supply lines in the display area AA can include: multiple first power supply lines VDD1, multiple first power supply lines VDD2, and multiple first power supply lines VDD3. The first power supply line VDD1 can be configured to transmit the first voltage signal Vdd1, the first power supply line VDD2 can be configured to transmit the first voltage signal Vdd2, and the first power supply line VDD3 can be configured to transmit the first voltage signal Vdd3. The first voltage signals Vdd1, Vdd2, and Vdd3 can be first voltage signals with different voltage values.

[0164] In some examples, as Figure 4 shown, each column of pixel circuits can be electrically connected to one first power supply line and is configured to receive the first voltage signal. One column of pixel circuits PX1-1 in the first sub-pixel group P1 can be electrically connected to one first power supply line VDD1 and is configured to receive the first voltage signal Vdd1; one column of pixel circuits PX2-1 in the second sub-pixel group P2 can be electrically connected to one first power supply line VDD2 and is configured to receive the first voltage signal Vdd2; one column of pixel circuits PX3-1 in the third sub-pixel group P3 can be electrically connected to one first power supply line VDD3 and is configured to receive the first voltage signal Vdd3. For example, the first sub-pixel group P1 includes blue sub-pixels, the second sub-pixel group P2 includes red sub-pixels, and the third sub-pixel group P3 includes green sub-pixels; the first voltage signal Vdd1 provided to the first sub-pixel group P1 can be greater than the first voltage signal Vdd2 provided to the second sub-pixel group P2, and the first voltage signal Vdd2 provided to the second sub-pixel group P2 can be greater than the first voltage signal Vdd3 provided to the third sub-pixel group P3. In this example, since the blue sub-pixels require a larger first voltage signal, by providing the first voltage signals that meet the respective requirements for the blue sub-pixels, red sub-pixels, and green sub-pixels respectively, power consumption loss can be avoided, thereby achieving the purpose of saving power.

[0165] In some examples, as Figure 4As shown, the first border region B1 may include M first voltage supply groups, such as the first first voltage supply group 11, the second first voltage supply group 12, and the third first voltage supply group 13. Each first voltage supply group may be configured to provide a corresponding first voltage signal to at least one sub-pixel group. In this example, the first voltage supply group 11 may be configured to provide the first voltage signal Vdd1 to the first sub-pixel group, the first voltage supply group 12 may be configured to provide the first voltage signal Vdd2 to the second sub-pixel group, and the first voltage supply group 13 may be configured to provide the first voltage signal Vdd3 to the third sub-pixel group.

[0166] In some examples, as Figure 4 shown, the first voltage supply group 11 may include: a second power supply line 111 located in the second fan-out region B11, a first power supply line 112 located in the first fan-out region B13, a first power supply bent line 113 located in the bending region B12, and first voltage contact pads 114a and 114b located in the first signal access region B15. The first voltage supply group 12 may include: a second power supply line 121 located in the second fan-out region B11, a first power supply line 122 located in the first fan-out region B13, a first power supply bent line 123 located in the bending region B12, and first voltage contact pads 124a and 124b located in the first signal access region B15. The first voltage supply group 13 may include: a second power supply line 131 located in the second fan-out region B11, a first power supply line 132 located in the first fan-out region B13, a first power supply bent line 133 located in the bending region B12, and first voltage contact pads 134a and 134b located in the first signal access region B15.

[0167] In some examples, as Figure 4 shown, the second power supply lines 111, 121, and 131 located in the second fan-out region B11 may be arranged in sequence along the opposite direction of the second direction Y. The second power supply lines 111, 121, and 131 may be at least traces extending along the first direction X. The second power supply lines may be connected to the first power supply line through first-type voltage transfer electrodes. For example, the first-type voltage transfer electrodes may include: a first voltage transfer electrode 141, a second voltage transfer electrode 142, and a third voltage transfer electrode 143. Among them, the second power supply line 111 may be connected to the first power supply line VDD1 through the first voltage transfer electrode 141, the second power supply line 121 may be connected to the first power supply line VDD2 through the second voltage transfer electrode 142, and the second power supply line 131 may be connected to the first power supply line VDD3 through the third voltage transfer electrode 143.

[0168] In some examples, the second power supply lines 111, 121, and 131 may be of the same layer structure, the first voltage transfer electrodes 141, the second voltage transfer electrodes 142, and the third voltage transfer electrodes 143 may be of the same layer structure, and the first power supply lines VDD1, VDD2, and VDD3 may be of the same layer structure. For example, the first power supply lines VDD1, VDD2, and VDD3 may be located on a side of the first voltage transfer electrodes 141, the second voltage transfer electrodes 142, and the third voltage transfer electrodes 143 away from the substrate, and the second power supply lines 111, 121, and 131 may be located on a side of the first voltage transfer electrodes 141, the second voltage transfer electrodes 142, and the third voltage transfer electrodes 143 away from the substrate. The first power supply lines VDD1, VDD2, and VDD3 may be located on a side of the second power supply lines 111, 121, and 131 away from the substrate. This embodiment does not limit this.

[0169] In some examples, as Figure 4 shown, the first power supply bent lines 113, 123, and 133 located in the bending region B12 may be traces extending at least along the second direction Y. The first power supply bent lines 113, 123, and 133 may be of the same layer structure. The first power supply bent line 113 may connect the second power supply line 111 and the first power supply line 112, the first power supply bent line 123 may connect the second power supply line 121 and the first power supply line 122, and the first power supply bent line 133 may connect the second power supply line 131 and the first power supply line 132. For example, the first power supply bent line may be connected to the corresponding second power supply line through the second type of voltage transfer electrode, and the first power supply bent line may be directly connected to the first power supply line. However, this embodiment does not limit this. In some other examples, the first power supply bent line may be directly connected to both the first power supply line and the second power supply line.

[0170] In some examples, as Figure 4 shown, the first power supply lines 112, 122, and 132 located in the first fan-out region B13 may be arranged in sequence along the opposite direction of the second direction Y. Two ends of the first power supply line 112 may be respectively connected to the first voltage contact pads 114a and 114b in the first signal access region B15. Two ends of the first power supply line 122 may be respectively connected to the first voltage contact pads 124a and 124b in the first signal access region B15. Two ends of the first power supply line 132 may be respectively connected to the first voltage contact pads 134a and 134b in the first signal access region B15. The first voltage contact pads 114a, 124a, and 134a may be arranged adjacent to each other, and the first voltage contact pads 114b, 124b, and 124b may be arranged adjacent to each other.

[0171] In this example, three first voltage power supply groups are set in the first border area to provide three different first voltage signals, which can meet the different requirements of three sub-pixel groups that emit different color lights in the display area for the first voltage signal, thereby achieving the purpose of saving the power consumption of the first voltage signal.

[0172] Figure 5 It is a wiring schematic diagram of the first border area of at least one embodiment of the present disclosure. Figure 5 It mainly shows three second power supply lines 111, 121, and 131 in the second fan-out area B11, multiple bent connection lines in the bent area B12, and part of the wiring in the first fan-out area B13 (such as including first power supply lines 112a and 112b, 122a and 122b, and 132a and 132b); moreover, in Figure 5 a whole schematic illustration is made for multiple adjacent wiring of the same type.

[0173] In some examples, as Figure 5 shown, the second fan-out area B11 may at least include: three second power supply lines 111, 121, and 131, a second voltage fan-out line (not shown in the figure), multiple data fan-out lines (not shown in the figure), multiple driving fan-out lines (not shown in the figure), and multiple touch fan-out lines (not shown in the figure). The second voltage fan-out line may be configured to transmit a second voltage signal. The multiple data fan-out lines may be connected to multiple data lines in the display area and are configured to transmit data signals. The multiple driving fan-out lines may be connected to a gate driving circuit provided in the second border area and are configured to transmit driving control signals (such as including a clock signal, a start signal, etc.). The multiple data fan-out lines may include multiple first data fan-out lines located in the first conductive layer and multiple second data fan-out lines located in the second conductive layer.

[0174] In some examples, as Figure 5 shown, the multiple bent connection lines in the bent area B12 may include: multiple data bent lines (such as including a first group of data bent lines 163a, a second group of data bent lines 163b, a third group of data bent lines 163c, a fourth group of data bent lines 163d, a fifth group of data bent lines 163e, and a sixth group of data bent lines 163f), multiple driving bent lines (such as including a first group of driving bent lines 173a, a second group of driving bent lines 173b), multiple touch bent lines (such as including a first group of touch bent lines 183a, a second group of touch bent lines 183b, a third group of touch bent lines 183c, and a fourth group of touch bent lines 183d), multiple first power supply bent lines (such as including first power supply bent lines 113a, 113b, 113c, and 113d, 123a, 123b, 123c, and 123d, 133a, 133b, and 133c), and multiple second power supply bent lines (such as including second power supply bent lines 153a, 153b, 153c, and 153d).

[0175] In some examples, such as Figure 5 shown, within the bending region B12, the first set of driving bending lines 173a, the second power supply bending lines 153a, the first set of touch bending lines 183a, the first set of data bending lines 163a, the second set of touch bending lines 183b, the second power supply bending lines 153b, the second set of data bending lines 163b, the first power supply bending lines 113a, 123a, and 133a, the third set of data bending lines 163c, the first power supply bending lines 113b, 123b, 133b, 123c, and 113c, the fourth set of data bending lines 163d, the first power supply bending lines 113c, 123d, and 113d, the fifth set of data bending lines 163c, the second power supply bending lines 153c, the third set of touch bending lines 183c, the sixth set of data bending lines 163f, the fourth set of touch bending lines 183d, the second power supply bending lines 153d, and the second set of driving bending lines 173b may be arranged in sequence along the first direction X.

[0176] In some examples, such as Figure 5As shown, the first fan-out region B13 may include: multiple first power supply lines (such as including two first power supply lines 112a and 112b, two first power supply lines 122a and 122b, and two first power supply lines 132a and 132b), two second voltage lead-out lines (such as including second voltage lead-out lines 151 and 152), multiple data lead-out lines (including a first group of data lead-out lines 161 and a second group of data lead-out lines 162), multiple driving lead-out lines (including a first group of driving lead-out lines 171 and a second group of driving lead-out lines 172), and multiple touch lead-out lines (including a first group of touch lead-out lines 181 and a second group of touch lead-out lines 182). The first group of driving lead-out lines 171 and the second group of driving lead-out lines 172 may be located on both sides of the multiple data lead-out lines in the first direction X. The first group of driving lead-out lines 171 may be connected to multiple driving fan-out lines in the second fan-out region B11 through a first group of driving bending lines 173a, and the second group of driving lead-out lines 172 may be connected to multiple driving fan-out lines in the second fan-out region B11 through a second group of driving bending lines 173b. The first group of touch lead-out lines 181 may be connected to multiple touch fan-out lines in the second fan-out region B11 through a first group of touch bending lines 183a and a second group of touch bending lines 183b. The second group of touch lead-out lines 182 may be connected to multiple touch fan-out lines in the second fan-out region B11 through a third group of touch bending lines 183c and a fourth group of touch bending lines 183d. The second voltage lead-out line 151 may be connected to the second voltage fan-out lines in the second fan-out region B11 through second voltage bending lines 153a and 153b, and the second voltage lead-out line 152 may be connected to the second voltage fan-out lines in the second fan-out region B11 through second voltage bending lines 153c and 153d. The second voltage lead-out lines 151 and 152 may be configured to transmit second voltage signals.

[0177] In some examples, the two first power supply lines 112a and 112b may be arranged approximately symmetrically about the midline of the first border region in the first direction X, the two first power supply lines 122a and 122b may be arranged approximately symmetrically about the midline of the first border region in the first direction X, and the two first power supply lines 132a and 132b may be arranged approximately symmetrically about the midline of the first border region in the first direction X. The two first power supply lines 132a and 132b may be an integrally connected structure.

[0178] In some examples, such as Figure 5As shown, the line widths of the line segments of multiple first power supply lines in the same extension direction can be substantially the same. For example, the line widths (i.e., the lengths in the second direction Y) of the line segments of the first power supply lines 112a, 112b, 122a, 122b, 132a, and 132a extending in the first direction X can be substantially the same; the line widths (i.e., the lengths in the first direction X) of the line segments of the first power supply lines 112a, 112b, 122a, 122b, 132a, and 132a extending in the second direction Y can be substantially the same.

[0179] In some examples, the first power supply line 112a can be connected to the second power supply line 111 through the first power supply bent lines 113a and 113b, and the first power supply line 112b can be connected to the second power supply line 111 through the first power supply bent lines 113c and 113d. The first power supply line 122a can be connected to the second power supply line 121 through the first power supply bent lines 123a and 123b, and the first power supply line 122b can be connected to the second power supply line 121 through the first power supply bent lines 123c and 123d. The first power supply line 132a can be connected to the second power supply line 131 through the first power supply bent lines 133a and 133b, and the first power supply line 132b can be connected to the second power supply line 131 through the first power supply bent lines 133b and 133c.

[0180] In some examples, as Figure 5 shown, the first signal access area B15 can include: a plurality of contact pads, such as including a first group of power contact pads 31a and a second group of power contact pads 31b, and a group of intermediate contact pads 32. The first group of power contact pads 31a and the second group of power contact pads 31b are located on opposite sides of the group of intermediate contact pads 32 in the first direction X. The first group of power contact pads 31a can include: a plurality of first voltage contact pads (such as including Figure 4 the first voltage contact pads 114a, 124a, and 134a shown) and at least one second voltage contact pad, and the second voltage contact pad can be located on one side of the plurality of first voltage contact pads in the opposite direction of the first direction X; the second group of power contact pads 21b can include: a plurality of first voltage contact pads (such as including Figure 4 the first voltage contact pads 114b, 124b, and 134b shown) and at least one second voltage contact pad, and the second voltage contact pad can be located on one side of the plurality of first voltage contact pads in the first direction X.

[0181] In some examples, as Figure 5As shown, the second signal access area B14 may include: a plurality of input contact pads 34 and a plurality of output contact pads 33. The plurality of input contact pads 34 may be located on a side of the plurality of output contact pads 33 away from the bending area B12. The plurality of input contact pads 34 may be connected to a group of intermediate contact pads 32 through a plurality of contact pad leads. The plurality of output contact pads 33 may be connected to at least a first group of data lead-out lines 161 and a second group of data lead-out lines 162.

[0182] Figure 6 is Figure 5 a partial enlarged schematic diagram of area C1 in the figure. Figure 6 It shows the junction position between the display area AA and the first border area B1, mainly showing two rows and eight columns (for example, from the j-th column to the j + 7-th column, where j can be an integer greater than 0) of pixel circuits in the display area AA and the partial light-emitting elements connected to the pixel circuits, as well as a partial area of the second fan-out area B11 in the first border area B1.

[0183] In some examples, as Figure 6 shown, a plurality of pixel circuits in the display area AA may be arranged in an array along a first direction X and a second direction Y. The plurality of light-emitting elements in the display area AA may include: a first light-emitting element PX1-2 that emits first-color light, a second light-emitting element PX2-2 that emits second-color light, a third light-emitting element PX3-2 that emits third-color light, and a fourth light-emitting element PX4-2. The first light-emitting element PX1-2 and the second light-emitting element PX2-2 may be arranged at intervals along the first direction X and the second direction Y. The third light-emitting element PX3-2 and the fourth light-emitting element PX4-2 may be arranged at intervals along the first direction X and the second direction Y. The first light-emitting element PX1-2 and the second light-emitting element PX2-2 may be arranged in different rows and different columns from the third light-emitting element PX3-2 and the fourth light-emitting element PX4-2. The pixel circuits connected to the plurality of first light-emitting elements PX1-2 may be arranged in the same column. The pixel circuits connected to the plurality of second light-emitting elements PX2-2 may be arranged in the same column. The pixel circuits connected to the plurality of third light-emitting elements PX3-2 and the pixel circuits connected to the plurality of fourth light-emitting elements PX4-3 may be arranged in the same column. For example, the pixel circuits in the j-th column may be connected to the third light-emitting element PX3-2 and the fourth light-emitting element PX4-3 that emit third-color light. The pixel circuits in the j + 1-th column may be connected to the first light-emitting element PX1-2. The pixel circuits in the j + 2-th column may be connected to the third light-emitting element and the fourth light-emitting element. The pixel circuits in the j + 3-th column may be connected to the second light-emitting element. The pixel circuits in the j + 4-th column may be connected to the third light-emitting element and the fourth light-emitting element. The pixel circuits in the j + 5-th column may be connected to the first light-emitting element. The pixel circuits in the j + 6-th column may be connected to the third light-emitting element and the fourth light-emitting element. The pixel circuits in the j + 7-th column may be connected to the second light-emitting element.

[0184] In some examples, the first color light may be blue light, the second color light may be red light, and the third color light may be green light; the first light-emitting element may be a blue light-emitting element, the second light-emitting element may be a red light-emitting element, and the third and fourth light-emitting elements may be green light-emitting elements. In this example, every four columns of pixel circuits may form a group, and the four columns of pixel circuits within a group may be sequentially connected to a green light-emitting element, a blue light-emitting element, a green light-emitting element, and a red light-emitting element. For example, the pixel circuits in the j-th column to the (j + 3)-th column form a group, and the pixel circuits in the (j + 4)-th column to the (j + 7)-th column form a group.

[0185] In some examples, the sub-pixel PX1 includes a first light-emitting element PX1-2, the sub-pixel PX2 includes a second light-emitting element PX2-2, the sub-pixel PX3 includes a third light-emitting element PX3-2, and the sub-pixel PX4 includes a fourth light-emitting element PX4-2. The sub-pixel PX1 belongs to the first sub-pixel group PX1, the sub-pixel PX2 belongs to the second sub-pixel group P2, and the sub-pixels PX3 and PX4 belong to the third sub-pixel group P3.

[0186] In some examples, in a direction perpendicular to the display substrate, the display substrate may include: a bottom shielding layer, a first semiconductor layer, a first conductive layer, a second conductive layer, a second semiconductor layer, a third conductive layer, a fourth conductive layer, a fifth conductive layer, and a sixth conductive layer disposed on a substrate. A first insulating layer may be disposed between the bottom shielding layer and the first semiconductor layer, a second insulating layer may be disposed between the first semiconductor layer and the first conductive layer, a third insulating layer may be disposed between the first conductive layer and the second conductive layer, a fourth insulating layer may be disposed between the second conductive layer and the second semiconductor layer, a fifth insulating layer may be disposed between the second semiconductor layer and the third conductive layer, a sixth insulating layer may be disposed between the third conductive layer and the fourth conductive layer, a seventh insulating layer and an eighth insulating layer may be disposed between the fourth conductive layer and the fifth conductive layer, a ninth insulating layer may be disposed between the fifth conductive layer and the sixth conductive layer, and a tenth insulating layer may be disposed on a side of the sixth conductive layer away from the substrate. In some examples, the first to seventh insulating layers may be inorganic insulating layers, and the eighth, ninth, and tenth insulating layers may be organic insulating layers. However, this embodiment is not limited thereto.

[0187] The film layer structure of the display substrate in this example will be illustrated below by showing the manufacturing process of the display substrate. The "patterning process" as mentioned in this disclosure, for metal materials, inorganic materials or transparent conductive materials, includes processes such as coating photoresist, mask exposure, development, etching, and photoresist stripping. For organic materials, it includes processes such as coating organic materials, mask exposure, and development. Deposition can be carried out by any one or more of sputtering, evaporation, and chemical vapor deposition. Coating can be carried out by any one or more of spraying, spin coating, and inkjet printing. Etching can be carried out by any one or more of dry etching and wet etching. This disclosure does not make any limitations. A "thin film" refers to a thin film made of a certain material on a substrate by using deposition, coating, or other processes. If the "thin film" does not require a patterning process during the entire manufacturing process, the "thin film" can also be referred to as a "layer". If the "thin film" requires a patterning process during the entire manufacturing process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern". The shape of A can refer to the shape of the orthographic projection of A on the substrate.

[0188] In some examples, the manufacturing process of the display substrate may include the following operations. In the following examples, the film layer of a pixel circuit in the display area (for example, the pixel circuit located in the j-th column of the last row) is taken as an example for illustration.

[0189] (1), Provide a substrate. In some examples, the substrate can be a rigid substrate or a flexible substrate. For example, the rigid substrate can be, but is not limited to, one or more of glass and quartz. The flexible substrate can be, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyether ether ketone, polystyrene, polycarbonate, polyaryl acid ester, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fiber. In some examples, the flexible substrate may include a stacked first flexible material layer, a first inorganic material layer, a second flexible material layer, and a second inorganic material layer. The materials of the first flexible material layer and the second flexible material layer can be materials such as polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer soft film. The materials of the first inorganic material layer and the second inorganic material layer can be materials such as silicon nitride (SiNy, y>0) or silicon oxide (SiOx, x>0), etc., for improving the water and oxygen resistance of the substrate.

[0190] (2), Form a bottom shielding layer. In some examples, deposit a shielding metal thin film on the substrate, and pattern the shielding metal thin film through a patterning process to form a bottom shielding layer provided on the substrate.

[0191] Figure 7 is Figure 6 A partial schematic diagram of the display substrate after forming the shielding layer. In some examples, as Figure 7As shown, the bottom shielding layer may include: a first bottom structure 411 located in the display area AA and a second bottom structure 412 located in the second fan-out area B11. The bottom shielding layer may be generally a mesh structure. The first bottom structure 411 and the second bottom structure 412 may be an integrally connected structure. The first bottom structure 411 may be generally a mesh structure, and the second bottom structure 412 may be generally a strip structure extending along the first direction X.

[0192] (3) Form a first semiconductor layer. In some examples, on the substrate on which the foregoing structure is formed, a first insulating film and a first semiconductor film are sequentially deposited, and the first semiconductor film is patterned through a patterning process to form a first insulating layer and a first semiconductor layer disposed on the first insulating layer. In some examples, the material of the first semiconductor layer may be amorphous silicon (a-Si), polycrystalline silicon (p-Si), hexathiophene, polythiophene, or the like.

[0193] Figure 8 is Figure 6 a partial schematic diagram of the display substrate after forming the first semiconductor layer. In some examples, as Figure 8 shown, the first semiconductor layer in the display area AA may at least include: active layers of a plurality of first-type transistors of a plurality of pixel circuits (for example, including the active layer T10 of the first transistor T1, the active layer T30 of the third transistor T3, the active layer T40 of the fourth transistor T4, the active layer T50 of the fifth transistor T5, the active layer T60 of the sixth transistor T6, the active layer T70 of the seventh transistor T7, and the active layer T80 of the eighth transistor T8).

[0194] In some examples, the active layer of each transistor may include: a first region, a second region, and a channel region located between the first region and the second region. Among them, the material of the first semiconductor layer may include, for example, polycrystalline silicon. The channel region may not be doped with impurities and has semiconductor characteristics. The first region and the second region may be doped regions on both sides of the channel region, doped with impurities, and thus have conductivity. The impurities may vary according to the type of transistor. In some examples, the doped regions of the active layer may be interpreted as the source electrode or the drain electrode of the transistor. The portion of the active layer between the transistors may be interpreted as a wiring doped with impurities, which can be used to electrically connect the transistors. This embodiment is not limited thereto.

[0195] In some examples, as Figure 8As shown, the active layer T10 of the first transistor T1 and the active layer T40 of the fourth transistor T4 of the pixel circuit may be located on one side of the active layer T30 of the third transistor T3 in the second direction Y. The active layer T50 of the fifth transistor T5, the active layer T60 of the sixth transistor T6, the active layer T70 of the seventh transistor T7, and the active layer T80 of the eighth transistor T8 may be located on the side opposite to the active layer T30 of the third transistor T3 in the second direction Y. The active layer T30 of the third transistor T3, the active layer T40 of the fourth transistor T4, the active layer T50 of the fifth transistor T5, the active layer T60 of the sixth transistor T6, and the active layer T70 of the eighth transistor T7 of a single pixel circuit may be an integrally connected structure. The first region of the active layer T30 of the third transistor T3 may simultaneously serve as the second region of the active layer T40 of the fourth transistor T4 and the second region of the active layer T50 of the fifth transistor T5. The second region of the active layer T30 of the third transistor T3 may simultaneously serve as the first region of the active layer T60 of the sixth transistor T6. The second region of the active layer T60 of the sixth transistor T6 may simultaneously serve as the second region of the active layer T70 of the seventh transistor T7.

[0196] In some examples, the shapes of the active layer T10 of the first transistor T1, the active layer T40 of the fourth transistor T4, and the active layer T70 of the seventh transistor T7 may be generally in the shape of an "I", the shape of the active layer T30 of the third transistor T3 may be generally in the shape of a "U", the shapes of the active layer T60 of the sixth transistor T6 and the active layer T80 of the eighth transistor T8 may be generally in the shape of an "L", and the shape of the active layer T50 of the fifth transistor T5 may be generally in the shape of an "F".

[0197] In some examples, as Figure 8 shown, the display area AA may include a plurality of pixel circuit groups, and each pixel circuit group may include two pixel circuits arranged adjacent to each other in the first direction X. Each pixel circuit group may be arranged approximately symmetrically with respect to the midline of the pixel circuit group in the first direction X. The active layers T80 of the eighth transistors of the two pixel circuits in each pixel circuit group may be an integrally connected structure.

[0198] In some examples, the orthographic projection of the first bottom structure 411 on the substrate may at least partially overlap with the orthographic projection of the active layer T30 of the third transistor T3 of the pixel circuit. For example, the orthographic projection of the first bottom structure 411 on the substrate may cover the orthographic projection of the channel region of the active layer T30 on the substrate. The first bottom structure 411 in this example may shield the channel region of the active layer T30 of the third transistor T3, reducing the influence of external light on the third transistor, thereby ensuring the performance of the third transistor.

[0199] (4) Form a first conductive layer. In some examples, on the substrate forming the aforementioned structure, a second insulating film and a first conductive film are sequentially deposited, and the first conductive film is patterned through a patterning process to form a second insulating layer and a first conductive layer disposed on the second insulating layer. In some examples, the first conductive layer may also be referred to as a first gate metal layer, and the second insulating layer may also be referred to as a first gate insulating layer.

[0200] Fig.9A is Figure 6 a partial schematic diagram of the display substrate after forming the first conductive layer in Fig. 9B is Fig.9A a schematic diagram of the first conductive layer in Fig.9A and Fig. 9B As shown in

[0201] In some examples, as shown in Fig.9A and Fig. 9B the first conductive layer in the display area AA may at least include: a first electrode (such as the first electrode Cst-1) of the storage capacitor of multiple pixel circuits, multiple first scan lines (such as including the first scan line GL1(m)), multiple first reset control lines (such as including the first reset control line RST1(m)), multiple second reset control lines (such as including the second reset control line RST2(m)), and multiple light emission control lines (such as including the light emission control line EML(m)).

[0202] In some examples, as shown in Fig.9A and Fig. 9B the first conductive layer in the second fan-out area B11 may at least include: multiple first data fan-out lines 401. The multiple first data fan-out lines 401 may be sequentially arranged along the first direction X and extend toward the bending area side.

[0203] (5), Form a second conductive layer. In some examples, on the substrate forming the aforementioned structure, a third insulating film and a second conductive film are sequentially deposited, and the second conductive film is patterned through a patterning process to form a third insulating layer and a second conductive layer disposed on the third insulating layer. In some examples, the second conductive layer may also be referred to as a second gate metal layer, and the third insulating layer may also be referred to as a second gate insulating layer.

[0204] Fig. 10A is Figure 6 a partial schematic view of the display substrate after forming the second conductive layer in Fig. 10B is Fig. 10A a schematic view of the second conductive layer in Fig. 10A and Fig. 10B shown, the second conductive layer in the display area AA may at least include: the second electrodes of the storage capacitors of multiple pixel circuits (such as the second electrode Cst-2), and multiple second scan assist lines (such as including the second scan assist line GL2a(m)). The second scan assist line GL2a(m) may be located on one side of the second electrode Cst-2 of the storage capacitor of the corresponding pixel circuit in the second direction Y.

[0205] In some examples, as Fig. 10A and Fig. 10B shown, the second conductive layer in the second fan-out area B11 may at least include: multiple second data fan-out lines 402. The multiple second data fan-out lines 402 may be arranged in sequence along the first direction X and extend toward the bending area side. The multiple second data fan-out lines 402 and the multiple first data fan-out lines 401 may be arranged at intervals along the first direction X, and the orthographic projections of the first data fan-out line 401 and the second data fan-out line 402 on the substrate may have no overlap.

[0206] (6), Form a second semiconductor layer. In some examples, on the substrate forming the aforementioned pattern, a fourth insulating film and a second semiconductor film are sequentially deposited, and the second semiconductor film is patterned through a patterning process to form a fourth insulating layer and a second semiconductor layer disposed on the fourth insulating layer. In some examples, the material of the second semiconductor layer may include indium gallium zinc oxide (IGZO, Indium Gallium Zinc Oxide). In some examples, the fourth insulating layer may also be referred to as a third gate insulating layer.

[0207] Fig.11 is Figure 6 a partial schematic view of the display substrate after forming the second semiconductor layer in Fig.11As shown, the second semiconductor layer of the display region AA may at least include: the active layers of the second-type transistors of multiple pixel circuits, for example, including the active layer T20 of the second transistor T2. The shape of the active layer T20 of the second transistor T2 may be generally L-shaped. The orthographic projection of the active layer T20 of the second transistor T2 on the substrate may be located between the active layer T10 of the first transistor T1 and the active layer T50 of the fifth transistor T5 in the second direction Y.

[0208] (7) Form the third conductive layer. In some examples, on the substrate on which the foregoing pattern is formed, a fifth insulating film and a third conductive film are sequentially deposited, and the third conductive film is patterned through a patterning process to form a fifth insulating layer and a third conductive layer disposed on the fifth insulating layer. In some examples, the third conductive layer may also be referred to as a third gate metal layer, and the fifth insulating layer may also be referred to as a fourth gate insulating layer.

[0209] Fig. 12A is Figure 6 a partial schematic diagram of the display substrate after forming the third conductive layer in Fig. 12B is Fig. 12A a schematic diagram of the third conductive layer in Fig. 12A and Fig. 12B As shown, the third conductive layer of the display region AA may at least include: multiple first initial signal lines (for example, including the first initial signal line INIT1(m)), multiple second initial signal lines (for example, including the second initial signal line INIT2(m)), multiple third initial signal lines (for example, including the third initial signal line INIT3(m)), and multiple second scan lines (such as including the second scan line GL2(m)).

[0210] In some examples, the first initial signal line INIT1(m), the second initial signal line INIT2(m), the third initial signal line INIT3(m), and the second scan line GL2(m) may be generally in a zigzag shape extending along the first direction X. The first initial signal line INIT1(m), the second scan line GL2(m), the second initial signal line INIT2(m), and the third initial signal line INIT3(m) may be arranged in sequence along the opposite direction of the second direction X. An invalid first initial signal line may also be provided between the second initial signal line INIT2(m) and the third initial signal line INIT3(m).

[0211] In some examples, the overlapping region between the second scan line GL2(m) and the active layer T20 of the second transistor T2 can serve as the gate of the second transistor T2. The overlapping region between the second scan assist line GL2a(m) and the active layer T20 of the second transistor T2 can serve as the bottom gate of the second transistor T2. The second scan assist line GL2a(m) and the second scan line GL2(m) can be connected in the second border region to transmit the same second scan signal. However, this embodiment is not limited thereto.

[0212] (8) Form a sixth insulating layer. In some examples, deposit a sixth insulating thin film on the substrate on which the foregoing pattern is formed, and pattern the sixth insulating thin film through a patterning process to form a sixth insulating layer. In some examples, the sixth insulating layer may also be referred to as an interlayer insulating layer. The sixth insulating layer may be provided with a plurality of vias.

[0213] Fig.13 For Figure 6 is a partial schematic diagram of the display substrate after forming the sixth insulating layer. In some examples, as Fig.13 shown, the plurality of vias formed in the sixth insulating layer of the display area AA may include: the first via V1 to the tenth via V10, the eleventh via V11, the twelfth via V12, the thirteenth via V13, the fourteenth via V14, and the fifteenth via V15 to the seventeenth via V17. The sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer, and the second insulating layer within the first via V1 to the tenth via V10 may be removed to expose a partial surface of the first semiconductor layer. The sixth insulating layer, the fifth insulating layer, the fourth insulating layer, and the third insulating layer within the eleventh via V11 may be removed to expose a partial surface of the first conductive layer. The sixth insulating layer, the fifth insulating layer, and the fourth insulating layer within the twelfth via V12 may be removed to expose a partial surface of the second conductive layer. The sixth insulating layer and the fifth insulating layer within the thirteenth via V13 and the fourteenth via V14 may be removed to expose a partial surface of the second semiconductor layer. The sixth insulating layer within the fifteenth via V15 to the seventeenth via V17 may be removed to expose a partial surface of the third conductive layer.

[0214] In some examples, as Fig.13As shown, the multiple vias formed in the sixth insulating layer of the second fan-out region B11 may include: multiple twenty-first vias V21, multiple twenty-second vias V22, and multiple twenty-third vias V23. The sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer, the second insulating layer, and the first insulating layer within the multiple twenty-first vias V21 may be removed to expose a partial surface of the bottom shielding layer. The sixth insulating layer, the fifth insulating layer, the fourth insulating layer, and the third insulating layer within the multiple twenty-second vias V22 may be removed to expose a partial surface of the first conductive layer. The sixth insulating layer, the fifth insulating layer, and the fourth insulating layer within the multiple twenty-third vias V23 may be removed to expose a partial surface of the second conductive layer.

[0215] (9) Form a fourth conductive layer. In some examples, a fourth conductive thin film is deposited on the substrate on which the foregoing pattern is formed, and the fourth conductive thin film is patterned through a patterning process to form a fourth conductive layer on the sixth insulating layer. In some examples, the fourth conductive layer may also be referred to as a first source-drain metal layer.

[0216] Fig.14A is Figure 6 a partial schematic diagram of the display substrate after the fourth conductive layer is formed in Fig. 14B is Fig.14A a schematic diagram of the fourth conductive layer in Fig.14A and Fig. 14B As shown, the fourth conductive layer in the display region AA may at least include: multiple pixel connection electrodes (for example, including a first pixel connection electrode 301 to a ninth pixel connection electrode 309), multiple initial transmission lines (for example, including a first initial transmission line 41, a second initial transmission line 42, and a third initial transmission line 43).

[0217] In some examples, the first pixel connection electrode 301 can be connected to the first region of the active layer T10 of the first transistor T1 through the first via V1, and can also be connected to the first initial signal line INIT1(m) through the fifteenth via V15. The second pixel connection electrode 302 can be connected to the second region of the active layer T10 of the first transistor T1 through the second via V2, can also be connected to the second region of the active layer T30 of the third transistor T3 through the fourth via V4, and can also be connected to the first region of the active layer T20 of the second transistor T2 through the fourteenth via V14. The second pixel connection electrode 302 can realize the electrical connection of the first transistor T1, the second transistor T2, the third transistor T3, and the sixth transistor T6, and the second pixel connection electrode 302 can serve as the third node N3 of the pixel circuit. The third pixel connection electrode 303 can be connected to the second region of the active layer T20 of the second transistor T2 through the thirteenth via V13, and can also be connected to the first electrode Cst-1 of the storage capacitor through the eleventh via V11. The third pixel connection electrode 303 can realize the electrical connection of the second transistor T2, the storage capacitor, and the third transistor T3, and can serve as the first node N1 of the pixel circuit. The fourth pixel connection electrode 304 can be connected to the first region of the active layer T40 of the fourth transistor T4 through the third via V3. The fifth pixel connection electrode 305 can be connected to the second electrode Cst-2 of the storage capacitor through the twelfth via V12, and can also be connected to the first region of the fifth active layer T50 of the fifth transistor T5 through the sixth via V6. The sixth pixel connection electrode 306 can be connected to the second region of the active layer T60 of the sixth transistor T6 through the seventh via V7. The seventh pixel connection electrode 307 can be connected to the third initial signal line INIT3(m) through the sixteenth via V16, and can also be connected to the first region of the active layer T80 of the eighth transistor T8 through the tenth via V10. The eighth pixel connection electrode 308 can be connected to the first region of the active layer T70 of the seventh transistor T7 through the eighth via V8, and can also be connected to the second initial signal line INIT2(m) through the seventeenth via V17. The ninth pixel connection electrode 309 can be connected to the second region of the active layer T80 of the eighth transistor T8 through the ninth via V9, and can also be connected to the active layer T50 of the fifth transistor T5 through the fifth via V5.

[0218] In some examples, the first initial transmission line 41, the second initial transmission line 42, and the third initial transmission line 43 may be strip-shaped extending along the second direction Y. The first initial transmission line 41 may be connected to the first initial signal line INIT1(m). For example, the first initial transmission line 41 and the adjacent two first pixel connection electrodes may be an integrally connected structure, so as to realize the connection with the first initial signal line INIT1(m). The second initial transmission line 41 extending along the second direction Y is connected to the first initial signal line extending along the first direction X, and a grid-like structure for transmitting the first initial signal may be formed in the display area AA, which is beneficial to the transmission stability and uniformity of the first initial signal. The second initial transmission line 42 extending along the second direction Y is connected to the second initial signal line extending along the first direction X, and a grid-like structure for transmitting the second initial signal may be formed in the display area AA, which is beneficial to the transmission stability and uniformity of the second initial signal. The third initial transmission line 43 extending along the second direction Y is connected to the third initial signal line (for example, the third initial signal line INIT3(m)) extending along the first direction X, and a grid-like structure for transmitting the third initial signal may be formed in the display area AA, which is beneficial to the transmission stability and uniformity of the third initial signal.

[0219] In some examples, the first initial transmission line 41 may be located between two adjacent pixel circuit groups, for example, between the pixel circuits in the (j + 3)-th column and the pixel circuits in the (j + 4)-th column; the second initial transmission line 42 may be located between two adjacent pixel circuit groups, for example, between the pixel circuits in the (j + 5)-th column and the pixel circuits in the (j + 6)-th column; the third initial transmission line 43 may be located between two adjacent pixel circuit groups, for example, between the pixel circuits in the (j + 1)-th column and the pixel circuits in the (j + 2)-th column.

[0220] In some examples, as Fig.14A and Fig. 14B shown, the fourth conductive layer of the second fan-out region B11 may at least include: a plurality of frame transfer electrodes (for example, including a first frame transfer electrode 311, a second frame transfer electrode 312, a third frame transfer electrode 313, a fourth frame transfer electrode 314, a fifth frame transfer electrode 315, and a sixth frame transfer electrode 316), a plurality of first-type voltage transfer electrodes (such as including a plurality of first voltage transfer electrodes 141, a plurality of second voltage transfer electrodes 142, and a plurality of third voltage transfer electrodes 143), and a plurality of auxiliary electrodes (such as including a first auxiliary electrode 361 and a second auxiliary electrode 362).

[0221] In some examples, multiple border transfer electrodes may be arranged along the first direction X and located on the side of the first-type voltage connection electrodes and the multiple auxiliary electrodes close to the display area AA. The first border transfer electrode 311 may be connected to a second data fan-out line 402 through two vertically arranged twenty-second vias V22. The second border transfer electrode 312 may be connected to a first data fan-out line 401 through two vertically arranged twenty-third vias V23. The fifth border transfer electrode 315 may be connected to a second data fan-out line 402, and the sixth border transfer electrode 316 may be connected to a first data fan-out line 401. The third border transfer electrode 313 may be connected to a second data fan-out line 402 located in the second conductive layer. The fourth border transfer electrode 314 may be connected to a first data fan-out line 401 located in the first conductive layer.

[0222] In some examples, the first voltage transfer electrode 141 may have a first main body portion and a first protruding portion, and the first main body portion and the first protruding portion are an integrally connected structure. The shape of the first main body portion may be generally rectangular, and the shape of the first protruding portion may be generally dumbbell-shaped extending along the second direction Y. The first main body portion may be located on the side of the first border transfer electrode 311, the second border transfer electrode 312, and the third border transfer electrode 313 away from the display area AA, and the first protruding portion may be located on one side of the third border transfer electrode 313 in the first direction X. The first protruding portion of the first voltage transfer electrode 141 may be connected to the second bottom structure 412 of the bottom shielding layer through the twenty-first via V21.

[0223] In some examples, the second voltage transfer electrode 142 may have a second main body portion and a second protruding portion. The second main body portion and the second protruding portion are an integrally connected structure. The shape of the second main body portion may be generally rectangular, and the shape of the second protruding portion may be generally strip-shaped extending along the second direction Y. The second protruding portion may be located on one side of the sixth border transfer electrode 316 in the first direction X. The second main body portion may be located on the side of the fourth border transfer electrode 314, the fifth border transfer electrode 315, and the sixth border transfer electrode 316 away from the display area AA.

[0224] In some examples, the third voltage transfer electrode 143 may have a third main body portion 143-1 and a plurality of third protruding portions 143-2. The third main body portion 143-1 and the plurality of third protruding portions 143-2 may be an integrally connected structure. The third main body portion 143-1 may be generally strip-shaped extending along the first direction X. The third protruding portions 143-2 may be generally strip-shaped extending along the second direction Y. The plurality of third protruding portions 143-2 may be located on a side of the third main body portion 143-1 close to the display area AA. The plurality of third protruding portions 143-2 and the third main body portion 143-1 may be connected to form a plurality of accommodating areas, and the first voltage transfer electrode 141 and the second voltage transfer electrode 142 may be arranged at intervals in the plurality of accommodating areas. In other words, a first voltage transfer electrode 141 or a second voltage transfer electrode 142 may be disposed between two adjacent third protruding portions 143-2. In the first direction X, the third protruding portions 143-2, the first voltage transfer electrode 141, the third protruding portions 143-2, and the second voltage transfer electrode 142 may be periodically arranged.

[0225] In some examples, the first auxiliary electrode 361 may be located on a side of the first voltage transfer electrode 141 away from the display area AA and on a side of the third main body portion 143-1 of the third voltage transfer electrode 143 close to the display area AA. The first auxiliary electrode 361 may be generally rectangular. The second auxiliary electrode 362 may be located on a side of the second main body portion of the second voltage transfer electrode 142 close to the display area AA. The second auxiliary electrode 362 may be generally rectangular. By providing the first auxiliary electrode 361 and the second auxiliary electrode 362 in this example, it is beneficial to ensure the uniformity of the film layer pattern.

[0226] (10) Form a seventh insulating layer and an eighth insulating layer. In some examples, a seventh insulating thin film is deposited on the substrate on which the foregoing pattern is formed, and the seventh insulating thin film is patterned through a patterning process to form a seventh insulating layer; subsequently, an eighth insulating thin film is coated, and the eighth insulating thin film is patterned through a patterning process to form an eighth insulating layer. In some examples, the seventh insulating layer may also be referred to as a passivation layer, and the eighth insulating layer may also be referred to as a first planarization layer.

[0227] Fig.15 For Figure 6 a partial schematic diagram of the display substrate after forming the eighth insulating layer. In some examples, as Fig.15 shown, the plurality of vias opened in the eighth insulating layer of the display area AA may include: a thirty-first via V31 to a thirty-third via V33. The seventh insulating layer and the eighth insulating layer in the thirty-first via V31 to the thirty-third via V33 may be removed to expose a partial surface of the fourth conductive layer.

[0228] In some examples, as Fig.15As shown, the multiple vias formed in the eighth insulating layer of the second fan-out region B11 may include: the thirty-fourth via V34 to the forty-seventh via V47. The seventh insulating layer and the eighth insulating layer within the thirty-fourth via V34 to the forty-seventh via V47 may be removed to expose a partial surface of the fourth conductive layer.

[0229] (11) Form the fifth conductive layer. In some examples, a fifth conductive thin film is deposited on the substrate on which the foregoing pattern is formed, and the fifth conductive thin film is patterned through a patterning process to form the fifth conductive layer on the eighth insulating layer. In some examples, the fifth conductive layer may also be referred to as the second source-drain metal layer.

[0230] Fig.16A is Figure 6 a partial schematic diagram of the display substrate after forming the fifth conductive layer in Fig. 16B is Fig.16A a schematic diagram of the fifth conductive layer in Fig.16A and Fig. 16B As shown, the fifth conductive layer in the display region AA may at least include: a plurality of first anode connection electrodes 321, a plurality of data connection electrodes 323, a plurality of first power connection blocks 322, a plurality of first power horizontal transmission lines (such as including the first power horizontal transmission lines 34a and 34b), and a plurality of first data transfer lines (such as including the first data transfer lines 35a and 35b).

[0231] In some examples, the first anode connection electrode 321 may be connected to the sixth pixel connection electrode 306 through the thirty-first via V31 to achieve electrical connection to the second pole of the sixth transistor T6 in the pixel circuit. The data connection electrode 323 may be connected to the fourth pixel connection electrode 304 through the thirty-third via V33 to achieve electrical connection to the first pole of the fourth transistor T4 in the pixel circuit. The first power connection block 322 may be connected to the fifth pixel connection electrode 305 through the thirty-second via V32 to achieve electrical connection to the fifth transistor T5 in the pixel circuit and the second electrode of the storage capacitor.

[0232] In some examples, the shapes of the first power supply lateral transmission lines 34a and 34b can be generally in the shape of a broken line extending along the first direction X. The first power supply connection blocks 322 of the pixel circuits in the last row at columns j, j+2, j+4, and j+6 can be an integrally connected structure. The first power supply lateral transmission line 34a can be connected to the subsequently formed first power supply line VDD3 in the display area AA to form a mesh structure, and is configured to transmit the first voltage signal Vdd3, which can ensure the uniformity and stability of the transmission of the first voltage signal Vdd3. The first power supply connection lines of the pixel circuits in the penultimate row at columns j+1 and j+5 and the first power supply lateral transmission line 34b can be an integrally connected structure. The first power supply lateral transmission line 34b can be connected to the subsequently formed first power supply line VDD1 in the display area AA to form a mesh structure, and is configured to transmit the first voltage signal Vdd1, which can ensure the uniformity and stability of the transmission of the first voltage signal Vdd1. Similarly, the display area can also include a first power supply lateral transmission line connected to the first power supply line VDD2. The first power supply lateral transmission lines for transmitting different first voltage signals can be arranged at intervals in the second direction Y.

[0233] In some examples, the shapes of the first data transfer lines 35a and 35b can be generally in the shape of a broken line extending along the first direction X. By providing the first data transfer lines in this example, it can help to centrally fan out the data fan-out lines, which is beneficial for narrow border design.

[0234] In some examples, such as Fig.16A and Fig. 16B shown, the fifth conductive layer of the second fan-out area B11 can at least include: a plurality of border transfer electrodes (for example, including the seventh border transfer electrode 341, the eighth border transfer electrode 342, the ninth border transfer electrode 343, the tenth border transfer electrode 344, the eleventh border transfer electrode 345, and the twelfth border transfer electrode 346), a plurality of border power connection electrodes (such as including the first border power connection electrode 331, the second border power connection electrode 332, the third border power connection electrode 333, and the fourth border power connection electrode 334), and a plurality of second power supply lines (such as including the second power supply lines 111, 121, and 131).

[0235] In some examples, the shapes of the seventh frame transfer electrode 341, the eighth frame transfer electrode 342, the tenth frame transfer electrode 344, and the eleventh frame transfer electrode 345 can be approximately rectangular; the shapes of the ninth frame transfer electrode 343 and the twelfth frame transfer electrode 346 can be approximately L-shaped. The seventh frame transfer electrode 341 can be connected to the first frame transfer electrode 311 through the thirty-fifth via V35. The eighth frame transfer electrode 342 can be connected to the second frame transfer electrode 312 through the thirty-sixth via V36. The ninth frame transfer electrode 343 can be connected to the third frame transfer electrode 313 through the thirty-seventh via V37. The tenth frame transfer electrode 344 can be connected to the fourth frame transfer electrode 314 through the thirty-ninth via V39. The eleventh frame transfer electrode 345 can be connected to the fifth frame transfer electrode 315 through the fortieth via V40. The twelfth frame transfer electrode 346 can be connected to the sixth frame transfer electrode 316 through the forty-first via V41.

[0236] In some examples, the shapes of the first frame power connection electrode 331, the second frame power connection electrode 332, the third frame power connection electrode 333, and the fourth frame power connection electrode 334 can be approximately rectangular. The first frame power connection electrode 331 can be connected to a third protrusion 143-2 of the third voltage transfer electrode 143 through the thirty-fourth via V34. The second frame power connection electrode 332 can be connected to the first voltage transfer electrode 141 through the thirty-eighth via V38. The third frame power connection electrode 333 can be connected to the other third protrusion 143-2 of the third voltage transfer electrode 143. The fourth frame power connection electrode 334 can be connected to the second voltage transfer electrode 142 through the forty-second via V42.

[0237] In some examples, the second power supply lines 111, 121, and 131 can be approximately strip-shaped extending along the first direction X. The second power supply line 111 can be connected to the first main body of the first voltage transfer electrode 141 through a plurality of forty-third vias V43, and can also be connected to the second auxiliary electrode 362 through a plurality of forty-fourth vias V44. The second power supply line 121 can be connected to the first auxiliary electrode 361 through a plurality of forty-fifth vias V45, and can also be connected to the second main body of the second voltage transfer electrode 142 through a plurality of forty-sixth vias V46. The second power supply line 131 can be connected to the third main body of the third voltage transfer electrode 143 through a plurality of forty-seventh vias V47.

[0238] (12) Form the ninth insulating layer. In some examples, a ninth insulating film is coated on the substrate on which the foregoing pattern is formed, and the ninth insulating film is patterned through a patterning process to form the ninth insulating layer. In some examples, the ninth insulating layer can also be referred to as the second planarization layer.

[0239] Fig.17 For Figure 6 A partial schematic diagram of a display substrate after forming a ninth insulating layer. In some examples, as Fig.17 shown, the multiple vias formed in the ninth insulating layer of the display area AA may include: the fifty-first via V51 to the fifty-third via V53. The multiple vias formed in the ninth insulating layer of the second fan-out area B11 may include: the fifty-fifth via V55 to the sixty-fourth via V64. The ninth insulating layer within the fifty-first via V51 to the fifty-third via V53 and the fifty-fifth via V55 to the sixty-fourth via V64 may be removed to expose a partial surface of the fifth conductive layer.

[0240] (13) Form a sixth conductive layer. In some examples, on the substrate on which the foregoing pattern is formed, deposit a sixth conductive thin film, and pattern the sixth conductive thin film through a patterning process to form a sixth conductive layer on the ninth insulating layer. In some examples, the sixth conductive layer may also be referred to as a third source-drain metal layer.

[0241] Fig.18A For Figure 6 A partial schematic diagram of the display substrate after forming the sixth conductive layer. Fig.18B For Fig.18A A schematic diagram of the sixth conductive layer in Fig.18A And Fig.18B shown, the sixth conductive layer of the display area AA may at least include: multiple second anode connection electrodes 324, multiple data lines (for example, including data lines DL(j), DL(j + 1), DL(j + 2), DL(j + 3), DL(j + 4)), multiple first power lines (for example, including first power lines VDD1, VDD2, and VDD3), and multiple second data transfer lines (such as including second data transfer lines 36a and 36b).

[0242] In some examples, the second anode connection electrode 324 may be connected to the first anode connection electrode 321 through the fifty-first via V51 to electrically connect to the sixth transistor T6 of the pixel circuit. The multiple data lines may be in a zigzag shape extending along the second direction Y. For example, the data line DL(j) may be connected to the data connection electrode 323 through the fifty-third via V53 to electrically connect to the fourth transistor T4 of the pixel circuit. The second data transfer lines 36a and 36b may be in a straight line shape extending along the second direction Y. For example, the second data transfer line 36b may be connected to the first data transfer line 35a, and the second data transfer line 36a may be connected to the first data transfer line 35b.

[0243] In some examples, the first power supply lines VDD1, VDD2, and VDD3 can be substantially in a broken line shape extending along the second direction Y, and the first power supply lines VDD1, VDD2, and VDD3 can have non-uniform widths. The first power supply line VDD3 located in the j-th column can be electrically connected to the first power supply connection block 322 through the fifty-second via V52, enabling electrical connection to the first power supply lateral transmission line 34a, the fifth transistor T5 of the pixel circuit, and the storage capacitor.

[0244] In some examples, such as Fig.18A and Fig.18B shown, the sixth conductive layer of the second fan-out region B11 can at least include: the second sub-wire 512 of the second voltage fan-out line. The second voltage fan-out line can be a double-layer wire, for example, including a first sub-wire located in the fifth conductive layer and a second sub-wire 512 located in the sixth conductive layer. The second sub-wire 512 can have a plurality of first hollow portions, and the orthographic projection of the first hollow portions on the substrate can be substantially rectangular. In this example, by providing a plurality of first hollow portions in the second sub-wire 512, it is beneficial for the exhaust of the ninth insulating layer under the large-area metal block.

[0245] In some examples, the data line DL(j) connected to the pixel circuit in the j-th column can extend to the second fan-out region B11 and be connected to the seventh frame transfer electrode 341 through the fifty-ninth via V59. The data line DL(j + 1) connected to the pixel circuit in the (j + 1)-th column can extend to the second fan-out region B11 and be connected to the eighth frame transfer electrode 342 through the sixtieth via V60. The second data transfer line 36a located between the data lines DL(j) and DL(j + 1) can be connected to the ninth frame transfer electrode 343 through the sixty-first via V61. The data line DL(j + 2) connected to the pixel circuit in the (j + 2)-th column can extend to the second fan-out region B11 and be connected to the eleventh frame transfer electrode 345 through the sixty-third via V63. The data line DL(j + 3) connected to the pixel circuit in the (j + 3)-th column can extend to the second fan-out region B11 and be connected to the twelfth frame transfer electrode 346 through the sixty-fourth via V64. The second data transfer line 36b located between the data lines DL(j + 2) and DL(j + 3) can be connected to the tenth frame transfer electrode 344 through the sixty-second via V62. In this example, the data line and the second data transfer line can be connected to the first data fan-out line located in the first conductive layer or the second data fan-out line located in the second conductive layer through the frame transfer electrodes located in the fifth conductive layer and the fourth conductive layer.

[0246] In some examples, the first power supply line VDD3 connected to the pixel circuit of the j-th column can extend to the second fan-out region B11 and be connected to the first frame power supply connection electrode 331 through the fifty-fifth via V55, so as to be connected to a third protruding portion 143-2 of the third voltage transfer electrode 143. The first power supply line VDD1 connected to the pixel circuit of the (j + 1)-th column can extend to the second fan-out region B11 and be connected to the second frame power supply connection electrode 332 through the fifty-sixth via V56, so as to be connected to the first protruding portion of the first voltage transfer electrode 141. The first power supply line VDD3 connected to the pixel circuit of the (j + 2)-th column can extend to the second fan-out region B11 and be connected to the third frame power supply connection electrode 333 through the fifty-seventh via V57, so as to be connected to another third protruding portion 143-2 of the third voltage transfer electrode 143. The first power supply line VDD2 connected to the pixel circuit of the (j + 3)-th column can extend to the second fan-out region B11 and be connected to the fourth frame power supply connection electrode 333 through the fifty-eighth via V58, so as to be connected to the second protruding portion of the second voltage transfer electrode 142.

[0247] In some examples, the first power supply line VDD3 connected to the pixel circuit of the j-th column can be sequentially connected to the second power supply line 131 located in the fifth conductive layer through the first frame power supply connection electrode 331 located in the fifth conductive layer and the third voltage transfer electrode 143 located in the fourth conductive layer. The first power supply line VDD1 connected to the pixel circuit of the (j + 1)-th column can be sequentially connected to the second power supply line 111 located in the fifth conductive layer through the second frame power supply connection electrode 332 located in the fifth conductive layer and the first voltage transfer electrode 141 located in the fourth conductive layer. The first power supply line VDD3 connected to the pixel circuit of the (j + 2)-th column can be sequentially connected to the second power supply line 131 located in the fifth conductive layer through the third frame power supply connection electrode 333 located in the fifth conductive layer and the third voltage transfer electrode 143 located in the fourth conductive layer. The first power supply line VDD2 connected to the pixel circuit of the (j + 3)-th column can be sequentially connected to the second power supply line 121 located in the fifth conductive layer through the fourth frame power supply connection electrode 334 located in the fifth conductive layer and the second voltage transfer electrode 142 located in the fourth conductive layer.

[0248] (14) Form the tenth insulating layer and the anode layer. In some examples, a tenth insulating thin film is coated on the substrate on which the foregoing pattern is formed, and the tenth insulating thin film is patterned through a patterning process to form the tenth insulating layer, and the tenth insulating layer can be provided with a plurality of vias. Subsequently, an anode thin film is deposited, and the anode thin film is patterned through a patterning process to form the anode layer. In some examples, the tenth insulating layer can also be referred to as the third planarization layer.

[0249] Fig.19 For Figure 6Schematic diagram of the anode layer. In some examples, such as Fig.19 shown, the anode layer may include anodes of a plurality of light-emitting elements (for example, including anode 351 of the first light-emitting element PX1-2 in the first sub-pixel group P1, anode 352 of the second light-emitting element PX2-2 in the second sub-pixel group P2, anode 353 of the third light-emitting element PX3-2 in the third sub-pixel group P3, and anode 354 of the fourth light-emitting element PX4-2). The anode 353 of the third light-emitting element PX3-2 may be connected to the pixel circuit in the j-th column of the penultimate row through a via formed in the tenth insulating layer. The anode 354 of the fourth light-emitting element PX4-2 may be connected to the pixel circuit in the j-th column of the last row through a via formed in the tenth insulating layer. The anode 351 of the first light-emitting element PX1-2 may be connected to the pixel circuit in the (j + 1)-th column of the penultimate row. The anode 352 of the second light-emitting element PX2-2 may be connected to the pixel circuit in the (j - 1)-th column of the last row. In this example, the anodes of the first light-emitting element and the second light-emitting element may be connected to the corresponding pixel circuits by wire bonding. For example, the wire bonding may be an integral structure in which the connected anodes are interconnected.

[0250] In some examples, pixel circuits in the same column may be connected to light-emitting elements that emit light of the same color, so that different first power supply lines can provide a first voltage signal to light-emitting elements that emit light of different colors. For example, the j-th column pixel circuit is connected to the first power supply line VDD3 and is connected to a plurality of light-emitting elements that emit third-color light (for example, green light); the (j + 1)-th column pixel circuit is connected to the first power supply line VDD1 and is connected to a plurality of light-emitting elements that emit first-color light (for example, blue light); the (j + 2)-th column pixel circuit is connected to the first power supply line VDD3 and is connected to a plurality of light-emitting elements that emit third-color light (for example, green light); the (j + 3)-th column pixel circuit is connected to the first power supply line VDD2 and is connected to a plurality of light-emitting elements that emit second-color light (for example, red light).

[0251] In some examples, after forming the anode layer, a pixel definition layer, an organic light-emitting layer, and a cathode layer may be sequentially provided.

[0252] In some examples, the first conductive layer, the second conductive layer, the third conductive layer, the fourth conductive layer, the fifth conductive layer and the sixth conductive layer can be made of metal materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo), or alloy materials of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), and can be a single layer structure, or a multi-layer composite structure, such as Mo / Cu / Mo, etc. The first insulating layer, the second insulating layer, the third insulating layer, the fourth insulating layer, the fifth insulating layer, the sixth insulating layer and the seventh insulating layer can be made of any one or more of silicon oxide (SiOx, x>0), silicon nitride (SiNy, y>0) and silicon oxynitride (SiON), and can be a single layer, a multi-layer or a composite layer. The eighth insulating layer to the tenth insulating layer can be made of organic materials such as polyimide, acrylic or polyethylene terephthalate. However, this embodiment is not limited to this.

[0253] The structure of the display substrate of this embodiment and its preparation process are merely an exemplary description. In some examples, the corresponding structure can be changed and the patterning process can be increased or decreased according to actual needs. For example, the fifth conductive layer or the sixth conductive layer can be omitted. For another example, the bottom shielding layer can be omitted. The preparation process of this exemplary embodiment can be implemented using currently mature preparation equipment, can be well compatible with existing preparation processes, has simple process implementation, is easy to implement, has high production efficiency, low production cost, and high yield rate.

[0254] Fig. 20A , Fig.21A and Fig.22A for Figure 5 A partial enlarged schematic diagram of the middle area C2. Fig. 20A , Fig.21A and Fig.22A The structure of the fourth conductive layer and the fifth conductive layer in the region C2 is mainly shown. Fig. 20A The diagram mainly illustrates the transition area between the second power supply line 111 and the first power supply bending line 113a in the second fan-out area; Fig.21A It mainly illustrates the transition area between the second power supply line 121 and the first power supply bending line 123a in the second fan-out area; Fig.22A The diagram mainly illustrates a transition area between the second power supply line 131 and the first power supply bending line 133 a in the second fan-out area.

[0255] Fig. 20B for Fig. 20A Schematic diagram of the fourth conductive layer in . Fig. 20C for Fig. 20A Schematic diagram after the eighth insulating layer is formed. Fig.20D for Fig. 20A Schematic diagram of the fifth conductive layer in . Fig.21B for Fig.21A Schematic diagram of the fourth conductive layer in Fig. 21C is Fig.21A Schematic diagram after forming the eighth insulating layer in Fig.21D is Fig.21A Schematic diagram of the fifth conductive layer in Fig. 22B is Fig.22A Schematic diagram of the fourth conductive layer in Fig. 22C is Fig.22A Schematic diagram after forming the eighth insulating layer in Fig.22D is Fig.22A Schematic diagram of the fifth conductive layer in

[0256] In some examples, such as Fig. 20B , Fig.21B and Fig. 22B shown, the fourth conductive layer in the second fan-out region may at least include: a plurality of first-type voltage transfer electrodes (for example, including a first voltage transfer electrode 141, a second voltage transfer electrode 142, and a third voltage transfer electrode 143), a plurality of second-type voltage transfer electrodes (such as including a fourth voltage transfer electrode 144, a fifth voltage transfer electrode 145, and a sixth voltage transfer electrode 146), and a plurality of auxiliary connection electrodes (for example, including a first auxiliary connection electrode 147 and a second auxiliary connection electrode 148). The first-type voltage transfer electrodes in this example can achieve the connection between the first power supply line and the second power supply line, and the second-type voltage transfer electrodes can achieve the connection between the first power supply line, the second power supply line, and the first power supply bending line.

[0257] In some examples, the first voltage transfer electrode 141 can be connected to the first power supply line VDD1 in the display region, the second voltage transfer electrode 142 can be connected to the first power supply line VDD2 in the display region, and the third voltage transfer electrode 143 can be connected to the first power supply line VDD3 in the display region.

[0258] In some examples, the first auxiliary connection electrode 147 and the second auxiliary connection electrode 148 can be substantially strip-shaped extending along the second direction Y, and the length of the second auxiliary connection electrode 148 along the second direction Y can be greater than the length of the first auxiliary connection electrode 147 along the second direction Y. One first auxiliary connection electrode 147 can be connected to a first power supply line VDD2 in the display region, and one second auxiliary connection electrode 148 can be connected to a second power supply line VDD3 in the display region.

[0259] In some examples, such as Fig. 20BAs shown, the fourth voltage transfer electrode 144 may include a fourth main body portion 144-1, a plurality of fourth protrusions 144-2, and a plurality of fifth protrusions 144-3. The fourth main body portion 144-1, the plurality of fourth protrusions 144-2, and the plurality of fifth protrusions 144-3 may be an integrally connected structure. The fourth main body portion 144-1 may be generally rectangular, the fourth protrusions 144-2 may be generally L-shaped, and the fifth protrusions 144-3 may be generally rectangular. The fourth protrusions 144-2 and the fifth protrusions 144-3 may be located on a side of the fourth main body portion 144-1 close to the display area, and the fourth protrusions 144-2 and the fifth protrusions 144-3 may be spaced apart along the first direction X. A second auxiliary connection electrode 148 may be disposed between a fourth protrusion 144-2 and an adjacent fifth protrusion 144-3 in the first direction X, and a first auxiliary connection electrode 147 and a second auxiliary connection electrode 148 arranged along the first direction X may be disposed between a fifth protrusion 144-3 and an adjacent fourth protrusion 144-2 in the first direction X. The fourth protrusions 144-2 may be configured to be connected to the first power supply line VDD1 of the display area, and the fifth protrusions 144-3 may be configured not to be directly connected to the first power supply line.

[0260] In some examples, as Fig.21B As shown, the fifth voltage transfer electrode 145 may include a fifth main body portion 145-1, a plurality of sixth protrusions 145-2, and a plurality of seventh protrusions 145-3. The fifth main body portion 145-1, the plurality of sixth protrusions 145-2, and the plurality of seventh protrusions 145-3 may be an integrally connected structure. The fifth main body portion 145-1 may be generally rectangular, the sixth protrusions 145-2 may be generally L-shaped, and the seventh protrusions 145-3 may be generally rectangular. The sixth protrusions 145-2 and the seventh protrusions 145-3 may be located on a side of the fifth main body portion 145-1 close to the display area. A second auxiliary electrode 362 may be disposed on a side of the sixth protrusions 145-2 close to the display area, and a first voltage transfer electrode 141 may be disposed on a side of the seventh protrusions 145-3 close to the display area. The sixth protrusions 145-2 and the seventh protrusions 145-3 may be spaced apart along the first direction X, and a second auxiliary connection electrode 148 may be disposed between adjacent sixth protrusions 145-2 and seventh protrusions 145-3. One of the sixth protrusions 145-2 may be configured to be connected to a first power supply line VDD2 of the display area, and the seventh protrusions 145-3 may be configured not to be directly connected to the first power supply line.

[0261] In some examples, as Fig. 22BAs shown, the sixth voltage transfer electrode 146 may include a sixth main body portion 146-1 and a plurality of eighth protruding portions 146-2. The sixth main body portion 146-1 and the plurality of eighth protruding portions 146-2 may be an integrally connected structure. The shape of the sixth main body portion 146-1 may be generally rectangular, and the shape of the eighth protruding portion 146-2 may be generally strip-shaped extending along the second direction Y. The eighth protruding portion 146-2 may be located on the side of the sixth main body portion 146-1 close to the display area. Between two adjacent eighth protruding portions 146-2, a first voltage transfer electrode 141 and a first auxiliary electrode 361 arranged along the second direction Y may be provided, or a second voltage transfer electrode 142 and a second auxiliary electrode 362 arranged along the second direction Y may be provided.

[0262] In some examples, as Fig.20D , Fig.21D and Fig.22D shown, the fifth conductive layer in the first border area may at least include: second power supply lines 111, 121, and 131, first sub-traces 511 of the second voltage fan-out line, first power supply bending lines 113a, 123a, and 133a. The first power supply bending line 113a may extend from the bending area to the second fan-out area and be connected to the fourth voltage transfer electrode 144 in the second fan-out area. The first power supply bending line 123a may extend from the bending area to the second fan-out area and be connected to the fifth voltage transfer electrode 145 in the second fan-out area. The first power supply bending line 133a may extend from the bending area to the second fan-out area and be connected to the sixth voltage transfer electrode 146 in the second fan-out area.

[0263] In some examples, as Fig. 20C , Fig. 21C and Fig. 22C shown, the first border area may be provided with at least a first opening K1, a second opening K2, a third opening K3, and a first groove K4. The eighth insulating layer and the seventh insulating layer in the first opening K1, the second opening K2, and the third opening K3 may be removed to expose a part of the surface of the fourth conductive layer. The eighth insulating layer in the first groove K4 may be removed, and the seventh insulating layer may be retained.

[0264] In some examples, the second power supply lines 111, 121, and 131 may be generally straight lines extending along the first direction X. The second power supply lines 111, 121, and 131 may be arranged in sequence along the reverse direction of the second direction Y. The first sub-trace 511 of the second voltage fan-out line may be located on the side of the second power supply line 131 away from the display area. The orthographic projection of the first sub-trace 511 of the second voltage fan-out line on the substrate may cover the orthographic projection of the first groove K4 on the substrate. By retaining the seventh insulating layer in the first groove K4, insulation between the first sub-trace 511 of the second voltage fan-out line and the voltage transfer electrode can be achieved.

[0265] In some examples, the second power supply line 111 may be connected to the first voltage transfer electrode 141, the second auxiliary electrode 362, the fourth protrusions 144-2 and 144-3 of the fourth voltage transfer electrode 144. The second power supply line 121 may be connected to the second voltage transfer electrode 142, the first auxiliary electrode 361, the first auxiliary connection electrode 147, the sixth protrusions 145-2 and 145-3 of the fifth voltage transfer electrode 145. The second power supply line 131 may be connected to the third voltage transfer electrode 143, the second auxiliary connection electrode 148, and the sixth main body 146-1 of the sixth voltage transfer electrode 146.

[0266] In some examples, such as Fig. 20A and Fig.20D as shown, the first power supply bent line 113a may at least include: a first connection portion 113a-1, a bent portion 113a-2, and a second connection portion 113a-3 (as Fig.23A shown). The first connection portion 113a-1, the bent portion 113a-2, and the second connection portion 113a-3 may be an integrally connected structure. The shape of the first connection portion 113a-1 may be generally rectangular. The first connection portion 113a-1 may be located on a side of the first sub-wire 511 of the second voltage fan-out line away from the display area. The first connection portion 113a-1 may be connected to the fourth main body 144-1 of the fourth voltage transfer electrode 144 through the first opening K1. The bent portion 113a-2 may include a plurality of bent lines arranged in sequence along the first direction X. In this example, the fourth voltage transfer electrode 144 can achieve the electrical connection between the second power supply line 111 and the first power supply bent line 113a.

[0267] In some examples, such as Fig.21A and Fig.21D as shown, the first power supply bent line 123a may include: a first connection portion 123a-1, a bent portion 123a-2, and a second connection portion 123a-3 (as Fig.23A shown). The first connection portion 123a-1, the bent portion 123a-2, and the second connection portion 123a-3 may be an integrally connected structure. The shape of the first connection portion 123a-1 may be generally rectangular. The first connection portion 123a-1 may be located on a side of the first sub-wire 511 of the second voltage fan-out line away from the display area. The first connection portion 123a-1 may be connected to the fifth main body 145-1 of the fifth voltage transfer electrode 145 through the second opening K2. The bent portion 113a-2 may include a plurality of bent lines arranged in sequence along the first direction X. In this example, the fifth voltage transfer electrode 145 can achieve the electrical connection between the second power supply line 121 and the first power supply bent line 123a.

[0268] In some examples, such as Fig.22A and Fig.22D As shown, the first power supply bent line 133a may at least include: a first connection portion 133a-1, a bent portion 133a-2, and a second connection portion 133a-3 (as Fig.23A shown). The first connection portion 133a-1, the bent portion 133a-2, and the second connection portion 133a-3 may be an integrally connected structure. The shape of the first connection portion 133a-1 may be generally rectangular. The first connection portion 133a-1 may be located on a side of the first sub-wire 511 of the second voltage fan-out line away from the display area. The first connection portion 133a-1 may be connected to the sixth main body portion 146-1 of the sixth voltage transfer electrode 146 through the third opening K3. The bent portion 133a-2 may include a plurality of bent lines arranged in sequence along the first direction X. In this example, the second power supply line 131 and the first power supply bent line 133a can be electrically connected through the sixth voltage transfer electrode 146.

[0269] Regarding the connection manner between the first power supply line and the second power supply line in this example, reference may be made to the description of the foregoing embodiments, and thus it will not be elaborated herein.

[0270] Fig.23A is Figure 5 a partial enlarged schematic diagram of area C3 in Fig.23A which shows the structures of the fourth conductive layer, the fifth conductive layer, and the sixth conductive layer in area C3. Fig. 23B is Fig.23A a schematic diagram of the fourth conductive layer in Fig.23C is Fig.23A a schematic diagram after forming the eighth insulating layer in Fig.23D is Fig.23A a schematic diagram of the fifth conductive layer in Fig.23E is Fig.23A a schematic diagram after forming the ninth insulating layer in Fig.23F is Fig.23A a schematic diagram of the sixth conductive layer in

[0271] In some examples, such as FIG. 23A to FIG. 23FAs shown, the first power supply lines 112a, 122a, and 132a in the first fan-out region may be a three-layer routing structure. Each first power supply line may include: a first trace located in the fourth conductive layer, a second trace located in the fifth conductive layer, and a third trace located in the sixth conductive layer. For example, the first power supply line 112a may include: a first trace 112a-1 located in the fourth conductive layer, a second trace 112a-2 located in the fifth conductive layer, and a third trace 112a-3 located in the sixth conductive layer; the first power supply line 122a may include: a first trace 122a-1 located in the fourth conductive layer, a second trace 122a-2 located in the fifth conductive layer, and a third trace 122a-3 located in the sixth conductive layer; the first power supply line 132a may include: a first trace 132a-1 located in the fourth conductive layer, a second trace 132a-2 located in the fifth conductive layer, and a third trace 132a-3 located in the sixth conductive layer.

[0272] In some examples, as Fig.23C shown, the eighth insulating layer in the first fan-out region may be provided with a fifth opening K5, a sixth opening K6, and a seventh opening K7. The eighth insulating layer and the seventh insulating layer within the fifth opening K5, the sixth opening K6, and the seventh opening K7 may be removed to expose a partial surface of the fourth conductive layer. As Fig.23E shown, the ninth insulating layer in the first fan-out region may be provided with an eighth opening K8, a ninth opening K9, and a tenth opening K10. The ninth insulating layer within the eighth opening K8, the ninth opening K9, and the tenth opening K10 may be removed to expose a partial surface of the fifth conductive layer.

[0273] In some examples, as Figures 23A to 23F shown, the second connection portion 113a-3 of the first power supply bent line 113a may extend to the first fan-out region and be connected to the first power supply line 112a in the first fan-out region. The second connection portion 113a-3 located in the fifth conductive layer and the second trace 112a-2 of the first power supply line 112a may be an integrally connected structure. The second trace 112a-2 may be connected to the first trace 112a-1 located in the fourth conductive layer through the fifth opening K5. The third trace 112a-3 located in the sixth conductive layer may be connected to the second trace 112a-2 located in the fifth conductive layer through the eighth opening K8. The orthographic projection of the third trace 112a-3 on the substrate may partially overlap with the orthographic projections of the second connection portions 123a-3 of the first power supply bent line 123a and 133a-3 of the first power supply bent line 133a on the substrate.

[0274] In some examples, as Figures 23A to 23FAs shown, the second connection portion 123a-3 of the first power supply bent line 123a can extend to the first fan-out region and be connected to the first power supply line 122a in the first fan-out region. The second connection portion 123a-3 located in the fifth conductive layer and the second trace 122a-2 of the first power supply line 122a can be an integrally connected structure. The second trace 122a-2 can be connected to the first sub-trace 122a-1 located in the fourth conductive layer through the sixth opening K6. The third trace 122a-3 located in the sixth conductive layer can be connected to the second trace 122a-2 located in the fifth conductive layer through the ninth opening K9. The orthographic projection of the third trace 122a-3 on the substrate and the orthographic projection of the second connection portion 133a-3 of the first power supply bent line 133a on the substrate can partially overlap.

[0275] In some examples, as Figures 23A to 23F As shown, the second connection portion 133a-3 of the first power supply bent line 133a can extend to the first fan-out region and be connected to the first power supply line 132a in the first fan-out region. The second connection portion 123a-3 located in the fifth conductive layer and the second trace 132a-2 of the first power supply line 132a can be an integrally connected structure. The second trace 132a-2 can be connected to the first trace 132a-1 located in the fourth conductive layer through the seventh opening K7. The third sub-trace 132a-3 located in the sixth conductive layer can be connected to the second trace 132a-2 located in the fifth conductive layer through the tenth opening K10.

[0276] In some examples, as Figure 23D As shown, multiple hollow portions can be provided in the regions where the second connection portion 113a-3 of the first power supply bent line 113a, the second connection portion 123a-3 of the first power supply bent line 123a, and the second connection portion 133a-3 of the first power supply bent line 133a overlap with the eighth insulating layer, so as to facilitate the exhaust of the eighth insulating layer.

[0277] Figure 24A is Figure 5 a partial enlarged schematic diagram of region C4 in Figure 24B is Figure 24A a schematic diagram of the fourth conductive layer in

[0278] Figure 24C is Figure 24A a schematic diagram after forming the eighth insulating layer in Figure 24D is Figure 24A a schematic diagram of the fifth conductive layer in

[0279] Figure 24E is Figure 24A a schematic diagram of the sixth conductive layer in

[0280] In some examples, as Figures 24A to 24EAs shown, the first power supply lines 112a and 112b in the first fan-out region can be arranged approximately symmetrically with respect to the midline of the first fan-out region in the first direction X; the first power supply lines 122a and 122b can be arranged approximately symmetrically with respect to the midline of the first fan-out region in the first direction X; the first power supply lines 132a and 132b can be arranged approximately symmetrically with respect to the midline of the first fan-out region in the first direction X.

[0281] In some examples, the first power supply lines 132a and 132b can be an integrally connected structure. As Figure 24B shown, the first trace 132a-1 of the first power supply line 132a located in the fourth conductive layer and the first trace 132b-1 of the first power supply line 132b located in the fourth conductive layer can be an integrally connected structure; as Figure 24D shown, the second trace 132a-2 of the first power supply line 132a located in the fifth conductive layer, the second trace 132b-2 of the first power supply line 132b located in the fifth conductive layer, and the first power supply bent line 133b can be an integrally connected structure; as Figure 24E shown, the third trace 132a-3 of the first power supply line 132a located in the sixth conductive layer and the third trace 132b-3 of the first power supply line 132b located in the sixth conductive layer can be an integrally connected structure.

[0282] In some examples, as Figure 24D shown, the second trace 112a-2 of the first power supply line 112a and the first power supply bent line 113b can be an integrally connected structure; the second trace 122a-2 of the first power supply line 122a and the first power supply bent line 123b can be an integrally connected structure; the second trace 112b-2 of the first power supply line 112b and the first power supply bent line 113c can be an integrally connected structure; the second trace 122b-2 of the first power supply line 122b and the first power supply bent line 123c can be an integrally connected structure.

[0283] In some examples, as Figure 24C shown, the eighth insulating layer in the first fan-out region can be provided with an eleventh opening K11, a twelfth opening K12, a thirteenth opening K13, a fourteenth opening K14, and a fifteenth opening K15. The eighth insulating layer and the seventh insulating layer within the eleventh opening K11, the twelfth opening K12, the thirteenth opening K13, the fourteenth opening K14, and the fifteenth opening K15 can be removed to expose a partial surface of the fourth conductive layer. The ninth insulating layer can be provided with an opening that exposes a partial surface of the fifth conductive layer.

[0284] In some examples, as Figures 24A to 24EAs shown, the second trace 112a-2 of the first power supply line 112a can be connected to the first trace 112a-1 through the eleventh opening K11; the second trace 122a-2 of the first power supply line 122a can be connected to the first trace 122a-1 through the twelfth opening K12; the second trace 132a-2 of the first power supply line 132a can be connected to the first trace 132a-1 through the thirteenth opening K13; the second trace 11ba-2 of the first power supply line 112b can be connected to the first trace 112b-1 through the fourteenth opening K14; the second trace 122b-2 of the first power supply line 122b can be connected to the first trace 122b-1 through the fifteenth opening K15. The third trace 112a-3 of the first power supply line 112a can be connected to the second trace 112a-2 through the opening in the ninth insulating layer; the third trace 122a-3 of the first power supply line 122a can be connected to the second trace 122a-2 through the opening in the ninth insulating layer; the third trace 132a-3 of the first power supply line 132a can be connected to the second trace 132a-2 through the opening in the ninth insulating layer; the third trace 112b-3 of the first power supply line 112b can be connected to the second trace 112b-2 through the opening in the ninth insulating layer; the third trace 122b-3 of the first power supply line 122b can be connected to the second trace 122b-2 through the opening in the ninth insulating layer.

[0285] Figure 25 For Figure 24A a partial enlarged schematic diagram of region C5 in. In some examples, the third trace of the sixth conductive layer of the first power supply line may have a fifth edge F5, the second trace of the fifth conductive layer may have a fourth edge F4, the first trace of the fourth conductive layer may have a third edge F3, the opening in the seventh insulating layer may have a first edge F1, and the opening in the eighth insulating layer may have a second edge F2. The orthographic projection of the opening in the seventh insulating layer on the substrate may cover the orthographic projection of the corresponding opening in the eighth insulating layer on the substrate. The orthographic projection of the third trace on the substrate may cover the orthographic projection of the corresponding second trace on the substrate, and the orthographic projection of the second trace on the substrate may cover the orthographic projection of the corresponding first trace on the substrate.

[0286] In the display substrate provided in this embodiment, three first voltage supply groups are provided in the first border region, and the first voltage signals required by the blue sub-pixels, red sub-pixels, and green sub-pixels can be designed separately, so as to provide different first voltage signals to the blue sub-pixels, red sub-pixels, and green sub-pixels, thereby reducing power consumption.

[0287] Figure 26 Another trace schematic diagram of the first border region of at least one embodiment of the present disclosure. Figure 27 For Figure 26 a partial enlarged schematic diagram of region C6 in. In some examples, such as Figure 26 andFigure 27 As shown, the first fan-out region B14 may include: a plurality of first power supply lines (such as including first power supply lines 112a and 112b, 122a and 122b, 132a and 132b). The line widths of the line segments of the plurality of first power supply lines in the same extension direction may be different, that is, the plurality of first power supply lines may adopt a non-uniform width design. For example, the line width (i.e., the length along the second direction Y) of the line segments of the first power supply lines 112a and 112b extending along the first direction X may be greater than the line width of the line segments of the first power supply lines 122a and 122b extending along the first direction X, and the line width of the line segments of the first power supply lines 122a and 122b extending along the first direction X may be greater than the line width of the line segments of the first power supply lines 132a and 132b extending along the first direction X; the line width (i.e., the length along the first direction X) of the line segments of the first power supply lines 112a and 112b extending along the second direction Y may be greater than the line width of the line segments of the first power supply lines 122a and 122b extending along the second direction Y, and the line width of the line segments of the first power supply lines 122a and 122b extending along the second direction Y may be greater than the line width of the line segments of the first power supply lines 132a and 132b extending along the second direction Y.

[0288] In some examples, the first power supply lines 112a and 112b may be configured to transmit a first type of first voltage signal Vdd1, the first power supply lines 122a and 122b may be configured to transmit a second type of first voltage signal Vdd2, and the first power supply lines 132a and 132b may be configured to transmit a third type of first voltage signal Vdd3. The first voltage signal Vdd1 is configured to be supplied to the first sub-pixel group (including a plurality of blue sub-pixels), the first voltage signal Vdd2 is configured to be supplied to the second sub-pixel group (including a plurality of red sub-pixels), and the first voltage signal Vdd3 is configured to be supplied to the third sub-pixel group (including a plurality of green sub-pixels). Since the current of the blue sub-pixels is relatively large, the impedance can be reduced by reducing the IR voltage drop of the first voltage signal Vdd1. In this example, by setting the line widths of the first power supply lines 112a and 112b to be greater than those of the other first power supply lines, it is beneficial to reduce the impedance of the first voltage signal Vdd1, thereby ensuring the display effect of the first sub-pixel group.

[0289] In some other examples, in order to avoid increasing the size of the first border region and with limited layout space for multiple first power supply lines providing different first voltage signals, the transmission voltage drop of the first voltage signal can be reduced by means of same-layer wiring. For example, since the pixel current of the blue sub-pixels is relatively large, the voltage drop of the first voltage signal caused by the blue sub-pixels is relatively large, which easily affects the display uniformity of the blue sub-pixels. By adopting a multi-layer metal wiring design for the first power supply lines 112a and 112b, the transmission voltage drop of the first voltage signal Vdd1 can be reduced, thereby improving the display uniformity of the blue sub-pixels. For instance, the number of wiring layers included in the first power supply lines 112a and 112b can be greater than the number of wiring layers included in the first power supply lines 122a and 122b and 132a and 132b. In some examples, the first power supply lines 122a, 122b, 132a, and 132 can be a three-layer wiring structure including the fourth conductive layer, the fifth conductive layer, and the sixth conductive layer; the first power supply lines 112a and 112b can be a four-layer wiring structure including the bottom shielding layer, the fourth conductive layer, the fifth conductive layer, and the sixth conductive layer. The wiring portion located in the bottom shielding layer can be arranged in the area within the first fan-out region that is not shielded by the first conductive layer and the second conductive layer. For example, it can be located below the first wiring of the fourth conductive layer within region 6. However, this embodiment is not limited thereto. In some other examples, the wiring portion of the first power supply lines 112a and 112b located in the bottom shielding layer can be located in the area on one side of the laterally extending driving lead-out line close to the second fan-out region B11.

[0290] For the remaining structure of the display substrate in this example, reference can be made to the description of the foregoing embodiment, and thus it will not be elaborated herein.

[0291] Figure 28 This is another wiring schematic diagram of the first border region of at least one embodiment of the present disclosure. Figure 29 For Figure 28 a partial enlarged schematic diagram of region C7 in. In some examples, as Figure 28 and Figure 29 shown, the first fan-out region B14 can include multiple first power supply lines 112, 122, and 132. The first power supply line 112 is configured to transmit the first voltage signal Vdd1, the first power supply line 122 is configured to transmit the first voltage signal Vdd2, and the first power supply line 132 is configured to transmit the first voltage signal Vdd3. The line widths of the line segments of the first power supply lines 112, 122, and 132 in the same extending direction can be substantially the same.

[0292] In some examples, as Figure 28 and Figure 29As shown, the first power supply lines 112, 122, and 132 may be located in different conductive layers. For example, the first power supply line 112 may be located in the fourth conductive layer, the first power supply line 122 may be located in the fifth conductive layer, and the first power supply line 132 may be located in the sixth conductive layer. A seventh insulating layer and an eighth insulating layer may be provided between the first power supply line 112 and the first power supply line 122, and a ninth insulating layer may be provided between the first power supply lines 122 and 132. The first power supply lines 122 and 132 may be provided with a plurality of hollow portions to facilitate the exhaust of the organic insulating layer (including the eighth insulating layer and the ninth insulating layer). Figure 28 and Figure 29 The plurality of hollow portions on the first power supply lines 122 and 132 are schematically omitted in

[0293] Figure 30A is Figure 28 a partial enlarged schematic view of region C8 in Figure 30A which schematically shows the structures of the fourth conductive layer, the fifth conductive layer, and the sixth conductive layer in region C8. Figure 30B is Figure 30A a schematic view of the fourth conductive layer and the fifth conductive layer in Figure 30C is Figure 30A a schematic view of the fifth conductive layer in Figure 31A is Figure 28 a partial enlarged schematic view of region C9 in Figure 31A which schematically shows the structures of the fourth conductive layer, the fifth conductive layer, and the sixth conductive layer in region C9. Figure 31B is Figure 31A a schematic view of the fourth conductive layer and the fifth conductive layer in Figure 31C is Figure 31A a schematic view of the fifth conductive layer in

[0294] In some examples, as Figures 30A to 31C shown, the first power supply line 122 located in the fifth conductive layer may be provided with a plurality of notches on the side close to the bending region, such as including a first notch Q1, a second notch Q2, a third notch Q3, a fourth notch Q4, and a fifth notch Q5. The first power supply line 122 and the first power supply bending lines 123a, 123b, and 123c may be an integrally connected structure. The first notch Q1 and the second notch Q2 may be located on both sides of the first power supply bending line 123a in the first direction X, the third notch Q3 and the fourth notch Q4 may be located on both sides of the first power supply bending line 123b in the first direction X, and the fourth notch Q4 may be located between the first power supply bending lines 123b and 123c. The fifth notch Q5 may be located on the side of the first power supply bending line 123c away from the fourth notch Q4.

[0295] In some examples, as Figure 30BAs shown, the first power supply bent line 113a located in the fifth conductive layer can extend into the first notch Q1 and is connected to the first power supply line 112 located in the fourth conductive layer through the openings of the eighth insulating layer and the seventh insulating layer. As Figure 31B As shown, the first power supply bent line 113b located in the fifth conductive layer can extend into the third notch Q3 and is connected to the first power supply line 112 located in the fourth conductive layer through the openings of the eighth insulating layer and the seventh insulating layer. The first power supply bent line 113c located in the fifth conductive layer can extend into the fifth notch Q5 and is connected to the first power supply line 112 located in the fourth conductive layer through the openings of the eighth insulating layer and the seventh insulating layer.

[0296] In some examples, as Figure 30A As shown, the first power supply bent line 133a located in the fifth conductive layer can extend into the second notch Q2, and the first power supply line 132 located in the sixth conductive layer can be connected to the first power supply bent line 133a through the opening of the ninth insulating layer. As Figure 31A As shown, the first power supply bent line 133b located in the fifth conductive layer can extend into the fourth notch Q4, and the first power supply line 132 located in the sixth conductive layer can be connected to the first power supply bent line 133b through the opening of the ninth insulating layer.

[0297] In some examples, the orthographic projections of the first power supply lines 112, 122, and 132 on the substrate may partially overlap. For example, the orthographic projection of the line segment of the first power supply line 132 located in the sixth conductive layer extending along the first direction X on the substrate may cover the orthographic projection of the extension of the first power supply line 122 located in the fifth conductive layer extending along the first direction X on the substrate, and the orthographic projection of the line segment of the first power supply line 122 located in the fifth conductive layer extending along the first direction X on the substrate may cover the orthographic projection of the extension of the first power supply line 112 located in the fourth conductive layer extending along the first direction X on the substrate.

[0298] In this example, by arranging multiple first power supply lines in different conductive layers, the routing width of the first power supply line does not need to be reduced, which is beneficial to reducing the impedance of the first power supply line and ensuring the display uniformity of the sub-pixels.

[0299] In some examples, the brightness of sub-pixels emitting different colors of light (such as blue sub-pixels, red sub-pixels, and green sub-pixels) can be controlled by the magnitude of the second voltage signal. For example, according to the different turn-on voltages of the RGB sub-pixels, by providing different second voltage signals to the RGB sub-pixels, the pixel circuit can output the same voltage to the anodes of the light-emitting elements emitting different colors of light to turn on the light-emitting elements emitting different colors of light. Furthermore, the maximum value of the data signal range of the RGB sub-pixels can be kept the same value to achieve fine grouping control of the brightness of the RGB sub-pixels and achieve the purpose of power consumption saving of the second voltage signal.

[0300] Figure 32 Schematic diagram of the transmission of the second voltage signal according to at least one embodiment of the present disclosure. In some examples, as Figure 32 shown, the multiple sub-pixels in the display area AA can be divided into three sub-pixel groups. For example, the first sub-pixel group can include multiple first sub-pixels PX1 that emit the first color light (e.g., blue light), the second sub-pixel group can include multiple second sub-pixels PX2 that emit the second color light (e.g., red light), and the third sub-pixel group can include multiple third sub-pixels PX3 that emit the third color light (e.g., green light). The first sub-pixel group can be connected to the second power supply line VSS1, the second sub-pixel group can be connected to the second power supply line VSS2, and the third sub-pixel group can be connected to the second power supply line VSS3. The second power supply line VSS1 can be configured to transmit the first type of second voltage signal Vss1, the second power supply line VSS2 can be configured to transmit the second type of second voltage signal Vss2, and the second power supply line VSS3 can be configured to transmit the third type of second voltage signal Vss3. The second voltage signals Vss1, Vss2, and Vss3 can be second voltage signals with different voltage values. For example, the second voltage signal Vss1 can be less than the second voltage signal Vss2, and the second voltage signal Vss2 can be less than the second voltage signal Vss3.

[0301] In some examples, the cathodes of the light-emitting elements of a column of first sub-pixels PX1 in the first sub-pixel group can be an integrally connected structure and serve as a second power supply line VSS1; the cathodes of the light-emitting elements of a column of second sub-pixels PX2 in the second sub-pixel group can be an integrally connected structure and serve as a second power supply line VSS2; the cathodes of the light-emitting elements of a column of third sub-pixels PX3 in the third sub-pixel group can be an integrally connected structure and serve as a second power supply line VSS3.

[0302] In some examples, as Figure 32 shown, the first border area B1 can include L second voltage supply groups, such as the first second voltage supply group 21, the second second voltage supply group 22, and the third second voltage supply group 23. Each second voltage supply group can be configured to provide a corresponding second voltage signal to at least one sub-pixel group. In this example, the second voltage supply group 21 can be configured to provide the second voltage signal Vss1 to the first sub-pixel group, the second voltage supply group 22 can be configured to provide the second voltage signal Vss2 to the second sub-pixel group, and the second voltage supply group 23 can be configured to provide the second voltage signal Vss3 to the third sub-pixel group.

[0303] In some examples, as Figure 32As shown, the second voltage power supply group 21 may include: a third power supply line 211 located in the second fan-out region B11, a fourth power supply line 212 located in the first fan-out region B13, a second power supply bending line 213 located in the bending region B12, and second voltage contact pads 214a and 214b located in the first signal access region B15. The second voltage power supply group 22 may include: a third power supply line 221 located in the second fan-out region B11, a fourth power supply line 222 located in the first fan-out region B13, a second power supply bending line 223 located in the bending region B12, and second voltage contact pads 224a and 224b located in the first signal access region B15. The second voltage power supply group 23 may include: a third power supply line 231 located in the second fan-out region B11, a fourth power supply line 232 located in the first fan-out region B13, a second power supply bending line 233 located in the bending region B12, and second voltage contact pads 234a and 234b located in the first signal access region B15.

[0304] In some examples, as Figure 32 shown, the third power supply lines 211, 221, and 231 located in the second fan-out region B11 may be arranged in sequence along the opposite direction of the second direction Y. The third power supply lines 211, 221, and 231 may be at least traces extending along the first direction X. The third power supply line may be connected to the second power supply line through a third type of voltage transfer electrode, and the third type of voltage transfer electrode may include: a seventh voltage transfer electrode 241, an eighth voltage transfer electrode 242, and a ninth voltage transfer electrode 243. Among them, the third power supply line 211 may be connected to the second power supply line VSS1 through the seventh voltage transfer electrode 241, the third power supply line 221 may be connected to the second power supply line VSS2 through the eighth voltage transfer electrode 242, and the third power supply line 231 may be connected to the second power supply line VSS3 through the ninth voltage transfer electrode 243.

[0305] In this example, by providing three second voltage power supply groups in the first border region to provide three different second voltage signals, the different requirements of the three sub-pixel groups that emit different color lights in the display region for the second voltage signal can be met, thereby achieving the purpose of saving the power consumption of the second voltage signal.

[0306] Figure 33 It is a schematic diagram of the traces in the first border region of at least one embodiment of the present disclosure. Figure 33 It mainly shows three third power supply lines 211, 221, and 231 in the second fan-out region B11, multiple bending connection lines in the bending region B12, and part of the traces in the first fan-out region B13 (such as including first power supply lines 212a and 212b, 222a and 222b, and 232a and 232b); moreover, in Figure 33 it, the multiple adjacent traces of the same type are schematically shown as a whole.

[0307] In some examples, as Figure 33 shown, the second fan-out region B11 may at least include: three third power supply lines 211, 221, and 231, a first voltage fan-out line (not shown in the figure), multiple data fan-out lines (not shown in the figure), multiple drive fan-out lines (not shown in the figure), and multiple touch fan-out lines (not shown in the figure). The first voltage fan-out line may be configured to transmit a first voltage signal.

[0308] In some examples, as Figure 33 shown, the multiple bent connection lines in the bent region B12 may include: multiple data bent lines (such as including a first group of data bent lines 163a, a second group of data bent lines 163b, a third group of data bent lines 163c, a fourth group of data bent lines 163d, a fifth group of data bent lines 163e, and a sixth group of data bent lines 163f), multiple drive bent lines (such as including a first group of drive bent lines 173a, a second group of drive bent lines 173b), multiple touch bent lines (such as including a first group of touch bent lines 183a, a second group of touch bent lines 183b, a third group of touch bent lines 183c, and a fourth group of touch bent lines 183d), multiple first power supply bent lines (such as including first power supply bent lines 193a, 193b, 193c, and 193d), multiple second power supply bent lines (such as including second power supply bent lines 213a, 213b, 213c, and 213d, 223a, 223b, 223c, and 223d, 233a, 233b, and 233c).

[0309] In some examples, as Figure 33 shown, within the bent region B12, the first group of drive bent lines 173a, the first power supply bent line 193a, the first group of touch bent lines 183a, the first group of data bent lines 163a, the second group of touch bent lines 183b, the first power supply bent line 193b, the second group of data bent lines 163b, the second power supply bent lines 213a, 223a, and 233a, the third group of data bent lines 163c, the second power supply bent lines 213b, 223b, 233b, 223c, and 213c, the fourth group of data bent lines 163d, the second power supply bent lines 213c, 223d, and 213d, the fifth group of data bent lines 163c, the first power supply bent line 193c, the third group of touch bent lines 183c, the sixth group of data bent lines 163f, the fourth group of touch bent lines 183d, the first power supply bent line 193d, and the second group of drive bent lines 173b may be arranged in sequence along the first direction X.

[0310] In some examples, as Figure 33As shown, the first fan-out region B13 may include: multiple fourth power supply lines (such as including two fourth power supply lines 212a and 212b, two fourth power supply lines 222a and 222b, and two fourth power supply lines 232a and 232b), two first voltage lead-out lines (such as including the first voltage lead-out line 191 and 192), multiple data lead-out lines (including the first group of data lead-out lines 161 and the second group of data lead-out lines 162), multiple driving lead-out lines (including the first group of driving lead-out lines 171 and the second group of driving lead-out lines 172), and multiple touch lead-out lines (including the first group of touch lead-out lines 181 and the second group of touch lead-out lines 182). The first voltage lead-out line 191 may be connected to the first voltage fan-out line in the second fan-out region B11 through the first voltage bending lines 193a and 193b, and the first voltage lead-out line 192 may be connected to the first voltage fan-out line in the second fan-out region B11 through the first voltage bending lines 193c and 193d. The first voltage lead-out lines 191 and 192 may be configured to transmit the first voltage signal.

[0311] Figure 34A is Figure 33 a partial enlarged schematic diagram of the region C10 in Figure 34A which schematically shows some film layers at the junction position between the display region AA and the first border region B1. Figure 34B is Figure 34A a schematic diagram of the fourth conductive layer in Figure 34C is Figure 34A a schematic diagram after forming the fifth conductive layer in Figure 34D is Figure 34A a schematic diagram after forming the anode layer in

[0312] In some examples, as Figure 34B shown, the fourth conductive layer of the first border region may at least include: third type voltage transfer electrodes (such as including the seventh voltage transfer electrode 241, the eighth voltage transfer electrode 242, and the ninth voltage transfer electrode 243), and multiple auxiliary electrodes (such as including the third auxiliary electrode 363 and the fourth auxiliary electrode 364).

[0313] In some examples, the seventh voltage transfer electrode 241 may include a seventh main body portion 241-1 and a ninth protruding portion 241-2, and the seventh main body portion 241-1 and the ninth protruding portion 241-2 may be an integrally connected structure. The shape of the seventh main body portion 241-1 may be generally rectangular, and the shape of the ninth protruding portion 241-2 may be generally L-shaped. The ninth protruding portion 241-2 is located on a side of the seventh main body portion 241-1 close to the display area. The eighth voltage transfer electrode 242 may include an eighth main body portion 242-1 and a tenth protruding portion 242-2. The shape of the eighth main body portion 242-1 may be generally rectangular, and the shape of the tenth protruding portion 242-2 may be generally L-shaped. The eighth main body portion 242-1 and the tenth protruding portion 242-2 may be an integrally connected structure. The ninth voltage transfer electrode 243 may include a ninth main body portion 243-1 and a plurality of eleventh protruding portions 243-2. The shape of the ninth main body portion 243-1 may be generally rectangular, and the shape of the eleventh protruding portion 243-2 may be strip-shaped extending along the second direction Y. The ninth main body portion 243-1 and the plurality of eleventh protruding portions 243-2 may be an integrally connected structure.

[0314] In some examples, the shapes of the third auxiliary electrode 363 and the fourth auxiliary electrode 364 may be generally rectangular. The seventh voltage transfer electrode 241 and the third auxiliary electrode 363 are aligned in the second direction Y, and the third auxiliary electrode 363 is located on a side of the seventh voltage transfer electrode 241 away from the display area and between the two eleventh protruding portions 243-2 of the ninth voltage transfer electrode 243. The eighth voltage transfer electrode 242 and the fourth auxiliary electrode 364 are aligned in the second direction Y, and the fourth auxiliary electrode 364 may be located on a side of the eighth voltage transfer electrode 242 close to the display area and between the two eleventh protruding portions 243-2 of the ninth voltage transfer electrode 243.

[0315] In some examples, such as Figure 34CAs shown, the fifth conductive layer of the first border region may at least include: third power supply lines 211, 221, and 231, and a plurality of border power connection electrodes (such as including a fifth border power connection electrode 335, a sixth border power connection electrode 336, a seventh border power connection electrode 337, and an eighth border power connection electrode 338). The fifth border power connection electrode 335, the sixth border power connection electrode 336, the seventh border power connection electrode 337, and the eighth border power connection electrode 338 may be arranged along the first direction X and are located on one side of the third power supply line 211 close to the display region. The fifth border power connection electrode 335 may be connected to the ninth protrusion 241-2 of the seventh voltage transfer electrode 241 through a via formed in the eighth insulating layer and the seventh insulating layer. The sixth border power connection electrode 336 may be connected to an eleventh protrusion 243-2 of the ninth voltage transfer electrode 243. The seventh border power connection electrode 337 may be connected to the tenth protrusion 242-2 of the eighth voltage transfer electrode 242. The eighth border power connection electrode 338 may be connected to the other eleventh protrusion 243-2 of the ninth voltage transfer electrode 243.

[0316] In some examples, as Figure 34D As shown, the anode layer of the first border region may at least include: a plurality of border power connection electrodes (such as including a ninth border power connection electrode 371, a tenth border power connection electrode 372, an eleventh border power connection electrode 373, and a twelfth border power connection electrode 374). The ninth border power connection electrode 371, the tenth border power connection electrode 372, the eleventh border power connection electrode 373, and the twelfth border power connection electrode 374 may be arranged along the first direction X and are located on one side of the third power supply line 211 close to the display region. The ninth border power connection electrode 371 may be connected to the fifth border power connection electrode 335. The tenth border power connection electrode 372 may be connected to the sixth border power connection electrode 336. The eleventh border power connection electrode 373 may be connected to the seventh border power connection electrode 337. The twelfth border power connection electrode 374 may be connected to the eighth border power connection electrode 338.

[0317] In some examples, as Figure 34AAs shown, the cathode layer of the display substrate may include: multiple second power supply lines (such as including second power supply lines VSS1, VSS2, and VSS3). The cathode in the display area may be graphically formed as multiple strip patterns extending along the second direction Y, and each strip pattern may serve as a second power supply line. The second power supply line VSS1 may be connected to the ninth border power connection electrode 371 of the anode layer through a via formed in the pixel definition layer, and thus connected to the third power supply line 211 through the seventh voltage transfer electrode 241 to receive the second voltage signal Vss1. One second power supply line VSS3 may be connected to the tenth border power connection electrode 372 of the anode layer through a via formed in the pixel definition layer, and thus connected to the third power supply line 231 through the ninth voltage transfer electrode 243 to receive the second voltage signal Vss3. Another second power supply line VSS3 may be connected to the twelfth border power connection electrode 374 of the anode layer through a via formed in the pixel definition layer, and thus connected to the third power supply line 231 through the ninth voltage transfer electrode 243 to receive the second voltage signal Vss3. The second power supply line VSS2 may be connected to the eleventh border power connection electrode 373 of the anode layer through a via formed in the pixel definition layer, and thus connected to the third power supply line 221 through the eighth voltage transfer electrode 242 to receive the second voltage signal Vss2.

[0318] In this example, by using the border power connection electrodes located in the anode layer and the fifth conductive layer and the third type of voltage transfer electrodes located in the fourth conductive layer, the electrical connection between the second power supply lines in the cathode layer and the third power supply lines in the fifth conductive layer can be achieved. In some other examples, when the cathode in the display area is graphically formed as multiple strip patterns extending along the first direction X, and each strip pattern serves as a second power supply line (in other words, when the second power supply lines extend along the first direction X), the Figure 34A structure shown can be rotated by 90 degrees, and the third power supply lines can be adjusted to extend along the second direction Y to achieve the electrical connection between the second power supply lines and the third power supply lines in the second border area. This embodiment does not limit this.

[0319] Regarding the wiring arrangement, width, and cross-line method within the second voltage power supply group of this example, reference can be made to the relevant content of the first voltage power supply group in the foregoing embodiments, so it will not be elaborated here.

[0320] In some other examples, the line segments of the fourth power supply lines of the three second voltage power supply groups arranged in the first border area along the same extension direction may be different. For example, reference can be made to the Figure 26 embodiment shown above, so it will not be elaborated here.

[0321] In some other examples, the fourth power supply lines of the three second voltage power supply groups arranged in the first border area may be arranged in different conductive layers. For example, reference can be made to the Figure 28The embodiments shown are not described herein again for the sake of brevity.

[0322] In some other examples, three first voltage supply groups and three second voltage supply groups may be provided in the first border area to provide three different first voltage signals and three different second voltage signals, so as to meet the different requirements of three sub-pixel groups that emit different color lights in the display area for the first voltage signal and the second voltage signal, thereby achieving the purpose of saving the power consumption of the first voltage signal and the second voltage signal.

[0323] This embodiment also provides a display substrate, including: a substrate, a plurality of sub-pixels, a plurality of second power supply lines, and L second voltage supply groups. The substrate includes a display area and a first border area located on one side of the display area. The plurality of sub-pixels and the plurality of second power supply lines are located in the display area. The plurality of sub-pixels are divided into N sub-pixel groups. Each sub-pixel group includes a plurality of sub-pixels that emit the same color light. Different sub-pixel groups are configured to emit different color lights. At least one sub-pixel includes: a pixel circuit and a light-emitting element connected to the pixel circuit. Each second power supply line is connected to the light-emitting elements of a plurality of sub-pixels that emit the same color light. The L second voltage supply groups are located in the first border area. The L second voltage supply groups are configured to provide different second voltage signals. Each second voltage supply group is configured to provide a second voltage signal to the light-emitting elements in at least one sub-pixel group through at least one second power supply line; wherein, both L and N are integers greater than 1, and L is less than or equal to N.

[0324] In some examples, the number of sub-pixel groups may be the same as the number of second voltage supply groups, that is, L may be equal to N. Each second voltage supply group may provide a second voltage signal to one sub-pixel group. Among them, different sub-pixel groups receive different second voltage signals. In some other examples, L may be less than N, and at least one second voltage supply group may provide a first voltage signal to at least two sub-pixel groups. Among them, the second voltage signals received by at least two sub-pixel groups may be the same. For example, one of the L second voltage supply groups may be configured to provide the same second voltage signal to two sub-pixel groups. However, this embodiment is not limited thereto.

[0325] In some examples, each of the L second voltage supply groups can be configured to provide a second voltage signal different from the remaining second voltage supply groups. In other words, the L second voltage supply groups can provide L different second voltage signals. In some other examples, at least two of the L second voltage supply groups can be configured to provide different second voltage signals. For example, the L second voltage supply groups can be configured to provide L - 1 different second voltage signals, two of the L second voltage supply groups can provide the same second voltage signal, and the remaining second voltage supply groups can be configured to provide different second voltage signals. This embodiment does not limit this.

[0326] In some examples, the display area can include multiple second power lines, and each second power line can be connected to the light-emitting elements of multiple sub-pixels that emit the same color of light. For example, the light-emitting elements of the sub-pixels can include an anode and a cathode. The cathode of the light-emitting element can be connected to the second power line. The multiple light-emitting elements in a sub-pixel group can be connected to multiple second power lines, and a second voltage supply group can be configured to provide a second voltage signal to the light-emitting elements in the sub-pixel group through the multiple second power lines. In some other examples, the multiple light-emitting elements in a sub-pixel group can be connected to one second power line, and a second voltage supply group can be configured to provide a second voltage signal to the light-emitting elements in the sub-pixel group through the one second power line. This embodiment does not limit this.

[0327] In this embodiment, by setting three second voltage supply groups in the first border area to provide three different second voltage signals, it is possible to meet the different requirements of three sub-pixel groups that emit different colors of light in the display area for the second voltage signal, thereby achieving the purpose of saving the power consumption of the second voltage signal.

[0328] In some exemplary embodiments, the N sub-pixel groups may include: a first sub-pixel group that emits a first color light, a second sub-pixel group that emits a second color light, and a third sub-pixel group that emits a third color light. The L second voltage supply groups may include: a first second voltage supply group that provides a first type of second voltage signal, a second second voltage supply group that provides a second type of second voltage signal, and a third second voltage supply group that provides a third type of second voltage signal. The first second voltage supply group is configured to provide the first type of second voltage signal to the first sub-pixel group. The second second voltage supply group is configured to provide the second type of second voltage signal to the second sub-pixel group. The third second voltage supply group is configured to provide the third type of second voltage signal to the third sub-pixel group. However, this embodiment is not limited thereto. In some other examples, the number of sub-pixel groups may be three, the number of second voltage supply groups may be two, the first second voltage supply group may be configured to provide the first type of second voltage signal to the first sub-pixel group (e.g., including blue sub-pixels), and the second first voltage supply group may be configured to provide the second type of second voltage signal to the second sub-pixel group (e.g., including red sub-pixels) and the third sub-pixel group (e.g., including green sub-pixels). This example can achieve grouped control of RGB brightness through the grouped design of the second voltage signal, thereby achieving the purpose of power consumption reduction of the second voltage signal.

[0329] In some exemplary embodiments, the first color light may be blue light, the second color light may be red light, and the third color light may be green light. The first type of second voltage signal may be less than the second type of second voltage signal, and the second type of second voltage signal may be less than the third type of second voltage signal.

[0330] For the remaining descriptions of the display substrate of this example, reference may be made to the descriptions of the foregoing embodiments, and thus will not be elaborated herein.

[0331] Figure 35 Schematic diagram of a display device according to at least one embodiment of the present disclosure. As Figure 35As shown, this embodiment provides a display device 91, including the display substrate 910 of the foregoing embodiment. In some examples, the display substrate 910 may be a flexible OLED display substrate, a QLED display substrate, a Micro-LED display substrate, or a Mini-LED display substrate. The display device may be a product having an image (including a static image or a dynamic image, where the dynamic image may be a video) display function. For example, the display device may be any one of: a monitor, a television, a billboard, a digital photo frame, a laser printer with a display function, a telephone, a mobile phone, a painting screen, a personal digital assistant (PDA), a digital camera, a portable video camera, a viewfinder, a navigator, a vehicle, a large-area wall, an information query device (such as a business query device in departments such as e-government, banks, hospitals, and power), a monitor, etc. Also, for example, the display device may also be a microdisplay, any one of a VR device or an AR device including the microdisplay, etc.

[0332] The drawings in the present disclosure only relate to the structures involved in the present disclosure, and other structures may refer to the general design. Without conflict, the embodiments of the present disclosure, that is, the features in the embodiments, may be combined with each other to obtain new embodiments. It should be noted that the above embodiments or implementation manners are merely exemplary and not restrictive. Therefore, the present disclosure is not limited to the content shown and described in detail herein. Various modifications, substitutions, or omissions may be made to the form and details of the implementation without departing from the scope of the present disclosure.

Claims

1. A display substrate, characterized in that, comprising: a substrate, comprising: a display area and a first border area located on one side of the display area; a plurality of sub-pixels and a plurality of first power supply lines, located in the display area, the plurality of sub-pixels being divided into N sub-pixel groups, each sub-pixel group comprising a plurality of sub-pixels emitting light of the same color, different sub-pixel groups being configured to emit light of different colors, at least one sub-pixel of the plurality of sub-pixels comprising: a pixel circuit and a light-emitting element connected to the pixel circuit, each first power supply line being connected to the pixel circuits of the plurality of sub-pixels emitting light of the same color; M first voltage supply groups, located in the first border area, the M first voltage supply groups being configured to provide different first voltage signals; each first voltage supply group being configured to supply a first voltage signal to the pixel circuits in at least one sub-pixel group through at least one first power supply line, wherein M and N are both integers greater than 1, and M is less than or equal to N.

2. The display substrate according to claim 1, characterized in that, the first border area comprises: a first fan-out area and a first signal access area arranged in sequence along the direction away from the display area; each first voltage supply group at least comprises: at least one first power supply line located in the first fan-out area and at least one first voltage contact pad located in the first signal access area; the at least one first power supply line is connected to the at least one first voltage contact pad.

3. The display substrate according to claim 2, characterized in that, the first border area further comprises: a second fan-out area and a bending area, the second fan-out area and the bending area being located on the side of the first fan-out area close to the display area, the bending area connecting the first fan-out area and the second fan-out area; each first voltage supply group further comprises: at least one second power supply line located in the second fan-out area, at least one first power supply bending line located in the bending area; the at least one second power supply line is connected to a plurality of first power supply lines transmitting the same first voltage signal, and the at least one first power supply bending line connects the at least one first power supply line and the at least one second power supply line.

4. The display substrate according to claim 3, characterized in that, the second power supply line extends at least along a first direction, the first power supply bending line extends at least along a second direction, the first power supply line extends at least along the second direction, the first direction intersects with the second direction; the at least one first power supply line is symmetrically arranged about the midline of the first border area along the first direction.

5. The display substrate according to claim 3, characterized in that, the second power supply line is connected to a plurality of first power supply lines through a first type of voltage transfer electrode, the at least one first power supply bending line is connected to the second power supply line and a plurality of first power supply lines through a second type of voltage transfer electrode; the first type of voltage transfer electrode and the second type of voltage transfer electrode are of the same layer structure.

6. The display substrate according to claim 2, characterized in that, The distance between the orthographic projections of the first power supply lines of at least two of the M first voltage power supply groups on the substrate is greater than 0, and the first power supply line includes at least two interconnected traces.

7. The display substrate according to claim 6, wherein, In a direction perpendicular to the display substrate, the display substrate includes: a first semiconductor layer, a first gate metal layer, a second gate metal layer, a second semiconductor layer, a third gate metal layer, a first source-drain metal layer, a second source-drain metal layer, and a third source-drain metal layer provided on the substrate; The first power supply line of at least one of the M first voltage power supply groups includes traces located in at least two of the first source-drain metal layer, the second source-drain metal layer, and the third source-drain metal layer.

8. The display substrate according to claim 2, wherein, The first power supply lines of different first voltage power supply groups are located in different conductive layers, and the orthographic projections of the first power supply lines of at least two first voltage power supply groups partially overlap on the substrate.

9. The display substrate according to claim 2, wherein, The line widths of the line segments of the first power supply lines of the M first voltage power supply groups in the same extension direction are the same.

10. The display substrate according to claim 2, wherein, The line widths of the line segments of the first power supply lines of at least two adjacent first voltage power supply groups in the same extension direction are different.

11. The display substrate according to claim 1, wherein, The N sub-pixel groups include: a first sub-pixel group that emits a first color light, a second sub-pixel group that emits a second color light, and a third sub-pixel group that emits a third color light; The M first voltage power supply groups include: a first first voltage power supply group that provides a first first voltage signal of a first type, a second first voltage power supply group that provides a second first voltage signal of a second type, and a third first voltage power supply group that provides a third first voltage signal of a third type; The first first voltage power supply group is configured to provide the first sub-pixel group with the first first voltage signal of the first type; The second first voltage power supply group is configured to provide the second sub-pixel group with the second first voltage signal of the second type; The third first voltage power supply group is configured to provide the third sub-pixel group with the third first voltage signal of the third type.

12. The display substrate according to claim 11, wherein, The first color light is blue light, the second color light is red light, and the third color light is green light; the first first voltage signal is greater than the second first voltage signal, and the second first voltage signal is greater than the third first voltage signal.

13. The display substrate according to claim 11, wherein, The display substrate further includes: a bottom shielding layer, and the bottom shielding layer is connected to the first first voltage power supply group.

14. The display substrate according to claim 11, wherein, The first border region includes: a first fan-out region and a first signal access region sequentially arranged along a direction away from the display region; Each first voltage supply group includes at least: at least one first power supply line located in the first fan-out region and at least one first voltage contact pad located in the first signal access region; the at least one first power supply line is connected to the at least one first voltage contact pad; The average line width of the first power supply lines of the first first voltage supply group is greater than the average line width of the first power supply lines of the second first voltage supply group; the average line width of the first power supply lines of the second first voltage supply group is greater than the average line width of the first power supply lines of the third first voltage supply group.

15. The display substrate according to claim 11, wherein, The first border region includes: a first fan-out region and a first signal access region sequentially arranged along the direction away from the display region; Each first voltage supply group includes at least: at least one first power supply line located in the first fan-out region and at least one first voltage contact pad located in the first signal access region; the at least one first power supply line is connected to the at least one first voltage contact pad; The first power supply lines of the first first voltage supply group, the first power supply lines of the second first voltage supply group, and the first power supply lines of the third first voltage supply group are single-layer traces and partially overlap in the orthographic projection on the substrate.

16. The display substrate according to claim 15, wherein, In the direction perpendicular to the display substrate, the display substrate at least includes: a first source-drain metal layer, a second source-drain metal layer, and a third source-drain metal layer provided on the substrate; The first power supply lines of the first first voltage supply group are located in the first source-drain metal layer, the first power supply lines of the second first voltage supply group are located in the second source-drain metal layer, and the first power supply lines of the third first voltage supply group are located in the third source-drain metal layer.

17. The display substrate according to any one of claims 1 to 16, wherein, The display substrate further includes: L second voltage supply groups located in the first border region, the L second voltage supply groups are configured to provide different second voltage signals, and each second voltage supply group is configured to provide a second voltage signal to the light-emitting elements in at least one sub-pixel group, where L is an integer greater than 1 and less than or equal to N; the second voltage signal is different from the first voltage signal.

18. The display substrate according to claim 17, wherein, The N sub-pixel groups include: a first sub-pixel group that emits first color light, a second sub-pixel group that emits second color light, and a third sub-pixel group that emits third color light; The L second voltage supply groups include: a first second voltage supply group that provides a first second voltage signal, a second second voltage supply group that provides a second second voltage signal, and a third second voltage supply group that provides a third second voltage signal; The first second voltage supply group is configured to provide the first second voltage signal to the first sub-pixel group; The second second voltage supply group is configured to provide the second second voltage signal to the second sub-pixel group; The third second-voltage power supply group is configured to provide a third second-voltage signal to the third sub-pixel group.

19. The display substrate according to claim 18, wherein, the first color light is blue light, the second color light is red light, and the third color light is green light; the first second-voltage signal is less than the second second-voltage signal, and the second second-voltage signal is less than the third second-voltage signal.

20. The display substrate according to claim 17, wherein, the light-emitting element includes an anode and a cathode; the cathodes of a plurality of light-emitting elements that emit the same color light are connected to each other and are connected to a second-voltage power supply group through at least a third-type voltage transfer electrode.

21. A display device, wherein, it includes the display substrate according to any one of claims 1 to 20.

22. A display substrate, wherein, it includes: a substrate including a display area and a first border area on one side of the display area; a plurality of sub-pixels and a plurality of second power supply lines located in the display area, the plurality of sub-pixels are divided into N sub-pixel groups, each sub-pixel group includes a plurality of sub-pixels that emit the same color light, different sub-pixel groups are configured to emit different color lights, at least one sub-pixel of the plurality of sub-pixels includes: a pixel circuit and a light-emitting element connected to the pixel circuit, and each second power supply line is connected to the light-emitting elements of a plurality of sub-pixels that emit the same color light; L second-voltage power supply groups located in the first border area, the L second-voltage power supply groups are configured to provide different second-voltage signals, and each second-voltage power supply group is configured to provide a second-voltage signal to the light-emitting elements in at least one sub-pixel group through at least one second power supply line; wherein, both L and N are integers greater than 1, and L is less than or equal to N.

23. The display substrate according to claim 22, wherein, the N sub-pixel groups include: a first sub-pixel group that emits the first color light, a second sub-pixel group that emits the second color light, and a third sub-pixel group that emits the third color light; the L second-voltage power supply groups include: a first second-voltage power supply group that provides a first second-voltage signal, a second second-voltage power supply group that provides a second second-voltage signal, and a third second-voltage power supply group that provides a third second-voltage signal; the first second-voltage power supply group is configured to provide the first second-voltage signal to the first sub-pixel group; the second second-voltage power supply group is configured to provide the second second-voltage signal to the second sub-pixel group; the third second-voltage power supply group is configured to provide the third second-voltage signal to the third sub-pixel group.

24. The display substrate according to claim 23, wherein, the first color light is blue light, the second color light is red light, and the third color light is green light; the first second-voltage signal is less than the second second-voltage signal, and the second second-voltage signal is less than the third second-voltage signal.

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