Display backboard, preparation method thereof and display device

Abstract

A display backplane, a preparation method thereof and a display device relate to but are not limited to the technical field of display, the display backplane comprises a substrate, a signal line, a first organic dielectric layer and an active layer, the signal line is arranged on the substrate, the first organic dielectric layer is arranged on one side of the signal line away from the substrate, and the active layer is arranged on the other side of the signal line away from the substrate. The active layer is arranged on one side, far away from the substrate, of the first organic dielectric layer, the first organic dielectric layer exposes at least part of the signal line, and the active layer is connected with the exposed signal line; the segment difference of the signal line is improved.

Description

Technical Field

[0001] This application relates to, but is not limited to, the field of display technology, and particularly relates to a display backplane, a preparation method thereof, and a display device. Background Art

[0002] In recent years, with the diversified expansion of the application fields of VR (Virtual Reality) and AR (Augmented Reality), the demand for VR and AR products has grown rapidly, and the requirements for display effects have also become higher and higher. Display devices require a higher pixel density (Pixels Per Inch, PPI). When the pixel density rate is higher than 2000 PPI, light leakage will occur in the vias of the transistors in the display device, affecting the display effect. Summary of the Invention

[0003] Embodiments of this application provide a display backplane, a preparation method thereof, and a display device, which improve the step difference of signal lines.

[0004] Embodiments of this application provide a display backplane, including: a substrate, signal lines, a first organic dielectric layer, and an active layer. The signal lines are disposed on the substrate. The first organic dielectric layer is disposed on a side of the signal lines away from the substrate. The active layer is disposed on a side of the first organic dielectric layer away from the substrate. At least a part of the signal lines is exposed by the first organic dielectric layer. The active layer is connected to the exposed signal lines.

[0005] In an exemplary embodiment, the thickness of the first organic dielectric layer is greater than the thickness of the signal lines, and the vertical distance from the surface of the side of the first organic dielectric layer away from the substrate to the surface of the substrate is greater than the vertical distance from the surface of the side of the signal lines away from the substrate to the surface of the substrate.

[0006] In an exemplary embodiment, the thickness of the first organic dielectric layer is less than the thickness of the signal lines, and the vertical distance from the surface of the side of the first organic dielectric layer away from the substrate to the surface of the substrate is less than the vertical distance from the surface of the side of the signal lines away from the substrate to the surface of the substrate.

[0007] In an exemplary embodiment, the thickness of the first organic dielectric layer is greater than half of the thickness of the signal lines.

[0008] In an exemplary embodiment, the thickness of the first organic dielectric layer is substantially the same as the thickness of the signal lines, and the surface of the side of the first organic dielectric layer away from the substrate is substantially flush with the surface of the side of the signal lines away from the substrate.

[0009] In an exemplary embodiment, the thickness of the first organic dielectric layer is greater than or equal to 0.1 micrometer and less than or equal to 2 micrometers.

[0010] In an exemplary embodiment, the active layer is in direct contact with a surface of the first organic dielectric layer away from the substrate.

[0011] In an exemplary embodiment, a buffer layer is provided between the active layer and the first organic dielectric layer. The active layer is in direct contact with a surface of the buffer layer away from the substrate. A first via hole is provided in the buffer layer, and the active layer is connected to the signal line through the first via hole.

[0012] In an exemplary embodiment, a light-shielding layer is further included. The light-shielding layer is provided on a side of the active layer away from the substrate, and a positive projection of the light-shielding layer on the substrate covers a positive projection of the first via hole on the substrate.

[0013] In an exemplary embodiment, an interlayer dielectric layer, a second organic dielectric layer, a first electrode, and a second electrode are further included. The interlayer dielectric layer is provided on a side of the active layer away from the substrate. The second organic dielectric layer is provided on a side of the interlayer dielectric layer away from the substrate. The first electrode is provided on a side of the second organic dielectric layer away from the substrate. The second electrode is provided on a side of the first electrode away from the substrate. A second via hole is provided between the first electrode and the active layer, and the first electrode is connected to the active layer through the second via hole. At least a part of a positive projection of the second electrode on the substrate overlaps with a positive projection of the first electrode on the substrate.

[0014] In an exemplary embodiment, an interlayer dielectric layer, a first electrode, and a second electrode are further included. The first electrode and the active layer are in the same layer and are connected as a whole. The interlayer dielectric layer is provided on a side of the active layer away from the substrate. The second electrode is provided on a side of the interlayer dielectric layer away from the substrate. At least a part of a positive projection of the second electrode on the substrate overlaps with a positive projection of the first electrode on the substrate.

[0015] The embodiment of the present application further provides a method for manufacturing a display backplane, including:

[0016] Forming a signal line, a first organic dielectric layer, and an active layer on a substrate;

[0017] Wherein, the signal line is provided on the substrate, the first organic dielectric layer is provided on a side of the signal line away from the substrate, the active layer is provided on a side of the first organic dielectric layer away from the substrate, at least a part of the signal line is exposed by the first organic dielectric layer, and the active layer is connected to the exposed signal line.

[0018] The embodiment of the present application further provides a display device, including the foregoing display backplane.

[0019] In the display backplane according to the embodiments of the present disclosure, a first organic dielectric layer is formed on the signal line. During the formation process, the first organic dielectric layer can flow. Compared with a buffer layer made of inorganic material, the first organic dielectric layer will not have cracks at the ramp of the signal line, improving the step difference of the signal line and avoiding the breakage of the subsequently formed buffer layer and active layer at the ramp of the signal line.

[0020] In the display backplane according to the embodiments of the present disclosure, the first organic dielectric layer covers the signal line, which can form a flat surface, improving the step difference of the signal line and avoiding the residue of the material for subsequently forming the gate at the ramp of the signal line, preventing the display backplane from short-circuiting.

[0021] In the display backplane according to the embodiments of the present disclosure, the thickness of the first organic dielectric layer is substantially the same as that of the signal line, exposing the surface of the signal line by the first organic dielectric layer. During the formation process, the first organic dielectric layer can flow. Compared with a buffer layer made of inorganic material, the first organic dielectric layer will not have cracks at the ramp of the signal line, improving the step difference of the signal line and avoiding the breakage of the subsequently formed active layer at the ramp of the signal line.

[0022] In the display backplane according to the embodiments of the present disclosure, by directly contacting the active layer with the surface of the signal line, the first via hole between the active layer and the signal line is eliminated, avoiding light leakage of the display backplane caused by the first via hole and simplifying the manufacturing process.

[0023] In the display backplane according to the embodiments of the present disclosure, the thickness of the first organic dielectric layer is less than that of the signal line, exposing the signal line by the first organic dielectric layer. During the formation process, the first organic dielectric layer can flow. Compared with a buffer layer made of inorganic material, the first organic dielectric layer will not have cracks at the ramp of the signal line, improving the step difference of the signal line and avoiding the breakage of the subsequently formed active layer at the ramp of the signal line.

[0024] In the display backplane according to the embodiments of the present disclosure, the first electrode and the active layer are connected as a whole, eliminating the second via hole provided between the first electrode and the active layer, avoiding light leakage of the display backplane caused by the second via hole and simplifying the manufacturing process.

[0025] Other features and advantages of the present application will be described in the subsequent specification, and some of them will become obvious from the specification or be understood by implementing the present application. Other advantages of the present application can be achieved and obtained through the solutions described in the specification and the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The accompanying drawings are used to provide an understanding of the technical solution of the present application and form a part of the specification. Together with the embodiments of the present application, they are used to explain the technical solution of the present application and do not constitute a limitation to the technical solution of the present application.

[0027] Figure 1 It is a schematic cross-sectional structure diagram of a related display backplane;

[0028] Figure 2 It is an enlarged view of the signal line of a related display backplane;

[0029] Figure 3 It is a schematic cross-sectional structure diagram of a display backplane according to an exemplary embodiment of the present disclosure;

[0030] Figure 4a It is a schematic diagram after forming a signal line in the manufacturing process of a display backplane according to an exemplary embodiment of the present disclosure;

[0031] Figure 4b It is a schematic diagram after forming a first organic dielectric layer in the manufacturing process of a display backplane according to an exemplary embodiment of the present disclosure;

[0032] Figure 4c It is a schematic diagram after forming a first insulating layer in the manufacturing process of a display backplane according to an exemplary embodiment of the present disclosure;

[0033] Figure 4d It is a schematic diagram after forming an active layer in the manufacturing process of a display backplane according to an exemplary embodiment of the present disclosure;

[0034] Figure 4e It is a schematic diagram after forming a gate in the manufacturing process of a display backplane according to an exemplary embodiment of the present disclosure;

[0035] Figure 4f It is a schematic diagram after forming a third insulating layer and a second organic dielectric layer in the manufacturing process of a display backplane according to an exemplary embodiment of the present disclosure;

[0036] Figure 4g It is a schematic diagram after forming a connection electrode and a third organic dielectric layer in the manufacturing process of a display backplane according to an exemplary embodiment of the present disclosure;

[0037] Figure 5 It is a schematic cross-sectional structure diagram of another display backplane according to an exemplary embodiment of the present disclosure;

[0038] Figure 6 It is a schematic cross-sectional structure diagram of another display backplane according to an exemplary embodiment of the present disclosure;

[0039] Figure 7 It is a schematic cross-sectional structure diagram of another display backplane according to an exemplary embodiment of the present disclosure;

[0040] Figure 8This is a schematic cross-sectional structure diagram of another display backplane according to an exemplary embodiment of the present disclosure. Detailed implementation manners

[0041] This application describes multiple embodiments, but the description is exemplary rather than restrictive, and it will be apparent to those of ordinary skill in the art that there can be more embodiments and implementation solutions within the scope covered by the embodiments described in this application. Although many possible feature combinations are shown in the drawings and discussed in the detailed implementation manners, many other combination ways of the disclosed features are also possible. Unless specifically restricted, any feature or element of any embodiment can be combined with any other feature or element in any other embodiment, or can replace any other feature or element in any other embodiment.

[0042] This application includes and contemplates combinations with features and elements known to those of ordinary skill in the art. The embodiments, features, and elements already disclosed in this application can also be combined with any conventional features or elements to form a unique inventive solution. Any feature or element of any embodiment can also be combined with features or elements from other inventive solutions to form another unique inventive solution. Therefore, it should be understood that any feature shown and / or discussed in this application can be implemented alone or in any suitable combination. Therefore, except for the limitations made according to the appended claims and their equivalent replacements, the embodiments are not subject to other limitations. In addition, various modifications and changes can be made within the protection scope of the appended claims.

[0043] In addition, when describing representative embodiments, the specification may have presented the method and / or process as a specific sequence of steps. However, to the extent that the method or process does not depend on the specific order of the steps described herein, the method or process should not be limited to the specific order of the steps described. As will be understood by those of ordinary skill in the art, other step sequences are possible. Therefore, the specific order of the steps set forth in the specification should not be construed as a limitation on the claims. In addition, the claims directed to the method and / or process should not be limited to performing their steps in the order written, and those skilled in the art can easily understand that these orders can be changed and still remain within the spirit and scope of the embodiments of this application.

[0044] Figure 1 This is a schematic cross-sectional structure diagram of a related display backplane. As Figure 1As shown, the related display backplane includes signal lines 21' disposed on a substrate 101', a first insulating layer 201' disposed on a side of the signal lines 21' away from the substrate, an active layer 31' disposed on a side of the first insulating layer 201' away from the substrate, a second insulating layer 202' disposed on a side of the active layer 31' away from the substrate, a gate electrode 32' disposed on a side of the second insulating layer 202' away from the substrate, a third insulating layer 203' disposed on a side of the gate electrode 32' away from the substrate, an organic dielectric layer 42' disposed on a side of the third insulating layer 203' away from the substrate, a first electrode 23' disposed on a side of the organic dielectric layer 42' away from the substrate, a fourth insulating layer 204' disposed on a side of the first electrode 23' away from the substrate, a light-shielding layer 24' disposed on a side of the fourth insulating layer 204' away from the substrate, and a second electrode 25' disposed on a side of the light-shielding layer 24' away from the substrate. The first insulating layer 201' is an inorganic material and can serve as a buffer layer. A first via hole V1' is provided in the first insulating layer 201', and the active layer 31' is connected to the signal lines 21' through the first via hole V1'; a second via hole V2' is provided in the organic dielectric layer 42', and the first electrode 23' is connected to the active layer 31' through a connection electrode 22' in the second via hole V2'; a positive projection of the light-shielding layer 24' on the substrate covers a positive projection of the first via hole V1' on the substrate, and the light-shielding layer 24' is used to block light leaking from the first via hole V1'.

[0045] Figure 2 It is an enlarged view of the signal line portion of the related display backplane. Through research by the inventors of the present application, it is found that by disposing the signal lines 21' on a side of the active layer 31' close to the substrate in the related display backplane, light leakage from the first via hole V1' can be reduced. However, as Figure 2 shown, due to the small line width of the signal lines 21', the slope angle of the signal lines 21' will be large, increasing the step difference of the signal lines 21', causing cracks 1' to occur at the climbing portion of the signal lines 21' in the subsequently formed first insulating layer 201' and active layer 31', and causing the material 2' for forming the gate electrode 32' subsequently to remain at the step difference of the signal lines 21', resulting in a short circuit in the display backplane.

[0046] An exemplary embodiment of the present disclosure provides a display backplane, including: a substrate, signal lines, a first organic dielectric layer, and an active layer, the signal lines are disposed on the substrate, the first organic dielectric layer is disposed on a side of the signal lines away from the substrate, the active layer is disposed on a side of the first organic dielectric layer away from the substrate, the first organic dielectric layer exposes at least a part of the signal lines, and the active layer is connected to the exposed signal lines.

[0047] Figure 3 It is a schematic cross-sectional structure diagram of a display backplane according to an exemplary embodiment of the present disclosure. In an exemplary embodiment, as Figure 3As shown, an embodiment of the present disclosure shows that the backplane includes a substrate 101, a signal line 21 disposed on the substrate 101, a first organic dielectric layer 41 disposed on the side of the signal line 21 away from the substrate, a first insulating layer 201 disposed on the side of the first organic dielectric layer 41 away from the substrate, an active layer 31 disposed on the side of the first insulating layer 201 away from the substrate, a second insulating layer 202 disposed on the side of the active layer 31 away from the substrate, a gate 32 disposed on the side of the second insulating layer 202 away from the substrate, a third insulating layer 203 disposed on the side of the gate 32 away from the substrate, an organic dielectric layer 42 disposed on the side of the third insulating layer 203 away from the substrate, a first electrode 23 disposed on the side of the second organic dielectric layer 42 away from the substrate, a fourth insulating layer 204 disposed on the side of the first electrode 23 away from the substrate, a light-shielding layer 24 disposed on the side of the fourth insulating layer 204 away from the substrate, and a second electrode 25 disposed on the side of the light-shielding layer 24 away from the substrate.

[0048] In an exemplary embodiment, the thickness of the first organic dielectric layer 41 is greater than the thickness of the signal line 21, and the perpendicular distance from the surface of the first organic dielectric layer 41 on the side away from the substrate to the surface of the substrate is greater than the perpendicular distance from the surface of the signal line 21 on the side away from the substrate to the surface of the substrate. The first insulating layer 201 is disposed on the surface of the first organic dielectric layer 41 on the side away from the substrate. A first via V1 is provided in the first insulating layer 201. The first via V1 penetrates through the first insulating layer 201 from the surface of the first insulating layer 201 on the side away from the substrate and extends to the surface of the signal line 21, and the first via V1 exposes the surface of the signal line 21. The active layer 31 is in direct contact with the surface of the first insulating layer 201 on the side away from the substrate, and the active layer 31 is connected to the signal line 21 through the first via V1. A second via V2 is provided in the second organic dielectric layer 42. The second via V2 penetrates through the second organic dielectric layer 42, the third insulating layer 203, and the second insulating layer 202 in sequence from the surface of the second organic dielectric layer 42 on the side away from the substrate and extends to the surface of the active layer 31. A connecting electrode 22 and a third organic dielectric layer 43 are provided in the second via V2. One end of the connecting electrode 22 perpendicular to the substrate is connected to the surface of the active layer 31, and the other end of the connecting electrode 22 perpendicular to the substrate is connected to the first electrode 23. The orthographic projection of the light-shielding layer 24 on the substrate covers the orthographic projection of the first via V1 on the substrate, and the light-shielding layer 24 is used to block the light leaking from the first via V1. At least part of the orthographic projection of the second electrode 25 on the substrate overlaps with the orthographic projection of the first electrode 23 on the substrate.

[0049] In an exemplary embodiment, the first insulating layer 201, the second insulating layer 202, the third insulating layer 203, and the fourth insulating layer 204 are all inorganic materials, such as silicon nitride, silicon oxide, etc. Among them, the first insulating layer 201 can also be referred to as a buffer layer, the second insulating layer 202 can also be referred to as a gate insulating layer (GI), and the third insulating layer 203 can also be referred to as an interlayer dielectric layer (ILD).

[0050] In an exemplary embodiment, the first organic dielectric layer 41, the second organic dielectric layer 42, and the third organic dielectric layer 43 can all be silicone oxide or silicone resin. Among them, the second organic dielectric layer 42 can also be referred to as a first planarization layer (PLN1), and the third organic dielectric layer 43 can also be referred to as a second planarization layer (PLN2).

[0051] In an exemplary embodiment, the connection electrode 22, the first electrode 23, and the second electrode 25 can all be light-transmissive conductive materials, such as ITO (indium tin oxide). Among them, the first electrode 23 can also be referred to as a pixel electrode, and the second electrode 25 can also be referred to as a common electrode.

[0052] In the display backplane according to the embodiment of the present disclosure, by forming the first organic dielectric layer 41 on the signal line 21, the first organic dielectric layer 41 can flow during the formation process. Compared with the buffer layer made of inorganic materials, the first organic dielectric layer 41 will not have cracks at the ramp of the signal line 21, improving the step difference of the signal line 21 and avoiding the fracture of the subsequently formed buffer layer and the active layer 31 at the ramp of the signal line 21.

[0053] In the display backplane according to the embodiment of the present disclosure, by covering the signal line 21 with the first organic dielectric layer 41, a flat surface can be formed, improving the step difference of the signal line 21 and avoiding the residue of the material for forming the gate 32 at the ramp of the signal line 21, preventing the display backplane from short-circuiting.

[0054] An exemplary illustration is given below through the preparation process of the display backplane. The "patterning process" mentioned in this disclosure, for metal materials, inorganic materials or transparent conductive materials, includes processes such as coating photoresist, mask exposure, development, etching, and photoresist stripping. For organic materials, it includes processes such as coating organic materials, mask exposure, and development. Deposition can be carried out using any one or more of sputtering, evaporation, and chemical vapor deposition. Coating can be carried out using any one or more of spraying, spin coating, and inkjet printing. Etching can be carried out using any one or more of dry etching and wet etching. This disclosure does not make any limitations. A "thin film" refers to a thin film made of a certain material on a first substrate using deposition, coating, or other processes. If the "thin film" does not require a patterning process during the entire manufacturing process, the "thin film" can also be referred to as a "layer". If the "thin film" requires a patterning process during the entire manufacturing process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern". The statement "A and B are arranged in the same layer" in this disclosure means that A and B are formed simultaneously through the same patterning process. The "thickness" of the film layer is the dimension of the film layer in the direction perpendicular to the display backplane. In the exemplary embodiments of this disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A contains the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0055] In an exemplary embodiment, the preparation process of the display backplane in this embodiment may include the following operations.

[0056] (101) Form signal lines. In an exemplary embodiment, forming signal lines may include: depositing a first conductive thin film on the substrate 101 and patterning the first conductive thin film through a patterning process to form the signal lines 21 disposed on the substrate 101, as Figure 4a shown.

[0057] In an exemplary embodiment, the substrate 101 may be a rigid substrate, such as glass; or the substrate 101 may be a flexible substrate, such as polyimide.

[0058] In an exemplary embodiment, the signal lines 21 may be a single-film layer structure, such as a metal film layer of molybdenum, copper, etc.; or the signal lines 21 may be a multi-film layer structure, such as a titanium / aluminum / titanium triple-layer structure.

[0059] In an exemplary embodiment, the shape of the signal lines 21 is linear, the maximum line width of the signal lines 21 is L, and the range of the maximum line width of the signal lines 21 is: L≤2um.

[0060] (102) Form a first organic dielectric layer. In an exemplary embodiment, forming the first organic dielectric layer may include: on the substrate on which the foregoing pattern is formed, through a spin coating process, form a first organic thin film on the substrate 101, so that the first organic thin film forms a first organic dielectric layer 41 covering the signal line 21, and the first organic dielectric layer 41 covers the side surface of the signal line 21 and the surface of the signal line 21 away from the substrate side, as Figure 4b shown.

[0061] In an exemplary embodiment, the thickness of the first organic dielectric layer 41 is H2, and the thickness of the signal line 21 is H1. The thickness of the first organic dielectric layer 41 and the thickness of the signal line 21 satisfy the relationship: H2 > H1, and the vertical distance from the surface of the first organic dielectric layer 41 away from the substrate to the surface of the substrate is greater than the vertical distance from the surface of the signal line 21 away from the substrate to the surface of the substrate. Wherein, the thickness of the first organic dielectric layer 41 refers to the dimension of the first organic dielectric layer 41 in the direction perpendicular to the substrate, and the thickness of the signal line 21 refers to the dimension of the signal line 21 in the direction perpendicular to the substrate.

[0062] In an exemplary embodiment, the thickness range of the first organic dielectric layer 41 is: 0.1um ≤ H2 ≤ 2um.

[0063] (103) Form a first insulating layer. In an exemplary embodiment, forming the first insulating layer may include: on the substrate on which the foregoing pattern is formed, first, through a chemical vapor deposition process, form a first insulating layer 201 on the first organic dielectric layer 41; subsequently, pattern the first insulating layer 201 through a patterning process, so that a first via V1 is formed in the first insulating layer 201, as Figure 4c shown.

[0064] In an exemplary embodiment, the first insulating layer 201 may be an inorganic material, for example, silicon nitride, silicon oxide, etc.

[0065] In an exemplary embodiment, the orthographic projection of the first via V1 on the substrate is located within the orthographic projection of the signal line 21 on the substrate. The first insulating layer 201 and the first organic dielectric layer 41 in the first via V1 are etched away to expose the surface of the signal line 21. The first via V1 is configured to enable the active layer formed subsequently to be connected to the signal line 21 through this via.

[0066] (104) Form an active layer. In an exemplary embodiment, forming the active layer may include: on the substrate on which the foregoing pattern is formed, deposit a semiconductor thin film on the first insulating layer 201, and pattern the semiconductor thin film through a patterning process to form an active layer 31 disposed on the first insulating layer 201. The first end of the active layer 31 is connected to the signal line 21 through the first via V1, as Figure 4d shown.

[0067] In an exemplary embodiment, the active layer 31 may be made of a metal oxide semiconductor, such as IGZO (indium gallium zinc oxide), etc. In some embodiments, the active layer may be made of low-temperature polycrystalline silicon (LTPS) or amorphous silicon (aSi), which will not be elaborated herein in the present disclosure.

[0068] (105) Form a gate. In an exemplary embodiment, forming the gate may include: on the substrate on which the foregoing pattern is formed, first form a second insulating layer 202 covering the active layer 31 on the first insulating layer 201; subsequently, deposit a second conductive thin film on the second insulating layer 202, and pattern the second conductive thin film through a patterning process to form a gate 32 disposed on the second insulating layer 202, and at least a part of the orthographic projection of the gate 32 on the substrate overlaps with the orthographic projection of the active layer 31 on the substrate, as Figure 4e shown.

[0069] (106) Form a third insulating layer and a second organic dielectric layer. In an exemplary embodiment, forming the third insulating layer and the second organic dielectric layer may include: on the substrate on which the foregoing pattern is formed, first form a third insulating layer 203 covering the gate 32 on the second insulating layer 202; subsequently, deposit a second organic thin film on the third insulating layer 203 to form a second organic dielectric layer 42 disposed on the third insulating layer 203; subsequently, pattern the second organic dielectric layer 42 through a patterning process to form a second via V2 in the second organic dielectric layer 42, as Figure 4f shown.

[0070] In an exemplary embodiment, the orthographic projection of the second via V2 on the substrate is within the range of the orthographic projection of the second end of the active layer 31 on the substrate, the second organic dielectric layer 42, the third insulating layer 203, and the second insulating layer 202 within the second via V2 are etched away to expose the surface of the second end of the active layer 31, and the second via V2 is configured to enable a connection electrode formed subsequently to be connected to the second end of the active layer 31 through this via.

[0071] (107)Form a connection electrode and a third organic dielectric layer. In an exemplary embodiment, forming a connection electrode and a third organic dielectric layer may include: depositing a layer of a third conductive thin film on the second organic dielectric layer 42 on the substrate on which the foregoing pattern is formed, patterning the third conductive thin film through a patterning process to form a connection electrode 22 disposed on the second organic dielectric layer 42, a part of the connection electrode 22 being disposed on the surface of the second organic dielectric layer 42 away from the substrate, a part of the connection electrode 22 covering the second end of the active layer 31 exposed by the second via V2 and the sidewall of the second via V2, and the connection electrode 22 being connected to the second end of the exposed active layer 31 through the second via V2; subsequently, forming a third organic dielectric layer 43 covering the connection electrode 22 in the second via V2, the third organic dielectric layer 43 filling the second via V2, and the surface of the third organic dielectric layer 43 away from the substrate being substantially flush with the surface of the second organic dielectric layer away from the substrate, as Figure 4g shown.

[0072] In an exemplary embodiment, the connection electrode 22 may be made of a light-transmissive conductive material, for example, ITO (indium tin oxide).

[0073] (108)Form a first electrode, a light-shielding layer, and a second electrode. In an exemplary embodiment, forming a first electrode, a light-shielding layer, and a second electrode may include: depositing a layer of a fourth conductive thin film on the second organic dielectric layer 42 on the substrate on which the foregoing pattern is formed, patterning the fourth conductive thin film through a patterning process to form a first electrode 23 disposed on the second organic dielectric layer 42, the first electrode 23 being in direct contact with the connection electrode 22; subsequently, forming a fourth insulating layer 204 covering the first electrode 23 on the second organic dielectric layer 42; subsequently, depositing a layer of a light-shielding thin film on the fourth insulating layer 204, patterning the light-shielding thin film through a patterning process to form a light-shielding layer 24 disposed on the fourth insulating layer 204; subsequently, depositing a layer of a fifth conductive thin film on the fourth insulating layer 204, patterning the fifth conductive thin film through a patterning process to form a second electrode 25 covering the light-shielding layer 24, as Figure 3 shown.

[0074] In an exemplary embodiment, at least a part of the orthographic projection of the first electrode 23 on the substrate overlaps with the orthographic projection of the connection electrode 22 on the surface of the second organic dielectric layer 42 away from the substrate on the substrate, and the first electrode 23 is in direct contact with the connection electrode 22. The first electrode 23 may be made of a light-transmissive conductive material, for example, ITO (indium tin oxide).

[0075] In an exemplary embodiment, the light transmittance of the light-shielding layer 24 to visible light is less than or equal to 10%. At least a part of the orthographic projection of the light-shielding layer 24 on the substrate overlaps with the orthographic projection of the first via V1 on the substrate. For example, the orthographic projection of the light-shielding layer 24 on the substrate covers the orthographic projection of the first via V1 on the substrate. The light-shielding layer 24 is configured to block the light leaking from the first via V1 and prevent light crosstalk between adjacent sub-pixels.

[0076] In an exemplary embodiment, at least a part of the orthographic projection of the second electrode 25 on the substrate overlaps with the orthographic projection of the first electrode 23 on the substrate. At least a part of the orthographic projection of the second electrode 25 on the substrate overlaps with the orthographic projection of the light-shielding layer 24 on the substrate. The second electrode 25 can be made of a transparent conductive material, for example, ITO (indium tin oxide).

[0077] Thus, the preparation of the display backplane of this embodiment is completed on the substrate.

[0078] The preparation process of the embodiment of the present disclosure can be well compatible with the existing preparation process, with simple process implementation, easy to implement, high production efficiency, low production cost, and high yield.

[0079] Figure 5 This is a schematic cross-sectional structure diagram of another display backplane according to an exemplary embodiment of the present disclosure. In an exemplary embodiment, as Figure 5 shown, the structure of the display backplane of this exemplary embodiment is basically the same as that of the display backplane of the embodiment shown in Figure 3 However, the structures of the first organic dielectric layer 41 and the active layer 31 of the display backplane of the embodiment of the present disclosure are different, and the first insulating layer (buffer layer) and the first via are not provided in the display backplane of the embodiment of the present disclosure.

[0080] In an exemplary embodiment, the thickness of the first organic dielectric layer 41 is substantially the same as the thickness of the signal line 21, and the surface of the first organic dielectric layer 41 away from the substrate is substantially flush with the surface of the signal line 21 away from the substrate, forming a plane; the first organic dielectric layer 41 exposes the surface of the signal line 21 away from the substrate. The active layer 31 is disposed on the plane formed by the first organic dielectric layer 41 and the signal line 21. A part of the active layer 31 is in direct contact with the surface of the first organic dielectric layer 41 away from the substrate, and another part of the active layer 31 is in direct contact with the exposed surface of the signal line 21 away from the substrate.

[0081] In the display backplane of the embodiment of the present disclosure, the thickness of the first organic dielectric layer 41 is substantially the same as the thickness of the signal line 21, so that the first organic dielectric layer 41 exposes the surface of the signal line 21. The first organic dielectric layer 41 can flow during the formation process. Compared with a buffer layer made of an inorganic material, the first organic dielectric layer 41 will not crack at the ramp of the signal line 21, improving the step difference of the signal line 21 and preventing the subsequent formed active layer 31 from breaking at the ramp of the signal line 21.

[0082] In the display backplane of the embodiment of the present disclosure, by directly contacting the active layer 31 with the surface of the signal line 21, the first via between the active layer 31 and the signal line 21 is eliminated, avoiding light leakage of the display backplane caused by the first via and simplifying the manufacturing process.

[0083] Figure 6 FIG. is a schematic cross-sectional structure diagram of another display backplane according to an exemplary embodiment of the present disclosure. In the exemplary embodiment, as Figure 6 shown, the structure of the display backplane of the present exemplary embodiment is substantially the same as the structure of the display backplane of the embodiment shown in Figure 3 However, the difference is that the structures of the first organic dielectric layer 41 and the active layer 31 of the display backplane of the embodiment of the present disclosure are different, and the first insulating layer (buffer layer) and the first via are not provided in the display backplane of the embodiment of the present disclosure.

[0084] In the exemplary embodiment, the thickness of the first organic dielectric layer 41 is less than the thickness of the signal line 21, and the vertical distance from the surface of the first organic dielectric layer 41 on the side away from the substrate to the surface of the substrate is less than the vertical distance from the surface of the signal line 21 on the side away from the substrate to the surface of the substrate. The first organic dielectric layer 41 exposes the surface of the signal line 21 on the side away from the substrate and a part of the side surface of the substrate. The active layer 31 is disposed on the surface of the first organic dielectric layer 41 on the side away from the substrate. A part of the active layer 31 is in direct contact with the surface of the first organic dielectric layer 41 on the side away from the substrate, and another part of the active layer 31 is in direct contact with at least a part of the exposed signal line 21.

[0085] In the exemplary embodiment, the thickness of the first organic dielectric layer 41 is greater than half of the thickness of the signal line 21, which can effectively improve the step difference of the signal line 21 and prevent the subsequent formed active layer 31 from breaking at the ramp of the signal line 21.

[0086] In the display backplane according to an embodiment of the present disclosure, the thickness of the first organic dielectric layer 41 is less than that of the signal line 21, so that the first organic dielectric layer 41 exposes the signal line 21. The first organic dielectric layer 41 can flow during the formation process. Compared with a buffer layer made of an inorganic material, the first organic dielectric layer 41 will not have cracks at the ramp of the signal line 21, improving the step difference of the signal line 21 and avoiding breakage of the subsequently formed active layer 31 at the ramp of the signal line 21.

[0087] In the display backplane according to an embodiment of the present disclosure, by directly contacting the active layer 31 with the signal line 21, the first via hole between the active layer 31 and the signal line 21 is eliminated, avoiding light leakage of the display backplane caused by the first via hole and simplifying the manufacturing process.

[0088] Figure 7 It is a schematic cross-sectional structure diagram of another display backplane according to an exemplary embodiment of the present disclosure. In the exemplary embodiment, as Figure 7 shown, the structure of the display backplane of the present exemplary embodiment is basically the same as that of the display backplane of the embodiment shown in Figure 3 However, the difference is that the first electrode 23 of the display backplane according to the embodiment of the present disclosure is on the same layer as the active layer 31 and is connected into one body, and the second organic dielectric layer, the second via hole, the connection electrode, the third organic dielectric layer and the fourth insulating layer are not provided in the display backplane according to the embodiment of the present disclosure.

[0089] In the exemplary embodiment, the first electrode 23 is connected to one end of the active layer 31 away from the first via hole V1 and can be formed by the same manufacturing process as the active layer 31. The gate 32 is disposed on the side of the active layer 31 away from the substrate, the third insulating layer 203 is disposed on the side of the gate 32 away from the substrate, and the light-shielding layer 24 and the second electrode 25 are disposed on the side of the third insulating layer 203 away from the substrate, and both the light-shielding layer 24 and the second electrode 25 are in direct contact with the surface of the third insulating layer 203 on the side away from the substrate.

[0090] In the display backplane according to an embodiment of the present disclosure, by connecting the first electrode and the active layer into one body, the second via hole provided between the first electrode and the active layer is eliminated, avoiding light leakage of the display backplane caused by the second via hole and simplifying the manufacturing process.

[0091] Figure 8 It is a schematic cross-sectional structure diagram of another display backplane according to an exemplary embodiment of the present disclosure. In the exemplary embodiment, as Figure 8 shown, the structure of the display backplane of the present exemplary embodiment is the same as that of the display backplane shown in Figure 5The structures of the display backplanes shown in the embodiments are basically the same. The difference is that in the embodiments of the present disclosure, the first electrode 23 of the display backplane is located in the same layer as the active layer 31 and is connected as a whole. In the embodiments of the present disclosure, the second organic dielectric layer, the second via, the connection electrode, the third organic dielectric layer, and the fourth insulating layer are not provided in the display backplane.

[0092] In an exemplary embodiment, the first electrode 23 is connected as a whole to one end of the active layer 31 away from the first via V1, and can be fabricated by the same fabrication process as the active layer 31. The gate 32 is disposed on a side of the active layer 31 away from the substrate, the third insulating layer 203 is disposed on a side of the gate 32 away from the substrate, and the light-shielding layer 24 and the second electrode 25 are disposed on a side of the third insulating layer 203 away from the substrate, and both the light-shielding layer 24 and the second electrode 25 are in direct contact with the surface of the third insulating layer 203 on the side away from the substrate.

[0093] In the display backplane of the embodiments of the present disclosure, the first electrode is connected to the active layer as a whole, eliminating the second via disposed between the first electrode and the active layer, avoiding light leakage of the display backplane caused by the second via, and simplifying the fabrication process.

[0094] The embodiments of the present disclosure provide a method for fabricating a display backplane, including:

[0095] Forming a signal line, a first organic dielectric layer, and an active layer on a substrate;

[0096] Wherein, the signal line is disposed on the substrate, the first organic dielectric layer is disposed on a side of the signal line away from the substrate, the active layer is disposed on a side of the first organic dielectric layer away from the substrate, the first organic dielectric layer exposes at least a part of the signal line, and the active layer is connected to the exposed signal line.

[0097] The embodiments of the present disclosure provide a display device, including any one of the display backplanes described above. The display device includes VR / AR display devices, mobile phones, tablet computers, smart wearable products (such as smart watches, bracelets, etc.), personal digital assistants (PDAs), in-vehicle computers, etc. The embodiments of the present application do not make special limitations on the specific forms of the above display devices.

[0098] In the description of the present application, it should be understood that the orientation or positional relationship indicated by the terms "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc. is based on the orientation or positional relationship shown in the drawings. It is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as a limitation on the present application.

[0099] In addition, the terms "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first", "second", etc. may explicitly or implicitly include at least one such feature.

[0100] In the description of the present application, the meaning of "a plurality of" is at least two, such as two, three, etc., unless otherwise specifically and clearly defined.

[0101] In the present application, unless otherwise clearly specified and defined, the terms "mounted", "connected", "coupled", "fixed", etc. shall be understood in a broad sense. For example, "connected" may be a fixed connection, a detachable connection, or an integral body; it may be a mechanical connection or an electrical connection; it may be directly connected or indirectly connected through an intermediate medium, and it may be the communication inside two elements or the interaction relationship between two elements, unless otherwise clearly defined. For those of ordinary skill in the art, the specific meanings of the above terms in the present application can be understood according to specific circumstances.

[0102] In the present application, unless otherwise clearly specified and defined, the first feature being "on" or "under" the second feature may be that the first and second features are in direct contact, or the first feature and the second feature are in indirect contact through an intermediate medium. Moreover, the first feature being "above", "over" and "on top of" the second feature may be that the first feature is directly above or obliquely above the second feature, or merely indicates that the first feature has a higher horizontal height than the second feature. The first feature being "under", "beneath" and "underneath" the second feature may be that the first feature is directly below or obliquely below the second feature, or merely indicates that the first feature has a lower horizontal height than the second feature.

[0103] In the description of this specification, the descriptions referring to terms such as "one embodiment", "some embodiments", "examples", "specific examples", or "some examples" etc. mean that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of this application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in a suitable manner in any one or more embodiments or examples. In addition, without contradiction, those skilled in the art can combine and combine the different embodiments or examples described in this specification and the features of different embodiments or examples.

[0104] Although the embodiments of this application have been shown and described above, it can be understood that the above embodiments are exemplary and should not be construed as limiting this application. Those of ordinary skill in the art can make changes, modifications, substitutions, and variations to the above embodiments within the scope of this application.

Claims

1. A display backplane, characterized in that: include: A substrate, a signal line, a first organic dielectric layer and an active layer, wherein the signal line is arranged on the substrate, the first organic dielectric layer is arranged on a side of the signal line away from the substrate, the active layer is arranged on a side of the first organic dielectric layer away from the substrate, the first organic dielectric layer exposes at least part of the signal line, and the active layer is connected to the exposed signal line.

2. The display backplane according to claim 1, characterized in that: The thickness of the first organic medium layer is greater than the thickness of the signal line, and the vertical distance from the surface of the first organic medium layer away from the substrate to the surface of the substrate is greater than the vertical distance from the surface of the signal line away from the substrate to the surface of the substrate.

3. The display backplane according to claim 1, characterized in that: The thickness of the first organic medium layer is smaller than the thickness of the signal line, and the vertical distance from the surface of the first organic medium layer away from the substrate to the surface of the substrate is smaller than the vertical distance from the surface of the signal line away from the substrate to the surface of the substrate.

4. The display backplane according to claim 3, characterized in that: The thickness of the first organic medium layer is greater than half of the thickness of the signal line.

5. The display backplane according to claim 1, characterized in that: The thickness of the first organic medium layer is substantially the same as that of the signal line, and a surface of the first organic medium layer away from the substrate is substantially flush with a surface of the signal line away from the substrate.

6. The display backplane according to claim 1, characterized in that: The thickness of the first organic medium layer is greater than or equal to 0.1 micrometers and less than or equal to 2 micrometers.

7. The display backplane according to any one of claims 1 to 6, characterized in that: The active layer is in direct contact with a surface of the first organic medium layer that is away from the substrate.

8. The display backplane according to any one of claims 1 to 6, characterized in that: A buffer layer is provided between the active layer and the first organic medium layer. The active layer is in direct contact with a surface of the buffer layer away from the substrate. A first via hole is provided in the buffer layer. The active layer is connected to the signal line through the first via hole.

9. The display backplane according to claim 8, characterized in that: It also includes a light shielding layer, which is arranged on a side of the active layer away from the substrate, and the orthographic projection of the light shielding layer on the substrate covers the orthographic projection of the first via hole on the substrate.

10. The display backplane according to any one of claims 1 to 6, characterized in that: It also includes an interlayer dielectric layer, a second organic dielectric layer, a first electrode and a second electrode, wherein the interlayer dielectric layer is arranged on a side of the active layer away from the substrate, the second organic dielectric layer is arranged on a side of the interlayer dielectric layer away from the substrate, the first electrode is arranged on a side of the second organic dielectric layer away from the substrate, the second electrode is arranged on a side of the first electrode away from the substrate, a second via hole is arranged between the first electrode and the active layer, the first electrode is connected to the active layer through the second via hole, and an orthographic projection of the second electrode on the substrate at least partially overlaps with an orthographic projection of the first electrode on the substrate.

11. The display backplane according to any one of claims 1 to 6, characterized in that: It also includes an interlayer dielectric layer, a first electrode and a second electrode, wherein the first electrode and the active layer are located in the same layer and are connected as a whole, the interlayer dielectric layer is arranged on a side of the active layer away from the substrate, the second electrode is arranged on a side of the interlayer dielectric layer away from the substrate, and the orthographic projection of the second electrode on the substrate overlaps at least partially with the orthographic projection of the first electrode on the substrate.

12. A method for preparing a display backplane, characterized in that: include: forming a signal line, a first organic medium layer and an active layer on a substrate; The signal line is arranged on the substrate, the first organic medium layer is arranged on a side of the signal line away from the substrate, the active layer is arranged on a side of the first organic medium layer away from the substrate, the first organic medium layer exposes at least part of the signal line, and the active layer is connected to the exposed signal line.

13. A display device, characterized in that: The invention comprises the display back panel as described in any one of claims 1 to 11.

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