Display panel and display device

Abstract

The invention discloses a display panel and a display device, and relates to the technical field of display. The method. The second cathode layer of the display panel is provided with the hollow area, so that the second cathode layer cannot cover the whole second display area. Compared with the cathode layer covering the whole second display area, the influence on the light transmittance can be effectively reduced, and the imaging effect of the camera located in the second display area is good.

Description

[0001] This application is a divisional application of a Chinese application with application number 202180000308.4, application date February 24, 2021, and invention title "Display Panel and Its Manufacturing Method, Display Device". Technical Field

[0002] This application relates to the field of display technologies, and particularly to a display panel and a display device. Background Art

[0003] Organic light-emitting diode (OLED) display panels have been widely used due to advantages such as self-luminescence, low driving voltage, and fast response speed. Summary of the Invention

[0004] This application provides a display panel and a display device, which can solve the problem of poor imaging effect of the camera in the display panel in the related art. The technical solution is as follows:

[0005] On the one hand, a display panel is provided. The display panel includes:

[0006] A substrate, which has a first display area and a second display area;

[0007] A first auxiliary electrode layer, a first anode layer, a first light-emitting layer, and a first cathode layer, which are located in the first display area and are stacked in sequence in a direction away from the substrate;

[0008] A second auxiliary electrode layer, a second anode layer, a second light-emitting layer, and a second cathode layer, which are located in the second display area and are stacked in sequence in a direction away from the substrate;

[0009] Wherein, the first auxiliary electrode layer is connected to the first cathode layer, the second auxiliary electrode layer is connected to the first auxiliary electrode layer, the second cathode layer is connected to the first cathode layer, and the second cathode layer has at least one hollowed-out area;

[0010] The display panel further includes a plurality of pixel circuits located in the second display area. Each pixel circuit includes at least one layer of opaque pattern; wherein, the second auxiliary electrode layer includes: a plurality of electrically connected auxiliary electrode patterns, and at least 50% of the orthographic projection area of at least one layer of opaque pattern in at least one pixel circuit on the substrate overlaps with the orthographic projection of the auxiliary electrode pattern on the substrate.

[0011] Optionally, the positive projection of the auxiliary electrode pattern on the substrate covers the positive projection of at least one layer of opaque pattern in at least one of the pixel circuits on the substrate.

[0012] Optionally, at least part of the edge of the positive projection of the auxiliary electrode pattern on the substrate is arc-shaped.

[0013] Optionally, the auxiliary electrode pattern includes: a first pattern and a second pattern;

[0014] The positive projection of the first pattern on the substrate overlaps with more than 50% of the positive projection area of at least one layer of opaque pattern in at least one of the pixel circuits on the substrate;

[0015] The second pattern is used for electrically connecting with the adjacent auxiliary electrode pattern.

[0016] Optionally, the shape of the positive projection of the first pattern on the substrate is circular.

[0017] Optionally, the substrate further has a peripheral area surrounding the first display area and the second display area;

[0018] The first auxiliary electrode layer and the first cathode layer are also located in the peripheral area, and the part of the first auxiliary electrode layer located in the peripheral area is electrically connected to the part of the first cathode layer located in the peripheral area.

[0019] Optionally, the positive projection of the first auxiliary electrode layer on the substrate covers the first display area;

[0020] The peripheral area includes: a first area and a second area arranged oppositely and parallelly, and a third area and a fourth area arranged oppositely and parallelly. The extending direction of the first area is perpendicular to the extending direction of the third area, and the distance between the second display area and the first area is less than the distance between the second display area and the second area;

[0021] Wherein, the part of the first auxiliary electrode layer located in the first area is connected to the part of the first cathode layer located in the first area, the part of the first auxiliary electrode layer located in the third area is connected to the part of the first cathode layer located in the third area, and the part of the first auxiliary electrode layer located in the fourth area is connected to the part of the first cathode layer located in the fourth area;

[0022] The part of the first auxiliary electrode layer located in the second area is not connected to the part of the first cathode layer located in the second area.

[0023] Optionally, multiple of the auxiliary electrode patterns overlap each other.

[0024] Optionally, the display panel further includes: a plurality of first connection electrodes located in the second display area, and the plurality of auxiliary electrode patterns are electrically connected through the plurality of first connection electrodes.

[0025] Optionally, the display panel further includes: an active layer, a buffer layer, a first gate insulating layer, a first gate layer, a second gate insulating layer, a second gate layer, an interlayer dielectric layer, and a first source-drain layer that are sequentially stacked in the first display area and the second display area in a direction away from the substrate;

[0026] The first source-drain layer includes multiple groups of first source-drain layer patterns corresponding to each pixel circuit; the active layer includes multiple groups of active patterns corresponding to each pixel circuit, the first gate layer includes multiple groups of first gate layer patterns corresponding to each pixel circuit, and the second gate layer includes multiple groups of second gate layer patterns corresponding to each pixel circuit;

[0027] At least one opaque pattern of the pixel circuit includes: a group of the first source-drain layer patterns located in the first source-drain layer, a group of the active patterns located in the active layer, a group of the first gate patterns located in the first gate layer, and a group of the second gate patterns located in the second gate layer.

[0028] Optionally, the display panel further includes: a first conductive layer in the same layer as the first source-drain layer, and a second conductive layer in the same layer as the second gate layer; the buffer layer, the first gate insulating layer, the second gate insulating layer, and the interlayer dielectric layer all have first vias; the second conductive layer and the first conductive layer are electrically connected to the auxiliary electrode pattern through the first vias;

[0029] The display panel further includes a passivation layer and a first planarization layer on a side of the first source-drain layer away from the substrate, and a plurality of first connection electrodes between the passivation layer and the first planarization layer;

[0030] The passivation layer has second vias, at least part of the first connection electrodes is located in the second vias and is connected to the first conductive layer; the plurality of first connection electrodes are used to connect the plurality of auxiliary electrode patterns.

[0031] Optionally, the display panel further includes: a passivation layer and a first planarization layer on a side of the first source-drain layer away from the substrate, a plurality of second connection electrodes between the passivation layer and the first planarization layer, a first signal transmission layer in the same layer as the first source-drain layer, and a third conductive layer in the same layer as the first gate layer;

[0032] The first gate insulating layer, the second gate insulating layer, and the interlayer dielectric layer each have a third via; the first signal transmission layer is electrically connected to the third conductive layer through the third via;

[0033] The passivation layer has a fourth via, and at least a part of the second connection electrode is located in the fourth via and is connected to the first signal transmission layer.

[0034] Optionally, the third conductive layer includes: a plurality of first signal line segments, a plurality of second signal line segments, and a plurality of third signal line segments;

[0035] Wherein, each of the signal line segments among the plurality of first signal line segments, the plurality of second signal line segments, and the plurality of third signal line segments is connected to one of the pixel circuits;

[0036] The plurality of second connection electrodes includes: a plurality of first-type second connection electrodes connecting the plurality of first signal line segments, a plurality of second-type second connection electrodes connecting the plurality of second signal line segments, and a plurality of third-type second connection electrodes connecting the plurality of third signal line segments.

[0037] Optionally, the plurality of first signal line segments are gate signal line segments for transmitting gate signals, the plurality of second signal line segments are reset control signal line segments for transmitting reset control signals, and the plurality of third signal line segments are light emission control signal line segments for transmitting light emission control signals.

[0038] Optionally, the display panel further includes: a plurality of third connection electrodes, and a fourth conductive layer; the fourth conductive layer includes a plurality of fourth signal line segments;

[0039] Wherein, each of the fourth signal line segments is connected to at least one of the pixel circuits, and at least a part of the fourth signal line segments among the plurality of fourth signal line segments are electrically connected through at least a part of the third connection electrodes.

[0040] Optionally, the display panel further includes a passivation layer and a first planarization layer on a side of the first source-drain layer away from the substrate, and a second source-drain layer on a side of the first planarization layer away from the first source-drain layer; the fourth conductive layer is on the same layer as the first source-drain layer, and the plurality of third connection electrodes are between the passivation layer and the first planarization layer; the display panel further includes: a fifth conductive layer on the same layer as the second source-drain layer, the fifth conductive layer includes a plurality of fifth signal line segments; the passivation layer has a fifth via;

[0041] At least a part of the third connection electrode is located in the fifth via hole and is connected to the fourth signal line segment. The first planar layer has a sixth via hole. At least a part of the fifth signal line segment is located in the sixth via hole and is connected to the third connection electrode.

[0042] Optionally, the multiple fourth signal line segments and the multiple fifth signal line segments are both positive power supply signal line segments for transmitting positive power supply signals.

[0043] Optionally, the fourth conductive layer is in the same layer as the first source-drain layer, and the multiple third connection electrodes are located between the passivation layer and the first planar layer; the passivation layer has a seventh via hole;

[0044] At least a part of the third connection electrode is located in the seventh via hole and is connected to the fourth signal line segment.

[0045] Optionally, the multiple fourth signal line segments are data signal line segments for transmitting data signals.

[0046] Optionally, the fourth conductive layer is in the same layer as the second gate layer, and the multiple third connection electrodes are located between the passivation layer and the first planar layer; the display panel further includes: a second signal transmission layer in the same layer as the first source-drain layer; an eighth via hole is formed in the second gate insulating layer and the interlayer dielectric layer; the second signal transmission layer is located in the eighth via hole, and the second signal transmission layer is connected to the fourth signal line segment;

[0047] The passivation layer has a ninth via hole. At least a part of the third connection electrode is located in the ninth via hole and is connected to the second signal transmission layer.

[0048] Optionally, the multiple fourth signal line segments are initialization signal line segments for transmitting initialization signals.

[0049] Optionally, the display panel further includes: an active layer, a buffer layer, a first gate insulating layer, a first gate layer, a second gate insulating layer, a second gate layer, an interlayer dielectric layer, a first source-drain layer, a passivation layer, and a first planarization layer that are located in the first display area and the second display area and are stacked in sequence in a direction away from the substrate; the display panel further includes a plurality of connection electrodes located between the passivation layer and the first planarization layer; at least some of the plurality of connection electrodes are used to electrically connect at least one of the first gate layer, the second gate layer, and the first source-drain layer in the first display area and at least one of the first gate layer, the second gate layer, and the first source-drain layer in the second display area, and / or, at least some of the plurality of connection electrodes are used to electrically connect at least two of the auxiliary electrode patterns located in the second display area, and / or, at least some of the plurality of connection electrodes are used to connect at least one layer of opaque patterns in at least two of the pixel circuits in the second display area;

[0050] Wherein, the plurality of connection electrodes have a plurality of connection points, the connection points include connection vias or overlapping structures corresponding to the respective patterns to which the plurality of connection electrodes are connected, and an overlapping area exists between the orthographic projection of the auxiliary electrode pattern on the substrate and the orthographic projection of at least one of the connection points on the substrate.

[0051] Optionally, the orthographic projection of the auxiliary electrode pattern on the substrate covers the orthographic projection of at least one of the connection points on the substrate.

[0052] Optionally, the second anode layer includes a plurality of anode patterns arranged at intervals; the display panel further includes: a pixel defining layer located on a side of the second anode layer away from the substrate;

[0053] The pixel defining layer has a plurality of tenth vias, and the tenth vias expose the corresponding anode patterns; the second light-emitting layer includes: a plurality of light-emitting layer patterns, and at least part of the light-emitting layer patterns are located in the tenth vias;

[0054] The second cathode layer at least partially covers the tenth vias, and at least one hollowed-out area of the second cathode layer does not overlap with the tenth vias.

[0055] Optionally, at least part of the boundary of the at least one hollowed-out area includes an arc.

[0056] Optionally, the first cathode layer and the second cathode layer are of an integral structure.

[0057] Optionally, the area of the overlapping part of the orthographic projection of the hollowed-out area on the substrate and the orthographic projection of the auxiliary electrode pattern on the substrate is less than 10% of the area of the hollowed-out area.

[0058] On the other hand, a method for manufacturing a display panel is provided. The method includes:

[0059] Providing a substrate, the substrate having a first display area and a second display area;

[0060] Forming a first auxiliary electrode layer, a first anode layer, a first light-emitting layer, and a first cathode layer that are sequentially stacked in the first display area;

[0061] Forming a second auxiliary electrode layer, a second anode layer, a second light-emitting layer, and a second cathode layer that are sequentially stacked in the second display area;

[0062] Forming a plurality of pixel circuits in the second display area;

[0063] Wherein, the first auxiliary electrode layer is connected to the first cathode layer, the second auxiliary electrode layer is connected to the first auxiliary electrode layer, the second cathode layer is connected to the first cathode layer, and the second cathode layer has at least one hollowed-out area; the second auxiliary electrode layer includes: a plurality of electrically connected auxiliary electrode patterns; at least 50% of the orthographic projection area of at least one opaque pattern in at least one of the pixel circuits on the substrate overlaps with the orthographic projection of one of the auxiliary electrode patterns on the substrate.

[0064] In yet another aspect, a display device is provided. The display device includes: an image sensor and a display panel as described in the above aspect;

[0065] The image sensor is located on a side of the substrate in the display panel away from the second anode layer and overlaps with the second display area of the substrate. Description of the Drawings

[0066] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following drawings are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0067] Figure 1 It is a schematic structural diagram of a display panel provided by an embodiment of the present application;

[0068] Figure 2 It is a top view of a substrate provided by an embodiment of the present application;

[0069] Figure 3 It is a schematic structural diagram of another display panel provided by an embodiment of the present application;

[0070] Figure 4 It is a top view of a display panel provided by an embodiment of the present application;

[0071] Figure 5 It is Figure 4 a schematic structural diagram of an auxiliary electrode pattern in

[0072] Figure 6 It is a top view of a display panel without an auxiliary electrode pattern provided by an embodiment of the present application;

[0073] Figure 7 It is a schematic diagram of a diffraction simulation test on the display panel shown in Figure 6 ;

[0074] Figure 8 It is a schematic diagram of a diffraction simulation test on the display panel shown in Figure 4 ;

[0075] Figure 9 It is a cross-sectional view of a display panel provided by an embodiment of the present application;

[0076] Figure 10 It is a cross-sectional view of another display panel provided by an embodiment of the present application;

[0077] Figure 11 It is a cross-sectional view of yet another display panel provided by an embodiment of the present application;

[0078] Figure 12 It is a cross-sectional view of still another display panel provided by an embodiment of the present application;

[0079] Figure 13 It is a cross-sectional view of still another display panel provided by an embodiment of the present application;

[0080] Figure 14 It is a top view of another display panel provided by an embodiment of the present application;

[0081] Figure 15 It is a cross-sectional view of still another display panel provided by an embodiment of the present application;

[0082] Figure 16 It is a schematic diagram of an auxiliary electrode pattern and a second cathode layer provided by an embodiment of the present application;

[0083] Figure 17 It is an equivalent circuit diagram of a pixel circuit provided by an embodiment of the present application;

[0084] Figure 18 It is a plan view of a sub-pixel in a first display area provided by an embodiment of the present application;

[0085] Figure 19 It is Figure 18Planar view of the active layer of sub-pixels included in one repeating unit;

[0086] Figure 20 is Figure 18 Planar view of the combination of the active layer and the first gate layer of sub-pixels included in one repeating unit;

[0087] Figure 21 is Figure 18 Planar view of the combination of the active layer and the first gate layer of sub-pixels included in one repeating unit;

[0088] Figure 22 is Figure 18 Planar view of the combination of the active layer, the first gate layer, the second gate layer, and the first source-drain layer of sub-pixels included in one repeating unit;

[0089] Figure 23 is Figure 18 Planar view of the combination of the active layer, the first gate layer, the second gate layer, the first source-drain layer, and the second source-drain layer of sub-pixels included in one repeating unit;

[0090] Figure 24 is Figure 18 Planar view of the combination of the active layer, the first gate layer, the second gate layer, the first source-drain layer, and the second source-drain layer of sub-pixels included in one repeating unit;

[0091] Figure 25 is Figure 18 Planar view of the combination of the active layer, the first gate layer, the second gate layer, the first source-drain layer, the second source-drain layer, and the first anode layer of sub-pixels included in one repeating unit;

[0092] Figure 26 Equivalent circuit diagram of another pixel circuit provided by an embodiment of the present application;

[0093] Figure 27 Planar view of sub-pixels in a second display area provided by an embodiment of the present application;

[0094] Figure 28 is Figure 27 Planar view of the active layer of sub-pixels included in one repeating unit;

[0095] Figure 29 is Figure 27 Planar view of the combination of the active layer and the first gate layer of sub-pixels included in one repeating unit;

[0096] Figure 30 is Figure 27 Planar view of the combination of the active layer, the first gate layer, and the second gate layer of sub-pixels included in one repeating unit;

[0097] Figure 31 is Figure 27 A plan view of a combination of an active layer, a first gate layer, a second gate layer, and a first source-drain layer of sub-pixels included in one repeating unit;

[0098] Figure 32 is Figure 27 A plan view of a combination of an active layer, a first gate layer, a second gate layer, a first source-drain layer, and a connecting electrode film layer of sub-pixels included in one repeating unit;

[0099] Figure 33 is Figure 27 A plan view of a combination of active layers, first gate layers, second gate layers, first source-drain layers, and connecting electrode film layers of three sub-pixels included in one repeating unit;

[0100] Figure 34 is Figure 27 A plan view of a combination of an active layer, a first gate layer, a second gate layer, a first source-drain layer, a connecting electrode film layer, and a second source-drain layer of sub-pixels included in one repeating unit;

[0101] Figure 35 is Figure 27 A plan view of a combination of an active layer, a first gate layer, a second gate layer, a first source-drain layer, a connecting electrode film layer, a second source-drain layer, and a second anode layer of one sub-pixel included in one repeating unit;

[0102] Figure 36 is Figure 27 A plan view of a combination of an active layer, a first gate layer, a second gate layer, a first source-drain layer, a connecting electrode film layer, a second source-drain layer, and a second anode layer of another sub-pixel included in one repeating unit;

[0103] Figure 37 is Figure 27 A plan view of a combination of an active layer, a first gate layer, a second gate layer, a first source-drain layer, a connecting electrode film layer, a second source-drain layer, and a second anode layer of yet another sub-pixel included in one repeating unit;

[0104] Figure 38 A flowchart of a method for manufacturing a display panel provided by an embodiment of the present application;

[0105] Figure 39 A flowchart of another method for manufacturing a display panel provided by an embodiment of the present application;

[0106] Figure 40 A schematic diagram of a first auxiliary electrode layer and a second auxiliary electrode layer provided by an embodiment of the present application;

[0107] Figure 41It is a schematic structural diagram of an active layer provided by an embodiment of the present application;

[0108] Figure 42 It is a schematic diagram of forming an active layer in a second display area provided by an embodiment of the present application;

[0109] Figure 43 It is a schematic diagram of forming an active layer in a first display area provided by an embodiment of the present application;

[0110] Figure 44 It is a schematic diagram of forming an active layer in a first display area and a second display area provided by an embodiment of the present application;

[0111] Figure 45 It is a schematic structural diagram of a first gate layer provided by an embodiment of the present application;

[0112] Figure 46 It is a schematic diagram of forming a first gate layer in a second display area provided by an embodiment of the present application;

[0113] Figure 47 It is a schematic diagram of forming a first gate layer in a first display area provided by an embodiment of the present application;

[0114] Figure 48 It is a schematic diagram of forming a first gate layer in a first display area and a second display area provided by an embodiment of the present application;

[0115] Figure 49 It is a schematic structural diagram of a first gate insulating layer provided by an embodiment of the present application;

[0116] Figure 50 It is a schematic diagram of forming a first gate insulating layer in a second display area provided by an embodiment of the present application;

[0117] Figure 51 It is a schematic diagram of forming a first gate insulating layer in a first display area and a second display area provided by an embodiment of the present application;

[0118] Figure 52 It is a schematic structural diagram of a second gate layer provided by an embodiment of the present application;

[0119] Figure 53 It is a schematic diagram of forming a second gate layer in a second display area provided by an embodiment of the present application;

[0120] Figure 54 It is a schematic diagram of forming a second gate layer in a first display area provided by an embodiment of the present application;

[0121] Figure 55Schematic diagram of forming a second gate layer in a first display area and a second display area provided by an embodiment of the present application;

[0122] Figure 56 Schematic diagram of the structure of an interlayer dielectric layer provided by an embodiment of the present application;

[0123] Figure 57 Schematic diagram of forming an interlayer dielectric layer in a second display area provided by an embodiment of the present application;

[0124] Figure 58 Schematic diagram of forming an interlayer dielectric layer in a first display area provided by an embodiment of the present application;

[0125] Figure 59 Schematic diagram of forming an interlayer dielectric layer in a first display area and a second display area provided by an embodiment of the present application;

[0126] Figure 60 Schematic diagram of the structure of a first source-drain layer provided by an embodiment of the present application;

[0127] Figure 61 Schematic diagram of forming a first source-drain layer in a second display area provided by an embodiment of the present application;

[0128] Figure 62 Schematic diagram of forming a first source-drain layer in a first display area provided by an embodiment of the present application;

[0129] Figure 63 Schematic diagram of forming a first source-drain layer in a first display area and a second display area provided by an embodiment of the present application;

[0130] Figure 64 Schematic diagram of the structure of a passivation layer provided by an embodiment of the present application;

[0131] Figure 65 Schematic diagram of forming a passivation layer in a second display area provided by an embodiment of the present application;

[0132] Figure 66 Schematic diagram of forming a passivation layer in a first display area provided by an embodiment of the present application;

[0133] Figure 67 Schematic diagram of forming a passivation layer in a first display area and a second display area provided by an embodiment of the present application;

[0134] Figure 68 Schematic diagram of the structure of a connecting electrode film layer provided by an embodiment of the present application;

[0135] Figure 69Schematic diagram of forming a connecting electrode film layer in a second display area provided by an embodiment of the present application;

[0136] Figure 70 Schematic diagram of forming a connecting electrode film layer in a first display area provided by an embodiment of the present application;

[0137] Figure 71 Schematic diagram of forming a connecting electrode film layer in a first display area and a second display area provided by an embodiment of the present application;

[0138] Figure 72 Schematic diagram of the structure of a first planarization layer provided by an embodiment of the present application;

[0139] Figure 73 Schematic diagram of forming a first planarization layer in a second display area provided by an embodiment of the present application;

[0140] Figure 74 Schematic diagram of forming a first planarization layer in a first display area provided by an embodiment of the present application;

[0141] Figure 75 Schematic diagram of forming a first planarization layer in a first display area and a second display area provided by an embodiment of the present application;

[0142] Figure 76 Schematic diagram of the structure of a second source-drain layer provided by an embodiment of the present application;

[0143] Figure 77 Schematic diagram of forming a second source-drain layer in a second display area provided by an embodiment of the present application;

[0144] Figure 78 Schematic diagram of forming a second source-drain layer in a first display area provided by an embodiment of the present application;

[0145] Figure 79 Schematic diagram of forming a second source-drain layer in a first display area and a second display area provided by an embodiment of the present application;

[0146] Figure 80 Schematic diagram of the structure of a second planarization layer provided by an embodiment of the present application;

[0147] Figure 81 Schematic diagram of forming a second planarization layer in a second display area provided by an embodiment of the present application;

[0148] Figure 82 Schematic diagram of forming a second planarization layer in a first display area provided by an embodiment of the present application;

[0149] Figure 83Schematic diagram of forming a second planarization layer in a first display region and a second display region provided by an embodiment of the present application;

[0150] Figure 84 Schematic diagram of a first anode layer and a second anode layer provided by an embodiment of the present application;

[0151] Figure 85 Schematic diagram of forming a second anode layer in a second display region provided by an embodiment of the present application;

[0152] Figure 86 Schematic diagram of forming a first anode layer in a first display region provided by an embodiment of the present application;

[0153] Figure 87 Schematic diagram of forming a first anode layer in a first display region and forming a second anode layer in a second display region provided by an embodiment of the present application;

[0154] Figure 88 Schematic diagram of the structure of a pixel defining layer provided by an embodiment of the present application;

[0155] Figure 89 Schematic diagram of forming a pixel defining layer in a second display region provided by an embodiment of the present application;

[0156] Figure 90 Schematic diagram of forming a pixel defining layer in a first display region provided by an embodiment of the present application;

[0157] Figure 91 Schematic diagram of forming a pixel defining layer in a first display region and a second display region provided by an embodiment of the present application;

[0158] Figure 92 Schematic diagram of the structure of a first cathode layer and a second cathode layer provided by an embodiment of the present application;

[0159] Figure 93 Schematic diagram of forming a second cathode layer in a second display region provided by an embodiment of the present application;

[0160] Figure 94 Schematic diagram of forming a first cathode layer in a first display region provided by an embodiment of the present application;

[0161] Figure 95 Schematic diagram of forming a first cathode layer in a first display region and forming a second cathode layer in a second display region provided by an embodiment of the present application;

[0162] Figure 96 Schematic diagram of the structure of a display device provided by an embodiment of the present application. Detailed implementation manners

[0163] To make the objectives, technical solutions, and advantages of this application more clear, the following will further describe the embodiments of this application in detail with reference to the accompanying drawings.

[0164] In the related art, to increase the screen-to-body ratio of a display panel, the camera of a display device can be disposed in the display area of the display panel. Among them, the display area of the display panel includes: an anode layer, a light-emitting layer, and a cathode layer that are sequentially stacked in a direction away from the substrate. The camera is disposed on a side of the anode layer away from the light-emitting layer.

[0165] However, since the cathode layer will affect the transmittance, the imaging effect of the camera disposed in the display area of the display panel is poor.

[0166] Figure 1 is a schematic structural diagram of a display panel provided by an embodiment of this application. Referring to Figure 1 It can be seen that the display panel 10 may include: a substrate 101, a first auxiliary electrode layer 102, a first anode layer 103, a first light-emitting layer 104, a first cathode layer 105, a second auxiliary electrode layer 106, a second anode layer 107, a second light-emitting layer 108, and a second cathode layer 109.

[0167] Figure 2 is a top view of a substrate 101 provided by an embodiment of this application. Combining Figure 1 and Figure 2 , the substrate 101 may have a first display area 101a and a second display area 101b. The first auxiliary electrode layer 102, the first anode layer 103, the first light-emitting layer 104, and the first cathode layer 105 may be located in the first display area 101a and are sequentially stacked in a direction away from the substrate 101. The second auxiliary electrode layer 106, the second anode layer 107, the second light-emitting layer 108, and the second cathode layer 109 may be located in the second display area 101b and are sequentially stacked in a direction away from the substrate 101. The second cathode layer 109 may have at least one hollowed-out area.

[0168] Since the second cathode layer 109 included in the display panel 10 has at least one hollowed-out area, the second cathode layer 109 does not entirely cover the second display area 101b. Compared with a cathode layer that entirely covers the second display area 101b, the influence on the light transmittance can be effectively reduced, and the imaging effect of the camera located in the second display area 101b is better.

[0169] In an embodiment of the present application, the first auxiliary electrode layer 102 may be connected to the first cathode layer 105, the second auxiliary electrode layer 106 may be connected to the first auxiliary electrode layer 102, and the second cathode layer 109 may be connected to the first cathode layer 105. That is, the first auxiliary electrode layer 102, the first cathode layer 105, the second auxiliary electrode layer 106, and the second cathode layer 109 are interconnected, and the signals transmitted in the first auxiliary electrode layer 102, the first cathode layer 105, the second auxiliary electrode layer 106, and the second cathode layer 109 may be the same.

[0170] Since the first auxiliary electrode layer 102, the first cathode layer 105, the second auxiliary electrode layer 106, and the second cathode layer 109 are all connected, the voltage difference of the power supply signals received by the first cathode layer 105 and the second cathode layer 109 can be made smaller, ensuring the brightness uniformity of the display panel 10 and resulting in a better display effect of the display panel 10.

[0171] Figure 3 It is a schematic structural diagram of another display panel provided by an embodiment of the present application. Refer to Figure 3 , in an embodiment of the present application, the display panel 10 may further include: a pixel circuit 110 located in the second display area 101b ( Figure 3 One pixel circuit 110 is shown in Figure 1 . Each pixel circuit 110 may include at least one layer of opaque pattern b. Among them,

[0172] Refer to Figure 1 and Figure 3 It can also be seen that the second auxiliary electrode layer 106 may include: a plurality of electrically connected auxiliary electrode patterns 1061. Since the plurality of auxiliary electrode patterns 1061 can be electrically connected, the interconnection between the plurality of auxiliary electrode patterns 1061 can be ensured, and the reliability of signal transmission of the plurality of auxiliary electrode patterns 1061 can be ensured.

[0173] Moreover, at least 50% of the area of the positive projection of at least one layer of opaque pattern b in at least one pixel circuit 110 on the substrate 101 overlaps with the positive projection of the auxiliary electrode pattern 1061 on the substrate 101. Alternatively, at least a part of the boundary of at least one layer of opaque pattern b in at least one pixel circuit 110 is located within the positive projection of the auxiliary electrode pattern 1061 on the substrate 101.

[0174] Thus, the positive projection of the auxiliary electrode pattern 1061 on the substrate 101 can cover at least one layer of the opaque pattern b in at least one pixel circuit 110 to a large extent. The diffraction effect of the pixel circuit 110 on the camera disposed in the second display area 101b can be small, ensuring the display effect of the display panel 10. Among them, the opaque pattern can be a pattern in a film layer with a transmittance less than the transmittance threshold. For example, the transmittance threshold is 10%.

[0175] Optionally, at least 50% of the area of the positive projection of at least one layer of the opaque pattern b in at least one pixel circuit 110 on the substrate 101 overlapping with the positive projection of the auxiliary electrode pattern 1061 on the substrate 101 can mean that the target ratio of the area of the positive projection of at least one layer of the opaque pattern b in at least one pixel circuit 110 on the substrate 101 overlaps with the positive projection of the auxiliary electrode pattern 1061 on the substrate 101. Among them, the target ratio can be 60%, 65%, 70%, 75%, 80%, 85%, 90% or 100%.

[0176] In summary, the embodiment of the present application provides a display panel. The second cathode layer included in the display panel has a hollowed-out area, so the second cathode layer does not entirely cover the second display area. Compared with the cathode layer that entirely covers the second display area, the influence on the light transmittance can be effectively reduced, and the imaging effect of the camera located in the second display area is better.

[0177] Optionally, the materials of the first auxiliary electrode layer 102 and the second auxiliary electrode layer 106 can both include: metal. For example, the materials of the first auxiliary electrode layer 102 and the second auxiliary electrode layer 106 can be molybdenum (Mo), or the materials of the first auxiliary electrode layer 102 and the second auxiliary electrode layer 106 can be aluminum alloy.

[0178] Among them, the materials of the first auxiliary electrode layer 102 and the second auxiliary electrode layer 106 can be the same or different, and the embodiment of the present application does not limit this.

[0179] In the embodiment of the present application, the positive projection of the auxiliary electrode pattern 1061 on the substrate 101 can cover the positive projection of at least one layer of the opaque pattern b in at least one pixel circuit 110 on the substrate 101. Among them, the multiple pixel circuits 110 can be located on the side of the second anode layer 107 close to the substrate 101.

[0180] Since the positive projection of the auxiliary electrode pattern 1061 on the substrate 101 covers the positive projection of at least one layer of the opaque pattern b in at least one pixel circuit 110 on the substrate 101, the diffraction effect of the pixel circuit 110 on the camera disposed in the second display area 101b can be avoided, and the display effect of the display panel 10 is better.

[0181] Reference Figure 3 It can also be seen that the display panel 10 may further include: an active layer 112, a buffer layer 111, a first gate layer 113, a first gate insulating layer 114, a second gate layer 115 ( Figure 3 not shown), a second gate insulating layer 116, an interlayer dielectric layer 117, a first source-drain layer 118, a passivation layer 119, a first planarization layer 120, a second source-drain layer 121 ( Figure 3 not shown), and a second planarization layer 122, which are sequentially stacked in a direction away from the substrate 101 in the first display area 101a and the second display area 101b. In addition, the display panel 10 may further include another buffer layer 123 on a side of the first auxiliary electrode layer 102 and the second auxiliary electrode layer 106 away from the substrate 101.

[0182] The first source-drain layer 118 includes multiple groups of first source-drain layer patterns corresponding to each pixel circuit 110. Each group of first source-drain layer patterns includes: a source 1181 and a drain 1182. The second source-drain layer 121 includes multiple groups of second source-drain layer patterns corresponding to each pixel circuit 110. The active layer 112 includes multiple groups of active patterns 1131 corresponding to each pixel circuit 110. The first gate layer 113 includes multiple groups of first gate patterns 1151 corresponding to each pixel circuit 110. The second gate layer 115 includes multiple groups of second gate patterns corresponding to each pixel circuit 110. The source 1181 and the drain 1182 may be connected to an active pattern 1131. The drain 1182 may also be connected to the second anode layer 107.

[0183] Reference Figure 3 , at least one layer of the opaque pattern b of each pixel circuit 110 includes: a group of first source-drain layer patterns located in the first source-drain layer 118, a group of active patterns 1151 located in the active layer 112, a group of first gate patterns 1151 located in the first gate layer 113, and a group of second gate patterns located in the second gate layer 115. That is, each pixel circuit 110 may include multiple layers of opaque patterns. The transmittance of each layer of the opaque pattern is less than the transmittance threshold.

[0184] Among them, a group of first source-drain layer patterns located in the first source-drain layer 118 are patterns belonging to the same pixel circuit 110. For example, a group of first source-drain layer patterns of the first source-drain layer 118 includes: a source 1181 and a drain 1182 of a transistor in the same pixel circuit 110. In addition, the first source-drain layer pattern further includes a transfer pattern. A group of active patterns 1151 located in the active layer 112 includes the active layers of transistors in each pixel circuit 110. A group of first gate patterns 1151 located in the first gate layer 113 includes the gates of transistors in each pixel circuit 110. A group of second gate patterns located in the second gate layer 115 includes capacitor plates.

[0185] Reference Figure 4 , the multi-layer opaque pattern b may include an overlapping portion c1 and a non-overlapping portion c2. The positive projection of the auxiliary electrode pattern 1061 on the substrate 101 covers the positive projection of at least one layer of the opaque pattern b in at least one pixel circuit 110 on the substrate 101, and can be used to represent that at least a part of the positive projection of the overlapping portion c1 on the substrate 101 is located within the positive projection of the auxiliary electrode pattern 1061 on the substrate 101. And at least a part of the positive projection of the non-overlapping portion c2 on the substrate 101 is located within the positive projection of the auxiliary electrode pattern 1061 on the substrate 101.

[0186] Due to manufacturing process limitations, the auxiliary electrode pattern 1061 may not be able to completely cover the positive projection of the pixel circuit 110 on the substrate 101, that is, it may not be able to completely cover the positive projection of the multi-layer opaque pattern b included in the pixel circuit 110 on the substrate 101. Therefore, in order to avoid an excessive diffraction effect of the pixel circuit 110 on the camera disposed in the second display area 101b, the positive projection of the auxiliary electrode pattern 1061 on the substrate 101 can be made to cover as much as possible the positive projection of the overlapping portion c1 of the multi-layer opaque pattern b on the substrate 101. That is, the part that the positive projection of the auxiliary electrode pattern 1061 on the substrate 101 cannot cover is mainly the non-overlapping portion c2 of the multi-layer opaque pattern b. For example, only a partial area of the active pattern 1131 included in the multi-layer opaque pattern that is projected onto the substrate 101 cannot be covered by the positive projection of the auxiliary electrode pattern 1061 on the substrate 101.

[0187] In the embodiment of the present application, the second anode layer 107, the second light-emitting layer 108, and the second cathode layer 109 can be divided into light-emitting units of a plurality of first sub-pixels. The positive projection of the light-emitting area of the light-emitting unit of the first sub-pixel on the substrate 101 can be located within the overlapping area of the auxiliary electrode pattern 1061 and the second cathode layer 109. Among them, each first sub-pixel, in addition to including a light-emitting unit, further includes a pixel circuit 110 disposed in the second display area 101b.

[0188] Reference Figure 1 Specifically, the second anode layer 107 may include a plurality of anode patterns 1071 arranged at intervals. The second light-emitting layer 108 may include a plurality of light-emitting layer patterns 1081. Moreover, the plurality of anode patterns 1071 and the plurality of light-emitting layer patterns 1081 may correspond to each other. Each anode pattern 1071, together with a corresponding light-emitting layer pattern 1081 and the second cathode layer 109, forms a light-emitting unit of a first sub-pixel. Among them, two adjacent anode patterns 1081 may be located on the same side of a hollowed-out area of the second cathode layer 109, or may be respectively located on both sides of a hollowed-out area. The embodiments of the present application do not make any limitation in this regard.

[0189] In the embodiments of the present application, the first anode layer 103, the first light-emitting layer 104, and the first cathode layer 105 can be divided into light-emitting units of a plurality of second sub-pixels. The orthographic projection of the light-emitting area of the light-emitting unit of the second sub-pixel on the substrate 101 may be located within the orthographic projection of the first cathode layer 105 on the substrate 101.

[0190] Among them, the first anode layer 103 may also include a plurality of anode patterns (not shown in the figure). The first light-emitting layer 104 may include a plurality of light-emitting layer patterns (not shown in the figure). The plurality of anode patterns and the plurality of light-emitting layer patterns correspond to each other one by one. Each anode pattern, together with a corresponding light-emitting layer pattern and the first cathode layer 105, may form a light-emitting unit of a second sub-pixel.

[0191] In the embodiments of the present application, the display panel 10 may further include a pixel circuit located in the first display area 101a. Each second sub-pixel, in addition to including a light-emitting unit, further includes a pixel circuit located in the first display area 101a.

[0192] Figure 4 is a top view of a display panel provided by the embodiments of the present application. Reference Figure 4 It can be seen that at least part of the edge of the orthographic projection of the auxiliary electrode pattern 1061 on the substrate 101 may be arc-shaped.

[0193] Optionally, the edge of the orthographic projection of the auxiliary electrode pattern 1061 on the substrate 101 may include an arc segment. Among them, the ratio of the length of the arc segment to the perimeter of the edge may be greater than or equal to 50%.

[0194] Exemplarily, the ratio of the length of the arc segment to the perimeter of the edge may be 100%, that is, the edge of the orthographic projection of the auxiliary electrode pattern 1061 on the substrate 101 may all be arc segments.

[0195] To avoid the diffraction effect of the pixel circuit 110 of the first sub-pixel on the camera disposed in the second display area 101b, the orthographic projection of the auxiliary electrode pattern 1061 on the substrate 101 can cover the orthographic projection of at least one opaque pattern b in the pixel circuit 110 of the first sub-pixel on the substrate 101. That is, the orthographic projection of the auxiliary electrode pattern 1061 on the substrate 101 can cover the orthographic projection of at least one opaque pattern in a pixel circuit 110 on the substrate 101.

[0196] Figure 5 Yes Figure 4 Schematic diagram of the structure of the auxiliary electrode pattern 1061 in. Refer to Figure 5 It can be seen that the auxiliary electrode pattern 1061 can include: a first pattern 10611 and a second pattern 10612. The orthographic projection of the first pattern 10611 on the substrate 101 overlaps with more than 50% of the orthographic projection area of at least one opaque pattern b in at least one pixel circuit 110 on the substrate 101. The second pattern 10612 can be used for electrical connection with an adjacent auxiliary electrode pattern 1061. Exemplarily, the orthographic projection of the first pattern 10611 on the substrate 101 can cover the orthographic projection of at least one opaque pattern b in a pixel circuit 110 on the substrate 101.

[0197] It should be noted that the edge of at least one opaque pattern b included in the pixel circuit 110 includes at least two sub-edges, and at least one corner located between the at least two sub-edges. The angle between the two sub-edges is less than 150 degrees. That is, the edge of at least one opaque pattern b included in the pixel circuit 110 can be a broken line segment.

[0198] In the embodiments of the present application, diffraction simulation tests can be performed on a display panel without the auxiliary electrode pattern 1061 (such as Figure 6 ), and a display panel provided with the auxiliary electrode pattern 1061 respectively. Among them, the steps of the diffraction simulation test can include: setting a point light source and a charge coupled device (CCD) on both sides of the display panel respectively. When the point light source emits light, the CCD is used to test the scattering situation of the light emitted by the point light source after passing through the display panel. Figure 7 And Figure 8 The central bright spot of can be used to represent the center of the point light source. The brighter the brightness of the surrounding bright spots, the more divergent the energy of the point light source after passing through the display panel, and the more serious the diffraction.

[0199] Refer to Figure 7 And Figure 8 It can be seen that Figure 7The shown test images indicate that the diffraction effect of the display panel without the auxiliary electrode pattern 1061 set is relatively strong (the brightness of the peripheral bright spots is relatively high), while Figure 8 the diffraction effect of the display panel with the auxiliary electrode pattern 1061 set on the surface of the shown test image is relatively weak (the brightness of the peripheral bright spots is relatively low).

[0200] In the embodiments of the present application, first patterns 10611 with different shapes are set in multiple display panels, and diffraction simulation tests are performed on the multiple display panels with the first patterns 10611 of different shapes set. According to the test results, it can be determined that when the shape of the orthographic projection of the first pattern 10611 on the substrate 101 is circular, the diffraction effect of the display panel is the weakest, that is, the effect of reducing diffraction is the best compared to the display panel without the auxiliary electrode pattern 1061 set. Thus, referring to Figure 5 it can be seen that the shape of the orthographic projection of the first pattern 10611 in the auxiliary electrode pattern 1061 on the substrate 101 can be circular.

[0201] As an alternative implementation, referring to Figure 1 , the multiple auxiliary electrode patterns 1061 overlap each other to achieve electrical connection of the multiple auxiliary electrode patterns 1061. For example, the second pattern 10612 of a certain auxiliary electrode pattern 1061 can overlap with the second pattern 10612 of another adjacent auxiliary electrode pattern 1061.

[0202] That is, for two adjacent auxiliary electrode patterns 1061 among the multiple auxiliary electrode patterns 1061, the orthographic projection of one auxiliary electrode pattern 1061 on the substrate 101 and the orthographic projection of the other auxiliary electrode pattern 1061 on the substrate 101 have an overlapping area. Among them, the range of the ratio of the area of the overlapping area to the area of the orthographic projection of the auxiliary electrode pattern 1061 on the substrate is 5% to 10%.

[0203] As another alternative implementation, referring to Figure 3 , the display panel 10 may further include: a plurality of first connection electrodes 124 located in the second display area 101b, and the plurality of auxiliary electrode patterns 1061 are electrically connected through the plurality of first connection electrodes 124.

[0204] Referring to Figure 9 , the display panel 10 further includes: a first conductive layer 125 in the same layer as the first source-drain layer 118, and a second conductive layer 126 in the same layer as the second gate layer 115. The buffer layer 111, the first gate insulating layer 114, the second gate insulating layer 116, and the interlayer dielectric layer 117 all have first vias. The second conductive layer 126 and the first conductive layer 125 can be electrically connected to the auxiliary electrode pattern 1061 through the first vias.

[0205] Moreover, the plurality of first connection electrodes 124 are located between the passivation layer 119 and the first planarization layer 120. The passivation layer 119 may have second vias, and at least a part of the first connection electrodes 124 is located in the second vias and connected to the first conductive layer 125.

[0206] Reference Figure 9 , Figure 9 As shown in , there are two auxiliary electrode patterns 1061, two first conductive patterns 1251 included in the first conductive layer 125, two second conductive patterns 1261 included in the second conductive layer 126, and one first connection electrode 124. Among them, there are two first vias in each of the buffer layer 111, the first gate insulating layer 114, the second gate insulating layer 116, and the interlayer dielectric layer 117. The two second conductive patterns 1261 and the two first conductive patterns 1251 correspond to each other one by one. The passivation layer 119 may have two second vias. One end of the first connection electrode 124 is located in one second via and connected to one first conductive pattern 1251, and the other end of the first connection electrode 124 is located in the other second via and connected to the other first conductive pattern 1251. Thus, the two auxiliary electrode patterns 1061 can be connected to the first connection electrode 124 through the first conductive pattern 1251 and the second conductive pattern 1261, thereby realizing the signal transmission of the two auxiliary electrode patterns 1061.

[0207] In the embodiment of the present application, the connection manner between the auxiliary electrode patterns 1061 in the first auxiliary electrode layer 102 and the second auxiliary electrode layer 106 may include two types. For example, the first auxiliary electrode layer 102 overlaps with the auxiliary electrode pattern 1061 in the second display area 101b close to the first display area 101a. Or, the first auxiliary electrode layer 102 is connected to the auxiliary electrode pattern 1061 in the second display area 101b close to the first display area 101a through the first connection electrode 124. Moreover, the connection manner may refer to the connection manner between the auxiliary electrode patterns 1061 in the second display area 101b, and the embodiment of the present application will not elaborate here.

[0208] In the embodiment of the present application, reference Figure 10 , the display panel 10 may further include: a plurality of second connection electrodes 127 located between the passivation layer 119 and the first planarization layer 120, a first signal transmission layer 128 in the same layer as the first source-drain layer 118, and a third conductive layer 129 in the same layer as the first gate layer 113.

[0209] The first gate insulating layer 114, the second gate insulating layer 116, and the interlayer dielectric layer 117 each have third vias. The first signal transmission layer 128 is connected to the third conductive layer 129 through the third vias. The passivation layer 119 has fourth vias, and at least a part of the second connection electrode 127 is located in the fourth vias and is connected to the first signal transmission layer 128.

[0210] In an embodiment of the present application, the third conductive layer 129 may include: a plurality of first signal line segments, a plurality of second signal line segments, and a plurality of third signal line segments. Each signal line segment 1291 among the plurality of first signal line segments, the plurality of second signal line segments, and the plurality of third signal line segments is connected to a pixel circuit 110.

[0211] The plurality of second connection electrodes 127 include: a plurality of first-type second connection electrodes 127 connecting the plurality of first signal line segments, a plurality of second-type second connection electrodes 127 connecting the plurality of second signal line segments, and a plurality of third-type second connection electrodes 127 connecting the plurality of third signal line segments.

[0212] Assume Figure 10 the two signal line segments 1291 shown in Figure 10 are both first signal line segments, then the second connection electrode 127 in Figure 10 is a first-type second connection electrode 127. Assume Figure 10 the two signal line segments 1291 shown in Figure 10 are both second signal line segments, then the second connection electrode 127 in Figure 10 is a second-type second connection electrode 127. Assume

[0213] Taking Figure 10 the two signal line segments 1291 shown in Figure 10 as both first signal line segments as an example. The first gate insulating layer 114, the second gate insulating layer 116, and the interlayer dielectric layer 117 each have two third vias. And, Figure 10 two first signal transmission patterns 1281 of the first signal transmission layer 128 are shown in Figure 10 , and each first signal transmission pattern 1281 is connected to a first signal line segment 1291 through a third via. The passivation layer 119 has two fourth vias. One end of the second connection electrode 127 is located in one of the fourth vias and is connected to one first signal transmission pattern 1281. The other end of the second connection electrode 127 is located in the other fourth via and is connected to the other first signal transmission pattern 1281. Thus, the two first signal line segments 1291 can be connected to the second connection electrode 127 through the two first signal transmission patterns 128, thereby realizing the signal transmission of the two first signal line segments 1291.

[0214] Among them, the multiple first signal line segments can all be gate signal line segments, the multiple second signal line segments can all be reset control signal line segments, and the multiple third signal line segments can all be emission control (EM) signal line segments. That is to say, the multiple gate signal line segments can be connected through multiple second connection electrodes 127 of the first type to realize the transmission of the gate signals of the multiple gate signal line segments. The multiple reset control signal line segments can be connected through multiple second connection electrodes 127 of the second type to realize the transmission of the reset control signals of the multiple reset control signal line segments. The multiple emission control signal line segments can be connected through multiple second connection electrodes 127 of the third type to realize the transmission of the emission control signals of the multiple emission control signal line segments.

[0215] In the embodiment of the present application, the first display area 101a includes gate signal lines, and the gate signal lines can be connected to the gate signal line segments of the second display area 101b close to the first display area 101a through the second connection electrodes 127. Moreover, the connection method can refer to the connection method between the respective gate signal line segments in the second display area 101b, which will not be elaborated in the embodiment of the present application. The first display area 101a includes reset control signal lines, and the reset control signal lines can be connected to the reset control signal lines of the second display area 101b close to the first display area 101a through the second connection electrodes 127. Moreover, the connection method can refer to the connection method between the respective reset control signal line segments in the second display area 101b, which will not be elaborated in the embodiment of the present application. The first display area 101a includes emission control signal lines, and the emission control signal lines can be connected to the emission control signal line segments of the second display area 101b close to the first display area 101a through the second connection electrodes 127. Moreover, the connection method can refer to the connection method between the respective emission control signal line segments in the second display area 101b, which will not be elaborated in the embodiment of the present application.

[0216] As a possible case, in the embodiment of the present application, referring to Figure 11 , the display panel 10 may further include: a plurality of third connection electrodes 130, a fourth conductive layer 131, and a fifth conductive layer 132. The plurality of third connection electrodes 130 may be located between the passivation layer 119 and the second planarization layer 122.

[0217] The fourth conductive layer 131 may be in the same layer as the first source-drain layer 118, and the fourth conductive layer 131 may include a plurality of fourth signal line segments 1311. The fifth conductive layer 132 may be in the same layer as the second source-drain layer 121, and the fifth conductive layer 132 may include a plurality of fifth signal line segments 1321. Each of the plurality of fourth signal line segments 1311 and the plurality of fifth signal line segments 1321 is connected to a pixel circuit 110, and the plurality of fourth signal line segments 1311 are electrically connected through a plurality of third connection electrodes 130, and the plurality of fifth signal line segments 1321 are electrically connected through a plurality of third connection electrodes 130.

[0218] Reference Figure 11 , the passivation layer 119 has a fifth via. At least a part of the third connection electrode 130 is located in the fifth via and is connected to the fourth signal line segment 1311. The first planarization layer 120 has a sixth via, and at least a part of the fifth signal line segment 1321 is located in the sixth via and is connected to the third connection electrode 130.

[0219] Figure 11 Two fourth signal line segments 1311 and two fifth signal line segments 1321 are shown in [reference]. The passivation layer 119 has two fifth vias. One end of the third connection electrode 130 is located in one fifth via and is connected to one fourth signal line segment 1311. The other end of the third connection electrode 130 is located in the other fifth via and is connected to the other fourth signal line segment 1311. Moreover, the first planarization layer 120 has two sixth vias, and at least a part of each fifth signal line segment 1321 is located in one sixth via and is connected to one third connection electrode 130. Thus, the two fourth signal line segments 1311 and the two fifth signal line segments 1321 can be connected through the third connection electrode 130, thereby realizing the signal transmission of the two fourth signal line segments 1311 and the two fifth signal line segments 1321.

[0220] Optionally, the plurality of fourth signal line segments 1311 and the plurality of fifth signal line segments 1321 are both positive power supply (voltage drain drain, VDD) signal line segments. That is, the plurality of fourth signal line segments 1311 and the plurality of fifth signal line segments 1321 can be connected through the plurality of third connection electrodes 130 to realize the transmission of the positive power supply signal.

[0221] In the embodiment of the present application, the first display area 101a includes a positive power supply signal line, and the positive power supply signal line can be connected to the positive power supply signal line segment of the second display area 101b close to the first display area 101a through the third connection electrode 127. Moreover, the connection manner can refer to the connection manner between the positive power supply signal line segments in the second display area 101b, and the embodiment of the present application will not elaborate herein.

[0222] As another possible case, in the embodiments of the present application, referring to Figure 12 , the display panel 10 may further include: a plurality of third connection electrodes 130 and a fourth conductive layer 131. The plurality of third connection electrodes 130 may be on the same layer as the second source-drain layer 121. The fourth conductive layer 131 may be on the same layer as the first source-drain layer 118, and the fourth conductive layer 131 may include a plurality of fourth signal line segments 1311. Each fourth signal line segment 1311 is connected to a pixel circuit 110, and at least some of the plurality of fourth signal line segments 1311 are electrically connected through at least some of the third connection electrodes 130.

[0223] Referring to Figure 12 , the passivation layer 119 may have seventh vias, at least a part of the third connection electrode 130 may be located in the seventh vias, and is connected to the fourth signal line segment 1311. Figure 12 Two fourth signal line segments 1311 are shown in

[0224] One end of the third connection electrode 130 is located in one seventh via and is connected to one fourth signal line segment 1311. The other end of the third connection electrode 130 is located in the other seventh via and is connected to the other fourth signal line segment 1311. Thus, the two fourth signal line segments 1311 are connected through the third connection electrode 130, thereby realizing signal transmission between the two fourth signal line segments 1311.

[0225] In the embodiments of the present application, the first display area 101a includes data signal lines, and the data signal lines may be connected to the data signal lines of the second display area 101b close to the first display area 101a through the third connection electrodes 127. And the connection manner may refer to the connection manner between the respective data signal line segments in the second display area 101b, which will not be elaborated herein in the embodiments of the present application.

[0226] As yet another possible case, referring to Figure 13 , in the embodiments of the present application, the display panel 10 may further include: a plurality of third connection electrodes 130, a fourth conductive layer 131, and a second signal transmission layer 133. The plurality of third connection electrodes 130 may be on the same layer as the second source-drain layer 121. The fourth conductive layer 131 is on the same layer as the second gate layer 115, and the fourth conductive layer 131 includes a plurality of fourth signal line segments 1311.

[0227] The second signal transmission layer 133 may be on the same layer as the first source-drain layer 118.

[0228] The second gate insulating layer 116 and the interlayer dielectric layer 117 may have an eighth via hole. The second signal transmission layer 133 may be located within the eighth via hole and may be connected to the fourth signal line segment 1311. The passivation layer 119 has a ninth via hole, and at least a portion of the third connection electrode 130 may be located within the ninth via hole and connected to the second signal transmission layer 133.

[0229] Figure 13 Two fourth signal line segments 1311 and two second signal transmission patterns 1331 included in the second signal transmission layer 133 are shown. The second gate insulating layer 116 and the interlayer dielectric layer 117 may have two eighth via holes. The two second signal transmission patterns 1331 are respectively located within one eighth via hole and connected to one fourth signal line segment 1311. The passivation layer 119 has two ninth via holes. One end of the third connection electrode 130 is located within one ninth via hole and connected to one second signal transmission pattern 1331. The other end of the third connection electrode 130 is located within the other ninth via hole and connected to the other second signal transmission pattern 1331. Thus, the two fourth signal line segments 1311 are connected through the third connection electrode 130, thereby realizing the signal transmission of the two fourth signal line segments 1311.

[0230] Optionally, the plurality of fourth signal line segments 1311 may all be initialization (vinit) signal line segments. That is, the plurality of fourth signal line segments 1311 are connected through the plurality of third connection electrodes 130 to realize the transmission of the initialization signal.

[0231] In the embodiment of the present application, the first display area 101a includes an initialization signal line, and the initialization signal line may be connected to the initialization signal line of the second display area 101b close to the first display area 101a through the third connection electrode 127. Moreover, the connection manner may refer to the connection manner between the respective initialization signal line segments in the second display area 101b, and the embodiment of the present application will not elaborate herein.

[0232] Combined with Figures 9 to 13, at least some of the multiple connection electrodes (multiple first connection electrodes, multiple second connection electrodes, and multiple third connection electrodes) in the display panel can be used to electrically connect at least one of the first gate layer, the second gate layer, and the first source-drain layer in the first TV area 101a, and at least one of the first gate layer, the second gate layer, and the first source-drain layer in the second display area 101b. And / or, at least some of the multiple connection electrodes in the display panel are used to electrically connect at least two auxiliary electrode patterns 1061 located in the second display area 101b. And / or, at least some of the multiple connection electrodes in the display panel are used to connect at least one opaque pattern layer in at least two pixel circuits in the second display area 101b.

[0233] Combined with Figures 9 to 13 , the multiple connection electrodes can have multiple connection points. The connection points include connection vias or overlapping structures where the multiple electrodes are connected to the respective patterns they are connected to. For example, the connection points include: the overlapping part of the orthographic projection of the connection electrode on the substrate 101 and the orthographic projection of the conductive layer on the substrate 101. The orthographic projection of the auxiliary electrode pattern 1061 on the substrate 101 can have an overlapping area with the orthographic projection of at least one connection point on the substrate 101.

[0234] Optionally, the orthographic projection of the auxiliary electrode pattern 1061 on the substrate 101 can cover the orthographic projection of at least one connection point on the substrate 101. For example Figure 9 shows two connection points, and the orthographic projection of the auxiliary electrode pattern 1061 on the substrate 101 covers the orthographic projection of the two connection points on the substrate 101.

[0235] Since the diffraction effect of the area where the multi-layer conductive film layers are stacked (i.e., the area where the connection points are located) on the camera is relatively large, while the diffraction effect of the area of the single-layer conductive film layer on the camera is relatively small, covering the orthographic projection of the connection point on the substrate 101 with the orthographic projection of the auxiliary electrode pattern 1061 on the substrate 101 can greatly reduce diffraction and improve the display effect of the display panel.

[0236] Combined with Figure 3 , and Figures 9 to 13 , the display panel 10 may further include: a pixel defining layer 134 on the side of the second anode layer 107 away from the substrate 101. Refer to Figure 3 , the pixel defining layer 134 may have multiple tenth vias, and at least some of the multiple light-emitting layer patterns 1081 included in the second light-emitting layer 108 can be located within the tenth vias. The second cathode layer 109 at least partially covers the tenth vias, and at least one hollowed-out area of the second cathode layer 109 does not overlap with the tenth vias.

[0237] Combined with Figure 3 , andFigures 9 to 13 , the display panel 10 may further include: a support layer 135 on a side of the pixel defining layer 134 away from the substrate 101. Refer to Figure 3 , the support layer 135 may have a plurality of support patterns. A positive projection of the plurality of support patterns on the substrate 101 at least partially does not overlap with a positive projection of the light emitting layer pattern 1081 on the substrate 101. A portion of the second cathode layer 109 other than the hollowed-out area may be connected to the light emitting layer pattern 1081 to ensure that the first sub-pixel located in the second display area 101b can emit light normally.

[0238] In the embodiment of the present application, refer to Figure 1 and Figure 3 , the first auxiliary electrode layer 102 and the second auxiliary electrode layer 106 may be located in the same layer, the first light emitting layer 104 and the second light emitting layer 108 may be located in the same layer, and the first cathode layer 105 and the second cathode layer 109 may be located in the same layer. For example, the first cathode layer 105 and the second cathode layer 109 may be an integral structure.

[0239] That is, the first auxiliary electrode layer 102 and the second auxiliary electrode layer 106 may be prepared by the same patterning process. The first light emitting layer 104 and the second light emitting layer 108 may be prepared by the same patterning process. The first cathode layer 105 and the second cathode layer 109 may be prepared by the same patterning process.

[0240] Figure 14 is a top view of another substrate provided by the embodiment of the present application. Refer to Figure 14 It can be seen that the substrate 101 further has a peripheral area 101c surrounding the first display area 101a and the second display area 101b. The first auxiliary electrode layer 102 and the first cathode layer 105 may also be located in the peripheral area 101c. And, refer to Figure 15 , a portion of the first auxiliary electrode layer 102 located in the peripheral area 101c may be connected to a portion of the first cathode layer 105 located in the peripheral area 101c.

[0241] Since a portion of the first auxiliary electrode layer 102 located in the peripheral area 101c is connected to a portion of the first cathode layer 105 located in the peripheral area 101c, there is no need to connect a portion of the first auxiliary electrode layer 102 located in the first display area 101a to a portion of the first cathode layer 105 located in the first display area 101a. Therefore, it is possible to avoid affecting the display effect of the first display area 101a due to the connection between the first auxiliary electrode layer 102 and the first cathode layer 105.

[0242] Optionally, the portion of the first auxiliary electrode layer 102 located in the peripheral region 101c and the portion of the first cathode layer 105 located in the peripheral region 101c can be respectively overlapped with at least one conductive pattern layer between the first auxiliary electrode layer 102 and the first cathode layer 105, so as to electrically connect the portion of the first auxiliary electrode layer 102 located in the peripheral region 101c and the portion of the first cathode layer 105 located in the peripheral region 101c.

[0243] Reference Figure 15 , the buffer layer 111, the first gate insulating layer 114, the second gate insulating layer 116, the interlayer dielectric layer 117, the passivation layer 119, the first planarization layer 120 and the second planarization layer 122 all have an eleventh via hole. The orthographic projection of the eleventh via hole on the substrate 101 is located in the peripheral region 101c, and the eleventh via hole exposes the portion of the first auxiliary electrode layer 102 located in the peripheral region 101c.

[0244] The display panel 10 further includes: a third signal transmission layer 136, a fourth signal transmission layer 137, a fifth signal transmission layer 138 and a sixth signal transmission layer 139 located in the eleventh via hole. Among them, the third signal transmission layer 136 is in the same layer as the second gate layer 115 and is connected to the first auxiliary electrode layer 102. The fourth signal transmission layer 137 is in the same layer as the first source-drain layer 118, the fifth signal transmission layer 138 is in the same layer as the second source-drain layer 121, and the sixth signal transmission layer 139 is in the same layer as the second anode layer 107.

[0245] The pixel defining layer 134 has a twelfth via hole. The orthographic projection of the twelfth via hole on the substrate 101 is located in the peripheral region 101c and exposes the sixth signal transmission layer 139. The orthographic projection of the portion of the first cathode layer 105 located in the peripheral region 101a on the substrate 101 at least partially overlaps with the orthographic projection of the sixth signal transmission layer 139 on the substrate 101 and is connected to the sixth signal transmission layer 139. Thus, the first auxiliary electrode layer 102 and the first cathode layer 105 are connected through the third signal transmission layer 136, the fourth signal transmission layer 137, the fifth signal transmission layer 138 and the sixth signal transmission layer 139, realizing the transmission of signals between the first auxiliary electrode layer 102 and the first cathode layer 105.

[0246] Reference Figure 14 , the peripheral region 101c may include: a first region 101c1 and a second region 101c2 arranged opposite and parallel to each other, and a third region 101c3 and a fourth region 101c4 arranged opposite and parallel to each other. The extending direction of the first region 101c1 may be perpendicular to the extending direction of the third region 101c3, and the distance between the second display region 101b and the first region 101c1 may be less than the distance between the second display region 101b and the second region 101c2.

[0247] Reference Figure 14 The first region 101c1 may be located above the first display region 101a, the second region 101c2 may be located below the first display region 101a, the third region 101c3 may be located on the left side of the first display region 101a, and the fourth region 101c4 may be located on the right side of the first display region 101a. The distance between the second display region 101b and the third region 101c3 may be equal to the distance between the second display region 101b and the fourth display region, that is, the second display region 101b may be located in the middle of the side of the first display region 101a close to the first region 101c1.

[0248] In the embodiment of the present application, the orthographic projection of the first auxiliary electrode layer 102 on the substrate 101 may cover the first display region 101a, that is, the first auxiliary electrode layer 102 may be prepared as a whole layer. Alternatively, the first auxiliary electrode layer 102 may only cover a part of the first display region 101a. The embodiment of the present application does not limit the shape of the first auxiliary electrode layer 102, as long as it is ensured that the first auxiliary electrode layer 102 can be connected to the first cathode layer 105 and the second auxiliary electrode layer 106.

[0249] On the premise that the orthographic projection of the first auxiliary electrode layer 102 on the substrate 101 covers the first display region 101a, the first auxiliary electrode layer 102 may be located in the first region 101c1, the second region 101c2, the third region 101c3, and the fourth region 101c4 of the peripheral region 101c. Moreover, the part of the first auxiliary electrode layer 102 located in the first region 101c1 is connected to the part of the first cathode layer 105 located in the first region 101c1. The part of the first auxiliary electrode layer 102 located in the third region 101c3 is connected to the part of the first cathode layer 105 located in the third region 101c3. The part of the first auxiliary electrode layer 102 located in the fourth region 101c4 is connected to the part of the first cathode layer 105 located in the fourth region 101c4. And, the part of the first auxiliary electrode layer 102 located in the second region 101c2 is not connected to the part of the first cathode layer 105 located in the second region 101c2.

[0250] Since other traces usually need to be provided in the second region 101c2, the non-connection between the part of the first auxiliary electrode layer 102 located in the second region 101c2 and the part of the first cathode layer 105 located in the second region 101c2 can avoid affecting the setting of other traces.

[0251] Optionally, the first connection electrode 124, the second connection electrode 127, and the third connection electrode 130 can all be made of a transparent conductive material. Thereby, the transmittance of the second display area 101b can be ensured, and the imaging effect of the camera can be improved. Exemplarily, the first connection electrode 124, the second connection electrode 127, and the third connection electrode 130 can all be made of indium tin oxide (ITO).

[0252] As an alternative implementation, referring to Figure 16 , the second cathode layer 109 can include: a plurality of cathode patterns 1091. The plurality of cathode patterns 1091 can overlap with each other, and after the plurality of cathode patterns 1091 overlap, they can enclose at least one hollowed-out area c.

[0253] Wherein, the orthographic projection of each cathode pattern 1091 on the substrate 101 can cover the orthographic projection of at least one light-emitting layer pattern 1081 on the substrate 101. For example, the orthographic projection of each cathode pattern 1091 on the substrate 101 can cover the orthographic projection of three light-emitting layer patterns 1081 on the substrate 101. The three light-emitting layer patterns are respectively the light-emitting layer patterns of three first sub-pixels. The three first sub-pixels are respectively a red (R) sub-pixel, a green (G) sub-pixel, and a blue (B) sub-pixel.

[0254] Referring to Figure 16 It can also be seen that the orthographic projection of each auxiliary electrode pattern 1061 on the substrate 101 can cover the orthographic projection of at least one opaque pattern in a pixel circuit 110 on the substrate 101. And, since the distances between the three pixel circuits 110 covered by each cathode pattern 1091 are relatively close, the three auxiliary electrode patterns 1061 covering these three pixel circuits 110 can be directly overlapped without being connected through the first connection electrode 124.

[0255] As another alternative implementation, referring to Figure 4 , each hollowed-out area in the second cathode layer 109 is formed by digging holes in the second cathode layer 109.

[0256] Optionally, the boundary of at least one hollowed-out area includes at least an arc. For example, the shape of the hollowed-out area can be circular or elliptical. Of course, the shape of at least one hollowed-out area can also be square, rectangular, etc. The embodiments of the present application do not limit the shape of the hollowed-out area. The area of the hollowed-out area ranges from 350 square micrometers to 630 square micrometers.

[0257] In the above two methods, the area of the overlapping part between the orthographic projection of each hollowed-out area on the substrate 101 and the orthographic projection of the auxiliary electrode pattern 1061 on the substrate 101 is less than 10% of the area of the hollowed-out area.

[0258] Figure 17 This is an equivalent circuit diagram of a pixel circuit provided by an embodiment of the present application. It should be noted that in the embodiment of the present application, the equivalent circuit diagram of the pixel circuit of the first sub-pixel located in the second display area 101b can be substantially the same as the equivalent circuit diagram of the pixel circuit of the second sub-pixel located in the first display area 101a. That is, Figure 17 The equivalent circuit diagram shown in can be the equivalent circuit diagram of the pixel circuit of the sub-pixel in the first display area 101b or the first display area 101a. However, the embodiment of the present application is not limited thereto. In the embodiment of the present application, there may be differences between the equivalent circuit diagram of the pixel circuit of the sub-pixel located in the first display area 101b and the equivalent circuit diagram of the pixel circuit of the sub-pixel located in the first display area 101a.

[0259] Figure 18 This is a plan view of a sub-pixel in the first display area provided by an embodiment of the present application, in which a plan view of a repeating unit in the first display area is schematically shown. Figure 19 is Figure 18 a plan view of the active layer of the sub-pixels included in a repeating unit in. Figure 20 is Figure 18 a plan view of the combination of the active layer and the first gate layer of the sub-pixels included in a repeating unit in. Figure 21 is Figure 18 a plan view of the combination of the active layer, the first gate layer and the second gate layer of the sub-pixels included in a repeating unit in. Figure 22 is Figure 18 a plan view of the combination of the active layer, the first gate layer, the second gate layer and the first source-drain layer of the sub-pixels included in a repeating unit in. Figure 23 is Figure 18 a plan view of the combination of the active layer, the first gate layer, the second gate layer, the first source-drain layer and the second source-drain layer of the sub-pixels included in a repeating unit in. Figure 24 is Figure 18 a plan view of the combination of the active layer, the first gate layer, the second gate layer, the first source-drain layer and the second source-drain layer of the sub-pixels included in a repeating unit in. Figure 25 is Figure 18 a plan view of the combination of the active layer, the first gate layer, the second gate layer, the first source-drain layer, the second source-drain layer and the first anode layer of the sub-pixels included in a repeating unit in.

[0260] In an embodiment of the present application, the pixel circuits in the first display area 101a and the pixel circuits in the second display area 101b of the display panel 10 may both include: a plurality of thin film transistors and a storage capacitor. The pixel circuit is used to drive the light emitting unit. The plurality of thin film transistors include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7. Each transistor includes a gate, a source, and a drain.

[0261] Moreover, the display panel 10 may further include a plurality of signal lines. For example, the plurality of signal lines include: a scan signal line (also referred to as a gate signal line) A1 for transmitting a scan signal, a reset control signal line A2 for transmitting a reset control signal (for example, the reset control signal may be the scan signal of the previous row), a light emission control line A3 for transmitting a light emission control signal, a data signal line A4 for transmitting a data signal, a positive power supply line A5 for transmitting a positive power supply signal, an initialization voltage line A6 for transmitting an initialization voltage Vint, and a negative power supply line A7 for transmitting a negative power supply signal.

[0262] The storage capacitor Cst may include two capacitor plates Cst1 and Cst2. In this document, the capacitor plate Cst1 may be referred to as one end, the first end, or the first storage capacitor electrode of the storage capacitor Cst, and the capacitor plate Cst2 may be referred to as the other end, the second end, or the second storage capacitor electrode of the storage capacitor Cst.

[0263] The first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 included in the pixel circuit may be formed along the active layer as shown in Figure 19 . The active layer may have a curved or bent shape and may include a first active pattern 112a corresponding to the first transistor T1, a second active pattern 112b corresponding to the second transistor T2, a third active pattern 112c corresponding to the third transistor T3, a fourth active pattern 112d corresponding to the fourth transistor T4, a fifth active pattern 112e corresponding to the fifth transistor T5, a sixth active pattern 112f corresponding to the sixth transistor T6, and a seventh active pattern 112g corresponding to the seventh transistor T7.

[0264] The active layer 112 may include, for example, polysilicon and, for example, include a channel region, a source region, and a drain region. The channel region may not be doped or may have a doping type different from that of the source region and the drain region, and thus has semiconductor characteristics. The source region and the drain region are respectively located on both sides of the channel region and are doped with impurities, and thus have conductivity. The impurities may vary depending on whether the thin film transistor is an N-type or P-type transistor.

[0265] The first transistor T1 includes a first active pattern 112a and a first gate G1. The first active pattern 112a includes a first channel region 1121a, a first source region 1123a, and a first drain region 1125a. The gate G1 of the first transistor T1 is electrically connected to the reset control signal line A2, and the source S1 of the first transistor T1 is electrically connected to the initialization voltage line A6. And the drain D1 of the first transistor T1 is electrically connected to one end Cst1 of the storage capacitor Cst, the drain D2 of the second transistor T2, and the gate G3 of the third transistor T3. The first transistor T1 is turned on according to the reset control signal RESET transmitted through the reset control signal line A2 to transmit the initialization voltage Vint to the gate G3 of the third transistor T3, thereby performing an initialization operation to initialize the voltage of the gate G3 of the third transistor T3. That is, the first transistor T1 is also referred to as an initialization transistor.

[0266] The second transistor T2 includes a second active pattern 112b and a second gate G2. The second active pattern 112b includes a second channel region 1121b, a second source region 1123b, and a second drain region 1125b. The gate G2 of the second transistor T2 is electrically connected to the scan signal line A1, the source S2 of the second transistor T2 is electrically connected to the node N3, and the drain D2 of the second transistor T2 is electrically connected to the node N1. The second transistor T2 is turned on according to the scan signal transmitted through the scan signal line A1 to electrically connect the gate G3 and the drain D3 of the third transistor T3 to each other, thereby performing the diode connection of the third transistor T3.

[0267] The third transistor T3 includes a third active pattern 112c and a third gate G3. The third active pattern 112c includes a third source region 1123c, a third drain region 1125c, and a third channel region 1121c connecting the third source region 1123c and the third drain region 1125c. The third source region 1123c and the third drain region 1125c extend in opposite two directions with respect to the third channel region 1121c. The third source region 1123c of the third transistor T3 is connected to the fourth drain region 1125d and the fifth drain region 1125e. The third drain region 1125c is connected to the second source region 1123b and the sixth source region 1123f. The gate G3 of the third transistor T3 is electrically connected to the first connection portion A8 through vias VAH1 and VAH2. The gate G3 of the third transistor T3 is electrically connected to the node N1, the source S3 of the third transistor T3 is electrically connected to the node N2, and the drain D3 of the third transistor T3 is electrically connected to the node N3. The third transistor T3 receives the data signal Dm according to the switching operation of the fourth transistor T4 to supply the driving current Id to the light emitting unit. That is, the third transistor T3 is also referred to as a driving transistor.

[0268] The fourth transistor T4 includes a fourth active layer 112d and a fourth gate G4. The fourth active layer 112d includes a fourth channel region 1121d, a fourth source region 1123c, and a fourth drain region 1125d. The fourth transistor T4 serves as a switching device for selecting a light-emitting target sub-pixel. The fourth gate G4 is connected to the scan signal line A1, the fourth source region 1123c is connected to the data signal line A4 through a via VAH4, and the fourth drain region 1125d is connected to the first transistor T1 and the fifth transistor T5, that is, electrically connected to the node N2. The fourth transistor T4 is turned on according to the scan signal Sn transmitted through the scan signal line A1 to perform a switching operation to transmit the data signal Dm to the source S3 of the third transistor T3.

[0269] The fifth transistor T5 includes a fifth active layer 112e and a fifth gate G5. The fifth active layer 112e includes a fifth channel region 1121e, a fifth source region 1123e, and a fifth drain region 1125e. The fifth source region 1123e can be connected to the positive power supply line A5 through a via VAH6. The gate G5 of the fifth transistor T5 is electrically connected to the light-emitting control line A3, the source S5 of the fifth transistor T5 is electrically connected to the positive power supply line A5. And the drain D5 of the fifth transistor T5 is electrically connected to the node N2.

[0270] The sixth transistor T6 includes a sixth active layer 112f and a sixth gate G6, and the sixth active layer 112f includes a sixth channel region 1121f, a sixth source region 1123f, and a sixth drain region 1125f. The sixth drain region 1125f can be connected to the anode pattern through a via VAH7. The gate G6 of the sixth transistor T6 is electrically connected to the light-emitting control line A3, the source S6 of the sixth transistor T6 is electrically connected to the node N3, and the drain D6 of the sixth transistor T6 is electrically connected to the node N4, that is, electrically connected to the anode pattern of the light-emitting unit. The fifth transistor T5 and the sixth transistor T6 are turned on concurrently (e.g., simultaneously) according to the light-emitting control signal En transmitted through the light-emitting control line A3 to transmit the driving voltage VDD to the light-emitting unit, thereby allowing the driving current Id to flow into the light-emitting unit.

[0271] The seventh transistor T7 includes a seventh active layer 112g and a seventh gate G7. The seventh active layer 112g includes a seventh source region 1123g, a seventh drain region 1125g, and a seventh channel region 1121g. The seventh drain region 1125g is connected to the first source region 1123a of the first transistor T1. The seventh drain region 1125g can be electrically connected to the initialization voltage line A6 through a via VAH8, a second connection portion A9, and a via VAH5. The gate G7 of the seventh transistor T7 is electrically connected to the reset control signal line A2, the source S7 of the seventh transistor T7 is electrically connected to the node N4, and the drain D7 of the seventh transistor T7 is electrically connected to the initialization voltage line A6.

[0272] One end of the storage capacitor Cst (hereinafter referred to as the first storage capacitor electrode) Cst1 is electrically connected to the node N1, and the other end (hereinafter referred to as the second storage capacitor electrode) Cst2 is electrically connected to the positive power supply line A5.

[0273] It should be noted that each of the thin film transistors T1, T2, T3, T4, T5, T6, and T7 is a p-channel field effect transistor. However, the embodiments of the present application are not limited thereto, and at least some of the thin film transistors T1, T2, T3, T4, T5, T6, and T7 may be n-channel field effect transistors.

[0274] The display panel 10 includes scan signal lines A1, reset control signal lines A2, emission control signal lines A3, and initialization voltage lines A6 that are arranged along the row direction to respectively apply a scan signal Sn, a reset control signal RESET, an emission control signal En, and an initialization voltage Vint to each sub-pixel. The display panel may further include data signal lines A4 and a positive power supply line A5 that intersect with the scan signal lines A1, the reset control signal lines A2, the emission control signal lines A3, and the initialization voltage lines A6 to respectively apply a data signal Dm and a driving voltage VDD to each sub-pixel.

[0275] As Figure 20 shown, the scan signal lines A1, the reset control signal lines A2, and the emission control signal lines A3 are all located in the first gate layer 113. The gates G1 to G7 of the above-mentioned respective transistors are also all located in the first gate layer 113. For example, the overlapping portions of the reset control signal line A2 and the active layer 112 respectively form the gate G1 of the first transistor T1 and the gate G7 of the seventh transistor T7, the overlapping portions of the scan signal line A1 and the active layer 112 respectively form the gate G2 of the second transistor T2 and the gate G4 of the fourth transistor T4, and the overlapping portions of the emission control signal line A3 and the active layer 112 respectively form the gate G6 of the sixth transistor T6 and the gate G5 of the fifth transistor T5.

[0276] Continuing to refer to Figure 20 , the display panel 10 may further include a plurality of first storage capacitor electrodes Cst1. The plurality of first storage capacitor electrodes Cst1 are also located in the first gate layer 113. The overlapping portion of the first storage capacitor electrode Cst1 and the active layer 1120 forms the third gate G3 of the third transistor T3. The first storage capacitor electrode Cst1 also forms one terminal of the storage capacitor Cst. That is, the first storage capacitor electrode Cst1 serves as both the gate G3 of the third transistor T3 and one electrode of the storage capacitor Cst.

[0277] For example, the positive projection of the first storage capacitor electrode Cst1 on the substrate 101 may be in a substantially rectangular shape. The "substantially rectangular" here may include a rectangle, a rectangle with at least one rounded corner, a rectangle with at least one chamfered corner, and other shapes.

[0278] As Figure 21 shown, the initialization voltage line A6 is located in the second gate layer 115. The display panel may further include a plurality of second storage capacitor electrodes Cst2. The plurality of second storage capacitor electrodes Cst2 are also located in the second gate layer 115. The plurality of second storage capacitor electrodes Cst2 are respectively arranged corresponding to the plurality of first storage capacitor electrodes Cst1. That is, the positive projection of the plurality of second storage capacitor electrodes Cst2 on the substrate 101 at least partially overlaps with the positive projection of the corresponding first storage capacitor electrode Cst1 on the substrate 101. The second storage capacitor electrode Cst2 forms another terminal of the storage capacitor Cst. That is, the first storage capacitor electrode Cst1 and the second storage capacitor electrode Cst2 are arranged opposite to each other, their positive projections on the substrate 101 at least partially overlap with each other, and a second gate insulating layer GI2 is provided therebetween. For example, the first storage capacitor electrode Cst1 may be electrically connected to the first connection portion A8 through vias VAH1 and VAH2, and the second storage capacitor electrode Cst2 may be electrically connected to the positive power supply line A5 through via VAH9. In this way, the overlapping portion of the first storage capacitor electrode Cst1 and the second storage capacitor electrode Cst2 may form the storage capacitor Cst.

[0279] Combined with Figure 21 and Figure 23 , the second storage capacitor electrode Cst2 may include a through hole TH2 to facilitate the electrical connection between the first storage capacitor electrode Cst1 located below the second storage capacitor electrode Cst2 and the components in the third conductive layer 23. For example, a part of the first connection portion A8 is formed in the via VAH1 to form a conductive plug. The conductive plug extends through the through hole TH2 and is electrically connected to the first storage capacitor electrode Cst1. In this way, one end of the first connection portion A8 is electrically connected to one end of the storage capacitor Cst1.

[0280] For example, the positive projection of the through hole TH2 on the substrate 1 may be in a substantially rectangular shape. The "substantially rectangular" here may include a rectangle or a square, a rectangle or a square with at least one rounded corner, a rectangle or a square with at least one chamfered corner, and other shapes.

[0281] Referring to Figure 22 , the data signal line A4 and the positive power supply line A5 are located in the first source-drain layer 118. In addition, the first connection portion A8 and the second connection portion A9 are also located in the first source-drain layer 118.

[0282] Referring toFigure 23 , Figure 24 and Figure 25 , the third connection part B1 is located in the second source-drain layer 121. One end of the third connection part B1 is electrically connected to the sixth transistor T6, and the other end is electrically connected to the anode pattern.

[0283] Reference Figure 25 , there is a passivation layer PVX between the second source-drain layer 121 and the first anode layer 103. The via VAH10 can penetrate through the passivation layer PVX. A part of the anode pattern of the first anode layer is formed in the via VAH10, and this part extends downward to be electrically connected to a part of the third connection part B1.

[0284] In this way, one end of the third connection part B1 is electrically connected to the sixth transistor T6 through the via VAH7, and the other end of the third connection part B1 is electrically connected to the anode pattern of the first anode layer through the via VAH10. In order to meet the requirements of the preset pixel density, each sub-pixel on the display panel needs to be arranged in a specified manner. In this way, the extension lengths of the third connection parts B1 in each sub-pixel can be equal or unequal.

[0285] For example, reference Figure 18 , Figure 23 and Figure 24 , where Figure 23 shows a plan view of the pixel circuit of a red sub-pixel or a blue sub-pixel, Figure 24 shows a plan view of the pixel circuit of a green sub-pixel. The extension length of the third connection part B1 in the sixth sub-pixel 23 can be less than the extension length of the third connection part B1 in the fourth sub-pixel 21 or the fifth sub-pixel 22.

[0286] It should be noted that in the following description, the differences between the structure of the first sub-pixel located in the second display area 101b and the structure of the second sub-pixel located in the first display area 101a are mainly described. For the same parts of the two, reference can be made to the above description.

[0287] It should also be noted that in order to make the description of this article more concise, in the following text, elements with the same or similar functions and / or structures in the first display area and the second display area can be represented by the same reference numerals. For example, each transistor, storage capacitor, and signal line located in the second display area can be represented by the reference numerals corresponding to each transistor, storage capacitor, and signal line located in the first display area respectively. It should be understood that in the following description, these elements are located in the second display area 101b.

[0288] Figure 26 is an equivalent circuit diagram of another pixel circuit provided by an embodiment of the present application. Figure 27It is a plan view of sub-pixels in a second display area provided by an embodiment of the present application, in which a plan view of a repeating unit in the second display area is schematically shown. Figure 28 is Figure 27 a plan view of the active layer of the sub-pixels included in one repeating unit in Figure 29 is Figure 27 a plan view of the combination of the active layer and the first gate layer of the sub-pixels included in one repeating unit in Figure 30 is Figure 27 a plan view of the combination of the active layer, the first gate layer and the second gate layer of the sub-pixels included in one repeating unit in Figure 31 is Figure 27 a plan view of the combination of the active layer, the first gate layer, the second gate layer and the first source-drain layer of the sub-pixels included in one repeating unit in Figure 32 is Figure 27 a plan view of the combination of the active layer, the first gate layer, the second gate layer, the first source-drain layer and the connection electrode film layer of the sub-pixels included in one repeating unit in Figure 33 is Figure 27 a plan view of the combination of the active layers, the first gate layer, the second gate layer, the first source-drain layer and the connection electrode film layer of 3 sub-pixels included in one repeating unit in Figure 34 is Figure 27 a plan view of the combination of the active layer, the first gate layer, the second gate layer, the first source-drain layer, the connection electrode film layer and the second source-drain layer of the sub-pixels included in one repeating unit in Figure 35 is Figure 27 a plan view of the combination of the active layer, the first gate layer, the second gate layer, the first source-drain layer, the connection electrode film layer, the second source-drain layer and the second anode layer of one sub-pixel included in one repeating unit in Figure 36 is Figure 27 a plan view of the combination of the active layer, the first gate layer, the second gate layer, the first source-drain layer, the connection electrode film layer, the second source-drain layer and the second anode layer of another sub-pixel included in one repeating unit in Figure 37 is Figure 27 a plan view of the combination of the active layer, the first gate layer, the second gate layer, the first source-drain layer, the connection electrode film layer, the second source-drain layer and the second anode layer of yet another sub-pixel included in one repeating unit in

[0289] Combined with Figures 26 to 37, in the first display area 101b, the pixel circuit may include: a plurality of thin film transistors and a storage capacitor Cst. The pixel circuit is used to drive the light-emitting unit. The plurality of thin film transistors include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7. Each transistor includes a gate, a source, and a drain.

[0290] The multiple signal lines include: a scan signal line A1 for transmitting a scan signal Sn, a reset control signal line A2 for transmitting a reset control signal RESET (for example, the reset control signal RESET may be the scan signal of the previous row), a light-emitting control line A3 for transmitting a light-emitting control signal En, a data signal line A4 for transmitting a data signal Dm, a positive power supply line A5 for transmitting a driving voltage VDD, an initialization voltage line A6 for transmitting an initialization voltage Vint, and a negative power supply line A7 for transmitting a VSS voltage.

[0291] Reference Figure 27 , for a first sub-pixel, the active patterns of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are formed as a continuously extending part of the active layer 112. In the embodiments of the present application, "continuously extending" means that there is no break in the middle.

[0292] Reference Figure 27 , the seventh active pattern 112g of the seventh transistor T7 is connected to the first active pattern 112a of the first transistor T1, the first active pattern 112a of the first transistor T1 is connected to the second active pattern 112b of the second transistor T2, the second active pattern 112b of the second transistor T2 is connected to the third active pattern 112c of the third transistor T3 and the sixth active pattern 112f of the sixth transistor T6, and the third active pattern 112c of the third transistor T3 is connected to the fourth active pattern 112d of the fourth transistor T4 and the fifth active pattern 112e of the fifth transistor T5.

[0293] Reference Figure 27 and Figure 28 , for a first sub-pixel located in the second display area 101b, the seventh active pattern 112g of the seventh transistor T7 extends from the first active pattern 112a of the first transistor T1 in a direction close to the scan signal line A1 of the first sub-pixel. That is, the seventh active pattern 112g of the seventh transistor T7 is located at the lower right of the first active pattern 112a of the first transistor T1. By such a setting method, the contour of the occupied area of the active layer of a first sub-pixel located in the second display area 101b is a square or approximately a square.

[0294] In the application embodiment, the "occupied area" represents the maximum area covered by the orthographic projection of a pattern, a layer structure, etc. on the substrate. Specifically, the orthographic projection of a pattern, a layer structure, etc. on the substrate has two side edges that are the farthest apart in the first direction X and two side edges that are the farthest apart in the second direction Y. The extension lines of these four side edges will intersect to enclose an area, and this area is the occupied area of the pattern, the layer structure, etc.

[0295] For a first sub-pixel located in the second display area 101b, the occupied area of its active layer has a square or approximately square shape. As Figure 27 shown, the occupied area of the active layer of a first sub-pixel located in the second display area 101b is schematically shown using a dashed box. This occupied area has a dimension along the first direction X (i.e., width W1) and a dimension along the second direction Y (i.e., length L1), where the length L1 is substantially equal to the width W1.

[0296] In the embodiment of the present application, the area of the occupied area of the active layer of a first sub-pixel located in the second display area 101b is smaller than the area of the occupied area of the active layer of a second sub-pixel of the same color located in the first display area 101a. Thus, the area of the occupied area of the pixel circuit 10 of the first sub-pixel located in the second display area 101b can be made smaller than the area of the occupied area of the pixel circuit of the second sub-pixel located in the first display area 101a.

[0297] As Figure 28 shown, the scan signal line A1, the reset control signal line A2, and the light emission control signal line A3 are all located in the first gate layer 113. The gates G1 to G7 of the above-mentioned various transistors are also all located in the first gate layer 113. The first storage capacitor electrode Cst1 is also located in the first gate layer 113.

[0298] Referring to Figure 28 , the overlapping parts of the scan signal line A1 and the active layer 112 respectively form the gate G2 of the second transistor T2 and the gate G4 of the fourth transistor T4. And, another overlapping part of the scan signal line A1 and the active layer 112 also forms the gate G7 of the seventh transistor T7. That is to say, in the embodiment of the present application, in the second display area 101b, the gates of the seventh transistor T7, the second transistor T2, and the fourth transistor are all supplied with the scan signal Sn.

[0299] As Figure 29 shown, the initialization voltage line A6 and the second storage capacitor electrode Cst2 are located in the second gate layer 115.

[0300] Referring to Figure 21, for a second sub-pixel located in the first display area 101a, the second storage capacitor electrode Cst2 includes a through hole TH2, and the combined orthographic projection of the solid part of the second storage capacitor electrode Cst2 and the through hole TH2 on the substrate 101 is in the shape of a rectangle or a rounded rectangle.

[0301] Referring to Figure 29 , for a first sub-pixel located in the second display area 101b, the second storage capacitor electrode Cst2 has a notch NTH1 at one corner. That is, the orthographic projection of the second storage capacitor electrode Cst2 on the substrate 101 is in an "L" shape. In other words, the combined orthographic projection of the solid part of the second storage capacitor electrode Cst2 and the notch NTH1 on the substrate 101 is in the shape of a rectangle or a rounded rectangle.

[0302] The notch NTH1 exposes a part of the first storage capacitor electrode Cst1 located under the second storage capacitor electrode Cst2 so that the first storage capacitor electrode Cst1 is electrically connected to other parts.

[0303] In the embodiment of the present application, the area of the orthographic projection of the second storage capacitor electrode Cst2 of a first sub-pixel located in the second display area 101b on the substrate 101 is smaller than the area of the orthographic projection of the second storage capacitor electrode Cst2 of a second sub-pixel located in the first display area 101a on the substrate 101. On this basis, the second storage capacitor electrode Cst2 of a first sub-pixel located in the second display area 101b is designed in an "L" shape, and there is no need to form the through hole in the second storage capacitor electrode Cst2, which is beneficial to ensuring a large overlapping area between the first storage capacitor electrode Cst1 and the second storage capacitor electrode Cst2 of a first sub-pixel located in the second display area 101b, that is, ensuring the capacitance value of the storage capacitor Cst.

[0304] As Figure 31 shown, the connection part 1A8, the connection part 1A9, the connection part 1B0 and the connection part 1B1 are located in the first source-drain layer 118.

[0305] A part of the connection part 1A8 is formed in the via hole VH6, and this part extends downward to be electrically connected to the part of the first storage capacitor electrode Cst1 exposed by the notch NTH1. Another part of the connection part 1A8 is formed in the via hole VH2, and this part extends downward to be electrically connected to the drain D2 of the second transistor T2 and the drain D1 of the first transistor T1. Through the connection part 1A8, the first storage capacitor electrode Cst1, the drain D2 of the second transistor T2 and the drain D1 of the first transistor T1 can be electrically connected.

[0306] A part of the connection part 1A9 is formed in the via hole VH12, and this part extends downward to be electrically connected to the initialization voltage line A6. Another part of the connection part 1A9 is formed in the via hole VH4, and this part extends downward to be electrically connected to the drain D7 of the seventh transistor T7. Through the connection part 1A9, the initialization voltage Vint transmitted by the initialization voltage line A6 can be supplied to the drain D7 of the seventh transistor T7.

[0307] A part of the connection part 1B0 is formed in the via hole VH5, and this part extends downward to be electrically connected to the source S7 of the seventh transistor T7. Another part of the connection part 1B0 is formed in the via hole VH10, and this part extends downward to be electrically connected to the drain D6 of the sixth transistor T6. Through the connection part 1B0, the source S7 of the seventh transistor T7 and the drain D6 of the sixth transistor T6 can be electrically connected.

[0308] A part of the connection part 1B1 is formed in the via hole VH7, and this part extends downward to be electrically connected to the second storage capacitor electrode Cst2. Another part of the connection part 1B1 is formed in the via hole VH9, and this part extends downward to be electrically connected to the source S5 of the fifth transistor T5. Through the connection part 1B1, the second storage capacitor electrode Cst2 and the source S5 of the fifth transistor T5 can be electrically connected.

[0309] Combined Figures 30 to 35 , in the second display area 101b, a connection electrode film layer f is provided. For example, the connection electrode film layer f can be composed of a transparent conductive material such as indium tin oxide (i.e., ITO). Among them, the connection electrode film layer f can include a plurality of first connection electrodes, a plurality of second connection electrodes, and a plurality of third connection electrodes.

[0310] For the convenience of description, refer to Figure 32 , in the second display area 101b, the plurality of first connection electrodes, the plurality of second connection electrodes, and the plurality of third connection electrodes that can be included in the connection electrode film layer f are divided into a plurality of conductive leads. For example, the plurality of conductive leads can include a first conductive lead 1A1, a second conductive lead 2A1, a third conductive lead 1A2, a fourth conductive lead 2A2, a fifth conductive lead 1A3, a sixth conductive lead 2A3, a seventh conductive lead 1A6, and an eighth conductive lead 2A6. That is, these conductive leads are all composed of a transparent conductive material such as indium tin oxide (i.e., ITO).

[0311] A part of the data signal line segment 1A4 is formed in the via hole VH3, and this part extends downward to be electrically connected to the source S4 of the fourth transistor T4, so as to supply the data signal Dm transmitted by the data signal line 1A4 to the fourth transistor T4.

[0312] The positive power supply line segment 1A5 is disconnected at the pixel circuit of the first sub-pixel in the second display area 101b and is divided into two parts. For the convenience of description, these two parts are respectively denoted as the first driving voltage sub-line 1A51 and the second driving voltage sub-line 1A52.

[0313] For example, the positive projection of the first driving voltage sub-line 1A51 on the substrate 101 intersects with the positive projection of the initialization voltage line A6 on the substrate 101. And the positive projection of the first driving voltage sub-line 1A51 on the substrate 101 at least partially overlaps with the positive projection of the reset control signal line A2 on the substrate 1.

[0314] For another example, the positive projection of the second driving voltage sub-line 1A52 on the substrate 101 intersects with the positive projection of the light emission control line A3 on the substrate 1. And the positive projection of the second driving voltage sub-line 1A52 on the substrate 101 at least partially overlaps with the positive projection of the second storage capacitor electrode Cst2 on the substrate 1. A part of the second driving voltage sub-line 1A52 is formed in the via VH7', and this part extends downward to be electrically connected to a part of the connection portion 1B1, so as to be electrically connected to the second storage capacitor electrode Cst2. In this way, the electrical connection between the positive power supply line, the second storage capacitor electrode Cst2, and the source S5 of the fifth transistor T5 can be realized.

[0315] The first driving voltage sub-line 1A51 and the second driving voltage sub-line 1A52 are spaced apart from each other by a certain distance in the second direction Y. For example, the positive projection of the end of the first driving voltage sub-line 1A51 close to the second driving voltage sub-line 1A52 on the substrate 101 at least partially overlaps with the positive projection of the reset control signal line A2 on the substrate 101, and the positive projection of the end of the second driving voltage sub-line 1A52 close to the first driving voltage sub-line 1A51 on the substrate 101 at least partially overlaps with the positive projection of the part of the second storage capacitor electrode Cst2 close to the light emission control line A3 on the substrate 101. The spaced-apart first driving voltage sub-line 1A51 and second driving voltage sub-line 1A52 will be electrically connected together through the connection portion.

[0316] In the second display area 101b, the scan signal line A1, the reset control signal line A2, the light emission control line A3, and the initialization voltage line A6 extending along the first direction X in each sub-pixel are respectively electrically connected through conductive leads located in the transparent conductive layer. In this way, in the light-transmitting area of the second display area 101b, only transparent conductive leads are arranged, and conductive leads made of opaque materials such as metals are not arranged. In this way, a relatively large light transmittance of the second display area 101b can be ensured.

[0317] Specifically, on both sides of the scan signal line A1 of a first sub-pixel, a first conductive lead 1A1 and a second conductive lead 2A1 are respectively provided. A part of the first conductive lead 1A1 is formed in the via VH15, and this part extends downward to be electrically connected to one end of the scan signal line A1. A part of the second conductive lead 2A1 is formed in the via VH16, and this part extends downward to be electrically connected to the other end of the scan signal line A1. With the help of the first conductive lead 1A1 and the second conductive lead 2A1, the scan signal lines A1 of the sub-pixels in the same row can be electrically connected to facilitate the supply of the scan signal Sn.

[0318] On both sides of the reset control signal line A2 of a first sub-pixel, a third conductive lead 1A2 and a fourth conductive lead 2A2 are respectively provided. A part of the third conductive lead 1A2 is formed in the via VH13, and this part extends downward to be electrically connected to one end of the reset control signal line A2. A part of the fourth conductive lead 2A2 is formed in the via VH14, and this part extends downward to be electrically connected to the other end of the reset control signal line A2. With the help of the third conductive lead 1A2 and the fourth conductive lead 2A2, the reset control signal lines A2 of the sub-pixels in the same row can be electrically connected to facilitate the supply of the reset signal Reset.

[0319] On both sides of the light emission control signal line A3 of a sub-pixel, a fifth conductive lead 1A3 and a sixth conductive lead 2A3 are respectively provided. A part of the fifth conductive lead 1A3 is formed in the via VH17, and this part extends downward to be electrically connected to one end of the light emission control signal line A3. A part of the sixth conductive lead 2A3 is formed in the via VH18, and this part extends downward to be electrically connected to the other end of the light emission control signal line A3. With the help of the fifth conductive lead 1A3 and the sixth conductive lead 2A3, the light emission control signal lines A3 of the sub-pixels in the same row can be electrically connected to facilitate the supply of the light emission control signal Em.

[0320] On both sides of the initialization voltage line A6 of a first sub-pixel, a seventh conductive lead 1A6 and an eighth conductive lead 2A6 are respectively provided. A part of the seventh conductive lead 1A6 is formed in the via VH11, and this part extends downward to be electrically connected to one end of the initialization voltage line A6. A part of the eighth conductive lead 2A6 is formed in the via VH12, and this part extends downward to be electrically connected to the other end of the initialization voltage line A6. With the help of the seventh conductive lead 1A6 and the eighth conductive lead 2A6, the initialization voltage lines A6 of the sub-pixels in the same row can be electrically connected to facilitate the supply of the light emission initialization voltage signal Vinit.

[0321] In the embodiments of the present application, the line width of at least one of the scan signal line, reset signal line, light emission control signal line, initialization voltage line, data signal line, and positive power supply line located in the second display area 101b may be less than or equal to the line width of the signal line for transmitting the same type of signal located in the first display area 101a.

[0322] For example, the line width of the data signal segment 1A4 located in the second display area 101b may be less than or approximately equal to the line width of the data signal line A1 located in the first display area 101a. For example, the line width of the data signal line 164 located in the second display area 101b may be between 1.5 μm (micrometers) and 3 μm, and the line width of the data signal line A4 located in the first display area 101a may be between 2.5 μm and 4 μm.

[0323] For example, the line width of the positive power supply segment 1A5 located in the second display area 101b may be less than or approximately equal to the line width of the positive power supply line A5 located in the first display area 101a. For example, the line width of the positive power supply line 1A5 located in the second display area 101b may be between 2 μm and 5 μm, and the line width of the positive power supply line A5 located in the first display area 101a may be between 4 μm and 7 μm.

[0324] For example, the line width of the scan signal line A1 located in the second display area 101b may be less than or approximately equal to the line width of the scan signal line A1 located in the first display area 101a. For example, the line width of the scan signal line A1 located in the second display area 101b may be between 2 μm and 3 μm, and the line width of the scan signal line A1 located in the first display area 101a may be between 3 μm and 4 μm.

[0325] For example, the line width of the initialization voltage line A6 located in the second display area 101b may be less than or approximately equal to the line width of the initialization voltage line A6 located in the first display area 101a. For example, the line width of the initialization voltage line A6 located in the first display area 101a may be between 2 μm and 3 μm, and the line width of the initialization voltage line A6 located in the first display area 101a may be between 3 μm and 6 μm.

[0326] In the embodiments of the present disclosure, the aspect ratios of the respective transistors T1 to T7 of the pixel circuit located in the second display area 101b may be approximately equal to the aspect ratios of the same type of transistors T1 to T7 of the pixel circuit located in the first display area 101a. The embodiments of the present application are not limited thereto. For example, the aspect ratios of the respective transistors T1 to T7 of the pixel circuit located in the second display area 101b may be less than the aspect ratios of the same type of transistors T1 to T7 of the pixel circuit located in the first display area 101a.

[0327] For example, the aspect ratio of the transistor T3 in the pixel circuit located in the second display region 101b may be approximately equal to the aspect ratio of the transistor T3 in the pixel circuit located in the first display region 101a. For example, the aspect ratio of the transistor T3 in the pixel circuit located in the second display region 101b and the aspect ratio of the transistor T3 in the pixel circuit located in the first display region 101a may be (2 - 4) / (20 - 26).

[0328] For example, the aspect ratio of the transistor T4 in the pixel circuit located in the second display region 101b may be approximately equal to the aspect ratio of the transistor T4 in the pixel circuit located in the first display region 101a. For example, the aspect ratio of the transistor T4 in the pixel circuit located in the second display region 101b and the aspect ratio of the transistor T4 in the pixel circuit located in the first display region 101a may be (2 - 3) / (2 - 4).

[0329] As Figure 32 shown, the connection portion 1B2 and the conductive connection portion 1B3 are located in the second gate layer 115.

[0330] A part of the connection portion 1B2 is formed in the via hole VH1, and this part extends downward to be electrically connected to the first driving voltage sub - line 1A51. Another part of the connection portion 1B2 is formed in the via hole VH7", and this part extends downward to be electrically connected to the second driving voltage sub - line 1A52. That is, through the connection portion 1B2, the first driving voltage sub - line 1A51 can be electrically connected to the second driving voltage sub - line 1A52. In this way, the positive power supply lines of the respective sub - pixels in the same column can be connected to facilitate the supply of the driving voltage signal VDD to each sub - pixel.

[0331] A part of the conductive connection portion 1B3 is formed in the via hole VH10', and this via hole VH10' exposes a part of the connection portion 1B0. In this way, the conductive connection portion 1B3 can be electrically connected to the connection portion 1B0.

[0332] As Figures 33 to 35 shown, the anode pattern of the first sub - pixel includes an anode main body 10711 and an anode connection portion 10712.

[0333] A part of the anode connection portion 10712 can be formed in the via hole VH10", and this via hole VH10" exposes a part of the conductive connection portion 1B3. In this way, the anode connection portion 10712 can be electrically connected to the conductive connection portion 1B3 and then connected to the connection portion 1B0. That is, through the conductive connection portion 1B3 and the connection portion 1B0, the anode pattern 1071, the source S7 of the seventh transistor T7, and the drain D6 of the sixth transistor T6 can be electrically connected.

[0334] For example, Figures 33 to 35The plan views of the red sub-pixel F1, blue sub-pixel F2, and green sub-pixel F3 located in the second display area 101b are respectively shown. As Figures 33 to 35 shown, in the second display area 101b, the pixel circuits of the red sub-pixel F1, blue sub-pixel F2, and green sub-pixel F3 can all be basically reduced to the size of the light-emitting unit and placed below the light-emitting unit. In this way, in the second display area 101b (i.e., the under-screen camera area), the pixel circuits of each sub-pixel can be built into the corresponding sub-pixel. Moreover, in the embodiments of the present application, by building the pixel circuits of each sub-pixel into the corresponding sub-pixel and hiding them below the light-emitting unit of the corresponding sub-pixel, it can ensure that the light transmittance of the second display area is relatively large, that is, it is beneficial to achieve a high light transmittance in the second display area.

[0335] In the embodiments of the present application, the occupied area of the pixel circuit of each sub-pixel in the second display area 101b can be represented by the following area: Refer to Figures 33 to 35 , for the pixel circuit of each sub-pixel, in the first direction X, the fifth active pattern 112e of the fifth transistor T5 and the seventh active pattern 112g of the seventh transistor T7 are respectively located on the leftmost and rightmost sides, that is, the distance between the two in the first direction X is the largest; in the second direction Y, the initialization voltage line A6 and the light-emitting control line A3 are respectively located on the uppermost and lowermost sides, that is, the distance between the two in the second direction Y is the largest. In this way, in the orthographic projection of the pixel circuit of a sub-pixel on the substrate, the fifth active pattern 112e of the fifth transistor T5 has a first side away from the seventh active pattern 112g of the seventh transistor T7, the seventh source pattern 112g of the seventh transistor T7 has a second side away from the fifth active pattern 112e of the fifth transistor T5, the initialization voltage line A6 has a third side away from the light-emitting control line A3, and the light-emitting control line A3 has a fourth side away from the initialization voltage line A6. Among them, the first side and the second side extend along the second direction Y, and the third side and the fourth side extend along the first direction X. The extension lines of these four sides will intersect to enclose a region. This region is the occupied area of the pixel circuit of a first sub-pixel located in the second display area 101b. Or rather, the occupied area of the pixel circuit of each sub-pixel in the second display area 101b can be represented by the following area: Refer to Figure 30 , and Figures 33 to 35 , eight vias VH11, VH12, VH13, VH14, VH15, VH16, VH17, VH18 are respectively located on the outermost side of the pixel circuit, and the vias VH9 and VH10 are located on the outermost side of the pixel circuit. Connecting the centers of every two adjacent vias among these 10 vias in sequence can enclose a region, as Figures 33 to 35The area AR1 surrounded by the dashed box shown in the figure can be the occupied area of the pixel circuit of a sub-pixel located in the second display area 101b.

[0336] In the embodiment of the present application, the occupied area of the light-emitting unit of the sub-pixel in the second display area 101b can be represented by the covered area of the positive projection of the anode pattern of the light-emitting unit on the substrate 101.

[0337] In the embodiment of the present application, the pixel density in the second display area 101b is basically equal to the pixel density in the first display area 101a. That is to say, within an equal area, the number of first sub-pixels arranged in the second display area 101b is basically equal to the number of second sub-pixels of the same color arranged in the first display area 101a. In this way, both the first display area and the second display area have a high pixel density, can achieve a high display quality, and have good display uniformity.

[0338] In the embodiment of the present application, unless otherwise specified, expressions such as "basically equal" and "basically equal to" can indicate that the ratio of the two values being compared is approximately equal to 1. For example, the ratio of the two values being compared can be within the range of 0.8 to 1.2.

[0339] Refer to Figure 28 , for a first sub-pixel located in the second display area 101b, the seventh active pattern 112g of the seventh transistor T7 extends from the first active pattern 112a of the first transistor T1 along the direction close to the scan signal line A1 of the first sub-pixel. That is, the seventh active pattern 112g of the seventh transistor T7 is located at the lower right of the first active pattern 112a of the first transistor T1. Through such a setting method, the outline of the occupied area of the active layer of a first sub-pixel located in the second display area 101b is square or approximately square. And, the first pattern 10611 in the auxiliary electrode pattern 1061 is circular in the positive projection on the substrate 101. Through such a setting method, it is beneficial to realize that the auxiliary electrode pattern 1061 covers the pixel circuit of the first sub-pixel.

[0340] For example, the positive projection of the auxiliary electrode pattern 1061 on the substrate 101 can cover the positive projection of the occupied area AR1 of at least one pixel circuit on the substrate 101. That is, it covers the positive projections of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the storage capacitor Cst of the pixel circuit on the substrate 101. Through such a setting, the diffraction effect of the pixel circuits of each sub-pixel on the camera of the second display area 101b can be reduced, and the display effect of the display panel 10 can be ensured.

[0341] In summary, the embodiment of the present application provides a display panel. The second cathode layer included in the display panel has a hollowed-out area, so the second cathode layer does not entirely cover the second display area. Compared with the cathode layer that entirely covers the second display area, it can effectively reduce the influence on the light transmittance, and the imaging effect of the camera located in the second display area is better.

[0342] Figure 38 It is a flowchart of a method for manufacturing a display panel provided by an embodiment of the present application. This method can be used to manufacture the display panel 10 as Figure 1 shown. Referring to Figure 38 , this method may include:

[0343] Step 201: Provide a substrate.

[0344] In the embodiment of the present application, when manufacturing the display panel 10, a substrate 101 can be obtained. Among them, the substrate 101 can be a glass substrate.

[0345] Step 202: Form a first auxiliary electrode layer, a first anode layer, a first light-emitting layer, and a first cathode layer that are sequentially stacked in the first display area.

[0346] In the embodiment of the present application, referring to Figure 1 , the first auxiliary electrode layer 102, the first anode layer 103, the first light-emitting layer 104, and the first cathode layer 105 can all be located in the first display area 101a of the substrate 101 and are sequentially stacked in a direction away from the substrate 101. Among them, the first auxiliary electrode layer 102 can be connected to the first cathode layer 105.

[0347] Step 203: Form a second auxiliary electrode layer, a second anode layer, a second light-emitting layer, and a second cathode layer that are sequentially stacked in the second display area.

[0348] In the embodiment of the present application, referring to Figure 1 , the second auxiliary electrode 106, the second anode layer 107, the second light-emitting layer 108, and the second cathode layer 109 can all be located in the second display area 101b of the substrate 101 and are sequentially stacked in a direction away from the substrate 101.

[0349] Among them, the second auxiliary electrode layer 106 can be connected to the first auxiliary electrode layer 102, the second cathode layer 109 can be connected to the first cathode layer 105, and the second cathode layer 109 can have at least one hollowed-out area.

[0350] Since the second cathode layer 109 included in the display panel 10 has at least one hollowed-out area, the second cathode layer 109 does not entirely cover the second display area 101b. Compared with the cathode layer that entirely covers the second display area 101b, the influence on the light transmittance can be effectively reduced, and the imaging effect of the camera located in the second display area 101b is better.

[0351] In the embodiment of the present application, the first auxiliary electrode layer 102 is connected to the first cathode layer 105, the second auxiliary electrode layer 106 is connected to the first auxiliary electrode layer 102, and the second cathode layer 109 is connected to the first cathode layer 105. That is to say, the first auxiliary electrode layer 102, the first cathode layer 105, the second auxiliary electrode layer 106, and the second cathode layer 109 are interconnected, which can make the voltage difference of the power supply signals received by the first cathode layer 105 and the second cathode layer 109 smaller, ensure the brightness uniformity of the display panel 10, and the display effect of the display panel 10 is better.

[0352] Step 204: Form a plurality of pixel circuits in the second display area.

[0353] In the embodiment of the present application, each pixel circuit 110 may include at least one layer of opaque pattern b. The second auxiliary electrode layer 106 may include: a plurality of auxiliary electrode patterns 1061 arranged at intervals. At least 50% of the positive projection area of at least one layer of opaque pattern b in at least one pixel circuit 110 on the substrate 101 overlaps with the positive projection of one auxiliary electrode pattern 1061 on the substrate 101. Thus, the diffraction effect of the pixel circuit 110 on the camera disposed in the second display area 101b can be relatively small, and the display effect of the display panel 10 can be ensured.

[0354] In summary, the embodiment of the present application provides a method for manufacturing a display panel. The second cathode layer included in the display panel manufactured by this method has a hollowed-out area, so the second cathode layer does not entirely cover the second display area. Compared with the cathode layer that entirely covers the second display area, the influence on the light transmittance can be effectively reduced, and the imaging effect of the camera located in the second display area is better.

[0355] Figure 39 It is a flowchart of another method for manufacturing a display panel provided by the embodiment of the present application. Refer to Figure 39 It can be seen that this method may include:

[0356] Step 301: Provide a substrate.

[0357] In the embodiment of the present application, when manufacturing the display panel 10, a substrate 101 can be obtained. Among them, the substrate 101 can be a glass substrate.

[0358] Step 302: Form a first auxiliary electrode layer in the first display area and a second auxiliary electrode layer in the second display area.

[0359] In the embodiment of the present application, referring to Figure 40 , a first auxiliary electrode layer 102 and a second auxiliary electrode layer 106 can be formed on one side of the substrate 101 by a single patterning process. Among them, the first auxiliary electrode layer 102 can be located in the first display area 101a of the substrate 101, and the second auxiliary electrode layer 106 can be located in the second display area 101b of the substrate 101.

[0360] Among them, the materials of the first auxiliary electrode layer 102 and the second auxiliary electrode layer 106 can be the same. Optionally, the materials of the first auxiliary electrode layer 102 and the second auxiliary electrode layer 106 can both include: metal. For example, they can both be molybdenum or they can both be aluminum alloy.

[0361] Optionally, the second auxiliary electrode layer 106 can include a plurality of auxiliary electrode patterns 1061 arranged at intervals, and at least part of the edges of the positive projection of each auxiliary electrode pattern 1061 on the substrate 101 can be arc-shaped.

[0362] Step 303: Form a first buffer layer in the first display area and the second display area.

[0363] Step 304: Form an active layer on the side of the first buffer layer away from the substrate.

[0364] Figure 41 is a schematic structural diagram of an active layer provided by an embodiment of the present application. Referring to Figure 41 , the width of the part of the active layer 112 located in the first display area 101a is greater than the width of the part of the active layer 112 located in the second display area 101b. Thereby, the transmittance and pixel density of the second display area 101b can be improved, ensuring the imaging effect of the camera located in the second display area 101b.

[0365] Optionally, the width range of the part of the active layer 112 located in the first display area 101a is 2.0 μm to 2.5 μm, and the width range of the part of the active layer 112 located in the second display area 101b is 1.4 μm to 1.6 μm.

[0366] In the embodiment of the present application, referring to Figures 42 to 44, the active layer 112 may include a plurality of strip-shaped patterns. Moreover, the orthographic projection of the pattern of the active layer 112 located in the first display area 101a on the substrate 101 and the orthographic projection of the first auxiliary electrode layer 102 on the substrate 101 have an overlapping area. The orthographic projection of the pattern of the active layer 112 located in the second display area 101b on the substrate 101 and the orthographic projection of the auxiliary electrode pattern 1061 on the substrate 101 have an overlapping area.

[0367] Among them, the material for making the active layer 112 may include polycrystalline silicon (poly).

[0368] Step 305: Form a second buffer layer on the side of the active layer away from the substrate.

[0369] In the embodiment of the present application, the material for making the buffer layer 111 may include: silicon nitride and silicon oxide.

[0370] Step 306: Form a first gate layer on the side of the buffer layer away from the substrate.

[0371] Figure 45 is a schematic structural diagram of a first gate layer provided by an embodiment of the present application. Refer to Figure 45 , the width of the part of the first gate layer 113 located in the first display area 101a is greater than the width of the part of the first gate layer 113 located in the second display area 101b. Thereby, the transmittance and pixel density of the second display area 101b can be improved, and the imaging effect of the camera located in the second display area 101b can be ensured.

[0372] Optionally, the width range of the part of the first gate layer 113 located in the first display area 101a is 3.0 μm to 3.4 μm, and the width range of the part of the first gate layer 113 located in the second display area 101b is 1.8 μm to 2.0 μm.

[0373] In the embodiment of the present application, refer to Figures 46 to 48 , a first gate layer 113 may be formed on the side of the second buffer layer 113 away from the substrate 101. Combining Figures 4 , the first gate layer 113 may include a plurality of strip-shaped patterns. Moreover, the orthographic projection of the pattern of the first gate layer 113 located in the first display area 101a on the substrate 101 and the orthographic projection of the first auxiliary electrode layer 102 on the substrate 101 have an overlapping area. The orthographic projection of the pattern of the first gate layer 113 located in the second display area 101b on the substrate 101 and the orthographic projection of the auxiliary electrode pattern 1061 on the substrate 101 have an overlapping area.

[0374] Step 307: Form a first gate insulating layer on a side of the first gate layer away from the substrate.

[0375] Reference ​ , for the convenience of showing each via hole 114a in the first gate insulating layer 114, ​ a filling pattern is adopted to represent the via hole 114a. Other areas without the drawn filling pattern are used to represent the areas where the first gate insulating layer 114 has solid materials. Combining ​ , the part of the first gate insulating layer 114 located in the second display area 101b has via holes 114a, and the part located in the first display area 101a does not have via holes 114a.

[0376] Step 308: Form a second gate layer on a side of the first gate insulating layer away from the substrate.

[0377] ​ is a schematic structural diagram of a second gate layer provided by an embodiment of the present application. Reference ​ , the width of the part of the second gate layer 115 located in the first display area 101a is greater than the width of the part of the second gate layer 115 located in the second display area 101b. Thereby, the transmittance and pixel density of the second display area 101b can be improved, and the imaging effect of the camera located in the second display area 101b can be ensured.

[0378] Optionally, the width range of the part of the second gate layer 115 located in the first display area 101a is 3.0 μm to 3.4 μm, and the width range of the part of the second gate layer 115 located in the second display area 101b is 1.8 μm to 2.0 μm.

[0379] In the embodiment of the present application, reference ​ , a second gate layer 115 can be formed on a side of the first gate insulating layer 114 away from the substrate 101. Reference ​ , the second gate layer 115 can include multiple patterns. Moreover, the orthographic projection of the pattern of the second gate layer 115 located in the first display area 101a on the substrate 101 and the orthographic projection of the first auxiliary electrode layer 102 on the substrate 101 have an overlapping area. The orthographic projection of the pattern of the second gate layer 115 located in the second display area 101b on the substrate 101 and the orthographic projection of the auxiliary electrode pattern 1061 on the substrate 101 have an overlapping area.

[0380] Step 309: Form a second gate insulating layer and an interlayer dielectric layer on a side of the second gate layer away from the substrate.

[0381] ​ is a schematic structural diagram of an interlayer dielectric layer provided by an embodiment of the present application. ​It is a schematic diagram of forming an interlayer dielectric layer in a second display area provided by an embodiment of the present application. ​ It is a schematic diagram of forming an interlayer dielectric layer in a first display area provided by an embodiment of the present application. ​ It is a schematic diagram of forming an interlayer dielectric layer in a first display area and a second display area provided by an embodiment of the present application.

[0382] For the convenience of showing each via hole 117a in the interlayer dielectric layer 117, ​ a filling pattern is used to represent the via hole 117a in [the figure]. Other areas without the drawn filling pattern are used to represent the areas where the interlayer dielectric layer 117 has solid materials. Combining ​ , both the part of the interlayer dielectric layer 117 located in the first display area 101a and the part located in the second display area 101b have via holes 117a.

[0383] It should be noted that each via hole 117a opened in the interlayer dielectric layer 117 is used for the film layer formed subsequently to be connected to the film layer on the side of the interlayer dielectric layer 117 close to the substrate 101. That is to say, each of these via holes 117a is a via hole for film layer connection. Therefore, the larger the aperture of the via hole, the smaller the transmittance; the smaller the aperture of the via hole, the larger the transmittance.

[0384] Therefore, in order to improve the transmittance and pixel density of the second display area 101b and ensure the imaging effect of the camera located in the second display area 101b, the aperture of the via hole 117a of the interlayer dielectric layer 117 located in the second display area 101a can be made smaller than the aperture of the via hole 117a of the interlayer dielectric layer 117 located in the first display area 101a.

[0385] Optionally, the aperture range of the via hole 117a of the interlayer dielectric layer 117 located in the first display area 101a is 2.3 μm to 2.5 μm, and the aperture range of the via hole 117a of the interlayer dielectric layer 117 located in the second display area 101b is 1.8 μm to 2.0 μm.

[0386] In the embodiment of the present application, the film layer structure of the second gate insulating layer 116 and the film layer structure of the interlayer dielectric layer 117 can be the same, which will not be elaborated herein in the embodiment of the present application.

[0387] Step 310: Form a first source-drain layer on the side of the interlayer dielectric layer away from the substrate.

[0388] ​ It is a schematic diagram of the structure of a first source-drain layer provided by an embodiment of the present application. Refer to ​, the width of the first source-drain layer 118 in the portion of the first display area 101a is greater than the width of the first source-drain layer 118 in the portion of the second display area 101b. Thereby, the transmittance and pixel density of the second display area 101b can be improved, ensuring the imaging effect of the camera located in the second display area 101b.

[0389] Optionally, the width range of the portion of the first source-drain layer 118 in the first display area 101a is 3.0 μm to 3.2 μm, and the width range of the portion of the first source-drain layer 118 in the second display area 101b is 1.4 μm to 1.6 μm.

[0390] In the embodiment of the present application, referring to ​ , the first source-drain layer 118 can be formed on the side of the interlayer dielectric layer 117 away from the substrate 101. Referring to ​ , the first source-drain layer 118 can include a plurality of patterns. Moreover, the orthographic projection of the pattern of the first source-drain layer 118 in the first display area 101a on the substrate 101 and the orthographic projection of the first auxiliary electrode layer 102 on the substrate 101 have an overlapping area. The orthographic projection of the pattern of the first source-drain layer 118 in the second display area 101b on the substrate 101 and the orthographic projection of the auxiliary electrode pattern 1061 on the substrate 101 have an overlapping area.

[0391] Step 311: Form a passivation layer on the side of the first source-drain layer away from the substrate.

[0392] ​ is a schematic structural diagram of a passivation layer provided by an embodiment of the present application. ​ is a schematic diagram of forming a passivation layer in the second display area provided by an embodiment of the present application. ​ is a schematic diagram of forming a passivation layer in the first display area provided by an embodiment of the present application. ​ is a schematic diagram of forming a passivation layer in the first display area and the second display area provided by an embodiment of the present application.

[0393] To facilitate showing each via hole 119a in the passivation layer 119, ​ the via holes 119a are represented by filled patterns in ​ . The other areas without drawn filled patterns are used to represent the areas where the passivation layer 119 has solid materials. Combining

[0394] It should be noted that each via hole 119a formed in the passivation layer 119 is used for the film layer formed subsequently to be connected to the film layer on the side of the passivation layer 119 close to the substrate 101. That is to say, each of the via holes 119a is a via hole for film layer connection. The larger the aperture of the via hole, the smaller the transmittance; the smaller the aperture of the via hole, the larger the transmittance.

[0395] Therefore, in order to improve the transmittance and pixel density of the second display area 101b and ensure the imaging effect of the camera located in the second display area 101b, the aperture of the via hole 119a of the passivation layer 119 in the first display area 101a can be made larger than the aperture of the via hole 119a of the passivation layer 119 in the second display area 101a.

[0396] Optionally, the aperture range of the via hole 119a of the passivation layer 119 in the first display area 101a is 4.5 μm to 5 μm, and the aperture range of the via hole 119a of the passivation layer 119 in the second display area 101b is 1.8 μm to 2.0 μm.

[0397] Step 312: Form a connection electrode film layer on the side of the passivation layer away from the substrate.

[0398] In the embodiment of the present application, referring to ​ , the connection electrode film layer f may include a plurality of first connection electrodes 124, a plurality of second connection electrodes 127, and a plurality of third connection electrodes 130. That is to say, the plurality of first connection electrodes 124, the plurality of second connection electrodes 127, and the plurality of third connection electrodes 130 can be prepared by the same preparation process. Among them, each connection electrode in the plurality of first connection electrodes 124, the plurality of second connection electrodes 127, and the plurality of third connection electrodes 130 can be made of a transparent conductive material. Thereby, the transmittance of the second display area 101b can be ensured, and the imaging effect of the camera is improved. For example, the first connection electrode 124, the second connection electrode 127, and the third connection electrode 130 can all be made of ITO.

[0399] Step 313: Form a first planarization layer on the side of the connection electrode film layer away from the substrate.

[0400] ​ It is a schematic structural diagram of a first planarization layer provided by an embodiment of the present application. ​ It is a schematic diagram of forming a first planarization layer in the second display area provided by an embodiment of the present application. ​ It is a schematic diagram of forming a first planarization layer in the first display area provided by an embodiment of the present application. ​ It is a schematic diagram of forming a first planarization layer in the first display area and the second display area provided by an embodiment of the present application.

[0401] To facilitate showing each via 120a in the first flat layer 120, ​ a filling pattern is adopted in [the figure] to represent the via 120a. Other areas without the drawn filling pattern are used to represent the areas where the first flat layer 120 has solid materials. Combining ​ , both the part of the first flat layer 120 located in the first display area 101a and the part located in the second display area 101b have vias 120a.

[0402] It should be noted that each via 120a formed in the first flat layer 120 is used for the film layer formed subsequently to connect with the film layer on the side of the first flat layer 120 close to the substrate 101. That is to say, each of these vias 120a is a via for film layer connection. The larger the aperture of the via, the smaller the transmittance; the smaller the aperture of the via, the larger the transmittance.

[0403] Therefore, in order to improve the transmittance and pixel density of the second display area 101b and ensure the imaging effect of the camera located in the second display area 101b, the aperture of the via 120a of the first flat layer 120 located in the first display area 101a can be made larger than the aperture of the via 120a of the first flat layer 120 located in the second display area 101a.

[0404] Optionally, the aperture range of the via 120a of the first flat layer 120 located in the first display area 101a is 2.3 μm to 2.5 μm, and the aperture range of the via 120a of the first flat layer 120 located in the second display area 101b is 1.8 μm to 2.0 μm.

[0405] Step 314: Form a second source-drain layer on the side of the first flat layer away from the substrate.

[0406] ​ is a schematic structural diagram of a second source-drain layer provided by an embodiment of the present application. Referring to ​ , the width of the part of the second source-drain layer 121 located in the first display area 101a is larger than the width of the part of the second source-drain layer 121 located in the second display area 101b. Thereby, the transmittance and pixel density of the second display area 101b can be improved, and the imaging effect of the camera located in the second display area 101b can be ensured.

[0407] Optionally, the width range of the part of the second source-drain layer 121 located in the first display area 101a is 4.5 μm to 5 μm, and the width range of the part of the second source-drain layer 121 located in the second display area 101b is 1.4 μm to 1.6 μm.

[0408] In the embodiment of the present application, referring to ​, the second source-drain layer 121 can be formed on the side of the first flat layer 120 away from the substrate 101. Refer to Figures 76 to 79 , the second source-drain layer 121 can include a plurality of patterns. Moreover, the projection of the pattern of the second source-drain layer 121 located in the first display area 101a on the substrate 101 overlaps with the projection of the first auxiliary electrode layer 102 on the substrate 101. The projection of the pattern of the second source-drain layer 121 located in the second display area 101b on the substrate 101 overlaps with the projection of the auxiliary electrode pattern 1061 on the substrate 101.

[0409] Step 315: Form a second flat layer on the side of the second source-drain layer away from the substrate.

[0410] Figure 80 FIG. is a schematic structural diagram of a second flat layer provided by an embodiment of the present application. Figure 81 FIG. is a schematic diagram of forming a second flat layer in a second display area provided by an embodiment of the present application. Figure 82 FIG. is a schematic diagram of forming a second flat layer in a first display area provided by an embodiment of the present application. Figure 83 FIG. is a schematic diagram of forming a second flat layer in a first display area and a second display area provided by an embodiment of the present application.

[0411] For the convenience of showing each via hole 122a in the second flat layer 122, Figures 80 to 83 the via holes 122a are represented by filling patterns. The other areas without the drawn filling patterns are used to represent the areas where the second flat layer 122 has solid materials. Combining Figures 80 to 83 , both the part of the second flat layer 122 located in the first display area 101a and the part located in the second display area 101b have via holes 122a.

[0412] It should be noted that each via hole 122a opened in the second flat layer 122 is used for the film layer formed subsequently to be connected to the film layer on the side of the second flat layer 122 close to the substrate 101. That is to say, each of these via holes 122a is a via hole for film layer connection. The larger the aperture of the via hole, the smaller the transmittance; the smaller the aperture of the via hole, the larger the transmittance.

[0413] Therefore, in order to improve the transmittance and pixel density of the second display area 101b and ensure the imaging effect of the camera located in the second display area 101b, the aperture of the via hole 122a of the second flat layer 122 located in the first display area 101a can be made larger than the aperture of the via hole 122a of the first flat layer 123 located in the second display area 101a.

[0414] Optionally, the aperture range of the vias 122a of the second flat layer 122 located in the first display area 101a is 3.8 μm to 4.1 μm, and the aperture range of the vias 122a of the second flat layer 122 located in the second display area 101b is 3.3 μm to 3.5 μm.

[0415] Step 316: Form a first anode layer in the first display area and a second anode layer in the second display area.

[0416] In the embodiment of the present application, the first anode layer 103 and the second anode layer 107 can be formed by the same patterning process. Among them, the first anode layer 103 can be located in the first display area 101a of the substrate 101, and the second anode layer 107 can be located in the second display area 101b of the substrate 101.

[0417] Figure 84 It is a schematic diagram of a first anode layer and a second anode layer provided by an embodiment of the present application. Figure 85 It is a schematic diagram of forming a second anode layer in the second display area provided by an embodiment of the present application. Figure 86 It is a schematic diagram of forming a first anode layer in the first display area provided by an embodiment of the present application. Figure 87 It is a schematic diagram of forming a first anode layer in the first display area and a second anode layer in the second display area provided by an embodiment of the present application.

[0418] Reference Figure 84 , the second anode layer 107 can include: a plurality of anode patterns 1071 arranged at intervals. Reference Figure 85 And Figure 87 , the orthographic projection of each anode pattern 1071 in the plurality of anode patterns 1071 on the substrate 101 can be located within the orthographic projection of an auxiliary electrode pattern 1061 on the substrate 101. Reference Figure 84 , the first anode layer 103 can include a plurality of anode patterns 1031 arranged at intervals. Reference Figure 86 And Figure 87 , the orthographic projections of the plurality of anode patterns 1031 on the substrate 101 are all located within the orthographic projection of the first auxiliary electrode layer 102 on the substrate 101.

[0419] In the embodiment of the present application, each anode pattern 1071 included in the second anode layer 107 can be used to form a light-emitting unit of a first sub-pixel. Each anode pattern 1031 included in the first anode layer 103 can be used to form a light-emitting unit of a second sub-pixel. The display panel 10 can include a plurality of sub-pixels, and the sub-pixels located in the second display area 101b among the plurality of sub-pixels are the first sub-pixels. The sub-pixels located in the first display area 101a among the plurality of sub-pixels are the second sub-pixels.

[0420] The plurality of sub-pixels include: a red sub-pixel, a green sub-pixel, and a blue sub-pixel. Moreover, both the first display area 101a and the second display area 101b can have sub-pixels of various colors. That is, the plurality of first sub-pixels in the first display area 101a include a red sub-pixel, a green sub-pixel, and a blue sub-pixel. The plurality of second sub-pixels in the second display area 101b include a red sub-pixel, a green sub-pixel, and a blue sub-pixel.

[0421] To improve the transmittance and pixel density of the second display area 101b and ensure the imaging effect of the camera located in the second display area 101b, the size of the anode pattern 1071 of the first sub-pixel located in the second display area 101b can be made smaller than the size of the anode pattern 1031 of the second sub-pixel located in the first display area 101a.

[0422] Optionally, the size of the anode pattern 1071 of the red sub-pixel located in the second display area 101b is smaller than the size of the anode pattern 1031 of the red sub-pixel located in the first display area 101a. The size of the anode pattern 1071 of the green sub-pixel located in the second display area 101b is smaller than the size of the anode pattern 1031 of the green sub-pixel located in the first display area 101a. The size of the anode pattern 1071 of the blue sub-pixel located in the second display area 101b is smaller than the size of the anode pattern 1031 of the blue sub-pixel located in the first display area 101a.

[0423] Exemplarily, the diameter range of the anode pattern 1031 of the red sub-pixel located in the first display area 101a is 30 μm to 32 μm, and the diameter range of the anode pattern 1071 of the red sub-pixel located in the second display area 101b is 20 μm to 22 μm. The diameter range of the anode pattern 1031 of the green sub-pixel located in the first display area 101a is 25 μm to 27 μm, and the diameter range of the anode pattern 1071 of the green sub-pixel located in the second display area 101b is 16 μm to 18 μm. The diameter range of the anode pattern 1031 of the blue sub-pixel located in the first display area 101a is 35 μm to 37 μm, and the diameter range of the anode pattern 1071 of the blue sub-pixel located in the second display area 101b is 23 μm to 25 μm.

[0424] Step 317: Form a pixel defining layer on the side of the first anode layer and the second anode layer away from the substrate.

[0425] Figure 88 It is a schematic structural diagram of a pixel defining layer provided by an embodiment of the present application. Figure 89 It is a schematic diagram of forming a pixel defining layer in the second display area provided by an embodiment of the present application.Figure 90 It is a schematic diagram of forming a pixel definition layer in a first display area provided by an embodiment of the present application. Figure 91 It is a schematic diagram of forming a pixel definition layer in a first display area and a second display area provided by an embodiment of the present application.

[0426] Referring to Figures 88 to 91 , the pixel definition layer 134 may have a plurality of tenth vias 134a, and each tenth via 134a may expose an anode pattern. For example, the tenth via 134a located in the first display area 101a of the pixel definition layer 134 may expose an anode pattern 1031 in the first anode layer 103, and the tenth via 134a located in the second display area 101b of the pixel definition layer 134 may expose an anode pattern 1071 in the second anode layer 107.

[0427] For the convenience of showing each tenth via 134a in the pixel definition layer 134, Figures 88 to 91 a filling pattern is used to represent the first via 134a in . Other areas without the drawn filling pattern are used to represent the areas where the pixel definition layer 134 has solid materials. Combining Figures 88 to 91 , both the part of the pixel definition layer 134 located in the first display area 101a and the part located in the second display area 101b have tenth vias 134a.

[0428] It should be noted that each tenth via 134a opened in the pixel definition layer 134 is used for the film layer formed subsequently to be connected to the film layer on the side of the pixel definition layer 134 close to the substrate 101. That is to say, each of these tenth vias 134a is a via for film layer connection. The larger the aperture of the tenth via, the smaller the transmittance; the smaller the aperture of the tenth via, the larger the transmittance.

[0429] Therefore, in order to improve the transmittance and pixel density of the second display area 101b and ensure the imaging effect of the camera located in the second display area 101b, the aperture of the tenth via 134a of the pixel definition layer 134 located in the first display area 101a can be made larger than the aperture of the tenth via 134a of the pixel definition layer 134 located in the second display area 101a.

[0430] Optionally, the aperture of the tenth viaduct 134a of the anode pattern 1071 for exposing the red sub-pixels located in the second display area 101b in the pixel defining layer 134 is smaller than the aperture of the tenth viaduct 134a of the anode pattern 1031 for exposing the red sub-pixels located in the first display area 101a in the pixel defining layer 134. The aperture of the tenth viaduct 134a of the anode pattern 1071 for exposing the green sub-pixels located in the second display area 101b in the pixel defining layer 134 is smaller than the aperture of the tenth viaduct 134a of the anode pattern 1031 for exposing the green sub-pixels located in the first display area 101a in the pixel defining layer 134. The aperture of the tenth viaduct 134a of the anode pattern 1071 for exposing the blue sub-pixels located in the second display area 101b in the pixel defining layer 134 is smaller than the aperture of the tenth viaduct 134a of the anode pattern 1031 for exposing the blue sub-pixels located in the first display area 101a in the pixel defining layer 134.

[0431] Exemplarily, the aperture range of the tenth viaduct 134a of the anode pattern 1031 for exposing the red sub-pixels located in the first display area 101a in the pixel defining layer 134 is 24 μm to 26 μm. The aperture range of the tenth viaduct 134a of the anode pattern 1071 for exposing the red sub-pixels located in the second display area 101b in the pixel defining layer 134 is 16 μm to 18 μm. The aperture range of the tenth viaduct 134a of the anode pattern 1031 for exposing the green sub-pixels located in the first display area 101a in the pixel defining layer 134 is 18 μm to 20 μm. The aperture range of the tenth viaduct 134a of the anode pattern 1071 for exposing the green sub-pixels located in the second display area 101b in the pixel defining layer 134 is 12 μm to 14 μm. The aperture range of the tenth viaduct 134a of the anode pattern 1031 for exposing the blue sub-pixels located in the first display area 101a in the pixel defining layer 134 is 29 μm to 31 μm. The aperture range of the tenth viaduct 134a of the anode pattern 1071 for exposing the blue sub-pixels located in the second display area 101b in the pixel defining layer 134 is 19 μm to 21 μm.

[0432] Step 318: Form a first light-emitting layer in the first display area and form a second light-emitting layer in the second display area.

[0433] In the embodiment of the present application, the first light-emitting layer 104 and the second light-emitting layer 108 can be formed by the same patterning process. Among them, the first light-emitting layer 104 can be located in the first display area 101a of the substrate 101, and the second light-emitting layer 108 can be located in the second display area 101b of the substrate 101.

[0434] Optionally, the first light-emitting layer 104 and the second light-emitting layer 108 can be prepared by using a fine metal mask (FMM).

[0435] Reference Figure 88 , the portion of the pixel defining layer 134 located in the first display area 101a and the portion located in the second display area 101b can both have tenth vias. The light-emitting layer pattern of the first light-emitting layer 104 can be located in the tenth via 134a of the portion of the pixel defining layer 134 in the first display area 101a, and is connected to an anode pattern exposed by the tenth via 134a. The light-emitting layer pattern 1081 of the second light-emitting layer 108 can be located in the tenth via of the portion of the pixel defining layer 134 in the second display area 101b, and is connected to an anode pattern exposed by the tenth via.

[0436] It should be noted that each light-emitting layer pattern included in the first light-emitting layer 104 can be used to form a light-emitting unit of a second sub-pixel, and each light-emitting layer pattern 1081 included in the second light-emitting layer 108 can be used to form a light-emitting unit of a first sub-pixel.

[0437] Step 319: Form a support layer on the side of the first light-emitting layer and the second light-emitting layer away from the substrate.

[0438] In the embodiment of the present application, a support layer 135 can be formed on the side of the first light-emitting layer 104 and the second light-emitting layer 108 away from the substrate 101. The support layer 135 can have a plurality of support patterns, and the orthographic projection of the plurality of support patterns on the substrate 101 at least partially does not overlap with the orthographic projection of the light-emitting layer pattern on the substrate 101. So that the subsequently formed cathode layer (the first cathode layer 105 or the second cathode layer 109) can contact the light-emitting layer pattern, ensuring that the display panel 10 can emit light normally.

[0439] Step 320: Form a first cathode layer in the first display area and a second cathode layer in the second display area.

[0440] In the embodiment of the present application, reference Figure 92 , the first cathode layer 105 and the second cathode layer 109 can be formed by the same patterning process. Among them, the first cathode layer 105 can be located in the first display area 101a of the substrate 101, and the second cathode layer 109 can be located in the second display area 101b of the substrate 101. Among them, the first cathode layer 105 can be connected to the second cathode layer 109.

[0441] Reference Figures 92 to 95, the first cathode layer 105 does not have a hollowed-out area, and the first cathode layer 105 is connected to the light-emitting layer pattern of the first light-emitting layer 104. The second cathode layer 109 has at least one hollowed-out area. Therefore, the portion of the second cathode layer 109 other than at least one hollowed-out area can be connected to the light-emitting layer pattern 1081 of the second light-emitting layer 108.

[0442] In the embodiment of the present application, the first cathode layer 105 and the first auxiliary electrode layer 102 formed in the above step 302 can also be located in the middle peripheral area 101c of the substrate 101. The portion of the first cathode layer 105 located in the peripheral area 101c can be connected to the portion of the first auxiliary electrode layer 102 located in the peripheral area 101c.

[0443] Since other traces usually need to be provided in the second area 101c2 of the peripheral area 101c, the portion of the first auxiliary electrode layer 102 located in the second area 101c2 is not connected to the portion of the first cathode layer 105 located in the second area 101c2, so as to avoid affecting the setting of other traces.

[0444] Moreover, the portion of the first auxiliary electrode layer 102 located in the first area 101c1 is connected to the portion of the first cathode layer 105 located in the first area 101c1. The portion of the first auxiliary electrode layer 102 located in the third area 101c3 is connected to the portion of the first cathode layer 105 located in the third area 101c3. The portion of the first auxiliary electrode layer 102 located in the fourth area 101c4 is connected to the portion of the first cathode layer 105 located in the fourth area 101c4.

[0445] In summary, the embodiment of the present application provides a method for manufacturing a display panel. The second cathode layer included in the display panel manufactured by this method has a hollowed-out area. Therefore, the second cathode layer does not entirely cover the second display area. Compared with the cathode layer that entirely covers the second display area, it can effectively reduce the influence on the light transmittance, and the imaging effect of the camera located in the second display area is better.

[0446] Figure 96 It is a schematic structural diagram of a display device provided by an embodiment of the present application. Refer to Figure 96 As can be seen, the display device may include: an image sensor 40 and a display panel 10 as provided in the above embodiment. The image sensor 40 can be located on the side of the substrate 101 of the display panel 10 away from the second auxiliary electrode layer 106 and in the second display area 101b of the substrate 101. Among them, the image sensor 30 can be a front camera of the display device for taking pictures.

[0447] Optionally, the display device may be any product or component with a display function, such as an OLED display device, a liquid crystal display device, an electronic paper, a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, or a navigator.

[0448] The above are only optional embodiments of the present application and are not intended to limit the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present application shall be included within the protection scope of the present application.

Claims

1. A display panel, characterized in that, the display panel includes: a substrate substrate having a first display area and a second display area, the first display area being located on one side of the second display area, and the transmittance of the second display area being greater than that of the first display area; a first auxiliary electrode layer, a first anode layer, a first light-emitting layer, and a first cathode layer located in the first display area and stacked in sequence in a direction away from the substrate substrate; a second auxiliary electrode layer, a second anode layer, a second light-emitting layer, and a second cathode layer located in the second display area and stacked in sequence in a direction away from the substrate substrate; wherein, the first auxiliary electrode layer is electrically connected to the first cathode layer, the second auxiliary electrode layer is connected to the first auxiliary electrode layer, the second cathode layer is connected to the first cathode layer, and the second cathode layer has at least one hollowed-out area; the display panel further includes a plurality of pixel circuits located in the second display area, each pixel circuit including at least one layer of opaque pattern; wherein, the second auxiliary electrode layer includes: a plurality of auxiliary electrode patterns electrically connected, and at least part of the boundary of at least one layer of opaque pattern of at least one pixel circuit among the plurality of pixel circuits is located within the orthographic projection of the corresponding auxiliary electrode pattern on the substrate substrate.

2. The display panel according to claim 1, characterized in that, the orthographic projection of the auxiliary electrode pattern on the substrate substrate covers the orthographic projection of at least one layer of opaque pattern of at least one pixel circuit on the substrate substrate.

3. The display panel according to claim 2, characterized in that, the at least one layer of opaque pattern includes multiple layers of opaque patterns; the multiple layers of opaque patterns include an overlapping portion and a non-overlapping portion, at least part of the orthographic projection of the overlapping portion on the substrate substrate is located within the orthographic projection of the corresponding auxiliary electrode pattern on the substrate substrate, and at least part of the orthographic projection of the non-overlapping portion on the substrate substrate is located within the orthographic projection of the corresponding auxiliary electrode pattern on the substrate substrate.

4. The display panel according to claim 3, characterized in that, the orthographic projection of the overlapping portion on the substrate substrate is located within the orthographic projection of the corresponding auxiliary electrode pattern on the substrate substrate.

5. The display panel according to claim 1, characterized in that, at least part of the edge of the orthographic projection of the auxiliary electrode pattern on the substrate substrate is arc-shaped.

6. The display panel according to claim 5, characterized in that, the edge of the orthographic projection of the auxiliary electrode pattern on the substrate substrate includes an arc segment, and the ratio of the length of the arc segment to the perimeter of the edge is greater than or equal to 50%.

7. The display panel according to claim 1, characterized in that, the auxiliary electrode pattern includes: a first pattern and a second pattern; the orthographic projection of the first pattern on the substrate substrate overlaps with more than 50% of the area of the orthographic projection of at least one layer of opaque pattern of at least one pixel circuit on the substrate substrate; the second pattern is used for electrical connection with an adjacent auxiliary electrode pattern.

8. The display panel according to claim 7, wherein, the shape of the orthographic projection of the first pattern on the substrate is circular.

9. The display panel according to claim 1, wherein, the substrate further has a peripheral area surrounding the first display area and the second display area; the first auxiliary electrode layer and the first cathode layer are also located in the peripheral area, and the part of the first auxiliary electrode layer located in the peripheral area is electrically connected to the part of the first cathode layer located in the peripheral area.

10. The display panel according to claim 9, wherein, the orthographic projection of the first auxiliary electrode layer on the substrate covers the first display area; the peripheral area includes: a first area and a second area arranged opposite and parallel to each other, and a third area and a fourth area arranged opposite and parallel to each other. The extending direction of the first area is perpendicular to the extending direction of the third area, and the distance between the second display area and the first area is less than the distance between the second display area and the second area; wherein, the part of the first auxiliary electrode layer located in the first area is connected to the part of the first cathode layer located in the first area, the part of the first auxiliary electrode layer located in the third area is connected to the part of the first cathode layer located in the third area, and the part of the first auxiliary electrode layer located in the fourth area is connected to the part of the first cathode layer located in the fourth area; the part of the first auxiliary electrode layer located in the second area is not connected to the part of the first cathode layer located in the second area.

11. The display panel according to any one of claims 1 to 10, wherein, multiple auxiliary electrode patterns overlap each other.

12. The display panel according to any one of claims 1 to 10, wherein, the display panel further includes: a plurality of first connection electrodes located in the second display area, and multiple auxiliary electrode patterns are electrically connected through the plurality of first connection electrodes.

13. The display panel according to any one of claims 1 to 10, wherein, the display panel further includes: an active layer, a buffer layer, a first gate insulating layer, a first gate layer, a second gate insulating layer, a second gate layer, an interlayer dielectric layer, and a first source-drain layer that are sequentially stacked in a direction away from the substrate in the first display area and the second display area; the first source-drain layer includes multiple groups of first source-drain layer patterns corresponding to each pixel circuit; the active layer includes multiple groups of active patterns corresponding to each pixel circuit, the first gate layer includes multiple groups of first gate layer patterns corresponding to each pixel circuit, and the second gate layer includes multiple groups of second gate layer patterns corresponding to each pixel circuit; at least one opaque pattern of the pixel circuit includes: a group of the first source-drain layer patterns located in the first source-drain layer, a group of the active patterns located in the active layer, a group of the first gate patterns located in the first gate layer, and a group of the second gate patterns located in the second gate layer.

14. The display panel according to claim 13, wherein, the display panel further includes: a first conductive layer in the same layer as the first source-drain layer, and a second conductive layer in the same layer as the second gate layer; buffer layers, a first gate insulating layer, the second gate insulating layer, and the interlayer dielectric layer each have a first via hole; the second conductive layer and the first conductive layer are electrically connected to the auxiliary electrode pattern through the first via hole; the display panel further includes a passivation layer and a first planarization layer on a side of the first source-drain layer away from the substrate, and a plurality of first connection electrodes between the passivation layer and the first planarization layer; the passivation layer has a second via hole, at least a part of the first connection electrode is located in the second via hole and is connected to the first conductive layer; the plurality of first connection electrodes are used to connect the plurality of auxiliary electrode patterns.

15. The display panel according to claim 13, wherein, the display panel further includes: a passivation layer and a first planarization layer on a side of the first source-drain layer away from the substrate, a plurality of second connection electrodes between the passivation layer and the first planarization layer, a first signal transmission layer in the same layer as the first source-drain layer, and a third conductive layer in the same layer as the first gate layer; the first gate insulating layer, the second gate insulating layer, and the interlayer dielectric layer each have a third via hole; the first signal transmission layer is electrically connected to the third conductive layer through the third via hole; the passivation layer has a fourth via hole, at least a part of the second connection electrode is located in the fourth via hole and is connected to the first signal transmission layer.

16. The display panel according to claim 15, wherein, the third conductive layer includes: a plurality of first signal line segments, a plurality of second signal line segments, and a plurality of third signal line segments; wherein each of the plurality of first signal line segments, the plurality of second signal line segments, and the plurality of third signal line segments is connected to one pixel circuit; the plurality of second connection electrodes includes: a plurality of first-type second connection electrodes connecting the plurality of first signal line segments, a plurality of second-type second connection electrodes connecting the plurality of second signal line segments, and a plurality of third-type second connection electrodes connecting the plurality of third signal line segments.

17. The display panel according to claim 16, wherein, the plurality of first signal line segments are gate signal line segments for transmitting gate signals, the plurality of second signal line segments are reset control signal line segments for transmitting reset control signals, and the plurality of third signal line segments are light emission control signal line segments for transmitting light emission control signals.

18. The display panel according to claim 13, wherein, the display panel further includes: a plurality of third connection electrodes, and a fourth conductive layer; the fourth conductive layer includes a plurality of fourth signal line segments; Wherein, each of the fourth signal line segments is connected to at least one of the pixel circuits, and at least some of the fourth signal line segments among the plurality of fourth signal line segments are electrically connected through at least some of the third connection electrodes.

19. The display panel according to claim 18, wherein, the display panel further includes a passivation layer and a first planarization layer on a side of the first source-drain layer away from the substrate, and a second source-drain layer on a side of the first planarization layer away from the first source-drain layer; the fourth conductive layer is in the same layer as the first source-drain layer, and the plurality of third connection electrodes are between the passivation layer and the first planarization layer; the display panel further includes: a fifth conductive layer in the same layer as the second source-drain layer, the fifth conductive layer including a plurality of fifth signal line segments; the passivation layer has a fifth via; at least part of the third connection electrode is located in the fifth via and is connected to the fourth signal line segment, the first planarization layer has a sixth via, and at least part of the fifth signal line segment is located in the sixth via and is connected to the third connection electrode.

20. The display panel according to claim 19, wherein, the plurality of fourth signal line segments and the plurality of fifth signal line segments are both positive power signal line segments for transmitting a positive power signal.

21. The display panel according to claim 18, wherein, the display panel further includes a passivation layer and a first planarization layer on a side of the first source-drain layer away from the substrate; the fourth conductive layer is in the same layer as the first source-drain layer, and the plurality of third connection electrodes are between the passivation layer and the first planarization layer; the passivation layer has a seventh via; at least part of the third connection electrode is located in the seventh via and is connected to the fourth signal line segment.

22. The display panel according to claim 21, wherein, the plurality of fourth signal line segments are data signal line segments for transmitting data signals.

23. The display panel according to claim 18, wherein, the display panel further includes a passivation layer and a first planarization layer on a side of the first source-drain layer away from the substrate; the fourth conductive layer is in the same layer as the second gate layer, and the plurality of third connection electrodes are between the passivation layer and the first planarization layer; the display panel further includes: a second signal transmission layer in the same layer as the first source-drain layer; the second gate insulating layer and the interlayer dielectric layer have an eighth via; the second signal transmission layer is located in the eighth via, and the second signal transmission layer is connected to the fourth signal line segment; the passivation layer has a ninth via, and at least part of the third connection electrode is located in the ninth via and is connected to the second signal transmission layer.

24. The display panel according to claim 18, wherein, the plurality of fourth signal line segments are initialization signal line segments for transmitting initialization signals.

25. The display panel according to claim 1, wherein, The display panel further includes: an active layer, a buffer layer, a first gate insulating layer, a first gate layer, a second gate insulating layer, a second gate layer, an interlayer dielectric layer, a first source-drain layer, a passivation layer, and a first planarization layer, which are sequentially stacked in a direction away from the substrate in the first display region and the second display region; the display panel further includes a plurality of connection electrodes located between the passivation layer and the first planarization layer; at least some of the plurality of connection electrodes are used to electrically connect at least one of the first gate layer, the second gate layer, and the first source-drain layer in the first display region and at least one of the first gate layer, the second gate layer, and the first source-drain layer in the second display region, and / or, at least some of the plurality of connection electrodes are used to electrically connect at least two of the auxiliary electrode patterns in the second display region, and / or, at least some of the plurality of connection electrodes are used to connect at least one opaque pattern layer in at least two of the pixel circuits in the second display region; Wherein, the plurality of connection electrodes have a plurality of connection points, and the connection points include connection vias or overlapping structures corresponding to the respective patterns to which the plurality of connection electrodes are connected, and an overlapping area exists between the orthographic projection of the auxiliary electrode pattern on the substrate and the orthographic projection of at least one of the connection points on the substrate.

26. The display panel according to claim 25, wherein, The orthographic projection of the auxiliary electrode pattern on the substrate covers the orthographic projection of at least one of the connection points on the substrate.

27. The display panel according to any one of claims 1 to 10, wherein, The second anode layer includes a plurality of anode patterns arranged at intervals; The display panel further includes: a pixel defining layer located on a side of the second anode layer away from the substrate; The pixel defining layer has a plurality of tenth vias, and the tenth vias expose the corresponding anode patterns; the second light-emitting layer includes: a plurality of light-emitting layer patterns, and at least part of the light-emitting layer patterns are located in the tenth vias; The second cathode layer at least partially covers the tenth vias, and at least one hollowed-out area of the second cathode layer does not overlap with the tenth vias.

28. The display panel according to claim 27, wherein, The second cathode layer includes: a plurality of cathode patterns, the plurality of cathode patterns overlap with each other, and at least one hollowed-out area is formed after the plurality of cathode patterns overlap; Wherein, the orthographic projection of each cathode pattern on the substrate covers the orthographic projection of at least one light-emitting layer pattern on the substrate.

29. The display panel according to claim 27, wherein, Each of the hollowed-out areas in the second cathode layer is formed by digging holes in the second cathode layer.

30. The display panel according to any one of claims 1 to 10, wherein, At least part of the boundary of the at least one hollowed-out area includes an arc.

31. The display panel according to any one of claims 1 to 10, wherein, The first cathode layer and the second cathode layer are of an integral structure.

32. The display panel according to any one of claims 1 to 10, wherein, the area of the overlapping part of the orthographic projection of the hollowed-out area on the substrate and the orthographic projection of the auxiliary electrode pattern on the substrate is less than 10% of the area of the hollowed-out area.

33. A display device, wherein, the display device includes: an image sensor and a display panel according to any one of claims 1 to 32; the image sensor is located on the side of the substrate of the display panel away from the second anode layer and overlaps with the second display area of the substrate.

34. The display device according to claim 33, wherein, the image sensor is a camera.

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