Display with silicon gate driver and semiconductor oxide pixels

Abstract

A display may include an array of pixels that receive control signals from a gate driver link. The pixel may be formed using a semiconductor oxide transistor, while the gate driver may be formed using a silicon transistor. Each gate driver may include a shift register sub-circuit and an output buffer sub-circuit. The shift register sub-circuit may include a first set of transistors controlled at least in part by one or more shift register clock signals. The output buffer sub-circuit may include a second set of transistors controlled at least in part by one or more output buffer clock signals. The output buffer clock signal may be switched independently of the shift register clock signal. Operating in this manner, the shift register clock signal may have a pulse width optimized for stability, while the output buffer clock signal may have a pulse width optimized for speed.

Description

[0001] This application claims priority to U.S. Patent Application No. 18 / 322,406, filed May 23, 2023, and U.S. Provisional Patent Application No. 63 / 416,896, filed Oct. 17, 2022, the entire disclosures of which are hereby incorporated by reference in their entireties. BACKGROUND OF THE INVENTION

[0002] The present disclosure generally relates to electronic devices having a display, and more particularly to display driver circuits for a display such as an organic light emitting diode (OLED) display.

[0003] Electronic devices typically include a display. For example, cellular phones, tablet computers, wristwatches, and portable computers typically include a display for presenting image content to a user. An OLED display has an array of display pixels based on light emitting diodes. In this type of display, a gate driver circuit is used to provide control signals to respective rows in the display pixel array. Designing the gate driver circuit can be challenging. SUMMARY OF THE INVENTION

[0004] An electronic device may include a display having an array of display pixels. The display pixels may be organic light emitting diode display pixels. Each display pixel may include an organic light emitting diode (OLED) that emits light, one or more storage capacitors, and only semiconductor oxide transistors, such as n-type semiconductor oxide transistors. A chain of gate driver circuits may be used to drive the display pixel array. The gate driver circuits may be implemented using only silicon transistors, such as p-type low temperature polycrystalline silicon transistors. Implementing all pixel transistors as semiconductor oxide transistors may enable low refresh rate operation, such as a display refresh rate below 10 Hz or as low as 1 Hz or less, while implementing all gate driver transistors as silicon transistors may help improve the robustness of the gate driver.

[0005] Each gate driver circuit may include a shift register sub-circuit and an output buffer sub-circuit. The shift register sub-circuit may be configured to receive a first shift register clock signal and a second shift register clock signal, receive a carry input signal, and generate a carry output signal. The output buffer sub-circuit may be configured to receive an output buffer clock signal and generate a corresponding gate output signal. The output buffer sub-circuit may include: a first transistor having a first source-drain terminal configured to receive the output buffer clock signal and a second source-drain terminal at which the gate output signal is generated; a second transistor having a first source-drain terminal coupled to the second source-drain terminal of the first transistor and a second source-drain terminal coupled to a power supply line; and a third transistor having a first source-drain terminal coupled to the gate terminal of the second transistor, a second source-drain terminal coupled to a node in the shift register sub-circuit, and a gate terminal configured to receive the second shift register clock signal.

[0006] In some embodiments, the output buffer sub-circuit may include: a first capacitor having a first terminal coupled to the gate terminal of the second transistor and a second terminal configured to receive the first shift register clock signal; a fourth transistor coupled between a carry output port of the shift register sub-circuit that generates the carry output signal and the gate terminal of the first transistor; a fifth transistor having a first source-drain terminal configured to receive an additional gate output signal and a second source-drain terminal coupled to the gate terminal of the first transistor; a second capacitor coupled between the second source-drain terminal of the fifth transistor and the gate terminal of the first transistor; and a third capacitor coupled between the gate terminal of the first transistor and the power supply line.

[0007] In some embodiments, the output buffer sub-circuit may include: a fourth transistor coupled between a carry output port of the shift register sub-circuit that generates the carry output signal and the gate terminal of the first transistor; and a second capacitor coupled across the gate terminal and the second source-drain terminal of the first transistor.

[0008] In some embodiments, the output buffer sub-circuit may include: a fourth transistor coupled between the gate terminal of the first transistor and a node in the shift register sub-circuit;

[0009] A fifth transistor having a gate terminal coupled to the gate terminal of the first transistor, a first source-drain terminal configured to receive a first shift register clock signal, and a second source-drain terminal; a sixth transistor coupled between the second source-drain terminal of the fifth transistor and an additional power supply line; and a second capacitor coupled across the gate terminal and the second source-drain terminal of the fifth transistor. Description of the Drawings

[0010] Figure 1 is a diagram of an exemplary electronic device having a display according to some embodiments.

[0011] Figure 2 is a diagram of an exemplary display having an organic light-emitting diode display pixel array coupled to a gate driver circuit according to some embodiments.

[0012] Figure 3 is a circuit diagram of an exemplary display pixel according to some embodiments.

[0013] Figure 4 is a timing diagram showing a short strobe pulse for a continuous data loading operation according to some embodiments.

[0014] Figure 5A is a circuit diagram of an exemplary gate driver circuit having a shift register sub-circuit and an output buffer sub-circuit according to some embodiments.

[0015] Figure 5B is a diagram showing the operation Figure 5A of an exemplary waveform involved in the gate driver circuit shown according to some embodiments.

[0016] Figure 5C is a block diagram showing a plurality of gate driver circuits coupled together in a chain according to some embodiments.

[0017] Figure 5D is a timing diagram showing various clock signal waveforms that can be used to control a plurality of gate driver circuits connected in a chain according to some embodiments.

[0018] Figure 6A is a circuit diagram of an exemplary gate driver circuit including additional isolation transistors for reducing coupling from an output buffer clock signal according to some embodiments.

[0019] Figure 6B is a diagram showing the operation Figure 6A of an exemplary waveform involved in the gate driver circuit shown according to some embodiments.

[0020] Figure 7A is a circuit diagram of an exemplary gate driver circuit having a shift register sub - circuit and an output buffer sub - circuit powered by different ground voltages according to some embodiments.

[0021] Figure 7B shows the operation according to some embodiments Figure 7A is a timing diagram of exemplary waveforms involved in the gate driver circuit shown.

[0022] Figure 8A is a circuit diagram of an exemplary gate driver circuit according to some embodiments, the gate driver circuit having a shift register sub - circuit that generates a carry - out signal and an output buffer sub - circuit that receives the carry - out signal and a gate output signal from another gate driver circuit in a previous row.

[0023] Figure 8B shows the operation according to some embodiments Figure 8A is a timing diagram of exemplary waveforms involved in the gate driver circuit shown.

[0024] Figure 8C shows, according to some embodiments, a block diagram of a plurality of gate driver circuits of the type shown coupled together in a chain Figure 8A shown.

[0025] Figure 9A is a circuit diagram of an exemplary gate driver circuit according to some embodiments, the gate driver circuit having a shift register sub - circuit that generates a carry - out signal and an output buffer sub - circuit that does not receive the carry - out signal.

[0026] Figure 9B shows the operation according to some embodiments Figure 9A is a timing diagram of exemplary waveforms involved in the gate driver circuit shown.

[0027] Figure 10A is a circuit diagram of an exemplary gate driver circuit according to some embodiments, the gate driver circuit having a shift register sub - circuit that generates a carry - out signal and an output buffer sub - circuit that does not receive the carry - out signal.

[0028] Figure 10B shows the operation according to some embodiments Figure 10A is a timing diagram of exemplary waveforms involved in the gate driver circuit shown.

[0029] Figure 11A is a circuit diagram of another specific implementation of an exemplary gate driver circuit according to some embodiments.

[0030] Figure 11Bis a timing diagram showing exemplary waveforms involved in the gate driver circuit shown according to some embodiments Figure 11A as shown.

[0031] Figure 11C is a block diagram showing a plurality of gate driver circuits of the type shown coupled together in a chain according to some embodiments Figure 11A as shown.

[0032] Figure 12 is a circuit diagram of another implementation of an exemplary gate driver circuit according to some embodiments

[0033] Figure 13 is a circuit diagram of another implementation of an exemplary gate driver circuit configured to receive a reset signal according to some embodiments DETAILED DESCRIPTION

[0034] Figure 1 An exemplary electronic device of a type that may be provided with a display is shown. As Figure 1 shown, the electronic device 10 may have a control circuit 16. The control circuit 16 may include storage and processing circuitry for supporting the operation of the device 10. The storage and processing circuitry may include storage devices such as hard disk drive storage, non-volatile memory (e.g., flash memory configured to form a solid state drive or other electrically programmable read only memory), volatile memory (e.g., static or dynamic random access memory), and so forth. The processing circuitry in the control circuit 16 may be used to control the operation of the device 10. The processing circuitry may be based on one or more microprocessors, application processors, microcontrollers, digital signal processors, baseband processors, power management units, audio chips, application specific integrated circuits, etc.

[0035] Input-output circuitry in the device 10 such as the input-output device 12 may be used to allow data to be provided to the device 10 and to allow data to be provided from the device 10 to external devices. The input-output device 12 may include buttons, joysticks, rollers, touch pads, keypads, keyboards, microphones, speakers, audio generators, vibrators, cameras, sensors, light emitting diodes and other status indicators, data ports, etc. A user may control the operation of the device 10 by supplying commands through the input-output device 12 and may receive status information and other outputs from the device 10 using the output resources of the input-output device 12.

[0036] The input-output device 12 may include one or more displays, such as display 14. Display 14 may be a touch screen display including a touch sensor for collecting touch inputs from a user, or display 14 may be insensitive to touch. The touch sensor of display 14 may be based on an array of capacitive touch sensor electrodes, an acoustic touch sensor structure, a resistive touch component, a force-based touch sensor structure, a light-based touch sensor, or other suitable touch sensor arrangements.

[0037] Control circuitry 16 may be used to run software on device 10, such as operating system code and applications. During operation of device 10, the software running on control circuitry 16 may use the pixel array in display 14 to display images on display 14. Device 10 may be a tablet computer, a laptop computer, a desktop computer, a display, a cellular phone, a media player, a watch device, or other wearable electronic device, or other suitable electronic device.

[0038] Display 14 may be an organic light emitting diode display or may be a display based on other types of display technologies. In this document, a configuration in which display 14 is an organic light emitting diode (OLED) display is sometimes described as an example. However, this is merely illustrative. Any suitable type of display may be used in device 10 if desired.

[0039] Display 14 may have a rectangular shape (i.e., display 14 may have a rectangular coverage area and a rectangular peripheral edge extending around the rectangular coverage area) or may have other suitable shapes. Display 14 may be planar or may have a curved profile.

[0040] Figure 2 A top view of a portion of display 14 is shown. As Figure 2 shown, display 14 may have an array of pixels 22 formed on a substrate 36. Substrate 36 may be formed of glass, metal, plastic, ceramic, porcelain, or other substrate materials. Pixels 22 may receive data signals through signal paths such as data lines D (sometimes referred to as data signal lines, column lines, etc.), and may receive one or more control signals through control signal paths such as horizontal control lines G (sometimes referred to as gate lines, scan lines, emission lines, row lines, etc.). There may be any suitable number of rows and columns of pixels 22 in display 14 (e.g., dozens or more, hundreds or more, or thousands or more).

[0041] Each pixel 22 may include a light-emitting diode 26 that emits light 24 under the control of a pixel control circuit formed by thin-film transistor circuits such as thin-film transistor 28 and thin-film capacitors. The thin-film transistor 28 may be a polysilicon thin-film transistor, a semiconductor oxide thin-film transistor (such as an indium gallium zinc oxide transistor), or a thin-film transistor formed of other semiconductors. The pixel 22 may include light-emitting diodes of different colors (e.g., red, green, and blue) to provide the ability to display a color image on the display 14.

[0042] The display 14 may further include a source driver circuit 30 and a gate driver circuit 34 formed on a substrate 36. The source driver circuit 30 and the gate driver circuit 34 may be used to control the operation of the pixels 22. The source driver circuit 30 may be formed of an integrated circuit, a thin-film transistor circuit, and / or other suitable electronic circuits. Figure 2 The source driver circuit 30 may include a communication circuit for communicating with a system control circuit such as Figure 1 the control circuit 16 via a path 32. The path 32 may be formed of traces on a flexible printed circuit or other cables. During operation, the control circuit (e.g., Figure 1 the control circuit 16) may provide information about an image to be displayed on the display 14 to the circuit 30.

[0043] To display an image on the display pixels 22, the source driver circuit 30 may supply image data to data lines D (e.g., data lines extending along the columns of the pixels 22), while sending a clock signal and other control signals to a support display driver circuit such as the gate driver circuit 34 via a path 38. If needed, the source driver circuit 30 may also supply the clock signal and other control signals to additional gate driver circuits on opposite edges of the display 14, such as the gate driver circuit 34' (e.g., the gate driver circuits may be formed on more than one side of the display pixel array). If needed, the gate driver circuits may be formed along three different edges of the pixel array, or may be formed along four different edges of the pixel array.

[0044] The gate driver circuit 34 (sometimes referred to as a horizontal line control circuit or a row driver circuit) can be implemented as part of an integrated circuit and / or can be implemented using thin-film transistor circuitry. The horizontal / row control lines G in the display 14 can carry gate line signals (scan line control signals or scan signals), emission enable control signals (emission signals), and / or other horizontal control signals for controlling the pixels of each row. Any suitable number of horizontal control signals can be present for each row of pixels 22 (e.g., one or more row control lines, two or more row control lines, three or more row control lines, four or more row control lines, five or more row control lines, etc.). The gate driver circuit 34 can include a plurality of gate driver circuits connected in a chain. For example, each gate driver can be configured to generate one or more scan signals and / or carry signals, and the one or more scan signals and / or carry signals are fed forward to subsequent gate drivers in the chain or are fed back to previous gate drivers in the chain.

[0045] The active components within the display 14 can be implemented using thin-film transistors such as semiconductor oxide transistors and silicon transistors. A "semiconductor oxide" transistor can be defined herein as a thin-film transistor having a channel region formed of a semiconductor oxide material (e.g., indium gallium zinc oxide or IGZO, indium tin zinc oxide or ITZO, indium gallium tin zinc oxide or IGTZO, indium tin oxide or ITO, or other semiconductor oxide materials), and is typically an n-type (n-channel) transistor. In contrast, a "silicon transistor" can be defined herein as a thin-film transistor having a channel region formed of silicon material (such as polysilicon) deposited using a low-temperature process. A silicon transistor having such a type of polysilicon active material deposited using a low-temperature process is thus sometimes referred to as an LTPS (low-temperature polysilicon) transistor.

[0046] According to an embodiment, the pixels 22 within the active area of the display 14 can be implemented using only semiconductor oxide (e.g., n-type) transistors. In other words, the pixels 22 do not include any silicon transistors. Semiconductor oxide transistors exhibit lower leakage than silicon transistors, so implementing the pixels 22 using only semiconductor oxide transistors can be beneficial and have technical advantages by helping to reduce flicker (e.g., by preventing current from leaking out of one or more storage nodes within the pixels 22) and by enabling the display 14 to operate at a low refresh rate. For example, implementing the pixels 22 using only semiconductor oxide transistors can enable the display 14 to operate using a refresh rate lower than 60 Hz, lower than 30 Hz, lower than 10 Hz, 1 Hz, 2 Hz, 1 Hz - 10 Hz, or less than 1 Hz. The example of the pixels 22 including only semiconductor oxide transistors Figure 2 is illustrative. If desired, each pixel 22 can include one or more semiconductor oxide transistors and / or can include one or more silicon transistors.

[0047] Compared with pixel 22, the gate driver circuit 34 formed along the peripheral edge of the display 14 can be implemented using only silicon (e.g., LTPS) transistors. In other words, the gate driver circuit 34 does not include any semiconductor oxide transistors. As an example, the gate driver circuit 34 can be implemented using only p-type metal oxide semiconductor (PMOS) silicon transistors. As another example, the gate driver circuit 34 can be implemented using only n-type metal oxide semiconductor (NMOS) silicon transistors. As another example, the gate driver circuit 34 can be implemented using both PMOS and NMOS silicon transistors. Compared with semiconductor oxide transistors, silicon transistors provide improved reliability and robustness. Therefore, implementing the gate driver circuit 34 using only silicon transistors can be beneficial and have a technical advantage by extending the lifespan of the gate driver circuit 34, where a large amount of switching activity occurs during the lifespan of the gate driver circuit and where leakage is not a major issue compared to pixel 22. An example of pixel 22 including only silicon transistors Figure 2 is illustrative. If desired, the gate driver circuit 34 can include one or more silicon transistors and / or can include one or more semiconductor oxide transistors.

[0048] Figure 3 is a circuit diagram of an illustrative display pixel 22 within the display 14. As Figure 3 shown, the display pixel 22 can include a light-emitting element such as an organic light-emitting diode 26, one or more capacitors such as a storage capacitor Cst, and thin-film transistors such as a driving transistor Tdrive and a data loading transistor Tdata. The light-emitting diode 26 can have an associated diode capacitance Coled (not shown). As described above, all transistors within pixel 22 (such as transistors Tdrive and Tdata) can be implemented as semiconductor oxide transistors.

[0049] The driving transistor Tdrive has a gate terminal G, a drain terminal D, and a source terminal S. The terms "source" and "drain" terminals used to describe the current-conducting terminals of a transistor are sometimes interchangeable and may sometimes be referred to herein as "source-drain" terminals. For example, the drain terminal D of the driving transistor can be referred to as the first source-drain terminal, while the source terminal S of the driving transistor can be referred to as the second source-drain terminal, or vice versa. The transistor Tdrive and the light-emitting diode 26 can be serially coupled between a positive power supply line and a ground power supply line. In Figure 3In the example, the storage capacitor Cst can be coupled across the gate terminal and the source terminal of the driving transistor Tdrive. The data loading transistor Tdata can have a first source-drain terminal coupled to the gate terminal of the transistor Tdrive, a second source-drain terminal coupled to the data line D (e.g., a column line carrying a data signal), and a gate terminal configured to receive a gate driver output signal GOUT from the gate line G. Thus, the gate output signal GOUT is sometimes referred to as a gate line signal or a scan control signal.

[0050] Figure 3 The illustrated display pixel 22 is exemplary. If desired, the pixel 22 can include additional transistors, such as one or more emission transistors (e.g., transistors activated during the emission phase of the pixel 22), one or more initialization transistors (e.g., transistors activated during the initialization phase to initialize the internal node of the pixel 22 to an initialization voltage level or a reference voltage level), one or more anode reset transistors (e.g., transistors activated during the reset phase to reset the anode terminal of the diode 26 to a reset voltage level), one or more bias transistors (e.g., transistors activated during the threshold voltage sampling phase or the on-bias stress phase to bias the internal node of the pixel 22 to a known voltage level), one or more additional capacitors (e.g., capacitors configured to boost the drive current flowing through the driving transistor during the emission phase), and / or other additional components. If desired, one or more scan (row control) signals, two or more scan signals, three or more scan signals, one or more emission (row control) signals, two or more emission signals, other row control or column control signals, or other global control signals can be used to control the pixel 22.

[0051] Figure 4 is a timing diagram showing a short strobe pulse that can be used to load data signals into consecutive rows of the pixel 22. In Figure 4 it, the gate output signal GOUT(n) can be used to control the data loading transistor in the pixel 22 in row n of the display pixel array, and the gate output signal GOUT(n + 1) can be used to control the data loading transistor in the pixel 22 in row (n + 1) of the display pixel array. As Figure 4As shown, the gate output signal GOUT(n) can be pulsed high to load the data signal D(1) into a row of pixels, and the gate output signal GOUT(n+1) can then be pulsed high to load the data signal D(2) into the subsequent row of pixels. Each strobe pulse can have a pulse width fixed to one row time or less (e.g., the pulse width can be less than 1H). The timing of the signal GOUT (sometimes referred to as the data load scan signal or data programming control signal) used to control the data load transistor is the most critical because it has the strictest timing margin. Since the duration of the data load GOUT pulse can be fixed to one row time (1H) or shorter, the gate driver circuit that generates these GOUT pulses must exhibit sufficient drive capability to drive the signal GOUT high and low at the speed required by the display 14.

[0052] According to an embodiment, Figure 5A is a circuit diagram of an exemplary gate driver circuit 40 configured to generate a gate output signal GOUT with a fast rise time and / or fall time. As Figure 5A shown, the gate driver 40 can include a logic sub-circuit 42 and an output buffer sub-circuit 44. The logic sub-circuit 42 portion of the gate driver 40 can receive a carry input signal CR_IN from the gate driver in the previous row and can output a carry output signal CR_OUT to the gate driver in the subsequent row. Operating in this manner, the logic sub-circuit 42 is sometimes referred to herein and defined as a "shift register" sub-circuit 42. As an example, all transistors within the gate driver circuit 40 are implemented as silicon transistors (e.g., all transistors within the gate driver 40 can be implemented as PMOS LTPS thin film transistors).

[0053] The shift register sub-circuit 42 can include transistors T1-T7 and TA and capacitors C Q1 and C QB1 . The transistors T1-T8 and TA are thus sometimes referred to as logic or shift register transistors. Transistor T1 can have a gate terminal coupled to node Q1, a drain terminal configured to receive a logic (shift register) clock signal CLK_B, and a source terminal coupled to a carry output port that generates the carry output signal CR_OUT. The signal CR_OUT can be fed to one or more subsequent gate driver stages in the gate driver chain. Capacitor C Q1 can be coupled across the gate terminal and the source terminal of transistor T1. Transistor T2 can have a drain terminal coupled to the carry output port, a gate terminal coupled to node QB1, and a source terminal coupled to a high (positive) power supply voltage VGH. Capacitor C QB1It can be coupled across the gate terminal and the source terminal of transistor T2. The voltage VGH can be 5V, 6V, 7V, 3V to 10V, greater than 10V, greater than 15V, 20V, 15V - 25V, greater than 20V, or any suitable positive power supply voltage level.

[0054] Transistor TA can have a first source - drain terminal coupled to node Q1, a second source - drain terminal coupled to node Q0, and a gate terminal configured to receive a low (ground) power supply voltage VGL. The power supply voltage VGL can be 0V, - 2V, - 4V, - 6V, less than - 8V, - 10V, - 5V to - 15V, less than - 10V, or any suitable ground or negative power supply voltage level.

[0055] Transistors T3, T7, and T6 can be serially coupled. In particular, transistor T3 can have a source terminal coupled to node Q0, a drain terminal configured to receive a carry - in input signal from a previous stage via a feed - forward path (e.g., receive a signal CR_IN from the previous gate driver stage in the chain), and a gate terminal configured to receive a logic (shift register) clock signal CLK_A. Transistor T7 can have a drain terminal coupled to node Q0, a gate terminal configured to receive a clock signal CLK_B, and a source terminal. Transistor T6 can have a drain terminal coupled to the source terminal of transistor T7, a gate terminal coupled to node QB1, and a source terminal coupled to a high voltage VGH.

[0056] Transistor T5 can have a drain terminal coupled to the power supply voltage VGL, a gate terminal configured to receive a clock signal CLK_A, and a source terminal coupled to node QB1. Transistor T4 can have a first source - drain terminal coupled to node QB1, a second source - drain terminal configured to receive a clock signal CLK_A, and a gate terminal coupled to node Q0.

[0057] The output buffer sub - circuit 44 can include transistor T8 serially coupled with transistor T9. Transistors T8 and T9 in the output buffer sub - circuit 44 are sometimes referred to as output buffer transistors. The first output buffer transistor T8 has a source terminal configured to receive an output buffer clock signal CLK_BUF, a gate terminal coupled to node Q1, and a drain terminal coupled to a gate driver output port that generates a gate output signal GOUT. The size of transistor T8 can be relatively large to help ensure that the gate output signal GOUT has a sufficiently short rise time and fall time. The signal GOUT can, for example, represent a signal for controlling Figure 3The scan signal of the data loading transistor Tdata in it or other switching transistors within the pixel 22. The second output buffer transistor T9 has a source terminal coupled to the gate driver output port, a gate terminal coupled to the node QB2, and a drain terminal coupled to the low power supply signal VGL.

[0058] The output buffer sub-circuit 44 may further include a transistor T11 and a capacitor C QB2 . The transistor T11 has a first source-drain terminal coupled to the node QB2, a second source-drain terminal coupled to the node QB1, and a gate terminal configured to receive the shift register clock signal CLK_B. The capacitor C QB2 may have a first terminal coupled to the node QB2 and a second terminal configured to receive the shift register clock signal CLK_A. Connected in this way, the transistor T11 and the capacitor C QB2 can be used to ensure that the node QB2 is less than VGL when the output buffer transistor T9 needs to be turned on.

[0059] The shift register clock signals CLK_A and CLK_B that control the logic sub-circuit portion 42 of the gate driver 40 are separated and isolated from the output buffer clock signal CLK_BUF of the output buffer portion 44 of the gate driver 40. Using isolated clock signals to control two different portions of the gate driver 40 allows the shift register sub-circuit 42 to operate with a greater processing margin and a longer lifespan (e.g., by allowing sufficient time for the internal nodes within the sub-circuit 42 to stabilize / stabilize), while enabling the output buffer sub-circuit 44 to operate independently at a faster speed to meet the more stringent timing constraints specified during the data programming phase. Generally, the pulse width of the shift register (logic) clock signal can be as long as needed, while the pulse width of the output buffer clock signal can be as short as needed.

[0060] Figure 5B is a timing diagram showing Figure 5A the operation of the gate driver 40 of the type shown. As Figure 5B shown, the clock signal CLK_B can be a delayed version of the clock signal CLK_A (or vice versa). The shift register clock signals CLK_A and CLK_B also have a wider pulse width than the output buffer clock signal CLK_BUF, which allows the internal nodes (such as the nodes Q1 and QB1) within the sub-circuit 42 to have time to stabilize.

[0061] At time t1, the carry input signal CR_IN from the previous row pulses low (from time t1 to t2), which can be synchronized with the CLK_A pulses that turn on the transistors T3 and T5, which can be due to the capacitor C QB2Due to capacitive coupling, nodes Q0 and Q1 drop from VGH to VGL, and node QB2 drops from VGL to (2VGL - VGH). At time t2, signals CR_IN and CLK_A can be driven high, which can cause node QB1 to be driven from VGL to VGH using transistor T4, and can cause node QB2 to jump back to VGL via capacitor C QB2 is jumped back to VGL.

[0062] At time t3, signal CLK_B can be pulsed low (from time t3 to t6), which causes the carry output signal CR_OUT to be pulsed low through transistor T1. At the same time, node Q1 is pushed down to an even lower level (e.g., from VGL to 2VGL - VGH) via coupling through capacitor C Q1 . At time t3, node QB2 can be pulled up (e.g., from VGL to VGH) using transistor T11.

[0063] At time t4, the output buffer clock signal CLK_BUF can be pulsed high, which causes the gate output signal GOUT to be pulsed high through transistor T8. The clock signal CLK_BUF can have a pulse width PW_SC. At time t5, the output buffer clock signal CLK_BUF can be made inactive, which causes the gate output signal GOUT to return to its initial level.

[0064] At time t6, the rising edge of the shift register clock signal CLK_B will cause the carry output signal CR_OUT to return to its initial VGH level. At the same time, due to coupling through capacitor C Q1 , node Q1 will rise back to VGL.

[0065] At time t7, a pulse of CLK_A when the current feed carry input signal CR_IN is high will cause node Q0 to be reset to its initial high level while resetting node QB1 low. The rising of node Q0 will also cause node Q1 to be driven back to VGH via transistor TA. By having a separate (isolated) output buffer clock pulse CLK_BUF that is narrower than the shift register clock pulses in CLK_A and CLK_B, the gate driver 40 is able to generate a gate output signal GOUT with fast enough rise and fall times.

[0066] Figure 5C is a block diagram showing a plurality of gate driver circuits 40 of the type described in combination Figure 5A and Figure 5B coupled together in a chain. As Figure 5C shown, the gate driver circuit 34 can include a chain of gate drivers 40, such as gate drivers 40-1, 40-2, 40-3, and 40-4. Although in Figure 5COnly four gate drivers 40 are shown, but the gate driver circuit 34 may include hundreds or thousands of gate drivers 40 connected in a chain. The gate driver 40-1 may be configured to generate a first gate output signal GOUT(4n+1). The gate driver 40-2 may be configured to generate a second gate output signal GOUT(4n+2). The gate driver 40-3 may be configured to generate a third gate output signal GOUT(4n+3). The gate driver 40-4 may be configured to generate a fourth gate output signal GOUT(4n+4).

[0067] In Figure 5C the example of, each gate driver 40 may receive a carry input signal from the gate drivers in the above two rows and may thus generate a carry output signal that is fed forward to the gate drivers in the below two rows. For example, the gate driver 40-1 in row (4n+1) may receive a carry input signal from row (4n-1) and may output a carry output signal to row (4n+3). As another example, the gate driver 40-3 in row (4n+3) may receive a carry input signal from row (4n+1) and may output a carry output signal to row (4n+5). This is only illustrative. Generally, the gate driver 40 may receive a carry input signal from the gate drivers in any previous row (e.g., from the above one row, above two rows, above three rows, above four rows, or above more than four rows) and may output a carry output signal to another gate driver in any subsequent row (e.g., to the below one row, below two rows, below three rows, below four rows, or below more than four rows).

[0068] Although each gate driver 40 includes two shift register clock ports (e.g., CLK_A and CLK_B), four different shift register clock signals CLK_SR_1, CLK_SR_2, CLK_SR_3, and CLK_SR_4 can be used to control the gate driver circuit 34. The clock signal CLK_SR_1 can be fed to the CLK_A port of the first gate driver in each group of four gate drivers 40, and can be fed to the CLK_B port of the third gate driver in each group of four gate drivers 40. The clock signal CLK_SR_2 can be fed to the CLK_A port of the second gate driver in each group of four gate drivers 40, and can be fed to the CLK_B port of the fourth gate driver in each group of four gate drivers 40. The clock signal CLK_SR_3 can be fed to the CLK_B port of the first gate driver in each group of four gate drivers 40, and can be fed to the CLK_A port of the third gate driver in each group of four gate drivers 40. The clock signal CLK_SR_4 can be fed to the CLK_B port of the second gate driver in each group of four gate drivers 40, and can be fed to the CLK_A port of the fourth gate driver in each group of four gate drivers 40.

[0069] Although each gate driver 40 includes an output buffer clock port (e.g., CLK_BUF), four different output buffer clock signals CLK_BUF_1, CLK_BUF_2, CLK_BUF_3, and CLK_BUF_4 can also be used to control the gate driver circuit 34. The clock signal CLK_BUF_1 can be fed to the CLK_BUF port of the first gate driver in each group of four gate drivers 40. The clock signal CLK_BUF_2 can be fed to the CLK_BUF port of the second gate driver in each group of four gate drivers 40. The clock signal CLK_BUF_3 can be fed to the CLK_BUF port of the third gate driver in each group of four gate drivers 40. The clock signal CLK_BUF_4 can be fed to the CLK_BUF port of the fourth gate driver in each group of four gate drivers 40.

[0070] Figure 5D is a timing diagram showing at least some of the clock signal waveforms of the various clock signals that can be used to control Figure 5C the gate driver chain shown. As Figure 5DAs shown, the shift register clock signal CLK_SR_3 can be a delayed version of the shift register clock signal CLK_SR_1 and can have non-overlapping pulses. The shift register clock signal can switch between the power supply voltages VGL and VGH. At time ta, the output buffer signal CLK_BUF_3 can pulse high during the pulse width of CLK_SR_1. At time tb, the output buffer signal CLK_BUF_1 can pulse high during the pulse width of CLK_SR_3. The output buffer clock signals CLK_BUF_4 and CLK_BUF_2 can be similarly aligned with CLK_SR_2 and CLK_SR_4 (not shown to avoid obscuring the present embodiment). The output buffer clock signals can also switch between the power supply voltages VGL and VGH.

[0071] As described above, the size of the output buffer transistor T8 can be relatively large to ensure that the rise time and fall time of the gate output signal GOUT are fast enough. The large transistor T8 typically results in a large parasitic gate capacitance, which can couple the rising and falling edges of the output buffer clock signal CLK_BUF to the gate terminal of T8. Such parasitic coupling can cause an unintentional pulse at node Q1 (see the pulse 50 at time t4 in Figure 5B ), which can also cause an unintentional pulse in the carry output signal CR_OUT (see the pulse 52 at time t4).

[0072] Figure 6A Another embodiment of the gate driver circuit 40' is shown, which includes additional transistors configured to isolate the output buffer clock signal CLK_BUF from node Q1 and the carry output port. As Figure 6A shown, the gate driver 40' can include a shift register sub-circuit 42 and an output buffer sub-circuit 44'. Figure 6A The shift register sub-circuit 42 in the gate driver 40' can have the same structure as the shift register sub-circuit 42 in Figure 5A the gate driver 40 and need not be repeated in detail to avoid obscuring the present embodiment. As an example, all the transistors within the gate driver circuit 40' can be implemented as silicon transistors (e.g., all the transistors within the gate driver 40' can be implemented as PMOS LTPS thin film transistors).

[0073] The output buffer sub - circuit 44' may include a transistor T8 serially coupled with a transistor T9. The transistors T8 and T9 in the output buffer sub - circuit 44' are sometimes referred to as output buffer transistors. The first output buffer transistor T8 has a source terminal configured to receive an output buffer clock signal CLK_BUF, a gate terminal coupled to node Q2, and a drain terminal coupled to a gate driver output port that generates a gate output signal GOUT. The size of the transistor T8 may be relatively large to help ensure that the gate output signal GOUT has a sufficiently short rise time and fall time. The signal GOUT may represent, for example, a scan signal for controlling Figure 3 the data - loading transistor Tdata or other switching transistors within the pixel 22. The second output buffer transistor T9 has a source terminal coupled to the gate driver output port, a gate terminal coupled to node QB2, and a drain terminal coupled to a low - power supply signal VGL.

[0074] The output buffer sub - circuit 44' may further include a transistor T11 and a capacitor C QB2 . The transistor T11 has a first source - drain terminal coupled to node QB2 via path 58, a second source - drain terminal coupled to node QB1, and a gate terminal configured to receive a shift - register clock signal CLK_B. The capacitor C QB2 may have a first terminal coupled to node QB2 and a second terminal configured to receive a shift - register clock signal CLK_A. Connected in this way, the transistor T11 and the capacitor C QB2 can be used to ensure that node QB2 is less than VGL when the output buffer transistor T9 needs to be turned on.

[0075] The output buffer sub - circuit 44' may further include transistors T10, T1b, T2b, and a capacitor C Q2 . The transistor T10 may have a first source - drain terminal coupled to node Q2 (i.e., the gate terminal of the transistor T8), a second source - drain terminal coupled to node Q0 via path 56, and a gate terminal configured to receive a low voltage VGL. The transistor T1b may have a first source - drain terminal configured to receive a shift - register clock signal CLK_B, a second source - drain terminal, and a gate terminal coupled to node Q2. The capacitor C Q2It can be coupled across the gate terminal of transistor T1b and the second source-drain terminal. Transistor T2b can have a first source-drain terminal coupled to the second source-drain terminal of transistor T1b, a second source-drain terminal coupled to the high voltage VGH, and a gate terminal coupled to node QB1 via path 58. Configured in this way, transistors T10, T1b, and T2b can be jointly used to isolate any parasitic coupling that may be coupled to the gate terminal (node Q2) of T8 from the internal nodes of the shift register sub-circuit 42.

[0076] Figure 6B is a timing diagram showing Figure 6A the operation of the gate driver 40' of the type shown. At time t1, the carry input signal CR_IN from the previous row pulses low (from time t1 to t2), which can be synchronized with the CLK_A pulse that turns on transistors T3 and T5. This can be due to the capacitive coupling through capacitor C QB2 such that nodes Q0 and Q1 drop from VGH to VGL and node QB2 drops from VGL to (2VGL - VGH). Using transistor T10, the drop of node Q0 can also cause node Q2 to drop from VGH to VGL. At time t2, signals CR_IN and CLK_A can be driven high, which can cause node QB1 to be driven from VGL to VGH using transistor T4, and can cause node QB2 to jump back to VGL via capacitor C QB2

[0077] At time t3, signal CLK_B can pulse low (from time t3 to t6), which causes the carry output signal CR_OUT to pulse low through transistor T1. During this period, node Q2 can also drop from VGL to (2VGL - VGH). At the same time, node Q1 is pushed down to an even lower level (e.g., from VGL to 2VGL - VGH) through the coupling via capacitor C Q1 At time t3, transistor T11 can be used to pull up node QB2 (e.g., from VGL to VGH).

[0078] At time t4, the output buffer clock signal CLK_BUF can pulse high, which causes the gate output signal GOUT to pulse high through transistor T8. The clock signal CLK_BUF can have a pulse width PW_SC. At time t5, the output buffer clock signal CLK_BUF can be made inactive, which causes the gate output signal GOUT to return to its initial level.

[0079] At time t6, the rising edge of the shift register clock signal CLK_B will cause the carry output signal CR_OUT to return to its initial VGH level. At the same time, due to the coupling through capacitor C Q1 ​Upon coupling, node Q1 will rise back to VGL, and node Q2 will also rise back to VGL.

[0080] At time t7, a CLK_A pulse when the current feed - through carry - in input signal CR_IN is high will cause node Q0 to reset to its initial high level while resetting node QB1 to low. The rising of node Q0 will also cause node Q1 to be driven back to VGH via transistor TA. Node Q2 will also rise back to VGH. By having a separate (isolated) output buffer clock pulse CLK_BUF that is narrower than the shift - register clock pulses in CLK_A and CLK_B, the gate driver 40' can generate a gate output signal GOUT with fast enough rise and fall times.

[0081] As described above, the size of output buffer transistor T8 can be relatively large to ensure that the rise and fall times of the gate output signal GOUT are fast enough. The large transistor T8 typically results in a large parasitic gate capacitance, which can couple the rising and falling edges of the output buffer clock signal CLK_BUF to the gate terminal of T8. Such parasitic coupling can cause an unintentional pulse at node Q2 (see the pulse 54 at time t4 in Figure 6B ). Isolating node Q2 from the internal nodes of the shift - register sub - circuit 42 in this way using transistor T10 can have a technical advantage as the parasitic clock coupling will not affect the carry - out waveform.

[0082] Multiple gate drivers 40' can be coupled together in a chain in a manner similar to that already shown in Figure 5C . The carry signal can be fed from one gate driver 40' to another gate driver 40'. At least four different shift - register clock signals CLK_SR1, CLK_SR_2, CLK_SR_3, and CLK_SR4 can be used to control CLK_A and CLK_B ports in each set of four gate drivers 40'. Similarly, at least four different output buffer clock signals CLK_BUF_1, CLK_BUF_2, CLK_BUF_3, and CLK_BUF_4 can be used to control the CLK_BUF port in each set of four gate drivers 40'. The timing of these shift - register clock signals and output buffer clock signals used to control the chain of gate drivers 40' can be the same as or similar to the waveforms already shown in Figure 5D .

[0083] Figure 7A Another embodiment of a gate driver circuit 40” powered by two different low voltages VGL and VGL' is shown. As Figure 7A shown, the gate driver 40” can include a shift - register sub - circuit 42 and an output buffer sub - circuit 44”. Figure 7AThe shift register sub - circuit 42 in the gate driver 40” may have the same structure as the shift register sub - circuit 42 in the gate driver 40, and there is no need to repeat it in detail to avoid obscuring the present embodiment. As an example, all transistors within the gate driver circuit 40” may be implemented as silicon transistors (e.g., all transistors within the gate driver 40” may be implemented as PMOS LTPS thin - film transistors). Figure 5A The shift register sub - circuit 42 in the gate driver 40” may have the same structure as the shift register sub - circuit 42 in the gate driver 40, and there is no need to repeat it in detail to avoid obscuring the present embodiment. As an example, all transistors within the gate driver circuit 40” may be implemented as silicon transistors (e.g., all transistors within the gate driver 40” may be implemented as PMOS LTPS thin - film transistors).

[0084] The output buffer sub - circuit 44” may include a transistor T8 serially coupled with a transistor T9. The first output buffer transistor T8 has a source terminal configured to receive an output buffer clock signal CLK_BUF, a gate terminal coupled to node Q2, and a drain terminal coupled to a gate driver output port that generates a gate output signal GOUT. The size of the transistor T8 may be relatively large to help ensure that the gate output signal GOUT has a sufficiently short rise time and fall time. The signal GOUT may represent, for example, a scan signal for controlling Figure 3 the data - loading transistor Tdata or other switching transistors within the pixel 22. The second output buffer transistor T9 has a source terminal coupled to the gate driver output port, a gate terminal coupled to node QB2, and a drain terminal coupled to a low - power supply signal VGL.

[0085] The output buffer sub - circuit 44” may further include a transistor T11 and a capacitor C QB2 . The transistor T11 has a first source - drain terminal coupled to node QB2, a second source - drain terminal coupled to node QB1, and a gate terminal configured to receive a shift register clock signal CLK_B. The capacitor C QB2 may have a first terminal coupled to node QB2 and a second terminal configured to receive a shift register clock signal CLK_A. Connected in this way, the transistor T11 and the capacitor C QB2 can be used to ensure that node QB2 is less than VGL when the output buffer transistor T9 needs to be turned on.

[0086] The output buffer sub - circuit 44” may further include a transistor T10 and a capacitor C Q2 . The transistor T10 may have a first source - drain terminal coupled to node Q2 (i.e., the gate terminal of the transistor T8), a second source - drain terminal coupled to a carry - out output port, and a gate terminal configured to receive a low voltage VGL'. The low voltage VGL' may be less than VGL (e.g., VGL' may be at least one Vth less than VGL, where Vth represents the threshold voltage of the transistor T10). The capacitor C Q2 is coupled across the gate terminal and the drain terminal of the transistor T8.

[0087] Figure 7B It is shown Figure 7A 1 is a timing diagram of the operation of a gate driver 40" of the type shown. At time t1, the carry input signal CR_IN pulse from the previous row is low (from time t1 to t2), which can be synchronized with the CLK_A pulse that turns on transistors T3 and T5, which can be due to the capacitor C QB2 The capacitive coupling of CR_IN and CLK_A causes nodes Q0 and Q1 to drop from VGH to VGL and node QB2 to drop from VGL to (2VGL-VGH). At time t2, signals CR_IN and CLK_A may be driven high, which may cause node QB1 to be driven from VGL to VGH using transistor T4, and may cause node QB2 to be driven from VGL to VGH via capacitor C QB2 Jumped back to VGL.

[0088] At time t3, signal CLK_B may pulse low (from time t3 to t6), which causes the carry output signal CR_OUT to pulse low through transistor T1. During this period, node Q2 may also drop from VGH to VGL through transistor T10. At the same time, node Q1 is Q1 At time t3, node QB2 may be pulled up (eg, from VGL to VGH) using transistor T11.

[0089] At time t4, the output buffer clock signal CLK_BUF may pulse high, which causes the gate output signal GOUT to pulse high through transistor T8. The clock signal CLK_BUF may have a pulse width PW_SC. At time t5, the output buffer clock signal CLK_BUF may be deasserted, which causes the gate output signal GOUT to return to its initial level. At the falling edge of GOUT at time t5, node Q2 may be deasserted through capacitor C Q2 Coupled down to a voltage lower than VGL.

[0090] At time t6, the rising edge of the shift register clock signal CLK_B will cause the carry output signal CR_OUT to return to its initial VGH level. At the same time, due to the capacitor C Q1 With the coupling of transistor T10, node Q1 will rise back to VGL, and using transistor T10, node Q2 will rise back to VGH.

[0091] At time t7, a CLK_A pulse when the current feed - through carry input signal CR_IN is high will cause node Q0 to reset to its initial high level and will also reset node QB1 to low. The rising of node Q0 will also cause node Q1 to be driven back to VGH via transistor TA. By having a separate (isolated) output buffer clock pulse CLK_BUF that is narrower than the shift - register clock pulses in CLK_A and CLK_B, the gate driver 40” can generate a gate output signal GOUT with fast enough rise and fall times.

[0092] Multiple gate drivers 40” can be coupled together in a chain in a manner similar to that already shown in Figure 5C . The carry signal can be fed from one gate driver 40” to another gate driver 40”. At least four different shift - register clock signals CLK_SR1, CLK_SR_2, CLK_SR_3, and CLK_SR4 can be used to control the CLK_A and CLK_B ports in each group of four gate drivers 40”. Similarly, at least four different output - buffer clock signals CLK_BUF_1, CLK_BUF_2, CLK_BUF_3, and CLK_BUF_4 can be used to control the CLK_BUF ports in each group of four gate drivers 40”. The timing of these shift - register clock signals and output - buffer clock signals for controlling the chain of gate drivers 40” can be the same as or similar to the waveforms already shown in Figure 5D .

[0093] Figure 8A Another embodiment of the gate driver circuit 40”' is shown, where both the carry signal and the gate output signal are fed from a previous gate driver to a subsequent gate driver. As shown in Figure 8A , the gate driver 40”' can include a shift - register sub - circuit 42 and an output - buffer sub - circuit 44”'. Figure 8A The shift - register sub - circuit 42 in the gate driver 40”' of Figure 5A can have the same structure as the shift - register sub - circuit 42 in the gate driver 40 of

[0094] The output buffer sub - circuit 44”' may include a transistor T8 serially coupled with a transistor T9. The first output buffer transistor T8 has a source terminal configured to receive an output buffer clock signal CLK_BUF, a gate terminal coupled to node Q2, and a drain terminal coupled to a gate driver output port that generates a gate output signal GOUT. The transistor T8 may be relatively large in size to help ensure that the gate output signal GOUT has a sufficiently short rise time and fall time. The signal GOUT may represent, for example, a scan signal for controlling Figure 3 the data - loading transistor Tdata or other switching transistors within the pixel 22. The second output buffer transistor T9 has a source terminal coupled to the gate driver output port, a gate terminal coupled to node QB2, and a drain terminal coupled to a low - power supply signal VGL.

[0095] The output buffer sub - circuit 44”' may further include a transistor T11 and a capacitor C QB2 . The transistor T11 has a first source - drain terminal coupled to node QB2, a second source - drain terminal coupled to node QB1, and a gate terminal configured to receive a shift - register clock signal CLK_B. The capacitor C QB2 may have a first terminal coupled to node QB2 and a second terminal configured to receive a shift - register clock signal CLK_A. Connected in this way, the transistor T11 and the capacitor C QB2 can be used to ensure that node QB2 is less than VGL when the output buffer transistor T9 needs to be turned on.

[0096] The output buffer sub - circuit 44” may further include transistors T10, T12 and capacitors C Q21 and C Q21 . The transistor T10 may have a first source - drain terminal coupled to node Q2 (i.e., the gate terminal of transistor T8), a second source - drain terminal coupled to a carry - output port, and a gate terminal configured to receive a low voltage VGL. The capacitor C Q21 may have a first terminal coupled to node Q2 and a second terminal shunted (short - circuited) to VGL. In other embodiments, the second terminal of the capacitor C Q21 may instead be coupled (short - circuited) to VGH or other static voltage lines. The capacitor C Q22 may have a first terminal coupled to node Q2 and a second terminal coupled to the transistor T12. The transistor T12 may have a terminal coupled to the capacitor C Q22The first source-drain terminal, a second source-drain terminal configured to receive a signal GOUT_Prev (e.g., the gate output signal from the previous row), and a gate terminal configured to receive a low voltage VGL. Transistors T10 and T12 can act as isolation transistors to isolate any unintentional parasitic coupling from signals CLK_BUF and GOUT_Prev so as not to affect the carry output signal CR_OUT. When GOUT_Prev is pulsed, capacitor C Q22 can be used to push node Q2 to a lower voltage, while capacitor C Q21 can be used as a storage capacitor to hold the charge at node Q2 after transistor T12 is turned off.

[0097] Figure 8B is a timing diagram showing Figure 8A the operation of the gate driver 40''' of the type shown. At time t1, the carry input signal CR_IN from the previous row is pulsed low (from time t1 to t2), which can be synchronized with the CLK_A pulse that turns on transistors T3 and T5. This can cause nodes Q0 and Q1 to drop from VGH to VGL and node QB2 to drop from VGL to (2VGL - VGH) due to capacitive coupling through capacitor C QB2 . At time t2, signals CR_IN and CLK_A can be driven high, which can cause node QB1 to be driven from VGL to VGH using transistor T4, and can cause node QB2 to be jumped back to VGL via capacitor C QB2 . At time t2, signal CLK_BUF can also be pulsed high for a short period.

[0098] At time t3, signal CLK_B can be pulsed low, which causes the carry output signal CR_OUT to be pulsed low through transistor T1. During this period, node Q2 can also drop from VGH to a lower voltage through transistor T10. At the same time, node Q1 is pushed down to an even lower level (e.g., from VGL to 2VGL - VGH) through the coupling via capacitor C Q1 . At time t3, transistor T11 can be used to pull up node QB2 (e.g., from VGL to VGH).

[0099] At time t4, GOUT_Prev can be pulsed high. This can cause node Q2 to be pulled all the way down to VGL by the end of the falling edge of GOUT_Prev (at time t5).

[0100] At time t6, the output buffer clock signal CLK_BUF can be pulsed high, which causes the gate output signal GOUT to be pulsed high through transistor T8. The clock signal CLK_BUF can have a pulse width PW_SC. At time t7, the output buffer clock signal CLK_BUF can be made inactive, which causes the gate output signal GOUT to return to its initial level.

[0101] At time t8, the rising edge of the shift register clock signal CLK_B will cause the carry output signal CR_OUT to return to its initial VGH level. At the same time, due to the coupling through capacitor C Q1 , node Q1 will rise back to VGL, and using transistor T10, node Q2 will rise back to VGH.

[0102] At time t9, a pulse of CLK_A when the current feed carry input signal CR_IN is high will cause node Q0 to be reset to its initial high level, while resetting node QB1 low. The rising of node Q0 will also cause node Q1 to be driven back to VGH via transistor TA. By having a separate (isolated) output buffer clock pulse CLK_BUF that is narrower than the shift register clock pulses in CLK_A and CLK_B, the gate driver 40''' is able to generate a gate output signal GOUT with fast enough rise and fall times.

[0103] Figure 8C is a block diagram showing a plurality of gate driver circuits 40''' of the type described in connection with Figure 8A and Figure 8B coupled together in a chain. As Figure 8C shown, the gate driver circuit 34 can include a chain of gate drivers 40, such as gate drivers 40'''-1, 40'''-2, 40'''-3, and 40'''-4. Although only four gate drivers 40''' are shown in Figure 8C , the gate driver circuit 34 can include hundreds or thousands of gate drivers 40''' connected in a chain. The gate driver 40'''-1 can be configured to generate a first gate output signal GOUT(4n + 1). The gate driver 40'''-2 can be configured to generate a second gate output signal GOUT(4n + 2). The gate driver 40'''-3 can be configured to generate a third gate output signal GOUT(4n + 3). The gate driver 40'''-4 can be configured to generate a fourth gate output signal GOUT(4n + 4). The connection of the shift register clock signal and the output buffer clock signal is similar to the connection already described in connection with Figure 5C . However, Figure 8CIt is also shown that the gate output signal is fed from one stage to another (e.g., the signal GOUT from one row is fed to the GOUT_Prev port of the subsequent gate driver). The timing of these shift register clock signals and output buffer clock signals for controlling the chain of gate drivers 40”' can be the same as or similar to the waveforms already shown in Figure 5D and shown in

[0104] Figure 9A Another embodiment of the gate driver circuit 40”” powered by the power supply voltages VGL and VGH is shown. As Figure 9A shown, the gate driver 40”” may include a shift register sub-circuit 42 and an output buffer sub-circuit 44””. Figure 9A The shift register sub-circuit 42 in the gate driver 40”” of Figure 5A may have the same structure as the shift register sub-circuit 42 in the gate driver 40 of

[0105] and need not be repeated in detail so as not to obscure this embodiment. As an example, all transistors within the gate driver circuit 40”” may be implemented as silicon transistors (e.g., all transistors within the gate driver 40”” may be implemented as PMOS LTPS thin film transistors).

[0105] The output buffer sub-circuit 44”” may include a transistor T8 serially coupled to a transistor T9. The first output buffer transistor T8 has a source terminal configured to receive the output buffer clock signal CLK_BUF, a gate terminal coupled to node Q2, and a drain terminal coupled to the gate driver output port that generates the gate output signal GOUT. The size of the transistor T8 may be relatively large to help ensure that the gate output signal GOUT has a sufficiently short rise time and fall time. The signal GOUT may represent, for example, a scan signal for controlling the data loading transistor Tdata or other switching transistors within the pixel 22 in Figure 3 The second output buffer transistor T9 has a source terminal coupled to the gate driver output port, a gate terminal coupled to node QB2, and a drain terminal coupled to the low power supply signal VGL.

[0106] The output buffer sub-circuit 44”” may also include a transistor T11 and a capacitor C QB2 . The transistor T11 has a first source-drain terminal coupled to node QB2, a second source-drain terminal coupled to node QB1, and a gate terminal configured to receive the shift register clock signal CLK_B. The capacitor C QB2 may have a first terminal coupled to node QB2 and a second terminal configured to receive the shift register clock signal CLK_A. Connected in this way, the transistor T11 and the capacitor C QB2Can be used to ensure that node QB2 is less than VGL when the output buffer transistor T9 needs to be turned on.

[0107] The output buffer sub-circuit 44"" may further include transistors T12 - T15 and capacitor C Q2 . Capacitor C Q2 Can be coupled across the gate terminal and drain terminal of transistor T8. Transistor T12 may have a first source-drain terminal coupled to node Q2 (i.e., the gate terminal of transistor T8), a second source-drain terminal coupled to node A, and a gate terminal configured to receive the low voltage VGL. Transistor T13 may have a drain terminal coupled to the low voltage VGL, a gate terminal coupled to node Q1 in the shift register sub-circuit 42, and a source terminal coupled to node A. Transistor T14 may have a drain terminal coupled to node A, a gate terminal configured to receive the clock signal CLK_B, and a source terminal coupled to the source terminal of transistor T15. Transistor T15 may have a drain terminal coupled to the source terminal of T14, a gate terminal coupled to node QB1 in the shift register sub-circuit 42, and a source terminal coupled to the high power supply voltage VGH.

[0108] Figure 9B Is a timing diagram showing Figure 9A The operation of the gate driver 40"" of the type shown. At time t1, the carry input signal CR_IN from the previous row pulses low (from time t1 to t2), which may be synchronized with the CLK_A pulse that turns on transistors T3 and T5, which may cause nodes Q0 and Q1 to drop from VGH to VGL and node QB2 to drop from VGL to (2VGL - VGH) due to the capacitive coupling through capacitor C QB2 . At time t2, signals CR_IN and CLK_A may be driven high, which may cause node QB1 to be driven from VGL to VGH using transistor T4, and may cause node QB2 to jump back to VGL via capacitor C QB2 .

[0109] At time t3, the signal CLK_B may pulse low (from time t3 to t6), which causes the carry output signal CR_OUT to pulse low through transistor T1. During this period, node Q1 is pushed down to an even lower level (e.g., from VGL to 2VGL - VGH) due to the coupling through capacitor C Q1 . At time t3, node QB2 may be pulled up (e.g., from VGL to VGH) using transistor T11.

[0110] At time t4, the output buffer clock signal CLK_BUF can be pulsed high, which causes the gate output signal GOUT to be pulsed high through transistor T8. The clock signal CLK_BUF can have a pulse width PW_SC. At time t5, the output buffer clock signal CLK_BUF can be made inactive, which causes the gate output signal GOUT to return to its initial level. At the falling edge of GOUT at time t5, node Q2 can be capacitively coupled down to a voltage below VGL (e.g., from VGL to 2VGL - VGH). Q2 down to a voltage below VGL (e.g., from VGL to 2VGL - VGH).

[0111] At time t6, the rising edge of the shift register clock signal CLK_B will cause the carry output signal CR_OUT to return to its initial VGH level. At the same time, due to the capacitive coupling through capacitor C Q1 node Q1 will rise back to VGL.

[0112] At time t7, a pulse of CLK_A when the current feed - through carry - in signal CR_IN is high will cause node Q0 to be reset to its initial high level while resetting node QB1 low. The rising of node Q0 will also cause node Q1 to be driven back to VGH via transistor TA. By having a separate (isolated) output buffer clock pulse CLK_BUF that is narrower than the shift register clock pulses in CLK_A and CLK_B, the gate driver 40″ can generate a gate output signal GOUT with fast enough rise and fall times. Node Q2 will be driven back to VGH at a subsequent CLK_B pulse later.

[0113] Multiple gate drivers 40″ can be coupled together in a chain in a manner similar to that already shown in Figure 5C . The carry signal can be fed from one gate driver 40″ to another gate driver 40″. At least four different shift register clock signals CLK_SR1, CLK_SR_2, CLK_SR_3, and CLK_SR4 can be used to control the CLK_A and CLK_B ports in each group of four gate drivers 40″. Similarly, at least four different output buffer clock signals CLK_BUF_1, CLK_BUF_2, CLK_BUF_3, and CLK_BUF_4 can be used to control the CLK_BUF ports in each group of four gate drivers 40″. The timing of these shift register clock signals and output buffer clock signals for controlling the chain of gate drivers 40″ can be the same as or similar to the waveforms already shown in Figure 5D .

[0114] Figure 10A Another embodiment of a gate driver circuit 40″′ powered by supply voltages VGL and VGH is shown. As Figure 10AAs shown, the gate driver 40''' may include a shift register sub-circuit 42 and an output buffer sub-circuit 44'''. Figure 10A The shift register sub-circuit 42 in the gate driver 40''' may have the same structure as Figure 5A the shift register sub-circuit 42 in the gate driver 40, and need not be repeated in detail so as not to obscure the present embodiment. As an example, all transistors within the gate driver circuit 40''' may be implemented as silicon transistors (e.g., all transistors within the gate driver 40''' may be implemented as PMOS LTPS thin film transistors).

[0115] The output buffer sub-circuit 44''' may include a transistor T8 serially coupled to a transistor T9. The first output buffer transistor T8 has a source terminal configured to receive an output buffer clock signal CLK_BUF, a gate terminal coupled to node Q2, and a drain terminal coupled to a gate driver output port that generates a gate output signal GOUT. The size of the transistor T8 may be relatively large to help ensure that the gate output signal GOUT has a sufficiently short rise time and fall time. The signal GOUT may represent, for example, a scan signal for controlling Figure 3 the data load transistor Tdata or other switching transistors within the pixel 22. The second output buffer transistor T9 has a source terminal coupled to the gate driver output port, a gate terminal coupled to node QB2, and a drain terminal coupled to a low power supply signal VGL.

[0116] The output buffer sub-circuit 44''' may further include a transistor T11 and a capacitor C QB2 . The transistor T11 has a first source-drain terminal coupled to node QB2, a second source-drain terminal coupled to node QB1, and a gate terminal configured to receive a low voltage VGL. The capacitor C QB2 may have a first terminal coupled to node QB2 and a second terminal configured to receive a shift register clock signal CLK_B. Connected in this way, the transistor T5 and the capacitor C QB2 in the sub-circuit 42 can be used to ensure that node QB2 is less than VGL when the output buffer transistor T9 needs to be turned on.

[0117] The output buffer sub-circuit 44''' may further include transistors T12 - T15 and a capacitor C Q2 . The capacitor C Q2It can be coupled across the gate terminal and the drain terminal of transistor T8. Transistor T12 can have a first source-drain terminal coupled to node Q2 (i.e., the gate terminal of transistor T8), a second source-drain terminal coupled to node A, and a gate terminal configured to receive a low voltage VGL. Transistor T13 can have a drain terminal coupled to the low voltage VGL, a gate terminal coupled to node Q1 in the shift register sub-circuit 42, and a source terminal coupled to node A. Transistor T14 can have a drain terminal coupled to node A, a gate terminal configured to receive a clock signal CLK_B, and a source terminal coupled to the source terminal of transistor T15. Transistor T15 can have a drain terminal coupled to the source terminal of T14, a gate terminal coupled to node QB1 in the shift register sub-circuit 42, and a source terminal coupled to a high power supply voltage VGH. The use of transistor T14 is optional. In an embodiment where transistor T14 is omitted, node A can be directly connected to the drain terminal of T15. Omitting transistor T14 does not change the operation of the gate driver 40””'.

[0118] Figure 10B is a timing diagram showing Figure 10A the operation of a gate driver 40””' of the type shown. At time t1, the carry input signal CR_IN from the previous line pulses low (from time t1 to t2), which can be synchronized with the CLK_A pulse that turns on transistors T3 and T5, which can cause nodes Q0 and Q1 to drop from VGH to VGL and node Q2 to drop from VGH to VGL. At time t2, signals CR_IN and CLK_A can be driven high, which can cause node QB1 to be driven from VGL to VGH using transistor T4, and can cause node QB2 to be driven high to VGH via transistor T11.

[0119] At time t3, the signal CLK_B can pulse low (from time t3 to t6), which causes the carry output signal CR_OUT to pulse low through transistor T1. During this period, node Q1 is pushed down to an even lower level (e.g., from VGL to 2VGL-VGH) through the coupling via capacitor C Q1 .

[0120] At time t4, the output buffer clock signal CLK_BUF can pulse high, which causes the gate output signal GOUT to pulse high through transistor T8. The clock signal CLK_BUF can have a pulse width PW_SC. At time t5, the output buffer clock signal CLK_BUF can be made inactive, which causes the gate output signal GOUT to return to its initial level. At the falling edge of GOUT at time t5, node Q2 can be coupled down to a voltage below VGL (e.g., from VGL to 2VGL-VGH) through capacitor C Q2 .

[0121] At time t6, the rising edge of the shift register clock signal CLK_B will cause the carry output signal CR_OUT to return to its initial VGH level. At the same time, due to the coupling through capacitor C Q1 , node Q1 will rise back to VGL.

[0122] At time t7, a CLK_A pulse when the current feed carry input signal CR_IN is high will cause node Q0 to reset to its initial high level, while resetting node QB1 to the VGL low level. The rising of node Q0 will also cause node Q1 to be driven back to VGH via transistor TA. By having a separate (isolated) output buffer clock pulse CLK_BUF that is narrower than the shift register clock pulses in CLK_A and CLK_B, the gate driver 40''' can generate a gate output signal GOUT with a fast enough rise time and fall time. Node Q2 will be driven back to VGH at a subsequent CLK_B pulse later.

[0123] Multiple gate drivers 40''' can be coupled together in a chain in a manner similar to that already shown in Figure 5C . The carry signal can be fed from one gate driver 40''' to another gate driver 40'''. At least four different shift register clock signals CLK_SR1, CLK_SR_2, CLK_SR_3, and CLK_SR4 can be used to control the CLK_A and CLK_B ports in each group of four gate drivers 40'''. Similarly, at least four different output buffer clock signals CLK_BUF_1, CLK_BUF_2, CLK_BUF_3, and CLK_BUF_4 can be used to control the CLK_BUF port in each group of four gate drivers 40'''. The timing of these shift register clock signals and output buffer clock signals for controlling the chain of gate drivers 40''' can be the same as or similar to the waveforms already shown in Figure 5D .

[0124] Figure 11A is a circuit diagram of another specific implementation of the gate driver circuit 40*. As shown in Figure 11A , the gate driver 40* can include a shift register sub-circuit 42 and an output buffer sub-circuit 44*. Figure 11A The shift register sub-circuit 42 in the gate driver 40* of Figure 5A can have the same structure as the shift register sub-circuit 42 in the gate driver 40 of Figure 5A , and there is no need to repeat it in detail to avoid obscuring this implementation. As an example, all transistors within the gate driver circuit 40* can be implemented as silicon transistors (e.g., all transistors within the gate driver 40* can be implemented as PMOS LTPS thin film transistors).

[0125] The output buffer sub - circuit 44* may include a transistor T8 serially coupled with a transistor T9. The first output buffer transistor T8 has a source terminal configured to receive an output buffer clock signal CLK_BUF, a gate terminal coupled to node Q2, and a drain terminal coupled to a gate driver output port that generates a gate output signal GOUT. The transistor T8 may be relatively large in size to help ensure that the gate output signal GOUT has a sufficiently short rise time and fall time. The signal GOUT may represent, for example, a scan signal for controlling Figure 3 the data loading transistor Tdata or other switching transistors within the pixel 22. The second output buffer transistor T9 has a source terminal coupled to the gate driver output port, a gate terminal coupled to node QB2, and a drain terminal coupled to a low power supply signal VGL.

[0126] The output buffer sub - circuit 44* may also include transistors T11 - T15 and a capacitor C Q2 . The capacitor C Q2 may be coupled across the gate terminal and the drain terminal of the transistor T8. The transistor T11 has a first source - drain terminal coupled to node QB2, a second source - drain terminal coupled to node QB1, and a gate terminal configured to receive a low voltage VGL. The transistor T12 may have a first source - drain terminal coupled to node Q2 (i.e., the gate terminal of the transistor T8), a second source - drain terminal coupled to node A, and a gate terminal configured to receive a low voltage VGL. The transistor T13 may have a drain terminal coupled to the low voltage VGL, a gate terminal coupled to node Q1 in the shift register sub - circuit 42, and a source terminal coupled to node A. The transistor T14 may have a drain terminal coupled to node A, a gate terminal configured to receive a clock signal CLK_B, and a source terminal coupled to the transistor T15. The transistor T15 may have a drain terminal coupled to the source terminal of T14, a gate terminal coupled to node QB1 in the shift register sub - circuit 42, and a source terminal coupled to a high power supply voltage VGH.

[0127] The output buffer sub - circuit 44* may also include transistors T16 and capacitors C QB2 and C 1 . The capacitor C QB2 may have a first terminal coupled to node QB2 and a second terminal coupled to node B. The capacitor C 1It may have a first terminal coupled to node B and a second terminal coupled to the low power supply voltage VGL. Transistor T16 may have a first source-drain terminal coupled to node B, a second source-drain terminal configured to receive the shift register clock signal CLK_B, and a gate terminal coupled to the Q0 node (as indicated by the "n+3" notation) of another gate driver 40* from the following three rows. Configured in this way, transistor T16 can be used to maintain the voltage at node QB2 below VGL (e.g., turning off transistor T16 can isolate capacitor C QB2 from any noise or switching associated with the clock signal CLK_B). The gate terminal of transistor T16 is coupled to Q0(n+3) via transistor T17 Figure 12 The example is illustrative. In other embodiments, the gate terminal of transistor T16 may be coupled to Q1(n+3) (e.g., the Q1 node of another gate driver 40*** from the following three rows) via transistor T17.

[0128] Figure 11B is a timing diagram showing Figure 11A the operation of the gate driver 40* of the type shown. At time t1, the carry input signal CR_IN from the previous row pulses low (from time t1 to t2), which may be synchronized with the CLK_A pulse that turns on transistors T3 and T5, which may cause nodes Q0 and Q1 to drop from VGH to VGL and node Q2 to drop from VGH to VGL. Figure 11B Also shown are the fall times and rise times of node Q0 of the current row (e.g., row n) and subsequent rows such as rows (n+1), (n+2), and (n+3). At time t2, signals CR_IN and CLK_A may be driven high, which may cause node QB1 to be driven from VGL to VGH using transistor T4, and may cause node QB2 to be boosted high to VGH via transistor T11.

[0129] At time t3, the signal CLK_B may pulse low (from time t3 to t6), which causes the carry output signal CR_OUT to pulse low through transistor T1. During this period, node Q1 is pushed down to an even lower level (e.g., from VGL to 2VGL-VGH) via the coupling through capacitor C Q1 .

[0130] At time t4, the output buffer clock signal CLK_BUF may pulse high, which causes the gate output signal GOUT to pulse high through transistor T8. The clock signal CLK_BUF may have a pulse width PW_SC. At time t5, the output buffer clock signal CLK_BUF may be made inactive, which causes the gate output signal GOUT to return to its initial level. At the falling edge of GOUT at time t5, node Q2 may pass through capacitor CQ2 Coupled down to a voltage lower than VGL (eg, from VGL to 2VGL-VGH).

[0131] At time t6, the rising edge of the shift register clock signal CLK_B will cause the carry output signal CR_OUT to return to its initial VGH level. At the same time, due to the capacitor C Q1 coupled, node Q1 will rise back to VGL.

[0132] At time t7, a CLK_A pulse when the feed-forward input signal CR_IN is high will cause node Q0 to reset to its initial high level while resetting node QB1 to VGL low level. The rise of node Q0 will also cause node Q1 to be driven back to VGH via transistor TA. By having a separate (isolated) output buffer clock pulse CLK_BUF that is narrower than the shift register clock pulses in CLK_A and CLK_B, gate driver 40''' is able to generate a gate output signal GOUT with sufficiently fast rise and fall times. Node Q2 will later be driven back to VGH at a subsequent CLK_B pulse. Note that using Q0(n+3) to control transistor T16 can help ensure that transistor T16 remains disconnected before CLK_BUF is pulsed at time t4.

[0133] Figure 11C is a diagram showing the combination of components coupled together in a chain Figure 11A and Figure 11B A block diagram of a plurality of gate driver circuits 40* of the type described is shown. Figure 11C As shown, the gate driver circuit 34 may include a chain of gate drivers 40*, such as gate drivers 40*-1, 40*-2, 40*-3, and 40*-4. Figure 11C Only four gate drivers 40* are shown, but the gate driver circuit 34 may include hundreds or thousands of gate drivers 40* connected in a chain. Gate driver 40*-1 can be configured to generate a first gate output signal GOUT(4n+1). Gate driver 40*-2 can be configured to generate a second gate output signal GOUT(4n+2). Gate driver 40*-3 can be configured to generate a third gate output signal GOUT(4n+3). Gate driver 40*-4 can be configured to generate a fourth gate output signal GOUT(4n+4). The connection of the shift register clock signal and the output buffer clock signal is similar to that already combined Figure 5C However, Figure 11C Q0(n) is shown being fed back to the upper three stages (eg, Q0 of driver 40*-4 is fed back to the Q0(n+3) input of driver 40*-1, etc.).

[0134] Figure 12 This is a circuit diagram of another specific implementation of a gate driver circuit, such as gate driver circuit 40**. As Figure 12 shown, the gate driver 40** may include a shift register sub-circuit 42 and an output buffer sub-circuit 44**. Figure 12 The shift register sub-circuit 42 in the gate driver 40** may have the same structure as the shift register sub-circuit 42 in Figure 5A the gate driver 40, and there is no need to repeat it in detail to avoid obscuring this implementation. As an example, all transistors within the gate driver circuit 40** may be implemented as silicon transistors (e.g., all transistors within the gate driver 40** may be implemented as PMOS LTPS thin film transistors).

[0135] The output buffer sub-circuit 44** may include a transistor T8 serially coupled to a transistor T9. The first output buffer transistor T8 has a source terminal configured to receive an output buffer clock signal CLK_BUF, a gate terminal coupled to node Q2, and a drain terminal coupled to a gate driver output port that generates a gate output signal GOUT. The size of the transistor T8 may be relatively large to help ensure that the gate output signal GOUT has a sufficiently short rise time and fall time. The signal GOUT may represent, for example, a scan signal for controlling Figure 3 the data loading transistor Tdata or other switching transistors within the pixel 22. The second output buffer transistor T9 has a source terminal coupled to the gate driver output port, a gate terminal coupled to node QB2, and a drain terminal coupled to a low power supply signal VGL.

[0136] The output buffer sub-circuit 44** may also include transistors T11 - T15 and a capacitor C Q2 . The capacitor C Q2It can be coupled across the gate terminal and the drain terminal of transistor T8. Transistor T11 has a first source-drain terminal coupled to node QB2, a second source-drain terminal coupled to node QB1, and a gate terminal configured to receive a low voltage VGL. Transistor T12 can have a first source-drain terminal coupled to node Q2 (i.e., the gate terminal of transistor T8), a second source-drain terminal coupled to node A, and a gate terminal configured to receive a low voltage VGL. Transistor T13 can have a drain terminal coupled to the low voltage VGL, a gate terminal coupled to node Q1 in the shift register sub-circuit 42, and a source terminal coupled to node A. Transistor T14 can have a drain terminal coupled to node A, a gate terminal configured to receive a clock signal CLK_B, and a source terminal coupled to the source terminal of transistor T15. Transistor T15 can have a drain terminal coupled to the source terminal of T14, a gate terminal coupled to node QB1 in the shift register sub-circuit 42, and a source terminal coupled to a high power supply voltage VGH.

[0137] The output buffer sub-circuit 44** may further include transistors T16 - T17 and capacitors C QB2 、C 1 and C 2 。 Capacitor C QB2 can have a first terminal coupled to node QB2 and a second terminal coupled to node B. Capacitor C1 can have a first terminal coupled to node B and a second terminal coupled to the low power supply voltage VGL. Transistor T16 can have a first source-drain terminal coupled to node B, a second source-drain terminal configured to receive a shift register clock signal CLK_B, and a gate terminal. Capacitor C 2 can have a first terminal coupled to node B and a second terminal coupled to the gate terminal of transistor T16. Transistor T17 can have a gate terminal coupled to the low power supply voltage VGL, a first source-drain terminal coupled to the gate terminal of transistor T16, and a second source-drain terminal coupled to the Q0 node (as indicated by the "n + 3" notation) of another gate driver 40** from the following three rows. Configured in this way, transistor T16 can be used to maintain the voltage at node QB2 below VGL (e.g., turning off transistor T16 can isolate capacitor C QB2 from any noise or switching associated with the clock signal CLK_B).

[0138] Figure 12 The operation of the gate driver 40** is substantially similar to the timing diagram already shown in Figure 11B and does not need to be repeated in detail so as not to obscure the present embodiment. The only difference in the timing waveform of the gate driver 40** is that at the rising edge of Q0(n + 3), node QB2 can be due to capacitor C 2and C QB2 rises slightly due to capacitive coupling with Figure 11C The multiple gate drivers 40** can be coupled together in a chain using an arrangement similar or identical to the control scheme shown in

[0139] Figure 13 is a circuit diagram of another specific implementation of a gate driver circuit (such as gate driver circuit 40***) configured to receive a reset signal. As Figure 13 shown, the gate driver 40*** can include a shift register sub-circuit 42 and an output buffer sub-circuit 44***. Figure 13 The shift register sub-circuit 42 in the gate driver 40*** of Figure 5A can have the same structure as the shift register sub-circuit 42 in the gate driver 40 of

[0140] and need not be repeated in detail so as not to obscure the present implementation. As an example, all transistors within the gate driver circuit 40*** can be implemented as silicon transistors (e.g., all transistors within the gate driver 40*** can be implemented as PMOS LTPS thin film transistors). Figure 3 The output buffer sub-circuit 44*** can include a transistor T8 serially coupled with a transistor T9. The first output buffer transistor T8 has a source terminal configured to receive an output buffer clock signal CLK_BUF, a gate terminal coupled to node Q2, and a drain terminal coupled to a gate driver output port that generates a gate output signal GOUT. The size of the transistor T8 can be relatively large to help ensure that the gate output signal GOUT has a sufficiently short rise time and fall time. The signal GOUT can represent, for example, a scan signal for controlling

[0141] The output buffer sub-circuit 44*** can also include transistors T11 - T15 and a capacitor C Q2 The capacitor C Q2It can be coupled across the gate terminal and the drain terminal of transistor T8. Transistor T11 has a first source-drain terminal coupled to node QB2, a second source-drain terminal coupled to node QB1, and a gate terminal configured to receive a low voltage VGL. Transistor T12 can have a first source-drain terminal coupled to node Q2 (i.e., the gate terminal of transistor T8), a second source-drain terminal coupled to node A, and a gate terminal configured to receive a low voltage VGL. Transistor T13 can have a drain terminal coupled to the low voltage VGL, a gate terminal coupled to node Q1 in the shift register sub-circuit 42, and a source terminal coupled to node A. Transistor T14 can have a drain terminal coupled to node A, a gate terminal configured to receive a clock signal CLK_B, and a source terminal coupled to the source terminal of transistor T15. Transistor T15 can have a drain terminal coupled to the source terminal of T14, a gate terminal coupled to node QB1 in the shift register sub-circuit 42, and a source terminal coupled to a high power supply voltage VGH.

[0142] The output buffer sub-circuit 44*** may further include transistors T16 - T18 and capacitors C QB2 and C 1 . Capacitor C QB2 can have a first terminal coupled to node QB2 and a second terminal coupled to node B. Capacitor C 1 can have a first terminal coupled to node B and a second terminal coupled to a low power supply voltage VGL. Transistor T16 can have a first source-drain terminal coupled to node B, a second source-drain terminal configured to receive a shift register clock signal CLK_B, and a gate terminal coupled to the Q0 node (as indicated by the "n + 3" notation) of another gate driver 40*** from the following three rows.

[0143] The transistor T17 may have a source terminal coupled to node B, a drain terminal coupled to a low power supply voltage VGL, and a gate terminal configured to receive a reset signal. The reset signal may be a global reset signal that simultaneously controls each gate driver 40***. The transistor T18 may have a drain terminal coupled to node QB1, a source terminal coupled to the low power supply voltage VGL, and a gate terminal configured to receive the reset signal. Configured in this way, the transistors T16, T17, and T18 can be used to stabilize the low refresh rate of the gate driver (e.g., when the display operates at a refresh rate less than 30 Hz, less than 10 Hz, less than 5 Hz, 2 Hz or lower, 1 Hz or lower, etc.). For example, using transistors T16 and T17 can help minimize the impact of leakage from CLK_B to node B, while using transistor T18 can help minimize the impact of leakage from CLK_A to node QB1 through transistor T4. The global reset signal can be made valid during the vertical blanking period to turn on transistors T17 and T18. Transistors T17 and T18 can remain off during normal display refresh operations.

[0144] Figure 13 The operation of the gate driver 40*** is substantially similar to the timing diagram already shown in Figure 11B and need not be repeated in detail so as not to obscure the present embodiment. Multiple gate drivers 40*** can be coupled together in a chain using an arrangement similar or identical to the control scheme already shown in Figure 11C

[0145] According to one embodiment, a display is provided that includes: a pixel array, each pixel in the pixel array including a plurality of transistors, and all transistors in at least one pixel in the pixel array including semiconductor oxide transistors; and a plurality of gate driver circuits configured to generate corresponding gate output signals for controlling the pixel array, each gate driver circuit in the plurality of gate driver circuits including a plurality of transistors, and all transistors in at least one gate driver circuit in the plurality of gate driver circuits including silicon transistors.

[0146] According to another embodiment, all transistors in at least one pixel include n-type semiconductor oxide transistors.

[0147] According to another embodiment, all transistors in at least one gate driver circuit include p-type silicon transistors.

[0148] According to another embodiment, at least one gate driver circuit is configured to generate a given gate output signal in a gate output signal for controlling a data loading transistor in a row of pixels in an array; a first portion of a plurality of transistors in the at least one gate driver circuit includes a shift register sub-circuit configured to receive a shift register clock signal, receive a carry input signal, and generate a carry output signal; and a second portion of the plurality of transistors in the at least one gate driver circuit includes an output buffer sub-circuit configured to receive an output buffer clock signal and generate the given gate output signal.

[0149] According to another embodiment, the output buffer sub-circuit includes: a first transistor having a first source-drain terminal configured to receive the output buffer clock signal and a second source-drain terminal at which the given gate output signal is generated; and a second transistor having a first source-drain terminal coupled to the second source-drain terminal of the first transistor and a second source-drain terminal coupled to a power supply line.

[0150] According to another embodiment, the output buffer sub-circuit includes: a third transistor having a first source-drain terminal coupled to a gate terminal of the second transistor, a second source-drain terminal coupled to a node in the shift register sub-circuit, and a gate terminal configured to receive a second clock signal; and a first capacitor having a first terminal coupled to the gate terminal of the second transistor and a second terminal configured to receive a first clock signal.

[0151] According to another embodiment, the first clock signal and the second clock signal are applied to the shift register sub-circuit as the shift register clock signal.

[0152] According to another embodiment, the output buffer sub-circuit includes: a fourth transistor having a first source-drain terminal coupled to the gate terminal of the first transistor, a second source-drain terminal coupled to a node in the shift register sub-circuit, and a gate terminal coupled to the power supply line.

[0153] According to another embodiment, the output buffer sub-circuit includes: a fifth transistor having a first source-drain terminal configured to receive a gate output signal from another gate driver circuit in a gate driver circuit in a previous row, a second source-drain terminal coupled to the gate terminal of the first transistor, and a gate terminal coupled to the power supply line.

[0154] According to another embodiment, the output buffer sub-circuit includes: a second capacitor coupled between a second source-drain terminal of a fifth transistor and a gate terminal of a first transistor; and a third capacitor having a first terminal coupled to the gate terminal of the first transistor and a second terminal coupled to a power supply line or to an additional power supply line different from the power supply line.

[0155] According to another embodiment, the output buffer sub-circuit includes: a fourth transistor having a first source-drain terminal coupled to the gate terminal of the first transistor, a second source-drain terminal configured to a carry output port of the shift register sub-circuit, and a gate terminal coupled to an additional power supply line.

[0156] According to another embodiment, the output buffer sub-circuit further includes a second capacitor coupled between the gate terminal and the second source-drain terminal of the first transistor.

[0157] According to another embodiment, the output buffer sub-circuit includes: a fourth transistor having a first source-drain terminal coupled to the gate terminal of the first transistor, a second source-drain terminal coupled to a node in the shift register sub-circuit, and a gate terminal coupled to a power supply line.

[0158] According to another embodiment, the output buffer sub-circuit includes: a fifth transistor having a gate terminal coupled to the gate terminal of the first transistor, a first source-drain terminal configured to receive a first clock signal, and a second source-drain terminal; a sixth transistor having a gate terminal coupled to another node in the shift register sub-circuit, a first source-drain terminal coupled to the second source-drain terminal of the fifth transistor, and a second source-drain terminal coupled to an additional power supply line; and a second capacitor coupled across the gate terminal and the second source-drain terminal of the fifth transistor.

[0159] According to another embodiment, the output buffer sub-circuit includes: a third transistor having a first source-drain terminal coupled to the gate terminal of the second transistor, a second source-drain terminal coupled to a node in the shift register sub-circuit, and a gate terminal coupled to a power supply line; and a first capacitor having a first terminal coupled to the gate terminal of the second transistor and a second terminal configured to receive the first clock signal.

[0160] According to another embodiment, the shift register sub-circuit includes: a fourth transistor having a first source-drain terminal coupled to a node in the shift register sub-circuit, a second source-drain terminal coupled to a power supply line, and a gate terminal configured to receive a second clock signal different from the first clock signal.

[0161] According to one embodiment, a gate driver circuit is provided, the gate driver circuit comprising: a shift register sub-circuit configured to receive a shift register clock signal, receive a carry input signal, and generate a carry output signal; and an output buffer sub-circuit configured to receive an output buffer clock signal and generate a corresponding gate output signal, the output buffer sub-circuit comprising: a first transistor having a first source-drain terminal configured to receive the output buffer clock signal and having a second source-drain terminal at which the gate output signal is generated; a second transistor having a first source-drain terminal coupled to the second source-drain terminal of the first transistor and having a second source-drain terminal coupled to a power supply line; and a third transistor having a first source-drain terminal coupled to the gate terminal of the second transistor, a second source-drain terminal coupled to a node in the shift register sub-circuit, and a gate terminal configured to receive one of the shift register clock signals or coupled to the power supply line.

[0162] According to another embodiment, the output buffer sub-circuit further comprises: a first capacitor having a first terminal coupled to the gate terminal of the second transistor and having a second terminal configured to receive one of the shift register clock signals.

[0163] According to another embodiment, the output buffer sub-circuit further comprises: a fourth transistor coupled between a carry output port of the shift register sub-circuit that generates the carry output signal and the gate terminal of the first transistor; a fifth transistor having a first source-drain terminal configured to receive an additional gate output signal and having a second source-drain terminal coupled to the gate terminal of the first transistor; a second capacitor coupled between the second source-drain terminal of the fifth transistor and the gate terminal of the first transistor; and a third capacitor coupled between the gate terminal of the first transistor and the power supply line.

[0164] According to another embodiment, the output buffer sub-circuit further comprises: a fourth transistor coupled between a carry output port of the shift register sub-circuit that generates the carry output signal and the gate terminal of the first transistor; and a second capacitor coupled across the gate terminal and the second source-drain terminal of the first transistor.

[0165] According to another embodiment, the output buffer sub-circuit further includes: a fourth transistor coupled between the gate terminal of the first transistor and a node in the shift register sub-circuit; a fifth transistor having a gate terminal coupled to the gate terminal of the first transistor, a first source-drain terminal configured to receive another shift register clock signal among the shift register clock signals, and a second source-drain terminal; a sixth transistor coupled between the second source-drain terminal of the fifth transistor and an additional power supply line; and a second capacitor coupled across the gate terminal and the second source-drain terminal of the fifth transistor.

[0166] According to another embodiment, the output buffer sub-circuit further includes: a first capacitor having a first terminal coupled to the gate terminal of the second transistor and a second terminal coupled to a given node; a second capacitor having a first terminal coupled to the given node and a second terminal coupled to a power supply line; and a fourth transistor having a first source-drain terminal coupled to the given node, a second source-drain terminal configured to receive one of the shift register clock signals, and a gate terminal coupled to an internal node of an additional gate driver circuit in another row.

[0167] According to another embodiment, the output buffer sub-circuit further includes: a third capacitor having a first terminal coupled to the given node and a second terminal coupled to the gate terminal of the fourth transistor; and a fifth transistor having a first source-drain terminal coupled to the gate terminal of the fourth transistor, a gate terminal coupled to the power supply line, and a second source-drain terminal coupled to an internal node of an additional gate driver circuit in another row.

[0168] According to another embodiment, the output buffer sub-circuit further includes: a fifth transistor having a first source-drain terminal coupled to a given node, a second source-drain terminal coupled to the power supply line, and a gate terminal configured to receive a reset signal; and a sixth transistor having a first source-drain terminal coupled to the power supply line, a second source-drain terminal coupled to a node in the shift register sub-circuit, and a gate terminal configured to receive the reset signal.

[0169] According to one embodiment, a display is provided that includes: a pixel including a light-emitting diode, a storage capacitor, and an n-type transistor, the n-type transistor including an n-type driving transistor serially coupled to the light-emitting diode and an n-type data loading transistor coupled to a data line; and a gate driver configured to generate a gate output signal for controlling the n-type data loading transistor in the pixel, the gate driver including a shift register sub-circuit and an output buffer sub-circuit, the output buffer sub-circuit including a p-type silicon transistor that controls the connection between a clock signal and the gate output signal provided to the gate terminal of the n-type data loading transistor.

[0170] According to another embodiment, the pixel includes only n-type semiconductor oxide transistors.

[0171] According to another embodiment, the shift register sub-circuit is configured to receive a first shift register clock signal and a second shift register clock signal, receive a carry input signal, and generate a carry output signal; the output buffer sub-circuit is configured to receive an output buffer clock signal and generate a gate output signal; and the output buffer sub-circuit includes: a first transistor having a first source-drain terminal configured to receive the output buffer clock signal and a second source-drain terminal at which the gate output signal is generated; a second transistor having a first source-drain terminal coupled to the second source-drain terminal of the first transistor and a second source-drain terminal coupled to a power supply line; a third transistor having a first source-drain terminal coupled to the gate terminal of the second transistor, a second source-drain terminal coupled to a node in the shift register sub-circuit, and a gate terminal configured to receive the second shift register clock signal or coupled to the power supply line; and a capacitor having a first terminal coupled to the gate terminal of the second transistor and a second terminal configured to receive the first shift register clock signal or the second shift register clock signal.

[0172] The foregoing is merely illustrative and various modifications may be made to the embodiments. The foregoing embodiments may be implemented individually or in any combination.

Claims

1. A display device, the display device comprises: a pixel array, wherein each pixel in the pixel array includes a plurality of transistors, and all of the transistors in at least one pixel in the pixel array include semiconductor oxide transistors; and a plurality of gate driver circuits configured to generate corresponding gate output signals for controlling the pixel array, wherein each gate driver circuit in the plurality of gate driver circuits includes a plurality of transistors, and all of the transistors in at least one gate driver circuit in the plurality of gate driver circuits include silicon transistors.

2. The display device according to claim 1, wherein all of the transistors in the at least one pixel include n-type semiconductor oxide transistors.

3. The display device according to claim 2, wherein all of the transistors in the at least one gate driver circuit include p-type silicon transistors.

4. The display device according to claim 1, wherein: the at least one gate driver circuit is configured to generate a given gate output signal in the gate output signals for controlling data loading transistors in a pixel row in the array; a first portion of the plurality of transistors in the at least one gate driver circuit includes a shift register sub-circuit configured to receive a shift register clock signal, receive a carry input signal, and generate a carry output signal; and a second portion of the plurality of transistors in the at least one gate driver circuit includes an output buffer sub-circuit configured to receive an output buffer clock signal and generate the given gate output signal.

5. The display device according to claim 4, wherein the output buffer sub-circuit comprises: a first transistor having a first source-drain terminal configured to receive the output buffer clock signal and a second source-drain terminal at which the given gate output signal is generated; and a second transistor having a first source-drain terminal coupled to the second source-drain terminal of the first transistor and a second source-drain terminal coupled to a power supply line.

6. The display device according to claim 5, wherein the output buffer sub-circuit comprises: a third transistor having a first source-drain terminal coupled to the gate terminal of the second transistor, a second source-drain terminal coupled to a node in the shift register sub-circuit, and a gate terminal configured to receive a second clock signal; and a first capacitor having a first terminal coupled to the gate terminal of the second transistor and a second terminal configured to receive a first clock signal.

7. The display device according to claim 6, wherein the first clock signal and the second clock signal are applied to the shift register sub-circuit as the shift register clock signal.

8. The display according to claim 6, wherein the output buffer sub - circuit comprises: A fourth transistor having a first source - drain terminal coupled to the gate terminal of the first transistor, a second source - drain terminal coupled to a node of the shift register sub - circuit, and a gate terminal coupled to the power supply line.

9. The display according to claim 8, wherein the output buffer sub - circuit comprises: A fifth transistor having a first source - drain terminal configured to receive a gate output signal from another gate driver circuit in the gate driver circuit of the previous row, a second source - drain terminal coupled to the gate terminal of the first transistor, and a gate terminal coupled to the power supply line.

10. The display according to claim 9, wherein the output buffer sub - circuit comprises: A second capacitor coupled between the second source - drain terminal of the fifth transistor and the gate terminal of the first transistor; and A third capacitor having a first terminal coupled to the gate terminal of the first transistor and a second terminal coupled to the power supply line or to an additional power supply line different from the power supply line.

11. The display according to claim 6, wherein the output buffer sub - circuit comprises: A fourth transistor having a first source - drain terminal coupled to the gate terminal of the first transistor, a second source - drain terminal configured to the carry - out output port of the shift register sub - circuit, and a gate terminal coupled to an additional power supply line.

12. The display according to claim 11, wherein the output buffer sub - circuit further comprises a second capacitor coupled between the gate terminal and the second source - drain terminal of the first transistor.

13. The display according to claim 7, wherein the output buffer sub - circuit comprises: A fourth transistor having a first source - drain terminal coupled to the gate terminal of the first transistor, a second source - drain terminal coupled to a node in the shift register sub - circuit, and a gate terminal coupled to the power supply line.

14. The display according to claim 13, wherein the output buffer sub - circuit comprises: A fifth transistor having a gate terminal coupled to the gate terminal of the first transistor, a first source - drain terminal configured to receive the first clock signal, and a second source - drain terminal; A sixth transistor having a gate terminal coupled to another node in the shift register sub - circuit, a first source - drain terminal coupled to the second source - drain terminal of the fifth transistor, and a second source - drain terminal coupled to an additional power supply line; and A second capacitor coupled across the gate terminal and the second source - drain terminal of the fifth transistor.

15. The display according to claim 5, wherein the output buffer sub - circuit comprises: A third transistor having a first source-drain terminal coupled to the gate terminal of the second transistor, a second source-drain terminal coupled to a node in the shift register sub-circuit, and a gate terminal coupled to the power supply line; and A first capacitor having a first terminal coupled to the gate terminal of the second transistor and a second terminal configured to receive a first clock signal.

16. The display according to claim 15, wherein the shift register sub-circuit comprises: A fourth transistor having a first source-drain terminal coupled to the node in the shift register sub-circuit, a second source-drain terminal coupled to the power supply line, and a gate terminal configured to receive a second clock signal different from the first clock signal.

17. A gate driver circuit, the gate driver circuit comprises: A shift register sub-circuit configured to receive a shift register clock signal, receive a carry input signal, and generate a carry output signal; and An output buffer sub-circuit configured to receive an output buffer clock signal and generate a corresponding gate output signal, the output buffer sub-circuit comprising: A first transistor having a first source-drain terminal configured to receive the output buffer clock signal and a second source-drain terminal at which the gate output signal is generated; A second transistor having a first source-drain terminal coupled to the second source-drain terminal of the first transistor and a second source-drain terminal coupled to the power supply line; and A third transistor having a first source-drain terminal coupled to the gate terminal of the second transistor, a second source-drain terminal coupled to a node in the shift register sub-circuit, and a gate terminal configured to receive one of the shift register clock signals or coupled to the power supply line.

18. The gate driver circuit according to claim 17, wherein the output buffer sub-circuit further comprises: A first capacitor having a first terminal coupled to the gate terminal of the second transistor and a second terminal configured to receive one of the shift register clock signals.

19. The gate driver circuit according to claim 18, wherein the output buffer sub-circuit further comprises: A fourth transistor coupled between the carry output port of the shift register sub-circuit and the gate terminal of the first transistor, the carry output signal being generated at the carry output port; A fifth transistor having a first source-drain terminal configured to receive an additional gate output signal and a second source-drain terminal coupled to the gate terminal of the first transistor; A second capacitor coupled between the second source-drain terminal of the fifth transistor and the gate terminal of the first transistor; and A third capacitor coupled between the gate terminal of the first transistor and the power supply line.

20. The gate driver circuit according to claim 18, wherein the output buffer sub-circuit further comprises: A fourth transistor coupled between the carry output port of the shift register sub-circuit and the gate terminal of the first transistor, the carry output signal being generated at the carry output port; and A second capacitor coupled across the gate terminal and the second source-drain terminal of the first transistor.

21. The gate driver circuit according to claim 18, wherein the output buffer sub-circuit further comprises: A fourth transistor coupled between the gate terminal of the first transistor and a node in the shift register sub-circuit; A fifth transistor having a gate terminal coupled to the gate terminal of the first transistor, a first source-drain terminal configured to receive another shift register clock signal of the shift register clock signals, and a second source-drain terminal; A sixth transistor coupled between the second source-drain terminal of the fifth transistor and an additional power supply line; and A second capacitor coupled across the gate terminal and the second source-drain terminal of the fifth transistor.

22. The gate driver circuit according to claim 17, wherein the output buffer sub-circuit further comprises: A first capacitor having a first terminal coupled to the gate terminal of the second transistor and a second terminal coupled to a given node; A second capacitor having a first terminal coupled to the given node and a second terminal coupled to the power supply line; and A fourth transistor having a first source-drain terminal coupled to the given node, a second source-drain terminal configured to receive one of the shift register clock signals of the shift register clock signals, and a gate terminal coupled to an internal node of an additional gate driver circuit of another row.

23. The gate driver circuit according to claim 22, wherein the output buffer sub-circuit further comprises: A third capacitor having a first terminal coupled to the given node and a second terminal coupled to the gate terminal of the fourth transistor; and A fifth transistor having a first source-drain terminal coupled to the gate terminal of the fourth transistor, a gate terminal coupled to the power supply line, and a second source-drain terminal coupled to the internal node of the additional gate driver circuit of another row.

24. The gate driver circuit according to claim 22, wherein the output buffer sub-circuit further comprises: A fifth transistor having a first source-drain terminal coupled to the given node, a second source-drain terminal coupled to the power supply line, and a gate terminal configured to receive a reset signal; and a sixth transistor having a first source-drain terminal coupled to the power supply line, a second source-drain terminal coupled to the node in the shift register sub-circuit, and a gate terminal configured to receive the reset signal.

25. A display, the display comprising: a pixel including a light emitting diode, a storage capacitor, and an n-type transistor, the n-type transistor including an n-type driving transistor serially coupled with the light emitting diode and an n-type data loading transistor coupled to a data line; and a gate driver configured to generate a gate output signal for controlling the n-type data loading transistor in the pixel, the gate driver including a shift register sub-circuit and an output buffer sub-circuit, the output buffer sub-circuit including a p-type silicon transistor that controls the connection between a clock signal and the gate output signal provided to the gate terminal of the n-type data loading transistor.

26. The display according to claim 25, wherein the pixel includes only n-type semiconductor oxide transistors.

27. The display according to claim 25, wherein: the shift register sub-circuit is configured to receive a first shift register clock signal and a second shift register clock signal, receive a carry input signal, and generate a carry output signal; the output buffer sub-circuit is configured to receive an output buffer clock signal and generate the gate output signal; and the output buffer sub-circuit includes: a first transistor having a first source-drain terminal configured to receive the output buffer clock signal and having a second source-drain terminal at which the gate output signal is generated, a second transistor having a first source-drain terminal coupled to the second source-drain terminal of the first transistor and having a second source-drain terminal coupled to the power supply line, a third transistor having a first source-drain terminal coupled to the gate terminal of the second transistor, a second source-drain terminal coupled to a node in the shift register sub-circuit, and a gate terminal configured to receive the second shift register clock signal or coupled to the power supply line, and a capacitor having a first terminal coupled to the gate terminal of the second transistor and having a second terminal configured to receive the first shift register clock signal or the second shift register clock signal.

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