Instruction processing method and device, processor and computer equipment

Abstract

The embodiment of the invention discloses an instruction processing method and device, a processor and computer equipment, and the method comprises the steps: reading a target instruction, querying a prediction state of the target instruction, predicting and generating a prediction validity mark of the target instruction in response to a result of the target instruction, and generating a prediction validity mark of the target instruction in response to the prediction validity mark of the target instruction. And querying a predicted value of the target instruction, and before the target instruction is executed, sending a wake-up signal to wake up a to-be-executed instruction depending on the target instruction to be executed according to the predicted value. Therefore, according to the embodiment of the invention, the prediction value of the target instruction can be acquired before the target instruction is executed, and the to-be-executed instruction depending on the target instruction is awakened to be executed, so that the execution delay influence of the target instruction is effectively reduced.

Description

Technical Field

[0001] The present invention relates to the field of computer technologies, and more particularly, to an instruction processing method, apparatus, processor, and computer device. Background Art

[0002] In a computer architecture, a processor can improve instruction-level parallelism and thus enhance processor performance by simultaneously issuing and executing multiple instructions. However, data dependencies between instructions significantly limit the development of instruction-level parallelism, and the relatively long latency of instructions (such as Load instructions) is particularly obvious. Therefore, how to optimize the latency of instructions has become the focus explored by the academic and industrial communities. Summary of the Invention

[0003] In view of this, embodiments of the present invention provide an instruction processing method, apparatus, processor, and computer device, which effectively reduce the impact of the execution latency of a target instruction by obtaining a predicted value of the target instruction and waking up pending instructions dependent on the target instruction for execution before the target instruction is executed.

[0004] In a first aspect, an embodiment of the present invention provides an instruction processing method, the method comprising:

[0005] Reading a target instruction;

[0006] Querying a predicted status of the target instruction;

[0007] In response to the result of the target instruction being predictable, generating a prediction validity flag for the target instruction;

[0008] In response to the target instruction having a prediction validity flag, querying a predicted value of the target instruction;

[0009] Before the target instruction is executed, sending a wake-up signal to wake up pending instructions dependent on the target instruction to execute according to the predicted value.

[0010] Further, the method further comprises:

[0011] Executing the target instruction to obtain a true value of the target instruction;

[0012] Comparing the predicted value and the true value of the target instruction;

[0013] In response to the predicted value and the true value of the target instruction being the same, sending an instruction execution completion signal;

[0014] In response to the predicted value and the true value of the target instruction being different, sending a cancellation signal to cancel the execution results of executed instructions directly or indirectly dependent on the target instruction.

[0015] Further, the method further includes:

[0016] In response to a difference between a predicted value and an actual value of the target instruction, updating the predicted value of the target instruction according to the actual value.

[0017] Further, the querying the predicted state of the target instruction includes:

[0018] Querying a prediction value table or a prediction model according to a program counter of the target instruction to obtain the predicted state of the target instruction.

[0019] Further, the method further includes:

[0020] Performing a decoding operation on the target instruction;

[0021] Performing a renaming operation on the decoded target instruction;

[0022] Performing a dispatching operation on the renamed target instruction to send the target instruction to a corresponding execution queue;

[0023] Performing a launching operation on the target instruction in the execution queue to send the target instruction from the execution queue to a corresponding instruction execution unit;

[0024] Wherein, if the result of the target instruction is predictable, the target instruction performing the renaming operation, the dispatching operation, and the launching operation carries a prediction validity flag.

[0025] Further, the querying the predicted value of the target instruction in response to the target instruction having a prediction validity flag includes:

[0026] In response to the target instruction entering a launching stage and performing a corresponding launching operation, querying whether the target instruction carries a corresponding prediction validity flag;

[0027] In response to the target instruction carrying the corresponding prediction validity flag, querying a prediction value table or a prediction model according to a program counter of the target instruction to obtain the predicted value of the target instruction.

[0028] In a second aspect, an embodiment of the present invention provides an instruction processing apparatus, where the instruction processing apparatus includes:

[0029] An instruction reading unit configured to read a target instruction;

[0030] A state querying unit configured to query the predicted state of the target instruction, and generate a prediction validity flag for the target instruction in response to the result of the target instruction being predictable;

[0031] A predicted value query unit, configured to query the predicted value of the target instruction in response to the target instruction having a prediction validity flag;

[0032] A wake-up signal sending unit, configured to send a wake-up signal before the target instruction is executed, so as to wake up the to-be-executed instruction dependent on the target instruction to execute according to the predicted value.

[0033] Further, the device further includes:

[0034] An instruction execution unit, configured to execute the target instruction and obtain the true value of the target instruction;

[0035] A comparison unit, configured to compare the predicted value and the true value of the target instruction, and send an instruction execution completion signal in response to the predicted value and the true value of the target instruction being the same, and send a cancellation signal in response to the predicted value and the true value of the target instruction being different, so as to cancel the execution result of the executed instruction directly or indirectly dependent on the target instruction.

[0036] Further, the device further includes:

[0037] A decoding unit, configured to perform a decoding operation on the target instruction;

[0038] A renaming unit, configured to perform a renaming operation on the decoded target instruction;

[0039] A dispatching unit, configured to perform a dispatching operation on the renamed target instruction to send the target instruction to a corresponding execution queue;

[0040] An issuing unit, configured to perform an issuing operation on the target instruction in the execution queue to send the target instruction from the execution queue to a corresponding instruction execution unit;

[0041] Wherein, if the result of the target instruction is predictable, the target instruction performing the renaming operation, the dispatching operation, and the issuing operation carries a prediction validity flag.

[0042] In a third aspect, an embodiment of the present invention provides a processor, where the processor includes at least one processing core, and the processing core is configured to execute the method as described above.

[0043] In a fourth aspect, an embodiment of the present invention provides a computer device, including a memory and a processor, where the memory is used to store one or more computer program instructions, and wherein the one or more computer program instructions are executed by the processor to implement the method as described above.

[0044] Fifth aspect, an embodiment of the present invention provides a computer-readable storage medium, in which a computer program is stored, and when the computer program is executed by a processor, the method described above is implemented.

[0045] Sixth aspect, an embodiment of the present invention provides a computer program product, when the computer program product runs on a computer, the computer is enabled to execute the method described above.

[0046] In the embodiment of the present invention, by reading a target instruction, querying the prediction status of the target instruction, in response to the result of the target instruction being predictable, generating a prediction validity flag for the target instruction, in response to the target instruction having a prediction validity flag, querying the predicted value of the target instruction, before the target instruction is executed, sending a wake-up signal to wake up a to-be-executed instruction that depends on the target instruction to execute according to the predicted value. Thus, the embodiment of the present invention can obtain the predicted value of the target instruction before the target instruction is executed and wake up the to-be-executed instruction that depends on the target instruction to execute, effectively reducing the impact of the execution delay of the target instruction, while reducing the design complexity and optimizing the processor energy consumption ratio. Description of the Drawings

[0047] Through the following description of the embodiments of the present invention with reference to the drawings, the above and other objects, features, and advantages of the present invention will become clearer. In the drawings:

[0048] Figure 1 is a flowchart of an instruction processing method according to an embodiment of the present invention;

[0049] Figure 2 is a flowchart of another instruction processing method according to an embodiment of the present invention;

[0050] Figure 3 is a schematic diagram of an instruction processing process according to an embodiment of the present invention;

[0051] Figure 4 is a schematic diagram of an instruction processing device according to an embodiment of the present invention;

[0052] Figure 5 is a schematic diagram of a computer device according to an embodiment of the present invention. Detailed Embodiments

[0053] The following describes the present application based on embodiments, but the present application is not limited to these embodiments. In the following detailed description of the present application, some specific details are described in detail. Those skilled in the art can fully understand the present application without the description of these details. In order to avoid obscuring the essence of the present application, well-known methods, processes, flows, elements, and circuits are not described in detail.

[0054] In addition, those of ordinary skill in the art should understand that the accompanying drawings provided herein are for illustrative purposes only and are not necessarily drawn to scale.

[0055] Unless the context clearly requires otherwise, words such as "including" and "comprising" in the entire application document should be construed in an inclusive sense rather than an exclusive or exhaustive sense; that is, it means "including but not limited to".

[0056] In the description of this application, it should be understood that terms such as "first" and "second" are only used for descriptive purposes and cannot be construed as indicating or implying relative importance. In addition, in the description of this application, unless otherwise specified, the meaning of "a plurality" is two or more.

[0057] For the solutions described in this specification and the embodiments, if they involve personal information processing, they will be processed on the premise of having a legal basis (such as obtaining the consent of the personal information subject, or being necessary for performing a contract, etc.), and will only be processed within the specified or agreed scope. If the user refuses to process personal information other than the necessary information required for the basic functions, it will not affect the user's use of the basic functions.

[0058] Figure 1 It is a flowchart of the instruction processing method of the embodiment of the present invention. As Figure 1 shown, the instruction processing method of the embodiment of the present invention includes the following steps:

[0059] Step S110, read the target instruction. In this embodiment, after the processor or the processing core in the processor receives the instruction to be processed, the instruction to be processed is stored in the memory or the instruction cache, and the processor or the processing core in the processor reads the next batch of instructions to be processed from the memory or the instruction cache in the fetch stage.

[0060] Further, the target instruction of this embodiment can be a data loading instruction (i.e., Load instruction) read from the memory or the instruction cache, or other instructions executable by the processor. This embodiment does not limit this. Among them, the Load instruction is used to load data from the memory into the corresponding register.

[0061] Step S120, query the prediction status of the target instruction. The processor of this embodiment pre-stores a value prediction table (Value Prediction Table, VPT) or a prediction model, and the value prediction table or the prediction model can be determined according to the execution of historical corresponding instructions.

[0062] Optionally, this embodiment may record the correspondence between historical corresponding instructions of the same instruction type and their execution results to obtain a prediction value table. In another alternative implementation, this embodiment may construct a prediction model based on historical corresponding instructions of the same instruction type and their execution results, and predict the execution results corresponding to each instruction based on this prediction model to form a prediction value table. Further, after constructing a prediction model according to historical corresponding instructions of the same instruction type and their execution results, when reading a new instruction of the same type, this embodiment may use this prediction model to determine whether the execution result of the currently read target instruction can be predicted. This embodiment does not limit the method of querying and obtaining the prediction status of the target instruction.

[0063] In an alternative implementation, this embodiment constructs a prediction value table or a prediction model according to historical corresponding instructions, their corresponding program counters (PCs), and execution results. Further, this embodiment queries the prediction value table or the prediction model according to the program counter of the target instruction to obtain the prediction status of the target instruction. The PC is an important register in the processor, mainly used to store the memory address of the next instruction to be executed.

[0064] Further, this embodiment may use a hash function to implement the mapping between the PC and the prediction value to obtain the corresponding prediction value table. It should be understood that this embodiment does not limit the mapping method of the prediction value table, as long as it can implement querying the prediction status of the corresponding instruction through the PC, and no further examples will be given here.

[0065] Step S130, in response to the predictability of the result of the target instruction, generate a prediction validity flag for the target instruction.

[0066] Further, this embodiment determines whether the execution result of the target instruction can be predicted based on a pre-determined prediction value table or prediction model. If the execution result of the target instruction can be predicted, it indicates that the result of the target instruction is predictable, and a prediction validity flag (predicate enable) for the target instruction is generated. That is, this embodiment uses the prediction validity flag to indicate that the execution result of the target instruction can be predicted.

[0067] Further, in this embodiment, if the result of the target instruction is unpredictable, the pending instructions dependent on the target instruction are woken up after the execution of the instruction pipeline of the target instruction, so as to execute the pending instructions dependent on the target instruction based on the actual execution result of the target instruction.

[0068] Further, the pipeline for the processor or the processing core in the processor to process instructions may include a fetch stage, a decode stage, a rename stage, a dispatch stage, an issue stage, an execute stage, and a commit stage. Among them, the fetch stage may also perform a fetch operation to read instructions from memory or the instruction cache. The decode stage is to perform a decode operation on the instructions to translate the read instructions into micro-operations that the processor or the processing core can execute. The rename stage is to perform a rename operation on the decoded instructions to avoid register dependencies between instructions, thereby avoiding data conflicts. Among them, in the rename stage, the logical register corresponding to the target instruction will be mapped to a corresponding set of physical registers. The dispatch stage is to perform a dispatch operation on the renamed instructions to send the renamed instructions to the corresponding execution queue. The issue stage is to perform an issue operation on the instructions in the execution queue to send the corresponding prepared instructions from the execution queue to the corresponding execution unit. The execute stage is to control the execution unit to execute the corresponding instructions to implement the actual arithmetic operations corresponding to the instructions. The commit stage is the last stage in the instruction execution pipeline, which is used to write the instruction execution result into the target register or memory, which determines whether the instruction execution result finally takes effect. It should be understood that the above stages of the pipeline are merely exemplary, and the pipeline for processing instructions can be customized based on the differences of the processor or the processing core, and will not be exemplified one by one here.

[0069] Further, after reading the target instruction and querying the predicted state of the target instruction in this embodiment, the decoding operation is continued on the target instruction, and the rename operation is performed on the decoded target instruction, and the dispatch operation is performed on the renamed target instruction to send the target instruction to the corresponding execution queue, and the issue operation is performed on the prepared target instruction in the execution queue to send the target instruction from the execution queue to the corresponding execution unit.

[0070] Among them, if the result of the target instruction is predictable, the rename operation, dispatch operation, and issue operation in the target instruction execution pipeline carry a prediction validity flag. If the result of the target instruction is unpredictable, the rename operation, dispatch operation, issue operation, execution operation, and commit operation are sequentially performed according to the normal instruction execution pipeline to complete the instruction execution.

[0071] Step S140, in response to the target instruction having a prediction validity flag, query the predicted value of the target instruction.

[0072] In an alternative implementation, in the issue stage before the execution stage of the target instruction, this embodiment queries whether the target instruction carries a corresponding prediction validity flag. Further, in response to the target instruction entering the issue stage and performing the corresponding issue operation, this embodiment queries whether the target instruction carries a corresponding prediction validity flag. In response to the target instruction carrying the corresponding prediction validity flag, it queries the prediction value table or prediction model according to the program counter of the target instruction to obtain the prediction value of the target instruction. It should be understood that due to certain differences that may exist in different processors or the instruction execution pipelines of processors, this embodiment does not limit the operation stage for querying the prediction value of the target instruction, as long as it is before the instruction execution stage.

[0073] Further, if the target instruction does not carry a prediction validity flag, it indicates that the result of the target instruction is unpredictable. In this embodiment, the target instruction is sent from the execution queue to the corresponding execution unit, and then the execution unit is controlled to perform the actual arithmetic operation corresponding to the target instruction. After the execution result is submitted, the pending instructions that depend on the target instruction are woken up to execute based on the corresponding actual execution result.

[0074] Step S150, before the target instruction is executed, a wake-up signal is sent to wake up the pending instructions that depend on the target instruction to execute according to the prediction value.

[0075] Further, after this embodiment queries the prediction value of the target instruction and before the target instruction is executed, a wake-up signal is sent to wake up the pending instructions that depend on the target instruction to execute according to the prediction value of the target instruction. Further optionally, if this embodiment queries and obtains the prediction value of the target instruction in the issue stage of the target instruction, a wake-up signal can be sent after the issue stage and before the execution stage of the target instruction to wake up the pending instructions that depend on the target instruction to execute according to the prediction value of the target instruction. As described above, due to certain differences that may exist in the pipelines of processors or processing cores, this embodiment can determine the operation stage for querying the prediction value of the target instruction based on the actual application situation. Furthermore, the timing for this embodiment to send the wake-up signal is after obtaining the prediction value of the target instruction and before the execution stage of the target instruction. This embodiment does not limit the specific wake-up timing of the wake-up signal.

[0076] In the embodiment of the present invention, it is determined in the instruction fetch stage whether the execution result of the target instruction can be predicted. When the result of the target instruction is predictable, the target instruction is made to carry a prediction validity flag to proceed with the subsequent processes of the pipeline. Then, in the issue stage before the instruction execution stage, it is determined whether the target instruction carries a prediction validity flag to determine whether other pending instructions that depend on the target instruction can be instruction-dependent in advance. After it is determined in the issue stage of the target instruction that the target instruction carries a prediction validity flag, a wake-up signal is sent before the target instruction enters the execution stage to wake up the pending instructions that depend on the target instruction to execute according to the predicted value. Thus, in the instruction fetch stage of the present invention, it is queried whether the execution result of the target instruction is predicted, and the predicted value of the target instruction is not obtained until the issue stage before the execution stage, and the predicted value of the target instruction is obtained based on the program counter. This enables this embodiment to avoid the transfer and storage of the predicted value of the target instruction in stages such as the decoding stage, the renaming stage, the dispatch stage, and the issue stage. This reduces the design complexity of the chip. While ensuring relatively low chip area and power consumption, it realizes the function of pre-executing the pending instructions that depend on the target instruction through the predicted value before the target instruction is executed, effectively reducing the impact of the execution delay of the target instruction.

[0077] Figure 2 It is a flowchart of another instruction processing method according to an embodiment of the present invention. The instruction processing method of this embodiment is a processing process after the target instruction enters the execution stage. In an optional implementation manner, as Figure 2 shown, after the target instruction of this embodiment enters the execution stage, it includes the following execution steps:

[0078] Step S210, execute the target instruction and obtain the true value of the target instruction. For example, if the target instruction is a Load instruction, then executing the target instruction means loading the corresponding data, and the true value of the target instruction is the loaded data.

[0079] Step S220, compare the predicted value and the true value of the target instruction.

[0080] Step S230, determine whether the predicted value and the true value of the target instruction are the same. If they are the same, execute step S240. If they are different, execute step S250.

[0081] Step S240: In response to the predicted value and the true value of the target instruction being the same, send an instruction execution completion signal. In this embodiment, since the execution of other instructions that are directly or indirectly dependent on the target instruction and are awakened based on the wake-up signal is based on the predicted value of the target instruction, and there may be an error in the predicted value of the target instruction. Therefore, even if other instructions that are directly or indirectly dependent on the target instruction have been executed based on the predicted value of the target instruction, it is necessary to delay sending the completion signal, that is, delay submission, until it is determined that the predicted value and the true value of the target instruction are the same. At this time, it is determined that the execution results of the instructions that depend on or are indirectly dependent on the predicted value of the target instruction are also accurate. Therefore, after it is determined that the predicted value and the true value of the target instruction are the same, a completion signal can be sent to submit the target instruction and the execution results of the instructions that depend on or are indirectly dependent on the target instruction and have been executed.

[0082] Step S250: In response to the predicted value and the true value of the target instruction being different, send a cancel signal (cancel signal) to cancel the execution results of the instructions that are directly or indirectly dependent on the target instruction and have been executed. That is to say, if the predicted value and the true value of the target instruction are different, since the execution of other instructions that are directly or indirectly dependent on the target instruction and are awakened based on the wake-up signal is based on the predicted value of the target instruction, the execution results of the instructions that depend on or are indirectly dependent on the predicted value of the target instruction are also incorrect. It is necessary to cancel the execution results of the instructions that depend on or are indirectly dependent on the predicted value of the target instruction. For example, clear the data in the write register or cache corresponding to the instructions that are directly or indirectly dependent on the target instruction and have been executed, cancel the outstanding memory requests, update the rename table (that is, release or reset the physical registers allocated to the instructions that are directly or indirectly dependent on the target instruction and have been executed), and the program counter, etc. Thus, in this embodiment, when the predicted value of the target instruction is predicted incorrectly, a cancel signal is used to cancel the instructions that are directly or indirectly dependent on the target instruction and have been executed, without the need to empty all the instructions or data in the entire pipeline of the processor, simplifying the chip design complexity and at the same time optimizing the energy consumption ratio of the processor.

[0083] In an alternative implementation, the instruction processing method of this embodiment further includes: Step S260: In response to the predicted value and the true value of the target instruction being different, update the predicted value of the target instruction according to the true value of the target instruction. It should be understood that this embodiment does not limit the execution order of Step S250 and Step S260.

[0084] Further, when the prediction of the target instruction is incorrect in this embodiment, a reset process (i.e., the repick operation) is triggered to cancel the influence of the incorrect prediction and update the prediction value table or the prediction model to reflect the new correct information of the target instruction, that is, to update the prediction value table or the prediction model according to the true value of the target instruction to improve the prediction accuracy of the future prediction value of the target instruction. Further, the repick operation process of this embodiment may include pipeline rollback (i.e., canceling the operations of the executed instructions that directly or indirectly depend on the target instruction), renaming table update, and program counter restoration, so as to re-fetch instructions based on the restored program counter and restart the speculative execution of the target instruction based on the updated prediction value table or prediction model, thereby ensuring the accuracy and performance of the instruction processing program of the processor or processing core.

[0085] In the embodiment of the present invention, by reading a target instruction, querying the prediction status of the target instruction, generating a prediction validity flag of the target instruction in response to the predictability of the result of the target instruction, querying the predicted value of the target instruction in response to the target instruction having a prediction validity flag, and sending a wake-up signal before the target instruction is executed to wake up the to-be-executed instructions that depend on the target instruction to execute according to the predicted value. Thus, the embodiment of the present invention can effectively reduce the influence of the execution delay of the target instruction by obtaining the predicted value of the target instruction and waking up the to-be-executed instructions that depend on the target instruction to execute before the target instruction is executed, while reducing the design complexity and optimizing the energy consumption ratio of the processor.

[0086] Figure 3 It is a schematic diagram of the instruction processing process in the embodiment of the present invention. This embodiment takes the instruction execution pipeline including an instruction fetch stage, a decoding stage, a renaming stage, a dispatch stage, an issue stage, an execution stage, and a commit stage as an example for illustration. It should be understood that this embodiment is not limited thereto, and it can be adaptively adjusted and configured according to the pipeline stages of the actual processor or processing core. As Figure 3As shown, in this embodiment, during the instruction fetch stage, the target instruction is read from the memory or the instruction cache, and the prediction value table or the prediction model VPT is queried based on the PC value corresponding to the target instruction to determine the prediction status of the target instruction. At the same time, the read target instruction is decoded in the decoding stage, and the decoded target instruction is obtained and enters the rename stage to rename the decoded target instruction. Moreover, if the result of the target instruction is predictable, the prediction value table or the prediction model VPT feeds back a prediction validity flag in the rename stage. At this time, this embodiment passes the prediction validity flag of the target instruction along with the target instruction in the subsequent pipeline. Further, after passing through the rename stage, the target instruction with a predictable result is passed to the dispatch stage with the prediction validity flag to perform the dispatch operation, and then enters the issue stage to perform the issue operation to send the target instruction to the corresponding execution unit. Since the target instruction enters the execution stage after the issue stage, if the result of the target instruction is predictable, this embodiment needs to wake up the pending instructions dependent on the target instruction to be executed before the target instruction enters the execution stage for execution, so as to execute the pending instructions dependent on the target instruction in advance, thereby effectively reducing the impact of the execution delay of the target instruction. However, executing the pending instructions dependent on the target instruction requires the execution result of the target instruction. Therefore, this embodiment determines whether the target instruction carries a prediction validity flag in the issue stage. If it is determined that the target instruction carries a prediction validity flag, the prediction value table or the prediction model VPT is queried based on the PC value corresponding to the target instruction to obtain the prediction value of the target instruction. Furthermore, before the target instruction enters the execution stage, the pending instructions dependent on the target instruction are woken up through a wake-up signal, so that the pending instructions dependent on the target instruction can be executed in advance based on the prediction value of the target instruction, realizing the function of effectively reducing the impact of the execution delay of the target instruction.

[0087] Furthermore, after the target instruction is executed in the execution stage, the true value of the target instruction is obtained. This embodiment compares the prediction value and the true value of the target instruction in the comparison stage. If the prediction value and the true value of the target instruction are the same, a completion signal is sent to commit the execution results of the target instruction and the executed instructions directly or indirectly dependent on the target instruction. If the prediction value and the true value of the target instruction are different, a cancellation signal is sent to revoke the execution results of the executed instructions directly or indirectly dependent on the target instruction executed based on the prediction value of the target instruction, and the prediction value table or the prediction model VPT is updated based on the true value of the target instruction, and enters the repick operation to ensure the accuracy and performance of the instruction processing program of the processor or the processing core.

[0088] In the embodiment of the present invention, it is determined in the instruction fetch stage whether the execution result of the target instruction can be predicted. When the result of the target instruction is predictable, the target instruction is made to carry a prediction validity flag to proceed with the subsequent processes of the pipeline. Then, in the issue stage before the instruction execution stage, it is determined whether the target instruction carries a prediction validity flag to determine whether other pending instructions that depend on the target instruction can be instruction-dependent in advance. After it is determined in the issue stage of the target instruction that the target instruction carries a prediction validity flag, a wake-up signal is sent before the target instruction enters the execution stage to wake up the pending instructions that depend on the target instruction to execute according to the predicted value. Thus, in the instruction fetch stage of the present invention, it is queried whether the execution result of the target instruction is predicted, and the predicted value of the target instruction is not obtained until the issue stage before the execution stage, and the predicted value of the target instruction is obtained based on the program counter. This enables this embodiment to avoid the transmission and storage of the predicted value of the target instruction in stages such as the decoding stage, the renaming stage, the dispatch stage, and the issue stage, which reduces the design complexity of the chip. While ensuring that the chip area and power consumption are relatively low, it realizes the function of pre-executing the pending instructions that depend on the target instruction through the predicted value before the target instruction is executed, effectively reducing the impact of the execution delay of the target instruction. At the same time, in this embodiment, when the predicted value of the target instruction is predicted incorrectly, a cancellation signal is used to cancel the executed instructions that directly or indirectly depend on the target instruction, without having to clear all the instructions or data in the entire pipeline of the processor, which simplifies the chip design complexity and optimizes the energy consumption ratio of the processor.

[0089] Figure 4 is a schematic diagram of the instruction processing device according to an embodiment of the present invention. As Figure 4 shown, the instruction processing device 4 of this embodiment includes an instruction fetch unit 41, a status query unit 42, a predicted value query unit 43, and a wake-up signal sending unit 44.

[0090] The instruction fetch unit 41 is configured to fetch the target instruction. The status query unit 42 is configured to query the prediction status of the target instruction and generate a prediction validity flag for the target instruction in response to the result of the target instruction being predictable. The predicted value query unit 43 is configured to query the predicted value of the target instruction in response to the target instruction having a prediction validity flag. The wake-up signal sending unit 44 is configured to send a wake-up signal before the target instruction is executed to wake up the pending instructions that depend on the target instruction to execute according to the predicted value.

[0091] In an alternative implementation, the instruction processing device 4 further includes an instruction execution unit and a comparison unit. The instruction execution unit is configured to execute the target instruction and obtain the true value of the target instruction. The comparison unit is configured to compare the predicted value and the true value of the target instruction. In response to the predicted value and the true value of the target instruction being the same, an instruction execution completion signal is sent. In response to the predicted value and the true value of the target instruction being different, a cancellation signal is sent to cancel the execution results of the executed instructions that directly or indirectly depend on the target instruction.

[0092] In an alternative implementation, the instruction processing device 4 further includes a decoding unit, a renaming unit, a dispatching unit, and a launching unit. The decoding unit is configured to perform a decoding operation on the target instruction. The renaming unit is configured to perform a renaming operation on the decoded target instruction. The dispatching unit is configured to perform a dispatching operation on the renamed target instruction to send the target instruction to the corresponding execution queue. The launching unit is configured to perform a launching operation on the target instruction in the execution queue to send the target instruction from the execution queue to the corresponding instruction execution unit. Among them, if the result of the target instruction is predictable, the target instruction for performing the renaming operation, the dispatching operation, and the launching operation carries a prediction validity flag.

[0093] In an alternative implementation, the comparison unit is further configured to update the predicted value of the target instruction according to the true value in response to the predicted value and the true value of the target instruction being different.

[0094] In an alternative implementation, the status query unit 42 is further configured to query a prediction value table or a prediction model according to the program counter of the target instruction to obtain the prediction status of the target instruction.

[0095] In an alternative implementation, the predicted value query unit 43 is further configured to query whether the target instruction carries a corresponding prediction validity flag in response to the target instruction entering the launch stage and performing a corresponding launch operation. In response to the target instruction carrying the corresponding prediction validity flag, a prediction value table or a prediction model is queried according to the program counter of the target instruction to obtain the predicted value of the target instruction.

[0096] It should be understood that each unit in the instruction processing device of this embodiment can be a circuit module implemented by hardware or a virtual logic processing unit. This embodiment does not limit the actual implementation manner of each unit in the processor or processing core, and it can be designed according to the actual situation.

[0097] In an embodiment of the present invention, by reading a target instruction, querying the prediction status of the target instruction, generating a prediction validity flag of the target instruction in response to the result of the target instruction being predictable, querying the predicted value of the target instruction in response to the target instruction having a prediction validity flag, and sending a wake-up signal before the target instruction is executed to wake up a to-be-executed instruction dependent on the target instruction to execute according to the predicted value. Thus, the embodiment of the present invention can obtain the predicted value of the target instruction and wake up the to-be-executed instruction dependent on the target instruction to execute before the target instruction is executed, effectively reducing the impact of the execution delay of the target instruction, while reducing the design complexity and optimizing the processor energy consumption ratio.

[0098] Another embodiment of the present application relates to a processor, which includes at least one processing core configured to execute any one of the instruction processing methods as described above. Further, the processing core of this embodiment can implement any one of the above instruction processing methods by deploying the above instruction processing device.

[0099] Figure 5 It is a schematic diagram of a computer device according to an embodiment of the present invention. In this embodiment, the computer device 5 includes a server, a terminal, etc. As Figure 5 shown, the computer device 5: includes at least one processor 51; and, a memory 52 communicatively connected to at least one processor 51; and, a communication component 53 communicatively connected to a scanning device, and the communication component 53 receives and sends data under the control of the processor 51; wherein, the memory 52 stores instructions executable by at least one processor 51, and the instructions are executed by at least one processor 51 to implement the above instruction processing method.

[0100] Specifically, the computer device includes: one or more processors 51 and a memory 52, Figure 5 taking one processor 51 as an example. The processor 51 and the memory 52 can be connected by a bus or other means, Figure 5 taking the connection by a bus as an example. The memory 52, as a non-volatile computer-readable storage medium, can be used to store non-volatile software programs, non-volatile computer-executable programs, and modules. The processor 51 executes various functional applications and data processing of the device by running the non-volatile software programs, instructions, and modules stored in the memory 52, that is, implements the above instruction processing method.

[0101] The memory 52 may include a program storage area and a data storage area. Among them, the program storage area can store an operating system and application programs required for at least one function; the data storage area can store an option list and the like. In addition, the memory 52 may include a high-speed random access memory, and may also include a non-volatile memory, such as at least one magnetic disk storage device, a flash memory device, or other non-volatile solid-state storage devices. In some embodiments, the memory 52 may optionally include a memory remotely provided relative to the processor 51, and these remote memories can be connected to an external device through a network. Examples of the above network include but are not limited to the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0102] One or more modules are stored in the memory 52 and, when executed by one or more processors 51, execute the instruction processing method in any of the above method embodiments.

[0103] The above product can execute the method provided in the embodiments of the present application, and has corresponding functional modules and beneficial effects for executing the method. For technical details not described in detail in this embodiment, reference can be made to the method provided in the embodiments of the present application.

[0104] In the embodiment of the present invention, by reading a target instruction, querying the predicted state of the target instruction, generating a predicted validity flag of the target instruction in response to the result of the target instruction being predictable, querying the predicted value of the target instruction in response to the target instruction having a predicted validity flag, and sending a wake-up signal before the target instruction is executed to wake up a to-be-executed instruction dependent on the target instruction to execute according to the predicted value. Thus, the embodiment of the present invention can obtain the predicted value of the target instruction and wake up the to-be-executed instruction dependent on the target instruction to execute before the target instruction is executed, effectively reducing the impact of the execution delay of the target instruction, while reducing the design complexity and optimizing the processor energy consumption ratio.

[0105] Another embodiment of the present invention relates to a non-volatile storage medium for storing a computer-readable program, and the computer-readable program is used for a computer to execute the above partial or all method embodiments.

[0106] That is, those skilled in the art can understand that all or part of the steps in the methods of the above embodiments can be completed by instructing relevant hardware through a program. The program is stored in a storage medium, including several instructions to enable a device (which can be a single-chip microcomputer, a chip, etc.) or a processor to execute all or part of the steps of the methods described in the embodiments of the present application. The foregoing storage medium includes: various media that can store program codes, such as USB flash drives, mobile hard disks, read-only memories (ROM, Read-Only Memory), random access memories (RAM, Random Access Memory), magnetic disks, or optical discs.

[0107] The foregoing are only the preferred embodiments of the present application and are not used to limit the present application. For those skilled in the art, various modifications and changes can be made to the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A command processing method, characterized in that: The method comprises: Read the target instruction; querying a predicted state of the target instruction; In response to the result of the target instruction being predictable, generating a prediction validity flag of the target instruction; In response to the target instruction having a prediction validity flag, querying a prediction value of the target instruction; Before the target instruction is executed, a wake-up signal is sent to wake up the to-be-executed instructions that depend on the target instruction to be executed according to the prediction value.

2. The method according to claim 1, characterized in that: The method further comprises: Execute the target instruction to obtain the real value of the target instruction; comparing the predicted value and the actual value of the target instruction; In response to the predicted value and the actual value of the target instruction being the same, sending an instruction execution completion signal; In response to the prediction value and the actual value of the target instruction being different, a cancel signal is sent to cancel the execution result of the executed instruction that directly or indirectly depends on the target instruction.

3. The method according to claim 2, characterized in that The method further comprises: In response to the predicted value and the actual value of the target instruction being different, the predicted value of the target instruction is updated according to the actual value.

4. The method according to claim 1, characterized in that: The querying of the predicted state of the target instruction includes: A prediction value table or a prediction model is queried according to the program counter of the target instruction to obtain the prediction status of the target instruction.

5. The method according to claim 1, characterized in that The method further comprises: Performing a decoding operation on the target instruction; Performing a renaming operation on the decoded target instruction; Performing a dispatch operation on the renamed target instruction to send the target instruction to a corresponding execution queue; Performing an issue operation on the target instruction in the execution queue to send the target instruction from the execution queue to a corresponding instruction execution unit; If the result of the target instruction is predictable, the target instruction that performs the rename operation, the dispatch operation, and the issue operation carries a prediction validity flag.

6. The method according to claim 1, characterized in that In response to the target instruction having a prediction validity flag, querying the prediction value of the target instruction includes: In response to the target instruction entering the emission phase to perform a corresponding emission operation, querying whether the target instruction carries a corresponding prediction validity flag; In response to the target instruction carrying the corresponding prediction validity flag, a prediction value table or a prediction model is queried according to the program counter of the target instruction to obtain the prediction value of the target instruction.

7. An instruction processing device, characterized in that: The instruction processing device comprises: An instruction reading unit configured to read a target instruction; a state query unit configured to query the prediction state of the target instruction, and generate a prediction validity flag of the target instruction in response to the result of the target instruction being predictable; a prediction value query unit, configured to query a prediction value of the target instruction in response to the target instruction having a prediction validity flag; The wake-up signal sending unit is configured to send a wake-up signal before the target instruction is executed, so as to wake up the to-be-executed instruction that depends on the target instruction to be executed according to the predicted value.

8. The device according to claim 7, characterized in that The device also includes: An instruction execution unit, configured to execute the target instruction and obtain a real value of the target instruction; A comparison unit is configured to compare the predicted value and the actual value of the target instruction, and in response to the predicted value and the actual value of the target instruction being the same, send an instruction execution completion signal; in response to the predicted value and the actual value of the target instruction being different, send a cancellation signal to cancel the execution result of the executed instruction that directly or indirectly depends on the target instruction.

9. The device according to claim 7, characterized in that The device also includes: A decoding unit, configured to perform a decoding operation on the target instruction; a renaming unit configured to perform a renaming operation on the decoded target instruction; a dispatch unit configured to perform a dispatch operation on the renamed target instruction to send the target instruction to a corresponding execution queue; an issuing unit, configured to perform an issuing operation on the target instruction in the execution queue, so as to send the target instruction from the execution queue to a corresponding instruction execution unit; If the result of the target instruction is predictable, the target instruction that performs the rename operation, the dispatch operation, and the issue operation carries a prediction validity flag.

10. A processor, comprising at least one processing core, characterized in that: The processing core is configured to execute the method according to any one of claims 1-6.

11. A computer device comprising a memory and a processor, characterized in that: The memory is used to store one or more computer program instructions, wherein the one or more computer program instructions are executed by the processor to implement the method according to any one of claims 1 to 6.

12. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the method according to any one of claims 1 to 6 is implemented.

13. A computer program product, characterized in that When the computer program product is run on a computer, the computer is caused to execute the method according to any one of claims 1 to 6.

Images