Data processing method and device based on multi-core processor, equipment and medium

Abstract

The embodiment of the invention provides a data processing method and device based on a multi-core processor, equipment and a medium. The design of a directory, an address table item, a transaction table item and a data table item is introduced in the process of processing a request message initiated by any core of the multi-core processor; the efficiency of processing the request message and the related affairs and maintaining the cache consistency among the plurality of cores is effectively improved, and the cost and the overhead of maintaining the cache consistency are reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of computer processors, and particularly to a data processing method, apparatus, device, and medium based on a multi-core processor. Background Art

[0002] In the multi-core on-chip network (Multi-Core System-on-Chip, MCSoC) communication architecture of a multi-core processor, each core can act as a request node (Request Node, RN) to send a request message to the home node (Home Node, HN) to request the home node to process a transaction. The home node is responsible for scheduling and processing the message and the transaction corresponding to the message. During this process, each core stores a cache corresponding to the memory, which can improve the data access speed. However, if the data cached by each core is inconsistent, it may cause problems such as data competition, resource conflict, and even program running errors. Therefore, the home node also needs to be responsible for maintaining cache consistency among multiple cores.

[0003] However, with the increase in the number of cores and the complexity of business logic, the number of request messages sent by the cores has increased accordingly. In order to maintain cache consistency among the cores, the home node needs to perform frequent message passing and data synchronization. These processes will extend the response time and increase power consumption. If the home node is not properly processed, it may also lead to a data access bottleneck, and even affect the performance and efficiency of the entire system. Summary of the Invention

[0004] In view of the above problems, a data processing method, apparatus, device, and medium for a multi-core processor are provided to overcome or at least partially solve the above problems, including:

[0005] A data processing method based on a multi-core processor, the method includes:

[0006] Obtain a target cache address corresponding to a request message sent by any core;

[0007] Determine the address status of the target cache address according to a preset address entry; wherein, the address entry stores multiple cache addresses and the address status of each cache address;

[0008] When the address status of the target cache address indicates that the target cache address is not occupied, query in a preset directory according to the target cache address to obtain a query result; wherein, the directory stores multiple cache addresses and the cache status of each cache address, and the cache status includes the cache status of multiple cores for the cache address;

[0009] Based on the query result, perform message processing on the request message, and maintain cache coherence among multiple cores through pre-set transaction entries and data entries; wherein, the transaction entries are used to follow up the processing progress of the transaction corresponding to the request message and update the cache status of the target cache address in the directory, and the data entries are used to store the cache data to be written into the memory and the information corresponding to the cache data.

[0010] Optionally, the multi-core processor further includes multiple other cores except the core that sends the request message. The performing message processing on the request message according to the query result includes:

[0011] If the query result is that the cache status of the target cache address exists in the directory, determine a target core among the multiple other cores according to the cache status of the target cache address, or, if the query result is that the cache status of the target cache address does not exist in the directory, determine the multiple other cores as the target core;

[0012] Send a snooping request to the target core;

[0013] Receive the snooping response from the target core, and perform message processing on the request message according to the snooping response.

[0014] Optionally, when the address status of the target cache address indicates that the target cache address is not occupied, query in the pre-set directory according to the target cache address to obtain a query result, including:

[0015] When the address status of the target cache address indicates that the target cache address is not occupied, update the address status of the target cache address to indicate that the target cache address is occupied, and query in the pre-set directory according to the target cache address to obtain a query result;

[0016] The method further includes:

[0017] If the processing of the transaction is completed, mark the completion of the transaction processing through the transaction entry;

[0018] If the processing of writing the cache data into the memory is completed, mark the completion of writing the cache data through the data entry;

[0019] In the case where the transaction entry has marked the completion of the transaction processing and the data entry has marked the completion of writing the cache data, update the address status of the target cache address to indicate that the target cache address is not occupied;

[0020] Clear the data stored in the transaction table entry and the data table entry corresponding to the target cache address.

[0021] Optionally, it is characterized in that determining the address status of the target cache address according to the preset address table entry includes:

[0022] If the target cache address is not stored in the address table entry, store the target cache address in the address table entry and determine that the address status of the target cache address is that the target cache address is not occupied;

[0023] If the target cache address is stored in the address table entry, determine whether the target cache address is occupied according to the address status of the target cache address.

[0024] Optionally, before sending the monitoring request to the target core, it further includes:

[0025] Store the number of target cores through the transaction table entry;

[0026] Receiving the monitoring response of the target core includes:

[0027] When receiving the monitoring response of the target core, update the number of the target core in the transaction table entry.

[0028] Optionally, it is characterized in that in the process of performing message processing on the request message according to the query result and maintaining cache consistency among multiple cores through the preset transaction table entry and data table entry, the method further includes:

[0029] If there is cache data that needs to be written to memory, verify the integrity of the cache data to obtain a verification result, and store the cache data and the verification result in the data table entry;

[0030] When it is necessary to write the cache data to memory, determine the integrity of the cache data through the verification result in the data table entry;

[0031] If the verification result indicates that the cache data is complete data, write the cache data to memory through the data table entry.

[0032] Optionally, it is characterized in that the method further includes:

[0033] When the address status of the target cache address indicates that the target cache address is occupied, store the request message in the cache to suspend processing the request message.

[0034] A data processing device based on a multi-core processor, the device includes:

[0035] An address acquisition module, configured to acquire a target cache address corresponding to a request message sent by any core;

[0036] An address status determination module, configured to determine the address status of the target cache address according to a preset address entry; wherein, the address entry stores multiple cache addresses and the address status of each cache address;

[0037] A directory query module, configured to query in a preset directory according to the target cache address when the address status of the target cache address indicates that the target cache address is not occupied, and obtain a query result; wherein, the directory stores multiple cache addresses and the cache status of each cache address, and the cache status includes the cache status of multiple cores for the cache address;

[0038] A message processing module, configured to perform message processing on the request message according to the query result, and maintain cache consistency among multiple cores through preset transaction entries and data entries; wherein, the transaction entry is used to update the cache status of the target cache address in the directory and follow up the transaction process, and the data entry is used to store cache data to be written into the memory and information corresponding to the cache data.

[0039] Optionally, it includes a processor, a memory, and a computer program stored on the memory and capable of running on the processor. When the computer program is executed by the processor, the method for data processing of the multi-core processor as described above is implemented.

[0040] Optionally, a computer program is stored on the computer-readable storage medium. When the computer program is executed by a processor, the method for data processing of the multi-core processor as described above is implemented.

[0041] The embodiments of the present invention have the following advantages: The method of the embodiments of the present invention includes: obtaining a target cache address corresponding to a request message sent by any core, determining the address status of the target cache address according to a preset address entry, where the address entry stores multiple cache addresses and the address status of each cache address. When the address status of the target cache address indicates that the target cache address is not occupied, querying in a preset directory according to the target cache address to obtain a query result, where the directory stores multiple cache addresses and the cache status of each cache address, and the cache status includes the cache status of multiple cores for the cache address. According to the query result, performing message processing on the request message, and maintaining cache consistency among multiple cores through preset transaction entries and data entries, where the transaction entry is used to follow up the processing process of the transaction corresponding to the request message and update the cache status of the target cache address in the directory, and the data entry is used to store the cache data to be written into the memory and the information corresponding to the cache data. Through the query of the directory, since the directory stores multiple cache addresses and the cache status of each cache address, when the query result can confirm the cache status of the target cache address, the cache status of other cores can be quickly obtained, and the optimal processing can be performed on the request message and related transactions according to the cache status, reducing the cost and overhead of maintaining cache consistency; at the same time, through the design of the address entry, transaction entry and data entry, read-write conflicts can be effectively prevented, cache consistency among multiple cores can be efficiently maintained, and it is also convenient to track and manage the transaction corresponding to the request message. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] In order to more clearly illustrate the technical solutions of the present invention, the accompanying drawings required for the description of the present invention will be briefly introduced below. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention, and those of ordinary skill in the art can also obtain other drawings based on these drawings without creative efforts.

[0043] Figure 1 is a flowchart of the steps of a data processing method based on a multi-core processor provided by an embodiment of the present invention;

[0044] Figure 2 is an architecture diagram of a multi-core network-on-chip provided by an embodiment of the present invention;

[0045] Figure 3 is a schematic diagram of the data structure of an address entry provided by an embodiment of the present invention;

[0046] Figure 4 is a schematic diagram of the data structure of a directory provided by an embodiment of the present invention;

[0047] Figure 5 is a schematic diagram of the data structure of a transaction entry provided by an embodiment of the present invention;

[0048] Figure 6 It is a schematic diagram of the data structure of a data table entry provided by an embodiment of the present invention;

[0049] Figure 7 It is a flow chart of the core transaction processing during the request message processing provided by an embodiment of the present invention;

[0050] Figure 8 It is another flow chart of the core transaction processing during the request message processing provided by an embodiment of the present invention;

[0051] Figure 9 It is a specific application flow chart of a transaction table entry provided by an embodiment of the present invention;

[0052] Figure 10 It is a schematic diagram of the condition judgment for setting the transaction valid bit in the transaction table entry to 0 provided by an embodiment of the present invention;

[0053] Figure 11 It is a schematic diagram of the condition judgment for setting the data valid bit in the data table entry to 1 provided by an embodiment of the present invention;

[0054] Figure 12 It is a schematic diagram of the condition judgment for setting the data valid bit in the data table entry to 0 provided by an embodiment of the present invention;

[0055] Figure 13 It is a schematic diagram of the five - level processing pipeline of the request message provided by an embodiment of the present invention;

[0056] Figure 14 It is a specific flow chart of the query address status pipeline provided by an embodiment of the present invention;

[0057] Figure 15 It is a block diagram of a data processing device based on a multi - core processor provided by an embodiment of the present invention. Detailed implementation manners

[0058] To make the above - mentioned objects, features, and advantages of the present invention more obvious and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and specific implementation manners. Obviously, the described embodiments are part of the embodiments of the present invention, rather than all of them. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0059] Refer to Figure 1 , which shows a step - by - step flow chart of a data processing method based on a multi - core processor provided by an embodiment of the present invention, and specifically may include the following steps:

[0060] Step 101: Obtain the target cache address corresponding to the request message sent by any core;

[0061] In this embodiment, any core of the multi-core processor can send a request message, and the request message carries the address corresponding to the cache data that the core needs to request for processing, that is, the target cache address. Through the request message, the core can request to perform transaction processing on the cache data at the target cache address, and these transactions can include changing the cache state of the core for the cache data, reading the cache data, or writing the cache data into the memory, etc.

[0062] In a specific implementation, the multi-core processor can adopt a communication architecture of a multi-core on-chip network. As an example, as Figure 2 shown, this architecture consists of four cores of the multi-core processor (i.e., Core 0, Core 1, Core 2, Core 3), a master node, a crossbar, and subordinate nodes (SN). Each core has a secondary cache. When any one of the four cores initiates a request message, it is first scheduled by the crossbar and then sent to the master node for processing. The subordinate nodes are used for the master node to interact with the memory, such as loading data from the memory, writing data into the memory, etc.

[0063] Step 102: Determine the address status of the target cache address according to the preset address entry; wherein, the address entry stores multiple cache addresses and the address status of each cache address;

[0064] An entry is a data structure in a multi-core processor, and its main function is to track data blocks in the cache, including storing data, marking whether the data is valid, and storing other cache-related control information, cache status, etc.

[0065] In this embodiment, the preset address entry stores multiple cache addresses and the address status of each cache address, and the address status is used to indicate whether the cache address is occupied by a transaction. After obtaining the target cache address, traverse and search in the address entry to match the address status corresponding to the target cache address.

[0066] In a specific implementation, the data structure design of the preset address entry can be as Figure 3As shown, in this address entry, the 0th bit is the address validity bit (Add_valid), which is used to indicate the address status of the cache address. When Add_valid = 0, it indicates that the cache address is not occupied by a transaction. When Addr_valid = 0, it indicates that the cache address has been occupied by a transaction. The 0th to 40th bits are the address (Addr), which is used to store the cache address. After obtaining the target cache address, first check whether the address entry stores an Addr that matches the target cache address. If it exists, then determine the Add_valid corresponding to this Addr, and the address status of the target cache address can be determined.

[0067] In some embodiments of the present invention, determining the address status of the target cache address according to the preset address entry includes:

[0068] If the address entry does not store the target cache address, then store the target cache address into the address entry, and determine that the address status of the target cache address is that the target cache address is not occupied;

[0069] If the address entry stores the target cache address, then determine whether the target cache address is occupied according to the address status of the target cache address.

[0070] In this embodiment, if the address entry does not store the target cache address, it means that no core has sent a request message for this target cache address before. Then it can be determined that the target cache address is not occupied at this time, and the target cache address is stored into the address entry. If the address entry stores the target cache address, it means that a core has sent a request message for this target cache address before. At this time, the target cache address may be occupied because the previous request message has not been processed yet, or it may not be occupied because it has been processed. Specifically, it needs to be determined according to the address status stored in the address entry. Determining whether the target cache address is occupied through the address status in the address entry, and then starting the processing flow of the message and related transactions when it is not occupied can effectively prevent processing conflicts of the target cache address between cores.

[0071] In some embodiments of the present invention, the method further includes:

[0072] When the address status of the target cache address indicates that the target cache address is occupied, store the request message into the cache to pause processing the request message.

[0073] In this embodiment, since the address status indicates that the target cache address is occupied, it means that there are other request messages and transactions for the target cache address being processed at this time. To prevent data read / write conflicts, the request message needs to be stored in the cache first to suspend the processing of the request message.

[0074] In practical applications, the address status of the target cache address can be queried regularly. When it is queried that the target cache address is not occupied, the request message is taken out of the cache to resume the processing flow of the request message and ensure the timely processing of the request message.

[0075] Step 103: When the address status of the target cache address indicates that the target cache address is not occupied, query according to the target cache address in a preset directory to obtain a query result; wherein, the directory stores multiple cache addresses and the cache status of each cache address, and the cache status includes the cache status of multiple cores for the cache address.

[0076] The directory is a data structure in a multi-core processor and is used to store key information related to the cache. Each directory corresponds to a cache block or cache line in the processor cache.

[0077] The cache status, that is, the storage status of the cache data corresponding to the cache address by the core, such as the I (Invalid) state, SC (Share Clean) state, SD (Share Dirty) state, UC (Unique Clean) state, UD (Unique Dirty) state, and so on. Among them, the I state means that the core does not store the cache data or the stored cache data is invalid data; the SC state means that the cache data stored by the core is clean data, which is consistent with the data in the memory, and other cores may also store the cache data of this cache address; the SD state means that the cache data stored by the core is dirty data, which is inconsistent with the data in the memory, and other cores may also store the cache data of this cache address; the UC state means that only this core stores the cache data among all cores, and the cache data is clean data; the UD state means that only this core stores the cache data among all cores, and the cache data is dirty data.

[0078] In this embodiment, when the address status of the target cache address indicates that the target cache address is not occupied, the request message can be prepared for processing. Since cache coherence among multiple cores needs to be maintained during the processing of the request message, it is necessary to first determine the cache status of each core. At the same time, according to different types of transactions corresponding to the request message, obtaining the cache status of the core can also determine which core's cache data is used to process the transaction. For example, if the transaction type corresponding to the request message is to read data from memory, when the cache status of a certain core is obtained as the SD state and the cache statuses of other cores are all in the I state, it means that the cache data stored in the core with the SD state is the latest data relative to the data in memory. The cache data can be directly obtained from this core and returned to the core that initiated the request message, without having to read data from memory.

[0079] Based on this, the pre - set directory stores multiple cache addresses and the cache status of each cache address. Search for data matching the target cache address in this directory to obtain the query result. If there is a cache status corresponding to the target cache address, it can be considered that the directory hits at this time. On the contrary, if there is no cache status corresponding to the target cache address, it can be considered that the directory misses. When the directory hits, through the cache status corresponding to the target cache address stored in the directory, the cache status of each core can be quickly determined, without having to communicate with each core one by one to obtain its cache status, effectively reducing the communication overhead.

[0080] In the specific implementation, the design of the pre - set directory data structure can be as Figure 4 shown. Suppose the multi - core processor has 4 cores, denoted as Core0, Core1, Core2, and Core3 respectively. Then, bits 0 to 1 of the directory represent the cache status of Core0 for the cache address, bits 2 to 3 represent the cache status of Core1 for the cache address, and so on. Bits 8 to 47 are the address (Addr), used to store the cache address. In practical applications, the number of data bits used to store the cache status can also be increased accordingly according to the number of cores.

[0081] Step 104, according to the query result, process the request message, and maintain cache coherence among multiple cores through pre - set transaction entries and data entries. Among them, the transaction entry is used to follow up the processing progress of the transaction corresponding to the request message and update the cache status of the target cache address in the directory, and the data entry is used to store the cache data that needs to be written to memory and the information corresponding to the cache data.

[0082] In step 104, after obtaining the query result of the cache status of the target cache address in the directory, it is determined whether the directory is hit according to the query result, and the processing of obtaining the cache status of each core is performed accordingly, and then the request message is processed according to the cache status of each core. For example, if the directory is hit, the cache status of each core has been obtained through the directory, and then it is only necessary to communicate with the specified core to process the request message; if the directory is not hit, it is necessary to initiate communication with the cores one by one to obtain the cache status, and then determine which cores are associated with the transaction corresponding to the request message according to their cache status, or are associated with the cache consistency strategy, and then communicate with these cores to process the request message.

[0083] The process of processing the request message is also the process of processing the transaction. For example, when the core requests to write data to the memory, the data to be written is extracted from the request message, and then the write data transaction is processed; for another example, when the core requests to change the cache state, the relevant information of the cache state that the core expects to change is extracted from the request message, and the cache state change transaction is processed. When the request message and the corresponding transaction are processed, a response message is generated and returned to the core that initiated the request message, and the entire message processing process ends.

[0084] In some embodiments of the present invention, the multi-core processor further includes a plurality of other cores except the core that sends the request message, and the message processing of the request message according to the query result includes:

[0085] If the query result is that the directory has a cache state of the target cache address, determining the target core from the multiple other cores according to the cache state of the target cache address, or if the query result is that the directory does not have a cache state of the target cache address, determining the multiple other cores as the target core;

[0086] Sending a monitoring request to the target core;

[0087] A snoop response from the target core is received, and message processing is performed on the request message according to the snoop response.

[0088] In this embodiment, the target core is a core that needs to initiate a snoop request in order to obtain the cache status of the core, or a core that has learned the cache status through the directory and needs to initiate a snoop in order to process the request message and maintain cache consistency between multiple cores. The request message is processed by initiating a snoop request to the target core and receiving the snoop responses of these cores.

[0089] In an example of this embodiment, Figure 7As shown, there are a total of four cores, namely core0, core1, core2, and core3, as well as a master node (HN) and a slave node (SN). Core0 sends a request message to the master node HN. This request message corresponds to a ReadOnce read transaction request, indicating that core0 needs to obtain data from memory. After receiving the request message, HN first extracts the target cache address from the request message and queries for the address (Addr) that matches the target cache address from the address table entries in Figure 3 If there is an Addr and Addr_valid is 0, it means that the address status of the target cache address is unoccupied. Then, continue to query the cache status of the target cache address in the directory in Figure 4 At this time, the query result is that the directory does not have the cache status of the target cache address, that is, a directory miss. HN cannot obtain the cache status of other cores core1-core3, so it confirms that core1-core3 are all target cores that need to initiate snooping requests and sends SnpOnce snooping requests respectively.

[0090] Furthermore, the original cache status of core1 is the SD state, and the cached data it stores is dirty data. When it receives the SnpOnce snooping request, it needs to change the cache status to the SC state, so it returns a SnpRespData_SC_PD snooping response to HN, indicating that this is a snooping response with attached data, and this data is the cached data of core1. Core2 returns a SnpResp_I snooping response, indicating that this is a snooping response without attached data, and the original cache status or the changed cache status of core2 is the I state; Core3 returns a SnpResp_SC snooping response, indicating that this is a snooping response without attached data, and the original cache status or the changed cache status of core3 is the SC state.

[0091] Furthermore, since core0 requests to obtain memory data, and the cached data stored in core1 is dirty data, that is, the latest data. After HN receives the SnpRespData_SC_PD snooping response sent by core1, it sends the cached data of core1 to core0 in a CompData_I data message.

[0092] At the same time, since HN receives the SnpRespData_SC_PD snooping response returned by core1 that stores dirty data, in order to maintain consistency among multiple cores, it is necessary to write this cached data into memory. HN then sends a WriteNoSnpFull write transaction request to the slave node SN, declaring that data will be written into memory.

[0093] Further, HN receives the CompDBIDResp response from SN for the WriteNoSnpFull write transaction request, and then writes the cache data of core1 into the memory through the NCBWrData data packet.

[0094] Further, HN receives the CompAck transaction completion response from core0 for the CompData_I data packet, and the request packet and its corresponding transaction are processed.

[0095] In another example of this embodiment, as Figure 8 shown, there are a total of four cores, namely core0, core1, core2, and core3, as well as the host node (HN) and the slave node (SN). Core0 sends a request packet to the host node HN. This request packet corresponds to the CleanInvalid no-data request transaction, indicating that core0 needs to change the cache state to the SC state. After receiving the request packet, HN first extracts the target cache address from the request packet and queries for the address (Addr) that matches the target cache address from the address table entries in Figure 3 . Assuming that there is an Addr and the address valid bit (Addr_valid) is 0, it means that the address state of the target cache address is unoccupied, and then continue to query the cache state of the target cache address in the directory in Figure 4 . At this time, the query result is that the directory exists the cache state of the target cache address, that is, the directory hits. It is determined through the directory that the cache states of cores core0-core3 are I state, SC state, SD state, and I state respectively.

[0096] Further, since it is determined that the cache state of core2 is the SD state, that is, the cache data of core2 is dirty data. To maintain the consistency among multiple cores, it is necessary to write this cache data into the memory. Then, core2 is determined as the target core, and HN sends a SnpCleanInvalid snooping request to core2.

[0097] Further, the original cache state of core2 is the SD state. When it receives the SnpCleanInvalid snooping request, it needs to change the cache state to the I state, and then returns a SnpRespData_I_PD snooping response to HN, indicating that this is a snooping response with attached data, and this data is the cache data of core2.

[0098] After HN receives the SnpRespData_I_PD snooping response returned by core2, it then sends a WriteNoSnpFull write transaction request to the slave node SN, declaring that data will be written into the memory.

[0099] Further, HN receives the CompDBIDResp response from SN for the WriteNoSnpFull write transaction request, and then writes the cache data of core2 into the memory through the NCBWrData data packet.

[0100] Meanwhile, HN finishes processing the transaction of changing the cache state of core0, and returns a Comp_I no-data transaction completion response to core0, indicating that its cache state has been changed to the I state, and the request packet and its corresponding transaction have been processed.

[0101] In step 104, during the process of processing the request packet, since it is necessary to maintain cache coherence among multiple cores during the process of processing the request packet, the present invention also introduces the design of transaction entries and data entries, which can not only improve the efficiency of maintaining cache coherence, but also effectively prevent read-write conflicts during the process of processing the request packet and transactions.

[0102] The transaction entry is used to follow up the processing progress of the transaction corresponding to the request packet and update the cache state of the target cache address in the directory. The transaction entry can store some key information during the whole process of transaction processing to follow up the processing progress of the transaction. Based on the key information stored in the transaction, the processing progress of each transaction can be known, which is convenient for scheduling and managing the transactions and preventing data read-write conflicts between transactions. Moreover, during the process of transaction processing, the latest cache states of each core can also be obtained. Through the transaction entry, these cache states can be stored and updated to the cache states stored in the directory after the transaction processing is completed, so as to maintain the effectiveness and timeliness of the cache states stored in the directory and make it play a role in improving the maintenance of cache coherence.

[0103] In a specific implementation, the data structure design of the transaction entry can be as Figure 5 shown. Taking a multi-core processor with four cores as an example, in this transaction entry, the 0th bit is the transaction valid bit (Txn_valid), indicating whether the transaction is recorded or can also indicate whether the transaction is processed. 1 means the transaction is recorded or the transaction is not processed, and 0 means the transaction is not recorded or the transaction has been processed. The 1st to 7th bits are the Opcode of the transaction, indicating the type of the transaction. The 8th to 9th bits are the snooping number (Snp_num), indicating the remaining number of cores that need to communicate during the process of processing the packet. The 10th bit is the directory hit flag (Dir_hit), indicating whether the directory is hit, 1 for hit, and 0 for not hit. The 11th to 18th bits are the core cache states (Core_status), indicating the cache states of the four cores. The specific application of this transaction entry is as Figure 9As shown, when a request message is received, the transaction valid bit (Txn_valid) is set to 1, indicating that the transaction is recorded / processing has started and not completed. Meanwhile, the type of the transaction is recorded in the opcode, such as ReadOnce (reading memory data), CleanShare (changing the cache state to the SC state), etc. Further, by querying the directory, the remaining number of target cores that need to initiate snooping is determined and recorded in Snp_num. Also, if the directory is hit, Dir_hit is set to 1, and the cache state in the directory is stored in Core_status; if the directory is not hit, Dir_hit is set to 0, and since the cache states of each core cannot be determined, all data bits of Core_status are set to 0.

[0104] In an example of this embodiment, as Figure 7 shown, after receiving the request message from core0, Txn_valid is set to 1 through the transaction entry, and the ReadOnce transaction corresponding to the request message is recorded in the opcode. The directory is not hit, Dir_hit is set to 0, and since the cache states of each core cannot be determined, all data bits of Core_status are set to 0. Meanwhile, if snooping requests need to be sent to the target cores core1 - core3, the remaining number of target cores that need to initiate snooping is 3 and is recorded in Snp_num.

[0105] When the SnpRespData_SC_PD snooping response from core1 is received, the cache state of core1 is recorded in bits 13 - 14 of Core_status, recorded as 2’b10 (2’b indicates 2 - bit binary, and 10 indicates that the cache state of core1 is the SC state). When the SnpResp_I from core2 is received, the cache state of core2 is recorded in bits 15 - 16 of Core_status, recorded as 2’b00 (00 indicates that the cache state of core2 is the I state). When the SnpResp_SC response from core3 is received, the cache state of core2 is recorded in bits 17 - 18 of Core_status, recorded as 2b’10.

[0106] Further, after sending CompDat_I to core0, the cache state of core0 is recorded in bits 11 - 12 of Core_status, recorded as 2’b00.

[0107] Finally, when the request message and the corresponding transaction are processed, the data stored in Core_status in the transaction entry is updated to the cache state stored in the directory (i.e., Figure 4in the core 0 cache state, core 1 cache state, core 2 cache state, and core 3 cache state).

[0108] In another example of this embodiment, as Figure 8 shown, after receiving the request message of core0, set Txn_valid to 1 through the transaction entry, and record the CleanInvalid transaction corresponding to the request message in the opcode; the directory hits, set Dir_hit to 1, and confirm through the directory to core0-core3, which are in the I state, SC state, SD state, and I state respectively, then record Core_status as 8'b00_10_01_00 (8'b means 8-bit binary, 00 corresponds to the I state, 10 corresponds to the SC state, 01 corresponds to the SD state). And since the cache state of core2 is the SD state and a snooping request needs to be sent to the target core core2, the remaining number of target cores that need to initiate snooping is 1, which is recorded in Snp_num.

[0109] When HN receives the SnpRespData_I_PD snooping response of core2, at this time, the cache state of core2 needs to be changed from the SD state to the I state, then update the 2'b01 stored in the 15th - 16th bits of Core_status to 2'b00.

[0110] In some embodiments of the present invention, before sending the snooping request to the target core, it further includes:

[0111] Store the number of target cores through the transaction entry;

[0112] The receiving the snooping response of the target core includes:

[0113] When receiving the snooping response of the target core, update the number of the target core in the transaction entry.

[0114] In this embodiment, the transaction entry can store the number of target cores that need to initiate snooping, and whenever a snooping response of the core is received, the number of the target core is updated accordingly. For example, in the data structure of the transaction entry as Figure 5 shown, the number of target cores can be stored through the snooping number (Snp_num), and the value of Snp_num is updated each time a core snooping is received. By storing the number of target cores that need to initiate snooping and updating according to the received snooping response, it is convenient to track and manage the number of cores that need to initiate snooping in this transaction, and timely understand the completion progress of the snooping request initiation and the snooping response end.

[0115] In an example of this embodiment, as Figure 7As shown, if a listening request needs to be sent to core1-core3, the remaining number of target cores for which the listening needs to be initiated is 3, and this value is recorded in Snp_num. Further, a listening request for core1-core3 is sent. Whenever a listening response from a core is received, the value of Snp_num is decremented by 1. When listening responses from all of core1-core3 have been received, the value of Snp_num is 0, indicating that all listening responses have been received.

[0116] In another example of this embodiment, as Figure 8 shown, if a listening request needs to be sent to core2, the remaining number of target cores for which the listening needs to be initiated is 1, and this value is recorded in Snp_num. Further, a listening request for core2 is sent. When a listening response from core2 is received, the value of Snp_num is decremented by 1. At this time, the value of Snp_num is 0, indicating that all listening responses have been received.

[0117] In step 104, the data table entry is used to store the cache data that needs to be written to the memory and the information corresponding to the cache data. Since cache coherence also needs to be maintained during the process of processing packets, there are also cases where the cache data of a core needs to be written to the memory. For example, when the cache state of a certain core is obtained as the SD state, that is, the cache state of this core is inconsistent with the data in the memory. To maintain cache coherence, this cache data needs to be written to the memory and then synchronized among the cores. And the packet processing cycle is relatively long. When the cache data that needs to be written to the memory is obtained, it cannot be immediately written to the memory. Therefore, to prevent data loss, the present invention designs a data table entry to store the data that needs to be written to the memory and store the relevant information corresponding to this cache data, so as to perform validity judgment on the cache data and execute the corresponding write operation when writing the data. At the same time, when there are multiple transactions that need to write cache data to the memory, the data table entry can also facilitate the management and scheduling of the transactions for writing data and prevent data read-write conflicts.

[0118] In a specific implementation, the data structure design of the data table entry can be as Figure 6As shown below. In this data table entry, bit 0 is the Data_valid bit, indicating whether data has been recorded or the data write is completed. A value of 1 means the recording or writing is not completed, and a value of 0 means the data has not been recorded or the writing is completed, with the default value being 0. Bits 1 to 5 are used to store the data source. Among them, bit 1 is the SnpRespData_SD record, indicating that there is data in the data table entry and the data source is the SnpRespData transaction, and the core cache state is the SD state. Bit 2 is the SnpRespData record, indicating that there is data in the data table entry and the data source is the SnpRespData transaction. Bit 3 is the CompData record, indicating that there is data in the data table entry and the data source is the CompData transaction. Bit 4 is the NCBW record, indicating that there is data in the data table entry and the data source is the NCBWrData transaction. Bit 5 is the CBW record, indicating that there is data in the data table entry and the data source is the CBWrData transaction. It should be noted that Figure 6 The field segment representing the data source in Figure 6 is only an example. In actual applications, there can be more field segments to store the corresponding data sources, not limited to bits 1 to 5 only. Bits 6 to 69 are the Byte Enable (BE), indicating the byte enable of the data. Based on the byte enable, it can be determined whether the data is complete. Bits 70 to 581 are the data that needs to be written into the memory and recorded. The complete data is 512 bytes and is transmitted in 4 packets (i.e., Data 0, Data 1, Data 2, Data 3).

[0119] In an example of this embodiment, as Figure 7 shown, the cache data stored in core1 is dirty data. When HN receives the SnpRespData_SC_PD listen response from core1, in order to maintain cache consistency among multiple cores, it is necessary to write the cache data of core1 into the memory. At this time, the data table entry as shown in Figure 6 can be used to record the data_valid bit as 1, indicating that there is data that needs to be written into the memory and the writing is not completed, and record the SnpRespData_SC_PD ( Figure 6 not shown in Figure 6 ) representing the data source as 1, and record all other field segments representing the data source as 0. At the same time, record the data in Data 0 - Data 3.

[0120] Furthermore, when HN sends WriteNoSnpFull to SN and receives the CompDBIDResp response from SN, and then sends NCBWrData to SN, the cache data of core1 stored by it is written into the memory through the above data table entry. After the writing is completed, record data_valid as 0, indicating that the data writing is completed.

[0121] In another example of this embodiment, asFigure 8 As shown, the cached data stored in core2 is dirty data. When HN receives the SnpRespData_I_PD listening response from core2, in order to maintain cache consistency among multiple cores, it is necessary to write the cached data of core2 into the memory. At this time, it can be done through the data table entry as shown in Figure 6 Record the data valid bit as 1, indicating that there is data that needs to be written into the memory and has not been written yet, and record the SnpRespData_I_PD (not shown in Figure 6 as 1, and record all other fields representing the data source as 0. At the same time, record the data in Data0 - Data3.

[0122] Furthermore, when HN sends WriteNoSnpFull to SN and receives the CompDBIDResp response from SN, then sends NCBWrData to SN, and writes the cached data of core2 stored in it into the memory through the above - mentioned data table entry. After the writing is completed, record data_valid as 0, indicating that the data writing has been completed.

[0123] In some embodiments of the present invention, when the address status of the target cache address indicates that the target cache address is not occupied, query in a preset directory according to the target cache address, and the query result includes:

[0124] When the address status of the target cache address indicates that the target cache address is not occupied, update the address status of the target cache address to indicate that the target cache address is occupied, and query in a preset directory according to the target cache address to obtain a query result;

[0125] The method further includes:

[0126] If the processing of the transaction has been completed, mark the completion of the transaction processing through the transaction table entry;

[0127] If the processing of writing the cached data into the memory has been completed, mark the completion of writing the cached data through the data table entry;

[0128] In the case where the transaction table entry has marked the completion of the transaction processing and the data table entry has marked the completion of writing the cached data, update the address status of the target cache address to indicate that the target cache address is not occupied;

[0129] Empty the data stored in the transaction table entry and the data table entry corresponding to the target cache address.

[0130] In this embodiment, when the address status of the target cache address indicates that the target cache address is not occupied, it means that the processing of the request message and the transaction corresponding to the target cache address can start, and then the address status of the target cache address is updated to indicate that the target cache address is occupied. For example, through the address entry such as Figure 4 the address (Addr) matching the target cache address is queried, and it is determined that Addr_valid corresponding to Addr is 0, then Addr_valid can be updated to 1, indicating that the processing of the request message and the transaction starts, and the target cache address has been occupied by the current processing flow. In another example, if no data matching the target cache address is found in the address entry, it means that no core has initiated a request message for the target cache address before. Then, the target cache address is stored in Addr in the address entry, and Addr_valid is recorded as 0, which also indicates that the processing of the request message and the transaction starts, and the target cache address has been occupied by the current processing flow.

[0131] Furthermore, if the processing of the transaction is completed, the transaction entry is marked to indicate that the transaction processing is completed.

[0132] In a specific implementation, first, when the address status in the address entry indicates that the target cache address is not occupied, it can be considered that the processing of the transaction corresponding to the request message starts. At this time, Txn_valid in the transaction entry is set to 1. Then, as Figure 10 shown, when a transaction initiated by the core is received (it may be a request initiated by the core itself or a transaction such as a response to a snooping request), it can be determined whether the transaction is completed based on the type of the transaction, the transaction type recorded in Opcode in the transaction entry, and the remaining number of target cores that need to initiate snooping. When the conditions are met, Txn_valid in the transaction entry is set to 0. Specifically as follows:

[0133] 1) If a CompAck transaction completion response is received, the Opcode recorded in the transaction entry is one of ReadNoSnp, ReadOnce, ReadShared, ReadUnique, ReadOnceCleanInvalid, ReadOnceMakeInvalid, CleanUnique, MakeUnique, and the remaining snooping responses (Snp_num) are 0, then the transaction valid bit (Txn_valid) is set to 0.

[0134] 2) If the received SnpResp monitoring response has an Opcode recorded in the transaction table entry as one of CleanShared, CleanInvalid, MakeInvalid, WriteUniqueFull, WriteUniquePtl, WriteUniqueFull, and the remaining number of transactions is 0, then set Txn_valid to 0.

[0135] 3) If the received SnpRespData monitoring response with data has an Opcode recorded in the transaction table entry as one of CleanShared, CleanInvalid, WriteUniquePtl, and the remaining number of transactions is 0, then set Txn_valid to 0.

[0136] 4) If the received NCBWrData data packet has an Opcode recorded in the transaction table entry as one of WriteNoSnpFull, WriteNoSnpPtl, WriteUniqueFull, WriteUniquePtl, and the remaining number of transactions is 0, then set Txn_valid to 0.

[0137] 5) If the received CBWrData data packet has an Opcode recorded in the transaction table entry as one of WriteEvictFull, WriteCleanPtl, WriteBackFull, and the remaining number of transactions is 0, then set Txn_valid to 0.

[0138] Furthermore, if the process of writing the cache data to the memory has been completed, mark the cache data write completion through the data table entry.

[0139] In a specific implementation, first, it is possible to determine whether it is necessary to write the cache data of the core to the memory by judging the transaction type of the transaction returned by the core (which may be a request initiated by the core itself or a transaction such as a response to a monitoring request) and the cache state of the core. If it is necessary to write the cache data to the memory, then set Data_valid in the data table entry to 1. For example Figure 11As shown, when the received data is SnpRespData and the core cache status is one of SD, I_PD, SC_PD, SD_PD, U_PD, the data valid bit (Data_valid) is set to 1, indicating that the cached data needs to be written to memory and the cached data is stored through the data table entry; if the received data is one of CompData, BWrData, NCBWrData, Data_valid is set to 1, indicating that the cached data needs to be written to memory and the cached data is stored through the data table entry. Then, as Figure 12 shown, when the response message of CompDBIDResp is received (for example, the HN node receives the CompDBIDResp returned by the SN), it is considered that the cached data has been written, and Data_valid is set to 0.

[0140] Further, when the transaction table entry has marked the transaction processing as completed and the data table entry has marked the cached data writing as completed, the address status of the target cache address is updated to indicate that the target cache address is not occupied.

[0141] In a specific implementation, when the transaction corresponding to the request message and the writing of cached data for maintaining cache consistency among multiple cores are both completed, it is considered that all processing flows related to the request message initiated for the core have ended, and the occupation of the target cache address is released.

[0142] As an example, when Txn_valid in the transaction table entry is 0 and Data_valid in the data table entry is 0, the Addr_valid in the address table entry is updated from 1 to 0, indicating the release of the occupation of the target cache address.

[0143] Finally, the data stored in the transaction table entry and the data table entry corresponding to the target cache address is cleared to release resources.

[0144] In a specific implementation, when Txn_valid, Data_valid, and Addr_valid are all 0, it indicates that all processing flows for the request message and related transactions have been completed, and the data stored in the transaction table entry and the data table entry corresponding to the target cache address is cleared.

[0145] In an example of this embodiment, as Figure 7As shown, when HN receives a request message from core0, it queries the address status of the target cache address in the address table entry, that is, Addr_valid. If Addr_valid is 0, then Addr_valid is updated to 1; or if Addr_valid is not queried, then Addr_valid is stored in Addr and Addr_valid is set to 1. Setting Addr_valid to 1 means that the target cache address is occupied by the current processing flow of the request message and related transactions. At the same time, the relevant information of the transaction is recorded. The opcode in the transaction table entry is ReadOnce, and Txn_valid is set to 1, indicating the start of processing the transaction.

[0146] Further, when HN receives the SnpRespData_SC_PD listening response from core1 (also regarded as a kind of transaction), that is, the transaction type is SnpRespData, and the cache status of core1 is SC_PD, which meets Figure 11 one of the conditions in, Data_valid is set to 1, representing that the cache data of core1 needs to be written into the memory.

[0147] Further, when HN receives CompAck from core0, the opcode in the transaction table entry is ReadOnce, and since the listening responses of all core1 - 3 have been received, Snp_num in the transaction table entry is 0, which meets Figure 10 one of the conditions in, Txn_valid is set to 0, representing that the transaction processing is completed.

[0148] Further, when HN receives CompDBIDResp from SN, which meets Figure 12 the conditions shown in, Data_valid is set to 0, representing that the data writing is completed.

[0149] Finally, since both Data_valid and Txn_valid are set to 0, Addr_valid is updated to 0 to release the occupation of the target cache address, and the relevant data related to the target cache address in the transaction table entry and data table entry are cleared to release resources.

[0150] In another example of this embodiment, as Figure 8As shown, when HN receives a request message from core0, it queries the address status of the target cache address in the address entry, i.e., Addr_valid. If Addr_valid is 0, then Addr_valid is updated to 1; or if Addr_valid is not found, then Addr_valid is stored in Addr and Addr_valid is set to 1. Setting Addr_valid to 1 means that the target cache address is occupied by the current processing flow of the request message and related transactions. At the same time, relevant information of the transaction is recorded. The opcode in the transaction entry is CleanInvalid, and Txn_valid is set to 1, indicating that the transaction processing starts.

[0151] Further, when HN receives the SnpRespData_I_PD listen response from core2 (also regarded as a kind of transaction), i.e., the transaction type is SnpRespData and the cache status of core2 is I_PD, which meets Figure 11 one of the conditions in [], Data_valid is set to 1, representing that the cache data of core2 needs to be written into the memory.

[0152] Further, the opcode in the transaction entry is CleanInvalid, and since the listen response from core2 has been received and Snp_num in the transaction entry is 0, which meets Figure 10 one of the conditions in [], Txn_valid is set to 0, representing that the transaction processing is completed.

[0153] Further, when HN receives CompDBIDResp from SN, which meets Figure 12 the conditions shown in [], Data_valid is set to 0, representing that the data writing is completed.

[0154] Finally, since both Data_valid and Txn_valid are set to 0, Addr_valid is updated to 0 to release the occupation of the target cache address, and the relevant data related to the target cache address in the transaction entry and data entry is cleared to release resources.

[0155] In this embodiment, the address status of the address entry is used to indicate that the target cache address is occupied by the current processing flow. And when the transaction entry marks the completion of transaction processing and the data entry marks the completion of transaction processing, the occupation of the target cache address is released, which can effectively prevent conflicts in transaction processing or data reading and writing, and can meet the requirements in high-concurrency scenarios.

[0156] In some embodiments of the present invention, in the process of processing the request message according to the query result and maintaining cache consistency among multiple cores through preset transaction entries and data table entries, the method further includes:

[0157] If there is cache data that needs to be written to memory, verify the integrity of the cache data to obtain a verification result, and store the cache data and the verification result in the data table entry;

[0158] When the cache data needs to be written to memory, determine the integrity of the cache data through the verification result in the data table entry;

[0159] If the verification result indicates that the cache data is complete data, write the cache data to memory through the data table entry.

[0160] In a specific implementation, the verification result can be stored in a field segment in the data table entry. For example Figure 6 the byte enable (BE) field segment in the data table entry shown. Storing the verification result of the written data in the data table entry and verifying its integrity when data needs to be written can ensure that the written data is complete data and effectively improve the accuracy of the data.

[0161] In an example of this embodiment, as Figure 7 shown, when HN receives the SnpRespData_SC_PD listening response from core1, it indicates that there is cache data that needs to be written to memory. Subsequently, HN performs an integrity check on the cache data and records the integrity check result through the byte enable (BE) field segment in the data table entry. When the cache data is complete data, BE records 64’hffff_ffff_ffff_ffff (representing a 64-bit hexadecimal value with all data bits being 1).

[0162] Furthermore, when the cache data of core1 needs to be written to memory, the integrity of the cache data is verified through BE in the data table entry. If the verification result indicates that the cache data is complete data, HN writes the data stored in the data table entry to memory through the NCBWrData transaction.

[0163] In another example of this embodiment, as Figure 8As shown, when HN receives SnpRespData_I_PD from core2, it indicates that there is cache data that needs to be written into the memory. Subsequently, HN performs integrity check on the cache data and records the integrity check result in the BE field in the data table entry. When the cache data is complete data, BE records 64'hffff_ffff_ffff_ffff (indicating a 64-bit hexadecimal value, all data bits are 1).

[0164] Furthermore, when the cache data of core2 needs to be written to the memory, the integrity of the cache data is verified through the BE in the data table entry. If the verification result indicates that the cache data is complete, HN writes the data stored in the data table entry to the memory through the NCBWrData transaction.

[0165] In some embodiments of the present invention, the data processing method based on a multi-core processor can also be summarized into a five-stage processing pipeline, such as Figure 13 As shown, the five-level processing pipeline is: address acquisition, address status query, directory query, message processing, and message generation, as follows:

[0166] Addressing, that is, obtaining the target cache address corresponding to the request message sent by any core;

[0167] Querying the address status, that is, determining the address status of the target cache address according to a preset address table entry; wherein the address table entry stores multiple cache addresses and the address status of each cache address;

[0168] Querying a directory, i.e., when the address state of the target cache address indicates that the target cache address is not occupied, querying a preset directory according to the target cache address to obtain a query result; wherein the directory stores a plurality of cache addresses and a cache state of each cache address, and the cache state includes cache states of the cache addresses of a plurality of cores;

[0169] Message processing, that is, performing message processing on the request message according to the query result, and maintaining cache consistency between multiple cores through preset transaction table entries and data table entries; wherein the transaction table entry is used to follow up the processing progress of the transaction corresponding to the request message, and update the cache status of the target cache address in the directory, and the data table entry is used to store cache data that needs to be written to the memory and information corresponding to the cache data.

[0170] Message generation, that is, after processing the request message, generates a response message and returns it to the core that initiated the request message.

[0171] In this embodiment, the address status query process is as follows: Figure 14As shown in the figure. After receiving the input of a message (i.e., a request message), first determine whether the transaction corresponding to the request message is a request transaction:

[0172] If the transaction corresponding to the request message is a request transaction, query whether the target cache address in the request message exists in the address entry. If the target cache address exists and the address status of the target cache address indicates that the target cache address is occupied, put the message into the cache to suspend processing the request message; if the address status of the target cache address does not exist, it means that the target cache address is not occupied, then send the message to the lower-level pipeline.

[0173] If the transaction corresponding to the request message is not a request transaction, send the message to the lower-level pipeline.

[0174] The embodiments of the present invention have the following advantages: The method of the embodiments of the present invention includes: obtaining the target cache address corresponding to the request message sent by any core, determining the address status of the target cache address according to the preset address entry, where the address entry stores multiple cache addresses and the address status of each cache address. When the address status of the target cache address indicates that the target cache address is not occupied, query according to the target cache address in the preset directory to obtain a query result, where the directory stores multiple cache addresses and the cache status of each cache address, and the cache status includes the cache status of multiple cores for the cache address. According to the query result, perform message processing on the request message, and maintain cache consistency among multiple cores through the preset transaction entry and data entry. The transaction entry is used to follow up the processing progress of the transaction corresponding to the request message and update the cache status of the target cache address in the directory, and the data entry is used to store the cache data that needs to be written into the memory and the information corresponding to the cache data. Through the query of the directory, since the directory stores multiple cache addresses and the cache status of each cache address, when the query result can confirm the cache status of the target cache address, the cache status of other cores can be quickly obtained, and the optimal processing can be made for the request message and related transactions according to the cache status, reducing the cost and overhead of maintaining cache consistency; at the same time, through the design of the address entry, transaction entry and data entry, read-write conflicts can be effectively prevented, cache consistency among multiple cores can be efficiently maintained, and it is also convenient to track and manage the transaction corresponding to the request message.

[0175] Refer to Figure 15 , which shows a schematic structural diagram of a data processing device based on a multi-core processor provided by an embodiment of the present invention, and specifically may include the following modules:

[0176] An address fetching module 1501, configured to obtain the target cache address corresponding to the request message sent by any core;

[0177] An address status determination module 1502 is configured to determine the address status of the target cache address according to a preset address entry; wherein, the address entry stores multiple cache addresses and the address status of each cache address.

[0178] A directory query module 1503 is configured to, when the address status of the target cache address indicates that the target cache address is not occupied, query in a preset directory according to the target cache address to obtain a query result; wherein, the directory stores multiple cache addresses and the cache status of each cache address, and the cache status includes the cache status of multiple cores for the cache address.

[0179] A message processing module 1504 is configured to perform message processing on the request message according to the query result, and maintain cache consistency among multiple cores through preset transaction entries and data table entries; wherein, the transaction entry is used to update the cache status of the target cache address in the directory and follow up the transaction process, and the data table entry is used to store the cache data to be written into the memory and the information corresponding to the cache data.

[0180] In some embodiments of the present invention, the multi-core processor further includes multiple other cores except the core that sends the request message, and the message processing module 1504 includes:

[0181] A target core determination sub-module is configured to, if the query result is that the cache status of the target cache address exists in the directory, determine a target core among the multiple other cores according to the cache status of the target cache address, or, if the query result is that the cache status of the target cache address does not exist in the directory, determine the multiple other cores as the target core.

[0182] A listening initiation module is configured to send a listening request to the target core.

[0183] A listening processing module is configured to receive the listening response of the target core and perform message processing on the request message according to the listening response.

[0184] In some embodiments of the present invention, the message processing module 1504 further includes:

[0185] An address occupancy marking sub-module is configured to, when the address status of the target cache address indicates that the target cache address is not occupied, update the address status of the target cache address to indicate that the target cache address is occupied, and query in a preset directory according to the target cache address to obtain a query result.

[0186] The device further includes:

[0187] A transaction completion marking module, configured to, if the processing of the transaction has been completed, mark the completion of the transaction processing through the transaction entry;

[0188] A write completion marking module, configured to, if the processing of writing the cache data into the memory has been completed, mark the completion of writing the cache data through the data entry;

[0189] An address release marking module, configured to, when the transaction entry has marked the completion of the transaction processing and the data entry has marked the completion of writing the cache data, update the address status of the target cache address to indicate that the target cache address is not occupied;

[0190] Clear the data stored in the transaction entry and the data entry corresponding to the target cache address.

[0191] In some embodiments of the present invention, the address status determination module 1502 includes:

[0192] A first query address query result processing sub-module, configured to, if the target cache address is not stored in the address entry, store the target cache address into the address entry, and determine that the address status of the target cache address is that the target cache address is not occupied;

[0193] A second query address query result processing sub-module, if the target cache address is stored in the address entry, determine whether the target cache address is occupied according to the address status of the target cache address.

[0194] In some embodiments of the present invention, the device further includes:

[0195] A core number storage module, configured to store the number of the target core through the transaction entry;

[0196] The monitoring processing module includes:

[0197] A core number update module, configured to update the number of the target core in the transaction entry when receiving the monitoring response of the target core.

[0198] In some embodiments of the present invention, the device further includes:

[0199] A data verification result acquisition module, configured to, if there is cache data to be written into the memory, verify the integrity of the cache data, obtain a verification result, and store the cache data and the verification result into the data entry;

[0200] A data verification result reading module, configured to determine the integrity of the cache data through the verification result in the data entry when the cache data needs to be written into the memory;

[0201] A data writing module, configured to write the cached data into the memory through the data table entry if the verification result indicates that the cached data is complete data.

[0202] In some embodiments of the present invention, the device further includes:

[0203] A message caching module, configured to store the request message in the cache to suspend processing of the request message when the address status of the target cache address indicates that the target cache address is occupied.

[0204] Some embodiments of the present invention further provide an electronic device, which may include a processor, a memory, and a computer program stored on the memory and capable of running on the processor. When the computer program is executed by the processor, the data processing method based on a multi-core processor as described above is implemented.

[0205] Some embodiments of the present invention further provide a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the data processing method based on a multi-core processor as described above is implemented.

[0206] Some embodiments of the present invention further provide a computer program product, including a computer program. When the computer program is executed by a processor, the data processing method based on a multi-core processor as described above is implemented.

[0207] For the device embodiments, since they are basically similar to the method embodiments, the description is relatively simple. For the relevant parts, refer to the partial description of the method embodiments.

[0208] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data for analysis, stored data, displayed data, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties. And the collection, use, and processing of relevant data need to comply with the relevant laws, regulations, and standards of relevant countries and regions, and corresponding operation entrances are provided for users to choose to authorize or refuse.

[0209] Each embodiment in this specification is described in a progressive manner. Each embodiment focuses on the differences from other embodiments. The same or similar parts among the embodiments can be referred to each other.

[0210] Those skilled in the art should understand that the embodiments of the present invention can be provided as a method, apparatus, or computer program product. Therefore, the embodiments of the present invention can take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware aspects. Moreover, the embodiments of the present invention can take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk memory, CD-ROM, optical memory, etc.) that contain computer-usable program code.

[0211] The embodiments of the present invention are described with reference to the flowcharts and / or block diagrams of methods, terminal devices (systems), and computer program products according to the embodiments of the present invention. It should be understood that each flow and / or block in the flowchart and / or block diagram, as well as the combination of flows and / or blocks in the flowchart and / or block diagram, can be realized by computer program instructions. These computer program instructions can be provided to the processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing terminal devices to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing terminal devices generate a device for realizing the functions specified in one Figure 1 one flow or multiple flows and / or blocks Figure 1 one block or multiple blocks.

[0212] These computer program instructions can also be stored in a computer-readable memory that can direct a computer or other programmable data processing terminal device to work in a specific manner, so that the instructions stored in the computer-readable memory generate a manufactured article including an instruction device, and the instruction device realizes the functions specified in one Figure 1 one flow or multiple flows and / or blocks Figure 1 one block or multiple blocks.

[0213] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal device, so that a series of operation steps are executed on the computer or other programmable terminal device to generate a computer-implemented process. Thus, the instructions executed on the computer or other programmable terminal device provide steps for realizing the functions specified in one Figure 1 one flow or multiple flows and / or blocks Figure 1 one block or multiple blocks.

[0214] Although the preferred embodiments of the embodiments of the present invention have been described, those skilled in the art can make additional changes and modifications to these embodiments once they know the basic creative concept. Therefore, the appended claims are intended to be construed as including the preferred embodiments and all changes and modifications that fall within the scope of the embodiments of the present invention.

[0215] Finally, it should also be noted that in this text, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or terminal device comprising a series of elements not only includes those elements, but also includes other elements not expressly listed, or also includes elements inherent to such process, method, article or terminal device. Without further limitation, an element defined by the statement "comprising an..." does not exclude the presence of additional identical elements in the process, method, article or terminal device comprising the above elements.

[0216] The above has introduced in detail the data processing method, apparatus, device and medium based on a multi-core processor. In this text, specific examples are used to elaborate on the principle and implementation manner of the present invention. The description of the above embodiments is only used to help understand the method and its core idea of the present invention; at the same time, for those of ordinary skill in the art, according to the idea of the present invention, there will be changes in the specific implementation manner and application scope. In summary, the content of this specification should not be construed as a limitation to the present invention.

Claims

1. A data processing method based on a multi-core processor, characterized in that: The method comprises: Get the target cache address corresponding to the request message sent by any core; Determine the address state of the target cache address according to a preset address table entry; wherein the address table entry stores a plurality of cache addresses and the address state of each cache address; When the address state of the target cache address indicates that the target cache address is not occupied, querying a preset directory according to the target cache address to obtain a query result; wherein the directory stores a plurality of cache addresses and a cache state of each cache address, and the cache state includes cache states of the cache address of a plurality of cores; According to the query result, the request message is processed, and cache consistency is maintained among multiple cores through preset transaction table entries and data table entries; wherein the transaction table entry is used to follow up the processing progress of the transaction corresponding to the request message and update the cache status of the target cache address in the directory, and the data table entry is used to store cache data that needs to be written to the memory and information corresponding to the cache data.

2. The method according to claim 1, characterized in that The multi-core processor further includes a plurality of other cores except the core that sends the request message, and the message processing of the request message according to the query result includes: If the query result is that the directory has a cache state of the target cache address, determining the target core from the multiple other cores according to the cache state of the target cache address, or if the query result is that the directory does not have a cache state of the target cache address, determining the multiple other cores as the target core; Sending a monitoring request to the target core; A snoop response from the target core is received, and message processing is performed on the request message according to the snoop response.

3. The method according to claim 1, characterized in that When the address state of the target cache address indicates that the target cache address is not occupied, querying a preset directory according to the target cache address to obtain a query result includes: When the address state of the target cache address indicates that the target cache address is not occupied, updating the address state of the target cache address to indicate that the target cache address is occupied, and performing a query in a preset directory according to the target cache address to obtain a query result; The method further comprises: If the transaction has been processed, marking the transaction as completed through the transaction entry; If the process of writing the cache data into the memory has been completed, marking the completion of writing the cache data through the data table entry; When the transaction entry has marked that the transaction processing is completed and the data entry has marked that the cache data writing is completed, updating the address state of the target cache address to indicate that the target cache address is not occupied; The transaction entry and the data corresponding to the target cache address stored in the data entry are cleared.

4. The method according to any one of claims 1 to 3, characterized in that: The determining the address state of the target cache address according to the preset address table entry includes: If the target cache address is not stored in the address table entry, the target cache address is stored in the address table entry, and the address state of the target cache address is determined to be that the target cache address is not occupied; If the target cache address is stored in the address table entry, whether the target cache address is occupied is determined according to the address state of the target cache address.

5. The method according to claim 2, characterized in that: Before sending the monitoring request to the target core, the method further includes: Storing the number of target cores through the transaction table entry; The receiving the monitoring response of the target core includes: When a snoop response from the target core is received, the number of the target cores in the transaction table entry is updated.

6. The method according to any one of claims 1 to 3, characterized in that: In the process of performing message processing on the request message according to the query result, and maintaining cache consistency among multiple cores through preset transaction table entries and data table entries, the method further includes: If there is cache data that needs to be written to the memory, verify the integrity of the cache data, obtain a verification result, and store the cache data and the verification result in the data table entry; When the cache data needs to be written into the memory, the integrity of the cache data is determined by the verification result in the data table entry; If the verification result indicates that the cache data is complete data, the cache data is written into the memory through the data table entry.

7. The method according to any one of claims 1 to 3, characterized in that: The method further comprises: When the address status of the target cache address indicates that the target cache address is occupied, the request message is stored in the cache to suspend processing of the request message.

8. A data processing device based on a multi-core processor, characterized in that: The device comprises: An addressing module is used to obtain the target cache address corresponding to the request message sent by any core; An address status determination module, used to determine the address status of the target cache address according to a preset address table entry; wherein the address table entry stores a plurality of cache addresses and the address status of each cache address; A directory query module, configured to query a preset directory according to the target cache address to obtain a query result when the address status of the target cache address indicates that the target cache address is not occupied; wherein the directory stores a plurality of cache addresses and a cache status of each cache address, and the cache status includes cache status of the cache address by a plurality of cores; A message processing module is used to process the request message according to the query result, and maintain cache consistency between multiple cores through preset transaction table entries and data table entries; wherein the transaction table entry is used to update the cache status of the target cache address in the directory and follow up the transaction process, and the data table entry is used to store cache data that needs to be written to the memory and information corresponding to the cache data.

9. An electronic device, characterized in that: The invention comprises a processor, a memory and a computer program stored in the memory and capable of running on the processor, wherein when the computer program is executed by the processor, the method for data processing of a multi-core processor according to any one of claims 1 to 7 is implemented.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the method for data processing of a multi-core processor according to any one of claims 1 to 7 is implemented.

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