Display panel and display device

Abstract

The invention discloses a display panel and a display device, and relates to the technical field of display, the display panel comprises a driving circuit, the driving circuit comprises N levels of shift registers cascaded with each other, and N is greater than or equal to 2; the shift register includes: a first control unit; a second control unit; a third control unit; the fourth control unit is used for receiving the third voltage signal and the fourth voltage signal and generating an output signal in response to the signal of the second node and the signal of the fourth node; wherein the third voltage signal is a high-level signal, and the fourth voltage signal is a low-level signal; the potential of the first voltage signal is higher than that of the third voltage signal, and / or the potential of the second voltage signal is lower than that of the fourth voltage signal. The shift register solves the problem that a shift register in the prior art cannot meet different voltage requirements of a pixel circuit for different signals.

Description

[0001] This application is a divisional application of the patent with the application date of January 8, 2021, application number 202110024241.X, and invention title "Display Panel and Display Device". Technical Field

[0002] The present invention relates to the field of display technologies, and more particularly, to a display panel and a display device. Background Art

[0003] Currently, display technologies are widely used in the display of televisions, mobile phones, and public information, bringing great convenience to people's daily lives and work. In the prior art, a scanning driving circuit is required in a display panel for displaying images to provide a driving signal to a pixel circuit to control the display panel to implement the function of running and scanning, so that the image data input to the display panel can be refreshed in real time, thereby realizing dynamic display.

[0004] However, the existing scanning driving circuit cannot meet the different voltage requirements of the pixel circuit for different signals. Summary of the Invention

[0005] In view of this, the present invention provides a display panel and a display device to solve the problem that the shift register in the prior art cannot meet the different voltage requirements of the pixel circuit for different signals.

[0006] The present invention provides a display panel, including: a driving circuit, the driving circuit includes N cascaded shift registers, N≥2; the shift register includes: a first control unit, the first control unit is used to receive an input signal and control the signal of a first node in response to a first clock signal; a second control unit, the second control unit is used to receive a first voltage signal and a second voltage signal, and control the signal of a second node in response to the signal of the first node, the first clock signal, and a second clock signal; a third control unit, the third control unit is used to receive the first voltage signal and the second voltage signal, and control the signal of a fourth node in response to the signal of the second node and the signal of a third node, wherein the third node is connected to the first node, the first voltage signal is a high-level signal, and the second voltage signal is a low-level signal; a fourth control unit, the fourth control unit is used to receive a third voltage signal and a fourth voltage signal, and generate an output signal in response to the signal of the second node and the signal of the fourth node; wherein, the third voltage signal is a high-level signal, and the fourth voltage signal is a low-level signal; the potential of the first voltage signal is higher than the potential of the third voltage signal, and / or the potential of the second voltage signal is lower than the potential of the fourth voltage signal.

[0007] Based on the same concept, the present invention further provides a display device, and the display device includes the above display panel.

[0008] Compared with the prior art, the display panel and the display device provided by the present invention achieve at least the following beneficial effects:

[0009] In the display panel provided by the present invention, the first control unit, the second control unit, and the third control unit control the signals of the second node and the fourth node based on the input signal, the first clock signal, the second clock signal, the first voltage signal, and the second voltage signal. The fourth control unit is configured to receive the third voltage signal and the fourth voltage signal, and generate an output signal in response to the signals of the second node and the fourth node controlled by the first control unit, the second control unit, and the third control unit. That is, the first control unit, the second control unit, and the third control unit are the control parts in the shift register and play a control role. The fourth control unit is the output part in the shift register and is used to generate the output signal. The voltage signals (the third voltage signal and the fourth voltage signal) received by the fourth control unit are separately set from the voltage signals (the first voltage signal and the second voltage signal) received by the first control unit, the second control unit, and the third control unit. That is, the voltage signals of the control part in the shift register are separately set from the voltage signals of the output part. Thus, the voltage signals received by the fourth control unit can be set according to the requirements of different signals for the pixel circuit in the display panel, and the required signals can be selectively output, improving the flexibility of the signals output by the driving circuit.

[0010] Moreover, since the potential of the first voltage signal is higher than the potential of the third voltage signal, and / or the potential of the second voltage signal is lower than the potential of the fourth voltage signal, the waveform stability of the output signal generated by the fourth control unit can be improved, thereby improving the stability of the signals output by the driving circuit.

[0011] Of course, it is not necessary for any product implementing the present invention to simultaneously achieve all the above-described technical effects.

[0012] Other features and advantages of the present invention will become clear from the following detailed description of the exemplary embodiments of the present invention with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The drawings incorporated in and constituting a part of this specification illustrate embodiments of the present invention and, together with the description, serve to explain the principles of the present invention.

[0014] Figure 1 is a schematic plan view of a display panel provided by the present invention;

[0015] Figure 2 is a schematic structural view of a driving circuit provided by the present invention;

[0016] Figure 3 is a schematic frame structural view of a shift register provided by the present invention;

[0017] Figure 4 It is a circuit schematic diagram of a shift register provided by the present invention;

[0018] Figure 5 It is a circuit schematic diagram of another shift register provided by the present invention;

[0019] Figure 6 It is a circuit schematic diagram of yet another shift register provided by the present invention;

[0020] Figure 7 It is a circuit schematic diagram of yet another shift register provided by the present invention;

[0021] Figure 8 It is a circuit schematic diagram of yet another shift register provided by the present invention;

[0022] Figure 9 It is a circuit schematic diagram of yet another shift register provided by the present invention;

[0023] Figure 10 It is a circuit schematic diagram of yet another shift register provided by the present invention;

[0024] Figure 11 It is a circuit schematic diagram of yet another shift register provided by the present invention;

[0025] Figure 12 It is a driving timing diagram of a shift register provided by the present invention;

[0026] Figure 13 It is another driving timing diagram of a shift register provided by the present invention;

[0027] Figure 14 It is a structural schematic diagram of another driving circuit provided by the present invention;

[0028] Figure 15 It is a structural schematic diagram of yet another driving circuit provided by the present invention;

[0029] Figure 16 It is a circuit schematic diagram of a pixel circuit provided by the present invention;

[0030] Figure 17 It is a circuit schematic diagram of another pixel circuit provided by the present invention;

[0031] Figure 18 It is a planar schematic diagram of another display panel provided by the present invention;

[0032] Figure 19 It is a planar schematic diagram of yet another display panel provided by the present invention;

[0033] Figure 20 This is a schematic plan view of a display device provided by the present invention. Detailed implementation manners

[0034] Now, various exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. It should be noted that: unless otherwise specifically stated, the relative arrangements of components and steps, numerical expressions and values set forth in these embodiments do not limit the scope of the present invention.

[0035] The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way a limitation on the present invention or its application or use.

[0036] Technologies, methods and devices known to those of ordinary skill in the relevant art may not be discussed in detail, but where appropriate, the said technologies, methods and devices should be regarded as part of the specification.

[0037] In all the examples shown and discussed herein, any specific values should be construed as merely exemplary and not as limitations. Therefore, other examples of the exemplary embodiments may have different values.

[0038] It should be noted that: like reference numerals and letters denote like items in the following drawings, and thus, once an item is defined in one drawing, it need not be further discussed in subsequent drawings.

[0039] Figure 1 This is a schematic plan view of a display panel provided by the present invention. Refer to Figure 1 , this embodiment provides a display panel, including: a driving circuit 100 and a plurality of pixels 200, and each pixel 200 is provided with a pixel circuit 210. The driving circuit 100 is connected to the pixel circuit 210 through signal lines to provide a driving signal to the pixel circuit 210, so that the pixel circuit 210 drives the pixel 200 to emit light for displaying an image.

[0040] It should be noted that Figure 1 only one structure of the display panel is taken as an example for illustration Figure 1 and it is exemplarily shown that the driving circuit 200 is located on one side of the display panel. In other embodiments of the present invention, the driving circuit 200 may also be located on both sides of the display panel, and the present invention will not elaborate herein.

[0041] Figure 2 This is a schematic structural view of a driving circuit provided by the present invention. Figure 3 This is a schematic framework structure view of a shift register provided by the present invention. Refer to Figure 2 and Figure 3, in the embodiment of the present invention, the driving circuit 100 in the display panel includes N cascaded shift registers 110, where N≥2;

[0042] The shift register 110 in the driving circuit 100 includes a first control unit 10, a second control unit 20, a third control unit 30, and a fourth control unit 40.

[0043] Among them, the first control unit 10 is configured to receive an input signal IN and control the signal of the first node N1 in response to the first clock signal CK;

[0044] The second control unit 20 is configured to receive a first voltage signal VGH1 and a second voltage signal VGL1, and control the signal of the second node N2 in response to the signal of the first node N1, the first clock signal CK, and the second clock signal XCK;

[0045] The third control unit 30 is configured to receive the first voltage signal VGH1 and the second voltage signal VGL1, and control the signal of the fourth node N4 in response to the signal of the second node N2 and the signal of the third node N3, where the third node N3 is connected to the first node N1, the first voltage signal VGH1 is a high-level signal, and the second voltage signal VGL1 is a low-level signal;

[0046] The fourth control unit 40 is configured to receive a third voltage signal VGH2 and a fourth voltage signal VGL2, and generate an output signal OUT in response to the signal of the second node N2 and the signal of the fourth node N4; where the third voltage signal VGH2 is a high-level signal, and the fourth voltage signal VGL2 is a low-level signal; the potential of the first voltage signal VGH1 is higher than the potential of the third voltage signal VGH2, and / or, the potential of the second voltage signal VGL1 is lower than the potential of the fourth voltage signal VGL2.

[0047] Specifically, in the embodiments of the present invention, the first control unit 10, the second control unit 20, and the third control unit 30 control the signals of the second node N2 and the signals of the fourth node N4 based on the input signal IN, the first clock signal CK, the second clock signal XCK, the first voltage signal VGH1, and the second voltage signal VGL1. The fourth control unit 40 is configured to receive the third voltage signal VGH2 and the fourth voltage signal VGL2, and generate an output signal OUT in response to the signals of the second node N2 and the signals of the fourth node N4 controlled by the first control unit 10, the second control unit 20, and the third control unit 30. That is, the first control unit 10, the second control unit 20, and the third control unit 30 are the control parts in the shift register 110 and play a control role. The fourth control unit 40 is the output part in the shift register 110 and is used to generate the output signal. The voltage signals received by the fourth control unit 40 (the third voltage signal VGH2 and the fourth voltage signal VGL2) and the voltage signals received by the first control unit 10, the second control unit 20, and the third control unit 30 (the first voltage signal VGH1 and the second voltage signal VGL1) are separately set. That is, the voltage signals of the control part in the shift register 110 and the voltage signals of the output part are separately set. Thus, the voltage signals received by the fourth control unit 40 can be set according to the requirements of different signals for the pixel circuit in the display panel, and the required signals can be selectively output, improving the flexibility of the signals output by the driving circuit 100.

[0048] Moreover, since the potential of the first voltage signal VGH1 is higher than the potential of the third voltage signal VGH2, and / or the potential of the second voltage signal VGL1 is lower than the potential of the fourth voltage signal VGL2, the waveform stability of the output signal OUT generated by the fourth control unit 40 can be improved, thereby improving the stability of the signals output by the driving circuit 100.

[0049] Figure 4 is a circuit schematic diagram of a shift register provided by the present invention. Refer to Figure 4 , optionally, wherein the fourth control unit 40 includes a first transistor M1 and a second transistor M2;

[0050] The first transistor M1 receives the third voltage signal VGH2, and the second transistor M2 receives the fourth voltage signal VGL2 to generate the output signal OUT.

[0051] Specifically, the fourth control unit 40 includes a first transistor M1 and a second transistor M2. The first transistor M1 receives a third voltage signal VGH2, and the second transistor M2 receives a fourth voltage signal VGL2, and an output signal OUT is generated. The output signal OUT is controlled by the first transistor M1 and the second transistor M2 respectively. When the first transistor M1 is turned on, the output signal OUT is the third voltage signal VGH2, and when the second transistor M2 is turned on, the output signal OUT is the fourth voltage signal VGL2.

[0052] Continue to refer to Figure 4 , optionally, wherein both the first transistor M1 and the second transistor M2 are PMOS transistors;

[0053] The source of the first transistor M1 is connected to the third voltage signal VGH2, the drain is connected to the output signal OUT, and the gate is connected to the fourth node N4;

[0054] The source of the second transistor M2 is connected to the fourth voltage signal VGL2, the drain is connected to the output signal OUT, and the gate is connected to the second node N2.

[0055] Specifically, when the fourth node N4 is at a low level, the first transistor M1 is turned on, and the third voltage signal VGH2 is transmitted to the drain of the first transistor M1 to generate the output signal OUT. When the fourth node N4 is at a high level, the first transistor M1 is turned off. When the second node N2 is at a low level, the second transistor M2 is turned on, and the fourth voltage signal VGL2 is transmitted to the drain of the second transistor M2 to generate the output signal OUT. When the second node N2 is at a high level, the second transistor M2 is turned off. That is, the high level of the output signal OUT is determined by the fourth node N4, and the low level of the output signal OUT is determined by the second node N2.

[0056] Figure 5 is a circuit schematic diagram of another shift register provided by the present invention. Refer to Figure 5 , optionally, wherein both the first transistor M1 and the second transistor M2 are NMOS transistors;

[0057] The source of the first transistor M1 is connected to the third voltage signal VGH2, the drain is connected to the output signal OUT, and the gate is connected to the second node N2;

[0058] The source of the second transistor M2 is connected to the fourth voltage signal VGL2, the drain is connected to the output signal OUT, and the gate is connected to the fourth node N4.

[0059] Specifically, when the second node N2 is at a low level, the first transistor M1 is turned off. When the second node N2 is at a high level, the first transistor M1 is turned on, and the third voltage signal VGH2 is transmitted to the drain of the first transistor M1 to generate the output signal OUT. When the fourth node N4 is at a low level, the second transistor M2 is turned off. When the fourth node N4 is at a high level, the second transistor M2 is turned on, and the fourth voltage signal VGL2 is transmitted to the drain of the second transistor M2 to generate the output signal OUT. That is, the high level of the output signal OUT is determined by the second node N2, and the low level of the output signal OUT is determined by the fourth node N4.

[0060] Figure 6 is a circuit schematic diagram of another shift register provided by the present invention. Refer to Figure 6 Optionally, among them, both the first transistor M1 and the second transistor M2 are PMOS transistors;

[0061] The source of the first transistor M1 is connected to the third voltage signal VGH2, the drain is connected to the output signal OUT, and the gate is connected to the second node N2;

[0062] The source of the second transistor M2 is connected to the fourth voltage signal VGL2, the drain is connected to the output signal OUT, and the gate is connected to the fourth node N4.

[0063] Specifically, when the second node N2 is at a high level, the first transistor M1 is turned on, and the third voltage signal VGH2 is transmitted to the drain of the first transistor M1 to generate the output signal OUT. When the second node N2 is at a low level, the first transistor M1 is turned off. When the fourth node N4 is at a high level, the second transistor M2 is turned on, and the fourth voltage signal VGL2 is transmitted to the drain of the second transistor M2 to generate the output signal OUT. When the fourth node N4 is at a low level, the second transistor M2 is turned off. That is, the high level of the output signal OUT is determined by the second node N2, and the low level of the output signal OUT is determined by the fourth node N4.

[0064] Figure 7 is a circuit schematic diagram of another shift register provided by the present invention. Refer to Figure 7 Optionally, among them, both the first transistor M1 and the second transistor M2 are NMOS transistors;

[0065] The source of the first transistor M1 is connected to the third voltage signal VGH2, the drain is connected to the output signal OUT, and the gate is connected to the fourth node N4;

[0066] The source of the second transistor M2 is connected to the fourth voltage signal VGL2, the drain is connected to the output signal OUT, and the gate is connected to the second node N2.

[0067] Specifically, when the fourth node N4 is at a low level, the first transistor M1 is turned off. When the fourth node N4 is at a high level, the first transistor M1 is turned on, and the third voltage signal VGH2 is transmitted to the drain of the first transistor M1 to generate the output signal OUT. When the second node N2 is at a low level, the second transistor M2 is turned off. When the second node N2 is at a high level, the second transistor M2 is turned on, and the fourth voltage signal VGL2 is transmitted to the drain of the second transistor M2 to generate the output signal OUT. That is, the high level of the output signal OUT is determined by the fourth node N4, and the low level of the output signal OUT is determined by the second node N2.

[0068] Based on any of the above embodiments, in some embodiments of the present invention, in order to ensure the stability of the potentials of the second node N2 and the fourth node N4 and ensure the stability of the output signal OUT, optionally, the fourth control unit 40 further includes a first capacitor C1 and a second capacitor C2.

[0069] Figure 8 is a circuit schematic diagram of another shift register provided by the present invention. Refer to Figure 8 , the first plate of the first capacitor C1 is connected to the second voltage signal VGL1, and the second plate of the first capacitor C1 is connected to the fourth node N4. The first plate of the second capacitor C2 is connected to the second node N2, and the second plate of the second capacitor C2 is connected to the fourth voltage signal VGL2.

[0070] Figure 9 is a circuit schematic diagram of another shift register provided by the present invention. Refer to Figure 9 , the first plate of the first capacitor C1 is connected to the second voltage signal VGL1, and the second plate of the first capacitor C1 is connected to the fourth node N4. The first plate of the second capacitor C2 is connected to the second node N2, and the second plate of the second capacitor C2 is connected to the third voltage signal VGH2.

[0071] Figure 10 is a circuit schematic diagram of another shift register provided by the present invention. Refer to Figure 9 and Figure 10 , the first plate of the first capacitor C1 is connected to the second voltage signal VGL1, and the second plate of the first capacitor C1 is connected to the fourth node N4. The first plate of the second capacitor C2 is connected to the second node N2, and the second plate of the second capacitor C2 is connected to the third voltage signal VGH2.

[0072] Figure 11 is a circuit schematic diagram of another shift register provided by the present invention. Refer to Figure 11, the first plate of the first capacitor C1 is connected to the second voltage signal VGL1, and the second plate of the first capacitor C1 is connected to the fourth node N4. The first plate of the second capacitor C2 is connected to the second node N2, and the second plate of the second capacitor C2 is connected to the fourth voltage signal VGL2.

[0073] In other embodiments of the present application, the second plate of the first capacitor C1 is connected to the fourth node N4, and the connection method of the first plate of the first capacitor C1 can be adjusted. The first plate is connected to one of the first voltage signal VGH1, the second voltage signal VGL1, the third voltage signal VGH2, the fourth voltage signal VGL2, and the output signal OUT, and the potential of the fourth node N4 is stabilized by a fixed potential or an output signal.

[0074] The first plate of the second capacitor C2 is connected to the second node N2, and the connection method of the second plate of the second capacitor C2 can be adjusted. The second plate is connected to one of the first voltage signal VGH1, the second voltage signal VGL1, the third voltage signal VGH2, the fourth voltage signal VGL2, and the output signal OUT, and the potential of the second node N2 is stabilized by a fixed potential or an output signal.

[0075] Based on any of the above embodiments, as Figures 8 to 11 shown, optionally, the first control unit 10 includes: a fifth transistor M5, the source of the fifth transistor M5 is connected to the input signal IN, the drain is connected to the first node N1, and the gate is connected to the first clock signal CK.

[0076] The second control unit 20 includes: a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, a tenth transistor M10, an eleventh transistor M11, a twelfth transistor M12, and a fifth capacitor C5. Among them, the source of the sixth transistor M6 is connected to the first node N1, the drain is connected to the drain of the seventh transistor M7, and the gate is connected to the second clock signal XCK; the source of the seventh transistor M7 is connected to the first voltage signal VGH1, the drain is connected to the drain of the sixth transistor M6, and the gate is connected to the fifth node N5; the source of the eighth transistor M8 is connected to the first clock signal CK, the drain is connected to the fifth node N5, and the gate is connected to the first node N1; the source of the ninth transistor M9 is connected to the second clock signal XCK, the drain is connected to the fifth node N5, and the gate is connected to the first clock signal CK; the source of the tenth transistor M10 is connected to the second clock signal XCK, the drain is connected to the sixth node N6, and the gate is connected to the fifth node N5; the source of the eleventh transistor M11 is connected to the sixth node N6, the drain is connected to the second node N2, and the gate is connected to the second clock signal XCK; the source of the twelfth transistor M12 is connected to the first voltage signal VGH1, the drain is connected to the second node N2, and the gate is connected to the third node N3; the first pole of the fifth capacitor C5 is connected to the fifth node N5, and the second pole of the fifth capacitor C5 is connected to the sixth node N6.

[0077] Based on any of the above embodiments, as Figures 8 to 11 shown, optionally, the second control unit 20 further includes a thirteenth transistor M13 and a fourteenth transistor M14.

[0078] Among them, the source of the thirteenth transistor M13 is connected to the fifth node N5, the drain is connected to the gate of the tenth transistor M10, and the gate is connected to the second voltage signal VGL1; the source of the fourteenth transistor M14 is connected to the first node N1, the drain is connected to the third node N3, and the gate is connected to the second voltage signal VGL1.

[0079] Based on any of the above embodiments, as Figures 8 to 11 shown, optionally, the third control unit 30 includes a third transistor M3 and a fourth transistor M4.

[0080] Among them, the source of the third transistor M3 is connected to the first voltage signal VGH1, the drain is connected to the fourth node N4, and the gate is connected to the second node N2; the source of the fourth transistor M4 is connected to the second voltage signal VGL1, the drain is connected to the fourth node N4, and the gate is connected to the third node N3.

[0081] Since the first transistor M1 and the second transistor M2 are output transistors, in order to ensure the stability of the output signal OUT, higher requirements are imposed on the output performance of the first transistor M1 and the second transistor M2. Therefore, in some embodiments of the present invention, in order to improve the output performance of the first transistor M1 and the second transistor M2, the aspect ratio of the channel region of the first transistor M1 is greater than the aspect ratio of the channel region of the third transistor M3, and / or the aspect ratio of the channel region of the second transistor M2 is greater than the aspect ratio of the channel region of the fourth transistor M4.

[0082] Based on any of the above embodiments, as Figures 8 to 11 shown, optionally, the third control unit 30 further includes a third capacitor C3 and a fourth capacitor C4.

[0083] Wherein, the first plate of the third capacitor C3 is connected to the first voltage signal VGH1, and the second plate of the third capacitor C3 is connected to the second node N2; the first plate of the fourth capacitor C4 is connected to the second clock signal XCK or the second voltage signal VGL1, and the second plate of the fourth capacitor C4 is connected to the third node N3.

[0084] Since the functions of the first capacitor C1 and the second capacitor C2 are to stabilize the potentials of the second node N2 and the fourth node N4, and thus stabilize the output signal OUT, the capacitances of the first capacitor C1 and the second capacitor C2 need to be large enough to ensure that the potentials of the second node N2 and the fourth node N4 will not easily fluctuate.

[0085] Based on this, in some embodiments of the present invention, the capacitance value of the first capacitor C1 and the capacitance value of the second capacitor C2 are greater than the capacitance value of the third capacitor C3 and greater than the capacitance value of the fourth capacitor C4. Of course, the present invention is not limited thereto. In some other embodiments, in order to simplify the manufacturing process, the capacitance values of the first capacitor C1, the second capacitor C2, the third capacitor C3, and the fourth capacitor C4 can also be made equal.

[0086] Optionally, in some other embodiments of the present invention, in order to ensure the stability of the potentials of the second node N2 and the fourth node N4, the capacitance value of the fifth capacitor C5 can also be made less than the capacitance value of the first capacitor C1 and less than the capacitance value of the second capacitor C2. And since the stability of the second node N2 and the fourth node N4 affects the stability of the output signal OUT, while the stability of the fifth node N5 has little effect on the stability of the output signal OUT, the fifth capacitor C5 can be set to be smaller to save space.

[0087] Optionally, in some other embodiments of the present invention, the capacitance value of the fifth capacitor C5 is less than the capacitance value of the third capacitor C3 and less than the capacitance value of the fourth capacitor C4. The fifth capacitor C5 can be further set to be even smaller to save space.

[0088] The working process of the shift register according to the present invention will be described below in conjunction with the timing diagrams of the signals in the shift register.

[0089] Figure 12 is a driving timing diagram of the shift register provided by the present invention. Please refer to Figure 8 and Figure 12 .

[0090] In the T1 stage, the input signal IN is at a high level, the first clock signal CK is at a low level, the fifth transistor M5 is turned on, the input signal IN is transmitted to the first node N1, making the first node N1 at a high level, the ninth transistor M9 is turned on, the second voltage signal VGL1 is transmitted to the fifth node N5, making the fifth node N5 at a low level, the tenth transistor M10 is turned on, the second clock signal XCK is at a high level, the sixth node N6 remains at a high level, the sixth transistor M6 is turned off, the eleventh transistor M11 is turned off, the twelfth transistor M12 is turned off, the second node N2 remains at a high level, the second transistor M2 is turned off, the third transistor M3 is turned off, the third node N3 remains at a high level, the fourth transistor M4 is turned off, the fourth node N4 remains at a low level, the first transistor M1 is turned on, the third voltage signal VGH2 is transmitted to the output terminal, making the output signal OUT at a high level.

[0091] In the T2 stage, the input signal IN is at a high level, the first clock signal CK is at a high level, the fifth transistor M5 is turned off, the ninth transistor M9 is turned off, the first node N1 remains at a high level, the second clock signal XCK is at a low level, the sixth transistor M6 is turned on, the eighth transistor M8 is turned off, the fifth node N5 remains at a low level, the tenth transistor M10 is turned on, the second clock signal XCK is transmitted to the sixth node N6, making the sixth node N6 at a low level, the eleventh transistor M11 is turned on, the signal of the sixth node N6 is transmitted to the second node N2, making the second node N2 at a low level, the third transistor M3 is turned on, the first voltage signal VGH1 is transmitted to the fourth node N4, making the fourth node N4 at a high level, the first transistor M1 is turned off, the second transistor M2 is turned on, the fourth voltage signal VGL2 is transmitted to the output terminal, making the output signal OUT at a low level.

[0092] In the T3 stage, the input signal IN is at a high level, the first clock signal CK is at a low level, the fifth transistor M5 is turned on, the input signal IN is transmitted to the first node N1, making the first node N1 at a high level, the ninth transistor M9 is turned on, the second voltage signal VGL1 is transmitted to the fifth node N5, making the fifth node N5 at a low level, the tenth transistor M10 is turned on, the second clock signal XCK is at a high level, the sixth node N6 remains at a high level, the sixth transistor M6 is turned off, the eleventh transistor M11 is turned off, the twelfth transistor M12 is turned off, the third transistor M3 is turned off, the third node N3 remains at a high level, the fourth transistor M4 is turned off, the fourth node N4 remains at a high level, the first transistor M1 is turned off, the second node N2 remains at a low level, the second transistor M2 is turned on, the fourth voltage signal VGL2 is transmitted to the output terminal, making the output signal OUT at a low level.

[0093] In the T4 stage, the input signal IN is at a low level, the first clock signal CK is at a high level, the fifth transistor M5 is turned off, the ninth transistor M9 is turned off, the first node N1 remains at a high level, the second clock signal XCK is at a low level, the sixth transistor M6 is turned on, the eighth transistor M8 is turned off, the fifth node N5 remains at a low level, the tenth transistor M10 is turned on, the second clock signal XCK is transmitted to the sixth node N6, making the sixth node N6 at a low level, the eleventh transistor M11 is turned on, the signal of the sixth node N6 is transmitted to the second node N2, making the second node N2 at a low level, the third transistor M3 is turned on, the first voltage signal VGH1 is transmitted to the fourth node N4, making the fourth node N4 at a high level, the first transistor M1 is turned off, the second transistor M2 is turned on, the fourth voltage signal VGL2 is transmitted to the output terminal, making the output signal OUT at a low level.

[0094] In the T5 stage, the input signal IN is at a low level, the first clock signal CK is at a low level, the fifth transistor M5 is turned on, the input signal IN is transmitted to the first node N1, making the first node N1 at a low level, the ninth transistor M9 is turned on, the second voltage signal VGL1 is transmitted to the fifth node N5, making the fifth node N5 at a low level, the tenth transistor M10 is turned on, the second clock signal XCK is at a high level, the sixth node N6 remains at a high level, the sixth transistor M6 is turned off, the eleventh transistor M11 is turned off, the first node N1 controls the twelfth transistor M12 to be turned on, the first voltage signal VGH1 is transmitted to the second node N2, making the second node N2 at a high level, the third transistor M3 is turned off, the second transistor M2 is turned off, the fourteenth transistor M14 is turned on, the signal of the first node N1 is transmitted to the third node N3, the third node N3 is at a low level, the third node N3 controls the fourth transistor M4 to be turned on, the second voltage signal VGL1 is transmitted to the fourth node N4, making the fourth node N4 at a low level, the first transistor M1 is turned on, the third voltage signal VGH2 is transmitted to the output terminal, making the output signal OUT at a high level.

[0095] Figure 9 In the shift register shown, although the types of the first transistor M1 and the second transistor M2 are different from Figure 8 the types of the first transistor M1 and the second transistor M2 in the shift register shown, however, in the T1 stage to the T5 stage, the levels of the first node N1, the second node N2, the third node N3, the fourth node N4 and the fifth node N5 are the same as the above process, Figure 9 the voltage signal input to the first transistor M1 in Figure 8 is different from the voltage signal input to the first transistor M1 in Figure 9 the voltage signal input to the second transistor M2 in Figure 8 is also different from the voltage signal input to the second transistor M2 in Figure 9 therefore, the level of the output signal OUT in Figure 8 is the same as the level of the output signal OUT in Figure 9 That is, the timing diagram of the signals of each node in the shift register shown in Figure 12 is also as shown in

[0096] Figure 10 In the shift register shown, only the connection nodes of the first transistor M1 and the second transistor M2 are different from Figure 8 the connection nodes shown in Figure 12 therefore, in the T1 stage to the T5 stage, the levels of the first node N1, the second node N2, the third node N3, the fourth node N4 and the fifth node N5 are the same as the above process, and the difference is only in the level of the output signal OUT. As shown in Figure 12 shown, the change state of the level of the output signal OUT is the same as the change state of the level of the second node N2.Figure 13 is another driving timing diagram of the shift register provided by the present invention. Please refer to Figure 10 and Figure 13 . The level change state of the output signal OUT is the same as the level change state of the fourth node N4.

[0097] Figure 11 In the shift register shown, although the types of the first transistor M1 and the second transistor M2 are different from those of the first transistor M1 and the second transistor M2 in the shift register shown in Figure 10 , during the stages from T1 to T5, the levels of the first node N1, the second node N2, the third node N3, the fourth node N4, and the fifth node N5 are the same as those in the above process. Figure 11 The voltage signal input to the first transistor M1 in Figure 10 is different from the voltage signal input to the first transistor M1 in Figure 11 . The voltage signal input to the second transistor M2 in Figure 10 is also different from the voltage signal input to the second transistor M2 in Figure 11 . Therefore, the level of the output signal OUT in Figure 10 is the same as the level of the output signal OUT in Figure 11 . That is, the timing diagram of the signals of each node in the shift register shown in Figure 13 is also as shown in

[0098] It should be noted that since the first transistor M1 and the second transistor M2 generate the output signal OUT under the control of the fourth node N4 and the second node N2 respectively, and the high-level signal and the low-level signal of the second node N2 and the fourth node N4 are the first voltage signal VGH1 and the second voltage signal VGL1 respectively, that is, the control signals of the fourth control unit 40 are the first voltage signal VGH1 and the second voltage signal VGL1, and the received signals of the fourth control unit 40 are the third voltage signal VGH2 and the fourth voltage signal VGL2. Therefore, when the potential of the first voltage signal VGH1 is higher than the potential of the third voltage signal VGH2, and / or, the potential of the second voltage signal VGL1 is lower than the potential of the fourth voltage signal VGL2, the control signals of the fourth control unit 40 can have a higher level or a lower level than the received signals.

[0099] When the first transistor M1 and the second transistor M2 are PMOS transistors, when receiving a low level, if the level of the control signal is lower than the received low-level signal, it can ensure that the PMOS transistor operates in a more saturated state, thereby ensuring the stability of the output signal OUT and reducing the trailing phenomenon of signal output. Additionally, when the control signal is at a higher high level, if the level received by the PMOS transistor is also high, it can fully ensure that the PMOS transistor is turned off, fully reducing the risk of leakage current. Therefore, in the embodiments of the present invention, the stability of the output waveform can be fully improved, avoiding problems such as trailing and leakage current.

[0100] Similarly, when the first transistor M1 and the second transistor M2 are NMOS transistors, when receiving a high level, if the level of the control signal is higher than the received high-level signal, it can ensure that the NMOS transistor operates in a more saturated state, thereby ensuring the stability of the output signal OUT and reducing the trailing phenomenon of signal output. Additionally, when the control signal is at a lower low level, if the level received by the NMOS transistor is also low, it can fully ensure that the NMOS transistor is turned off, fully reducing the risk of leakage current. Therefore, in the embodiments of the present invention, the stability of the output waveform can be fully improved, avoiding problems such as trailing and leakage current.

[0101] In Figure 8 and Figure 10 Based on the shift register shown, optionally, the aspect ratio of the channel region of the second transistor M2 is greater than or equal to the aspect ratio of the channel region of the first transistor M1.

[0102] Specifically, since the second transistor M2 is the transistor connected to the fourth voltage signal VGL2, when the fourth voltage signal VGL2 is transmitted to the output terminal, making the output signal OUT at a low level, the potential of the second node N2 is at a low potential. For a PMOS transistor, when the source and the gate are both at a low potential, to ensure the stability of the low-level signal output by the PMOS transistor, that is, the output signal OUT, it is necessary to improve the output ability of the PMOS transistor as much as possible. And since the larger the aspect ratio of the channel region of the PMOS transistor, the stronger the output ability of the PMOS transistor, therefore, it is necessary to appropriately increase the aspect ratio of the channel region of the PMOS transistor.

[0103] For the first transistor M1, the third voltage signal VGH2 it is connected to is a high-level signal. When the fourth node N4 is at a low level, the PMOS transistor operates in a relatively saturated state and is fully turned on. Therefore, the requirement for its output ability is less than that of the second transistor M2, and its aspect ratio can be set appropriately smaller.

[0104] Based on this, in some embodiments of the present invention, the aspect ratio of the channel region of the second transistor M2 can be made greater than that of the channel region of the first transistor M1. Similarly, in order to simplify the manufacturing process, the aspect ratio of the channel region of the second transistor M2 can also be made equal to that of the channel region of the first transistor M1.

[0105] Of course, on the basis of the shift register shown in Figure 9 and Figure 11 , in some embodiments of the present invention, the aspect ratio of the channel region of the second transistor M2 can also be greater than or equal to that of the channel region of the first transistor M1. The reason is similar to the above reason and will not be elaborated here.

[0106] On the basis of the shift register shown in Figure 8 , optionally, the capacitance value of the first capacitor C1 is less than or equal to the capacitance value of the second capacitor C2.

[0107] Since the second plate of the second capacitor C2 is connected to the fourth voltage signal VGL2, the first plate of the second capacitor C2 is connected to the second node N2, the source of the second transistor M2 is connected to the fourth voltage signal VGL2, and the gate is connected to the second node N2. When the second transistor M2 is a PMOS transistor and the second node N2 is at a low level signal, the output of the second transistor M2 is unstable. By increasing the capacitance value of the second capacitor C2, the stability of the potential of the second node N2 can be improved. At this time, the capacitance value of the first capacitor C1 can be set to be less than the capacitance value of the second capacitor C2. Of course, in order to simplify the production process, the capacitance value of the first capacitor C1 can also be set to be equal to the capacitance value of the second capacitor C2.

[0108] On the basis of the shift register shown in Figures 9 - 11 , in some embodiments of the present invention, the capacitance value of the first capacitor C1 can also be less than or equal to the capacitance value of the second capacitor C2, which will not be elaborated here.

[0109] Continuing to refer to Figure 1 , Figure 2 and Figure 8 , optionally, the driving circuit includes N - stage shift registers, that is, it includes N cascaded shift registers ASG1 to ASGN. In the N - stage shift registers of the driving circuit, the signal of the fourth node N4 of the M - th stage shift register is connected to the input signal terminal of the (M + 1) - th stage shift register as the input signal of the (M + 1) - th stage shift register, where 1 ≤ M ≤ N.

[0110] Specifically, in the driving circuit, the signal Next of the fourth node N4 of the upper-level shift register serves as the input signal IN of the lower-level shift register, and the output signal OUT of each level of the shift register is used as the driving signal and input into the pixel circuit. However, the present invention is not limited thereto. In some other embodiments, as Figure 13 shown, when the change states of the output signal OUT and the fourth node N4 are the same, the output signal OUT of the Mth-level shift register can also be used as the input signal IN of the (M + 1)th-level shift register, and the signal Next of the fourth node N4 is used as the driving signal and input into the pixel circuit.

[0111] Continuing to refer to Figure 1 and Figure 2 , optionally, the display panel further includes:

[0112] The first voltage signal line XVGH1 provides the first voltage signal VGH1 for the driving circuit;

[0113] The second voltage signal line XVGL1 provides the second voltage signal VGL1 for the driving circuit;

[0114] The third voltage signal line XVGH2 provides the third voltage signal VGH2 for the driving circuit;

[0115] The fourth voltage signal line XVGL2 provides the fourth voltage signal VGL2 for the driving circuit.

[0116] Since the third voltage signal VGH2 and the fourth voltage signal VGL2 are used to generate the output signal OUT, and the output signal OUT is used to provide the driving signal for the pixel circuit 210 in the display area AA of the display panel, in order to save the space of the driving circuit 100 as much as possible and avoid too long wiring, the third voltage signal line XVGH2 and the fourth voltage signal line XVGL2 can be arranged on the side close to the display area AA.

[0117] Based on this, in some embodiments of the present invention, at least one of the third voltage signal line XVGH2 and the fourth voltage signal line XVGL2 is located on the side of at least one of the first voltage signal line XVGH1 and the second voltage signal line XVGL1 facing the display area of the display panel.

[0118] Continuing to refer to Figure 2, Optionally, the first voltage signal line XVGH1, the second voltage signal line XVGL1, the third voltage signal line XVGH2, and the fourth voltage signal line XVGL2 are all located on the side of the driving circuit 100 away from the display area AA of the display panel. Moreover, both the third voltage signal line XVGH2 and the fourth voltage signal line XVGL2 are located on the side of the first voltage signal line XVGH1 and the second voltage signal line XVGL1 closer to the display area AA, that is, on the side facing the display area AA of the display panel, so as to maximize the saving of the space of the driving circuit 100 and shorten the routing length.

[0119] Of course, the present invention is not limited thereto. Optionally, as Figure 14 shown, Figure 14 is a schematic structural diagram of another driving circuit provided by the present invention. Among them, the first voltage signal line XVGH1 and the second voltage signal line XVGL1 are located on the side of the driving circuit away from the display area AA of the display panel; the third voltage signal line XVGH2 and the fourth voltage signal line XVGL2 are located on the side of the driving circuit facing the display area AA of the display panel, so as to further save the space of the driving circuit 11 and shorten the routing length.

[0120] Since the potential of the first voltage signal VGH1 is higher than that of the third voltage signal VGH2, and / or the potential of the second voltage signal VGL1 is lower than that of the fourth voltage signal VGL2, therefore, the voltage values carried on the first voltage signal line XVGH1 and the second voltage signal line XVGL1 are larger. If their line widths are smaller, the resistance is larger, and the voltage loss on them will be greater. Therefore, optionally, the line width of at least one of the first voltage signal line XVGH1 and the second voltage signal line XVGL1 is greater than the line width of at least one of the third voltage signal line XVGH2 and the fourth voltage signal line XVGL2.

[0121] In the shift register, since the first transistor M1 and the second transistor M2 generate the output signal OUT, and the first transistor M1 and the second transistor M2 are generally transistors with a large width-to-length ratio, therefore, in order to further reduce the border of the display panel and reduce the space of the driving circuit 100, optionally, referring to Figure 15 , Figure 15 is a schematic structural diagram of another driving circuit provided by the present invention. Among them, the shift registers 110 are cascaded with each other along the first direction X1, and the first transistor M1 and the second transistor M2 are arranged along the second direction X2, where the first direction X1 is parallel to the second direction X2.

[0122] Continuing to refer to Figure 1 , Optionally, the display panel includes a pixel circuit 210, and the driving circuit 100 provides a first driving signal for the pixel circuit 210 through the first driving signal line 120, and the first driving signal is the output signal OUT.

[0123] Figure 16 is a circuit schematic diagram of a pixel circuit provided by the present invention, Figure 17 is a circuit schematic diagram of another pixel circuit provided by the present invention. Referring to Figure 16 and Figure 17 , the pixel circuit includes a driving transistor T0. Among them, Figure 16 the driving transistor T0 in Figure 17 is a PMOS transistor,

[0124] the driving transistor T0 in

[0125] is an NMOS transistor. Of course, the pixel driving circuit further includes other transistors T1 to T6 and other signal input terminals, which are not elaborated herein by the present invention. Figure 16

[0126] Figure 17

[0127] Figure 16

[0128] When the driving transistor T0 is a PMOS transistor, the gate reset mainly gives a low-level signal to the gate. However, in order to achieve high-frequency refreshing of the display panel, the gate reset signal should not be too low to shorten Figure 16 the charging time of the N1' node in the data writing stage in GL2 Therefore, the absolute value V of the fourth voltage signal VGL2 GH2 needs to be set smaller. And the absolute value V of the third voltage signal VGH2 GH2 corresponds to the non-reset stage, and it is required to be a relatively high level to ensure that the gate of the driving transistor T0 is not affected by this signal during the non-reset stage. Therefore, for the PMOS transistor, V

[0128] Based on this, optionally, the absolute value of the voltage of the first voltage signal VGH1 is V GH1 , and the absolute value of the voltage of the second voltage signal VGL1 is V GL1 , the absolute value of the voltage of the third voltage signal VGH2 is V GH2 , and the absolute value of the voltage of the fourth voltage signal VGL2 is V GL2 ; where, when the driving transistor T0 is a PMOS transistor, then ∣V GH1 - V GH2 | ≤ |V GL1 - V GL2 |; or, when the driving transistor T0 is an NMOS transistor, then ∣V GH1 - V GH2 | ≥ |V GL1 - V GL2 |.

[0129] Furthermore, for a PMOS transistor, if |V GL1 - V GL2 | ≥ V GL2 , for example, V GH1 is 9V and V GL2 is only 4V, then |V GL1 - V GL2 | is greater than V GL2 , then it can be ensured that during the reset stage, the potential of the gate of the driving transistor T0 will not be too low, ensuring the stable operation of the driving transistor T0. For an NMOS transistor, the level situation is exactly the opposite, but the principle is the same.

[0130] Based on this, optionally, when the driving transistor T0 is a PMOS transistor, ∣V GH1 - V GH2 | ≤ V GH2 , and |V GL1 - V GL2 | ≥ V GL2 ; or, when the driving transistor is an NMOS transistor, then ∣V GH1 - V GH2 | ≥ V GH2 , and |V GL1 - V GL2 | ≤ V GL2 .

[0131] Continuing to refer to Figure 16 and Figure 17 , optionally, the pixel circuit includes a data writing module 211, a compensation module 212, and a reset module 213;

[0132] The data writing module 211 is connected to the source of the driving transistor T0;

[0133] The compensation module 212 is connected between the gate and the drain of the driving transistor T0;

[0134] The reset module 213 is connected to the drain of the driving transistor T0;

[0135] The working process of the pixel circuit includes a reset stage and a bias stage. In the reset stage, both the reset module 213 and the compensation module 212 are turned on, and the gate of the driving transistor T0 receives a reset signal; in the bias stage, the reset module 213 is turned on, and the compensation module 212 is turned off, and the drain of the driving transistor T0 receives a bias signal.

[0136] Specifically, when the output signal OUT of the shift register is Figure 16 V0 (Vref / Vbias) in, in the reset stage, the output signal OUT, i.e., the reset signal, is used to reset the gate of the driving transistor T0; in the bias stage, the reset module 213 is turned on, and the output signal OUT, i.e., the bias signal, is used to Figure 16 charge the N3' node in, so that Figure 16 the potential of the N3' node in is higher than Figure 16 the potential of the N1' node in, avoiding the leakage current flowing from the N1' node to the N3' node in the driving transistor T0, which causes the potential of the N1' node to drop and affects the display of the display panel.

[0137] When the output signal OUT of the shift register is Figure 17 Vobs / Vini in, in the reset stage, the output signal OUT, i.e., the reset signal, is used to reset the gate of the driving transistor T0; in the bias stage, the output signal OUT, i.e., the bias signal, is used to Figure 17 adjust the potential of the N3' node in, so that Figure 17 the potential of the N3' node in is lower than Figure 17 the potential of the N1' node in. Different from Figure 16 is that the levels of the reset signal and the bias signal are different.

[0138] Continue to refer to Figure 16 , optionally, where the reset signal is the fourth voltage signal VGL2, and the bias signal is the third voltage signal VGH2, or rather, the reset signal is the output signal OUT generated by the fourth voltage signal VGL2, and the bias signal is the output signal OUT generated by the third voltage signal VGH2.

[0139] Specifically, in Figure 16During the light-emitting stage of the pixel circuit shown, there may be a situation where the potential of the gate N1' node of the driving transistor T0 is higher than the potential of the drain N3' node. For example, if the N2' node is 4.6V, the N1' node is 3V, and the N3' node may be 2V. For a PMOS transistor, after a long time like this, it will affect the stability of the PMOS transistor. Therefore, it is necessary to set a bias stage during the non-light-emitting stage to raise the potential of the N3' node through a bias signal, thereby eliminating the above-mentioned influence during the light-emitting stage. To fully implement this process, the high-level signal VGH2 of the bias signal needs to be as high as possible, and the low-level signal VGL2 of the reset signal does not need to be set too low. Therefore, it can be set that ∣V GH1 -V GH2 |≤|V GL1 -V GL2 |.

[0140] Alternatively, referring to Figure 17 further, the driving transistor is an NMOS transistor, the reset signal is the third voltage signal VGH2, and the bias signal is the fourth voltage signal VGL2. Or rather, the reset signal is the output signal OUT generated by the third voltage signal VGH2, and the bias signal is the output signal OUT generated by the fourth voltage signal VGL2.

[0141] Specifically, during Figure 17 the light-emitting stage of the pixel circuit shown, there may be a situation where the potential of the gate N1' node of the driving transistor T0 is lower than the potential of the drain N3' node. For example, if the N3' node is 4.6V and the N1' node is 3V, for an NMOS transistor, after a long time like this, it will affect the stability of the NMOS transistor. Therefore, it is necessary to set a bias stage during the non-light-emitting stage to lower the potential of the N3' node through a bias signal, thereby eliminating the above-mentioned influence during the light-emitting stage. To fully implement this process, the low-level signal VGL2 of the bias signal needs to be as low as possible, and the high-level signal VGH2 of the reset signal does not need to be set too low. Therefore, it can be set that ∣V GH1 -V GH2 |≥|V GL1 -V GL2 |.

[0142] Figure 18 is a schematic plan view of another display panel provided by the present invention. Referring to Figure 18 further, optionally, the display panel further includes a light-emitting element 220, and the light-emitting element 220 includes a cathode, an anode, and a light-emitting layer located between the cathode and the anode. The driving circuit 100 provides a second driving signal for the pixel circuit 210 through the second driving signal line 130, and the second driving signal is the output signal OUT; wherein,

[0143] The anode of the light-emitting element 220 is coupled to the second driving signal line 130, and the second driving signal, i.e., the output signal OUT, is used to selectively reset the light-emitting element 220.

[0144] Specifically, the output signal OUT of the shift register is Figure 16 Vini in. When the transistor T4 is turned on, the output signal OUT of the shift register, i.e., Vini, is transmitted to the anode of the light-emitting element 220 to reset the anode of the light-emitting element 220.

[0145] Alternatively, the output signal OUT of the shift register is Figure 17 VAR in. When the transistor T5 is turned on, the output signal OUT of the shift register, i.e., VAR, is transmitted to the anode of the light-emitting element 220 to reset the anode of the light-emitting element 220.

[0146] In an embodiment of the present invention, the absolute value of the voltage of the first voltage signal VGH1 is V GH1 , the absolute value of the voltage of the second voltage signal VGH2 is V GL1 , the absolute value of the voltage of the third voltage signal VGH3 is V GH2 , and the absolute value of the fourth voltage signal VGH4 is V GL2 . Since the reset signal of the anode of the light-emitting element 220 is generally at a low level, therefore, optionally, |V GH1 - V GH2 | ≤ |V GL1 - V GL2 |.

[0147] Moreover, since in some application scenarios, the potential of the reset signal cannot be too low, therefore, optionally, where |V GH1 - V GH2 | ≤ V GH2 , and |V GL1 - V GL2 | ≥ V GL2 .

[0148] In the above embodiment, only an example in which the display panel includes one driving circuit is described, and the present invention is not limited thereto. Figure 19 is a schematic plan view of another display panel provided by the present invention. Referring to Figure 19 , optionally, the display panel includes a first driving circuit 140 and a second driving circuit 150. The first driving circuit 140 includes N1-stage shift registers connected in cascade, and the second driving circuit 150 includes N2-stage shift registers connected in cascade, where N1 ≥ 2 and N2 ≥ 2.

[0149] Among them, the potential of at least one of the third voltage signals in the first driving circuit 140 and the third voltage signal in the second driving circuit 150 is higher than that of the other; and / or, the potential of at least one of the fourth voltage signals in the first driving circuit 140 and the fourth voltage signal in the second driving circuit 150 is lower than that of the other, so that the voltages of the output signals of the first driving circuit 140 and the second driving circuit 150 are different, so as to meet the different voltage requirements of different signals in the pixel circuit 210.

[0150] Continue to refer to Figure 19 , optionally, among them, the display panel further includes a pixel circuit 210, the first driving circuit 140 provides a third driving signal for the pixel circuit 210, and the second driving circuit 150 provides a fourth driving signal for the pixel circuit 210, that is, the output signal of the first driving circuit 140 is the third driving signal of the pixel circuit 210, and the output signal of the second driving circuit 150 is the fourth driving signal of the pixel circuit 210. Among them, the third driving signal and the fourth driving signal are different driving signals, such as reset signals with different voltages, so as to meet the different voltage requirements of different signals in the pixel circuit 210. Of course, the present invention is not limited to this. In some other embodiments, the third driving signal and the fourth driving signal may also be signals with different timings to provide two signals with different timings to the pixel circuit 210. For example, one of the third driving signal and the fourth driving signal is a reset signal, and the other is a scanning signal.

[0151] In some alternative embodiments, please refer to Figure 20 , Figure 20 is a schematic plan view of a display device provided by the present invention. The display device 1000 provided in this embodiment includes the display panel 000 provided in the above embodiment of the present invention. Figure 20 This embodiment only takes a mobile phone as an example to illustrate the display device 1000. It can be understood that the display device 1000 provided in the embodiments of the present invention may also be other display devices 1000 with a display function, such as a computer, a television, a vehicle-mounted display device, etc. The present invention does not make specific limitations in this regard. The display device 1000 provided in the embodiments of the present invention has the beneficial effects of the display panel 100 provided in the embodiments of the present invention. For specific descriptions of the display panel 000, reference may be made to the above embodiments. This embodiment will not be elaborated here.

[0152] As can be seen from the above embodiments, the display panel and the display device provided by the present invention at least achieve the following beneficial effects:

[0153] In the display panel provided by the present invention, the first control unit, the second control unit, and the third control unit control the signals of the second node and the fourth node based on an input signal, a first clock signal, a second clock signal, a first voltage signal, and a second voltage signal. The fourth control unit is configured to receive a third voltage signal and a fourth voltage signal, and generate an output signal in response to the signals of the second node and the fourth node controlled by the first control unit, the second control unit, and the third control unit. That is, the first control unit, the second control unit, and the third control unit are the control part in the shift register and play a control role. The fourth control unit is the output part in the shift register and is used to generate the output signal. The voltage signals received by the fourth control unit (the third voltage signal and the fourth voltage signal) are separately set from the voltage signals received by the first control unit, the second control unit, and the third control unit (the first voltage signal and the second voltage signal). That is, the voltage signals of the control part in the shift register are separately set from the voltage signals of the output part. Thus, the voltage signals received by the fourth control unit can be set according to the requirements of different signals for the pixel circuit in the display panel, and the required signals can be selectively output, improving the flexibility of the signals output by the driving circuit.

[0154] Moreover, since the potential of the first voltage signal is higher than the potential of the third voltage signal, and / or the potential of the second voltage signal is lower than the potential of the fourth voltage signal, the waveform stability of the output signal generated by the fourth control unit can be improved, thereby improving the stability of the signals output by the driving circuit.

[0155] Although some specific embodiments of the present invention have been described in detail by way of examples, those skilled in the art should understand that the above examples are for illustrative purposes only and not for limiting the scope of the present invention. Those skilled in the art should understand that the above embodiments can be modified without departing from the scope and spirit of the present invention. The scope of the present invention is defined by the appended claims.

Claims

1. A display panel, characterized in that, comprising: a driving circuit, the driving circuit includes N cascaded shift registers, N≥2; the shift register includes: a third control unit for controlling the signal of the fourth node, the third control unit receives a first voltage signal and a second voltage signal, the first voltage signal is a high-level signal, and the second voltage signal is a low-level signal; a fourth control unit for generating an output signal, the fourth control unit receives a third voltage signal and a fourth voltage signal, the third voltage signal is a high-level signal, and the fourth voltage signal is a low-level signal; wherein, the display panel includes a pixel circuit, the driving circuit provides a first driving signal for selectively resetting the gate of the driving transistor of the pixel circuit; the absolute value of the voltage of the first voltage signal is VGH1, the absolute value of the voltage of the second voltage signal is VGL1, the absolute value of the voltage of the third voltage signal is VGH2, and the absolute value of the voltage of the fourth voltage signal is VGL2; wherein, if the driving transistor is a PMOS transistor, then |VGH1 - VGH2| ≤ |VGL1 - VGL2|; or, if the driving transistor is an NMOS transistor, then |VGH1 - VGH2| ≥ |VGL1 - VGL2|.

2. The display panel according to claim 1, characterized in that, if the driving transistor is a PMOS transistor, then |VGH1 - VGH2| ≤ VGH2, and / or, |VGL1 - VGL2| ≥ VGL2; or, if the driving transistor is an NMOS transistor, then |VGH1 - VGH2| ≥ VGH2, and / or, |VGL1 - VGL2| ≤ VGL2.

3. The display panel according to claim 1, characterized in that, the pixel circuit includes a data writing module, a compensation module, and a reset module; the data writing module is connected to the source of the driving transistor; the compensation module is connected between the gate and the drain of the driving transistor; the reset module is connected to the drain of the driving transistor; the working process of the pixel circuit includes a reset stage and a bias stage. In the reset stage, both the reset module and the compensation module are turned on, and the gate of the driving transistor receives a reset signal; in the bias stage, the reset module is turned on, and the compensation module is turned off, and the drain of the driving transistor receives the bias signal; wherein, if the driving transistor is a PMOS transistor, the reset signal is the fourth voltage signal, and the bias signal is the third voltage signal; or, if the driving transistor is an NMOS transistor, the reset signal is the third voltage signal, and the bias signal is the fourth voltage signal.

4. The display panel according to claim 1, characterized in that, the fourth control unit includes a first transistor and a second transistor; The first transistor receives the third voltage signal, and the second transistor receives the fourth voltage signal to generate the output signal.

5. The display panel according to claim 4, wherein, both the first transistor and the second transistor are PMOS transistors; the source of the first transistor is connected to the third voltage signal, the drain is connected to the output signal, and the gate is connected to the fourth node; the source of the second transistor is connected to the fourth voltage signal, the drain is connected to the output signal, and the gate is connected to the second node; or, the source of the first transistor is connected to the third voltage signal, the drain is connected to the output signal, and the gate is connected to the second node; the source of the second transistor is connected to the fourth voltage signal, the drain is connected to the output signal, and the gate is connected to the fourth node.

6. The display panel according to claim 4, wherein, both the first transistor and the second transistor are NMOS transistors; the source of the first transistor is connected to the third voltage signal, the drain is connected to the output signal, and the gate is connected to the second node; the source of the second transistor is connected to the fourth voltage signal, the drain is connected to the output signal, and the gate is connected to the fourth node; or, the source of the first transistor is connected to the third voltage signal, the drain is connected to the output signal, and the gate is connected to the fourth node; the source of the second transistor is connected to the fourth voltage signal, the drain is connected to the output signal, and the gate is connected to the second node.

7. The display panel according to claim 4, wherein, the fourth control unit further includes a first capacitor and / or a second capacitor; a first electrode plate of the first capacitor is connected to one of the first voltage signal, the second voltage signal, the third voltage signal or the fourth voltage signal, and a second electrode plate of the first capacitor is connected to the fourth node; and / or, a first electrode plate of the second capacitor is connected to the second node, and a second electrode plate of the second capacitor is connected to the output signal or one of the first voltage signal, the second voltage signal, the third voltage signal or the fourth voltage signal.

8. The display panel according to claim 7, wherein, the capacitance value of the first capacitor is less than or equal to the capacitance value of the second capacitor.

9. The display panel according to claim 4, wherein, the width-to-length ratio of the channel region of the second transistor is greater than or equal to the width-to-length ratio of the channel region of the first transistor.

10. The display panel according to claim 1, wherein, in the N shift registers of the driving circuit, the signal of the fourth node of the M-th shift register is connected to the input signal terminal of the (M + 1)-th shift register as the input signal of the (M + 1)-th shift register, where 1 ≤ M ≤ N.

11. The display panel according to claim 1, wherein, The display panel includes a first driving circuit and a second driving circuit. The first driving circuit includes N1 stages of the shift registers cascaded with each other, and the second driving circuit includes N2 stages of the shift registers cascaded with each other, where N1≥2 and N2≥2; wherein, the potential of at least one of the third voltage signals in the first driving circuit and the third voltage signals in the second driving circuit is higher than that of the other; and / or, the potential of at least one of the fourth voltage signals in the first driving circuit and the fourth voltage signals in the second driving circuit is lower than that of the other.

12. The display panel according to claim 11, wherein, the first driving circuit provides a third driving signal for the pixel circuit, the second driving circuit provides a fourth driving signal for the pixel circuit, and the third driving signal and the fourth driving signal are different driving signals.

13. The display panel according to claim 4, wherein, the shift registers are cascaded with each other along a first direction, and the first transistor and the second transistor are arranged along a second direction, wherein the first direction is parallel to the second direction.

14. The display panel according to claim 1, wherein, the shift register further includes: a first control unit configured to control the signal of a first node, and the first node is connected to a third node; a second control unit configured to control the signal of a second node; wherein, the third control unit receives the first voltage signal and the second voltage signal, and controls the signal of the fourth node in response to the signals of the second node and the third node; the fourth control unit receives the third voltage signal and the fourth voltage signal, and generates an output signal in response to the signals of the second node and the fourth node.

15. A display panel, wherein, comprises: a driving circuit, the driving circuit includes N stages of shift registers cascaded with each other, N≥2; the shift register includes: a third control unit configured to control the signal of a fourth node, the third control unit receives a first voltage signal and a second voltage signal, the first voltage signal is a high-level signal, and the second voltage signal is a low-level signal; a fourth control unit configured to generate an output signal, the fourth control unit receives a third voltage signal and a fourth voltage signal, the third voltage signal is a high-level signal, and the fourth voltage signal is a low-level signal; wherein, the absolute value of the voltage of the first voltage signal is VGH1, the absolute value of the voltage of the second voltage signal is VGL1, the absolute value of the voltage of the third voltage signal is VGH2, and the absolute value of the fourth voltage signal is VGL2; wherein, |VGH1 - VGH2|≤|VGL1 - VGL2|.

16. The display panel according to claim 15, wherein, |VGH1 - VGH2| ≤ VGH2, and / or, |VGL1 - VGL2| ≥ VGL2.

17. The display panel according to claim 15, wherein, the display panel includes a light-emitting element, and the driving circuit provides a second driving signal for selectively resetting the light-emitting element.

18. The display panel according to claim 15, wherein, the shift register further includes: a first control unit for controlling the signal of a first node, the first node being connected to a third node; a second control unit for controlling the signal of a second node; wherein, a third control unit receives the first voltage signal and the second voltage signal, and controls the signal of a fourth node in response to the signals of the second node and the third node; a fourth control unit receives the third voltage signal and a fourth voltage signal, and generates an output signal in response to the signals of the second node and the fourth node.

19. A display device, wherein, it includes the display panel according to any one of claims 1 - 18.

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