Pixel circuit and display device including same

Abstract

The invention discloses a pixel circuit and a display device including the same. The pixel circuit includes: a driving element including a first electrode connected to a first node, a gate electrode connected to a second node, and a second electrode connected to a third node; a first switching element configured to connect the second node and the third node in response to a first strobe signal; a second switching element configured to apply a data voltage to the first node in response to a second strobe signal; a third switching element configured to connect a pixel driving voltage line to the first node in response to a third strobe signal; a fourth switching element configured to connect the third node to a fourth node in response to a third strobe signal; a fifth switching element configured to apply a first initialization voltage to the second node in response to a fourth strobe signal; and a sixth switching element configured to apply a second initialization voltage to the fourth node in response to a second strobe signal.

Description

Technical Field

[0001] The present disclosure relates to a pixel circuit, and more particularly, for example but not limited to, a pixel circuit capable of improving FFR performance by implementing OBS driving during an initialization phase using a pixel driving voltage or a data voltage, and a display device including the pixel circuit. Background Art

[0002] Electroluminescent display devices are classified into inorganic light-emitting display devices and organic light-emitting display devices according to the material of the light-emitting layer. An active matrix organic light-emitting display device includes an organic light-emitting diode (hereinafter referred to as "OLED") that emits light by itself, and has advantages such as a fast response speed, high luminous efficiency, high brightness, and a large viewing angle.

[0003] In an organic light-emitting display device, an organic light-emitting diode (referred to as "OLED") is formed in each pixel. These organic light display devices not only have a fast response, but also have excellent luminous efficiency, brightness, and viewing angle, and also have excellent contrast and color reproduction rate because they can represent a black tone as completely black.

[0004] Some display devices such as liquid crystal display devices or organic light-emitting display devices include a display panel having a plurality of sub-pixels, a driver that outputs a driving signal for driving the display panel, a power supply that generates power to supply the display panel or the driver, and the like.

[0005] In such a display device, when driving signals such as a scan signal, an EM signal, and a data signal are supplied to a plurality of pixels formed in the display panel, the selected pixels transmit light or directly emit light, thereby displaying an image.

[0006] Each sub-pixel includes a driving element that controls the current flowing through the light-emitting element and a plurality of switching elements that switch the current. In this case, the driving element and the plurality of switching elements can be implemented as an N-channel LTPS TFT or a P-channel LTPS TFT including low-temperature polycrystalline silicon.

[0007] The descriptions provided in the description of the background art section should not be assumed to be prior art merely because they are mentioned in the description of the background art section or are associated with the description of the background art section. The description of the background art section may include information describing one or more aspects of the subject technology, and the description in this section does not limit the present invention. Summary of the Invention

[0008] The inventors have recognized that in the prior art, when all elements are implemented as P-channel LTPS TFTs, due to the hysteresis characteristics of the TFTs, when the data voltage changes from black grayscale to white grayscale, the brightness is greatly reduced. Therefore, the present disclosure aims to solve all of the above needs and problems.

[0009] The present disclosure provides a pixel circuit and a display device including the pixel circuit.

[0010] It should be noted that the object of the present disclosure is not limited to the above object, and other objects of the present disclosure will be apparent to those skilled in the art from the following description.

[0011] According to an exemplary embodiment of the present disclosure, the pixel circuit may include: a driving element including a first electrode connected to a first node, a gate electrode connected to a second node, and a second electrode connected to a third node; a first switching element configured to connect the second node and the third node in response to a first strobe signal; a second switching element configured to apply a data voltage to the first node in response to a second strobe signal; a third switching element configured to connect a pixel driving voltage line to the first node in response to a third strobe signal; a fourth switching element configured to connect the third node to a fourth node in response to a third strobe signal; a fifth switching element configured to apply a first initialization voltage to the second node in response to a fourth strobe signal; a sixth switching element configured to apply a second initialization voltage to the fourth node in response to the second strobe signal; a capacitor connected between the pixel driving voltage line and the second node; and a light emitting element connected to the fourth node and a low-potential power voltage line.

[0012] According to an exemplary embodiment of the present disclosure, the pixel circuit may include: a driving element including a first electrode connected to a first node, a gate electrode connected to a second node, and a second electrode connected to a third node; a first switching element configured to connect the second node and the third node in response to a first strobe signal; a second switching element configured to apply a data voltage to the first node in response to a first strobe signal; a third switching element configured to connect a pixel driving voltage line to the first node in response to a second strobe signal; a fourth switching element configured to connect the third node to a fourth node in response to a third strobe signal; a fifth switching element configured to apply a first initialization voltage to the second node in response to a fourth strobe signal; a capacitor connected between the pixel driving voltage line and the second node; and a light emitting element connected to the fourth node and a low-potential power voltage line.

[0013] A display device according to an exemplary embodiment of the present disclosure may include: a pixel array in which a plurality of data lines, a plurality of gate lines, and a plurality of pixel circuits are arranged; a data driver that outputs data voltages to the plurality of data lines; and a gate driver that outputs gate signals to the plurality of gate lines, wherein each pixel circuit includes: a driving element including a first electrode connected to a first node, a gate electrode connected to a second node, and a second electrode connected to a third node; a first switching element configured to connect the second node and the third node in response to a first gate signal; a second switching element configured to apply a data voltage to the first node in response to a first gate signal; a third switching element configured to connect a pixel driving voltage line to the first node in response to a second gate signal; a fourth switching element configured to connect the third node to a fourth node in response to a third gate signal; a fifth switching element configured to apply a first initialization voltage to the second node in response to a fourth gate signal; a sixth switching element configured to apply a second initialization voltage to the fourth node in response to a second gate signal; a capacitor connected between the pixel driving voltage line and the second node; and a light-emitting element connected to the fourth node and a low-potential power voltage line.

[0014] A display device according to an exemplary embodiment of the present disclosure may include: a pixel array in which a plurality of data lines, a plurality of gate lines, and a plurality of pixel circuits are arranged; a data driver that outputs data voltages to the plurality of data lines; and a gate driver that outputs gate signals to the plurality of gate lines, wherein each pixel circuit includes: a driving element including a first electrode connected to a first node, a gate electrode connected to a second node, and a second electrode connected to a third node; a first switching element configured to connect the second node and the third node in response to a first gate signal; a second switching element configured to apply a data voltage to the first node in response to a first gate signal; a third switching element configured to connect a pixel driving voltage line to the first node in response to a second gate signal; a fourth switching element configured to connect the third node to a fourth node in response to a third gate signal; a fifth switching element configured to apply an initialization voltage to the second node in response to a fourth gate signal; a capacitor connected between the pixel driving voltage line and the second node; and a light-emitting element connected to the fourth node and a low-potential power voltage line.

[0015] The present disclosure can improve the FFR performance by implementing OBS driving in the initialization stage using a pixel driving voltage or a data voltage, without additional configurations such as a separate voltage source and a control TFT.

[0016] The present disclosure can improve the FFR performance such that the response time can be improved as the change speed from black gray level to white gray level increases.

[0017] In the present disclosure, as the stabilization time to white gray scale is shortened, flicker can be improved.

[0018] In the present disclosure, since a separate voltage source for driving the OBS and additional configurations such as control TFTs are not required, power consumption can be reduced, and thus low-power driving can be achieved.

[0019] The effects of this specification are not limited to the above effects, and other effects not mentioned will be clearly understood by those skilled in the art from the following description and the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The above and other objects, features, and advantages of the present disclosure will become more apparent to those of ordinary skill in the art by referring to the following detailed description of exemplary embodiments of the present disclosure with reference to the accompanying drawings, wherein:

[0021] Figure 1 is a block diagram showing a display device according to an exemplary embodiment of the present disclosure;

[0022] Figure 2 is for showing Figure 1 a cross-sectional view of the cross-sectional structure of the display panel shown;

[0023] Figure 3 is a diagram showing a pixel circuit according to a comparative example;

[0024] Figure 4 is for showing Figure 3 the driving timing of the pixel circuit shown;

[0025] Figure 5 is for explaining Figure 4 the problems that occur when the pixel circuit is driven;

[0026] Figure 6 is a diagram showing a pixel circuit according to a first exemplary embodiment of the present disclosure;

[0027] Figure 7 is for showing Figure 6 the driving timing of the pixel circuit shown;

[0028] Figure 8A , Figure 8B and Figure 8C are diagrams for explaining Figure 7 the operating principle of the pixel circuit;

[0029] Figure 9 is a diagram for comparing and explaining simulation results of the pixel circuit according to the first exemplary embodiment;

[0030] Figure 10A diagram showing a pixel circuit according to a second exemplary embodiment of the present disclosure;

[0031] Figure 11 To show Figure 10 A diagram showing the driving timing of the pixel circuit shown;

[0032] Figure 12A 、 Figure 12B And Figure 12C Are diagrams for explaining Figure 11 The operating principle of the pixel circuit;

[0033] Figure 13 Is a diagram for comparing and explaining the simulation results of the pixel circuit according to the second exemplary embodiment;

[0034] Figure 14 A diagram showing a pixel circuit according to a third exemplary embodiment of the present disclosure;

[0035] Figure 15 To show Figure 14 A diagram showing the driving timing of the pixel circuit shown; and

[0036] Figure 16A 、 Figure 16B And Figure 16C Are diagrams showing Figure 15 The operating principle of the pixel circuit shown.

[0037] Throughout the drawings and the detailed description, unless otherwise described, the same reference numerals should be understood to refer to the same elements, features, and structures. For clarity, illustration, and convenience, the relative sizes and descriptions of these elements may be exaggerated. Detailed Description

[0038] Referring to the preferred exemplary embodiments described in detail in conjunction with the accompanying drawings, the advantages and features of this specification and the methods for achieving them will become apparent. However, this specification is not limited to the exemplary embodiments to be described below and can be implemented in different forms. These exemplary embodiments are only provided to fully disclose the present disclosure and fully convey the scope of the present disclosure to those skilled in the art, and this specification is defined by the disclosed claims.

[0039] The shapes, sizes, dimensions (e.g., length, width, height, thickness, radius, diameter, area, etc.), ratios, angles, quantities, etc. of the elements shown in the drawings used to describe the exemplary embodiments of the present disclosure are only examples, and the present disclosure is not limited thereto. Throughout the specification, the same reference numerals generally represent the same elements. In addition, in the following description of the present disclosure, detailed explanations of known related technologies may be omitted to avoid unnecessarily obscuring the subject matter of the present disclosure.

[0040] When using terms such as "comprising", "having", "including", "containing", "constituting", "made of", "formed by", "composed of", etc. mentioned in this specification, other parts can be added unless "only" is used. Unless otherwise explicitly stated, the case of expressing a component in the singular form includes the plural form.

[0041] The dimensions including the size and thickness of each component shown in the drawings are shown for convenience of description, and the present disclosure is not limited to the size and thickness of the components shown, but it should be noted that the relative dimensions including the relative size, position and thickness of the components shown in each drawing submitted here are part of the present disclosure.

[0042] When interpreting a component, it should be understood that the error range is included even if there is no separate explicit description.

[0043] In the case of describing a positional relationship, for example, when the positional relationship between two parts is described as "on", "above", "over", "under", "below", "beside", "beneath", "near", "close to", "adjacent to", "on the side of", "close", etc., one or more other parts can be located between these two parts unless "adjacent" or "direct" is used.

[0044] Spatially relative terms such as "below", "under", "beneath", "lower", "above", "upper", etc. can be used herein to facilitate the description of the relationship of one element or feature to another element or feature as shown in the figures. It should be understood that in addition to the orientation shown in the figures, the spatially relative terms can also include different orientations of the elements during use or operation. For example, if the element in the figure is inverted, the element described as "below" or "under" other elements or features will be oriented "above" other elements or features. Therefore, the exemplary term "below" can include both the below and above orientations. Similarly, the exemplary terms "above" or "over" can include both the "above" and "below" orientations.

[0045] When describing a time relationship, terms such as "after", "subsequently", "next", "then", "before", etc. can include the case where any two events are not continuous, unless terms such as "immediately", "exactly" or "directly" are explicitly used.

[0046] Although first, second, etc. are used to describe various components, these components are not limited by these terms. These terms are only used to distinguish one component from another. Therefore, the first component mentioned below can also be the second component within the technical spirit of the present disclosure.

[0047] In addition, when describing the components of the present disclosure, terms such as first, second, A, B, (a), (b), etc. may be used herein. Each of these terms is not used to define the essence, order or sequence of the corresponding component, but is only used to distinguish the corresponding component from other components. In the case where a structural element or layer is described as being "connected", "coupled", "bonded" or "joined" to another structural element or layer, it is generally interpreted that the other structural element or layer can be "connected", "coupled", "bonded" or "joined" to the structural element or layer directly or indirectly.

[0048] It should be understood that the term "at least one" includes all combinations related to any one item. For example, "at least one of the first element, the second element and the third element" may include all combinations of two or more elements selected from the first element, the second element and the third element and each element of the first element, the second element and the third element.

[0049] The term "device" used herein may refer to a display device including a display panel and a driver for driving the display panel. Examples of the display device may include light-emitting elements and the like. In addition, examples of the device may include a laptop computer, a television, a computer monitor, an automotive device, a wearable device and an automotive equipment device, and complete product or final product sets of electronic devices (or equipment) or sets of devices (or equipment) respectively including light-emitting elements and the like, such as mobile electronic devices such as smartphones or electronic tablets, but the embodiments of the present disclosure are not limited thereto.

[0050] Throughout the present disclosure, the same reference numerals may refer to substantially the same elements.

[0051] The following exemplary embodiments may be partially or completely combined or combined with each other, and may be linked and operated in various ways technically. The exemplary embodiments may be executed independently or in association with each other.

[0052] Unless otherwise defined, all terms (including technical terms and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the exemplary embodiments belong. It will be further understood that terms, such as those defined in a common dictionary, should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and should not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0053] Hereinafter, various exemplary embodiments of the present disclosure will be described in detail with reference to the drawings.

[0054] In the display device of the present disclosure, the pixel circuit and the gate driving circuit may include a plurality of transistors. The transistors may be implemented as thin film transistors (TFTs). The active layer of the thin film transistor (TFT) may be formed of a semiconductor material, such as an oxide semiconductor, an amorphous semiconductor, or a polycrystalline semiconductor, but is not limited thereto.

[0055] The oxide semiconductor material may have an excellent effect of preventing leakage current and relatively low manufacturing cost. The oxide semiconductor may be made of metal oxides such as zinc (Zn), indium (In), gallium (Ga), tin (Sn), and titanium (Ti), or a combination of metals such as zinc (Zn), indium (In), gallium (Ga), tin (Sn), or titanium (Ti) and their oxides. Specifically, the oxide semiconductor may include zinc oxide (ZnO), zinc tin oxide (ZTO), zinc indium oxide (ZIO), indium oxide (InO), titanium oxide (TiO), indium gallium zinc oxide (IGZO), indium zinc tin oxide (IZTO), indium zinc oxide (IZO), indium gallium tin oxide (IGTO), and indium gallium oxide (IGO), but is not limited thereto.

[0056] The polycrystalline semiconductor material has a fast moving speed of carriers such as electrons and holes, so it has a high mobility, low power consumption, and excellent reliability. The polycrystalline semiconductor may be made of polycrystalline silicon (poly-Si). For example, the polycrystalline semiconductor may be made of low temperature polycrystalline silicon (LTPS), but is not limited thereto.

[0057] The amorphous semiconductor material may be made of amorphous silicon (a-Si), but is not limited thereto.

[0058] A transistor is a three-electrode element including a gate, a source, and a drain. The source is an electrode that supplies carriers to the transistor. In the transistor, carriers start to flow from the source. The drain is an electrode through which carriers leave the transistor. In the transistor, carriers flow from the source to the drain. In the case of an n-channel transistor, since the carriers are electrons, the source voltage is a voltage lower than the drain voltage, so that electrons can flow from the source to the drain. The n-channel transistor has a direction of current flowing from the drain to the source. In the case of a p-channel transistor (p-channel metal oxide semiconductor (PMOS)), since the carriers are holes, the source voltage is higher than the drain voltage, so that holes can flow from the source to the drain. In the p-channel transistor, since holes flow from the source to the drain, the current flows from the source to the drain. It should be noted that the source and drain of the transistor are not fixed. For example, the source and drain can be changed according to the applied voltage. Therefore, the present disclosure is not limited by the source and drain of the transistor. In the following description, the source and drain of the transistor will be referred to as the first electrode and the second electrode.

[0059] The strobe signal swings between a gate-on voltage and a gate-off voltage. The gate-on voltage is set to a voltage higher than the threshold voltage of the transistor, and the gate-off voltage is set to a voltage lower than the threshold voltage of the transistor.

[0060] The transistor turns on in response to the gate-on voltage and turns off in response to the gate-off voltage. In the case of an n-channel transistor, the gate-on voltage may be a gate-high voltage, and the gate-off voltage may be a gate-low voltage. In the case of a p-channel transistor, the gate-on voltage may be a gate-low voltage, and the gate-off voltage may be a gate-high voltage.

[0061] Figure 1 FIG. is a block diagram showing a display device according to an exemplary embodiment of the present disclosure, and Figure 2 FIG. is a diagram showing Figure 1 a cross-sectional structure of the shown display panel.

[0062] Referring to Figure 1 and Figure 2 , a display device according to an exemplary embodiment of the present disclosure includes a display panel 100, a display panel driving unit configured to write pixel data into pixels of the display panel 100, and a power supply unit 140 configured to generate power required to drive the pixels and the display panel driving unit.

[0063] The display panel 100 includes a pixel array AA that displays an input image. The pixel array AA includes a plurality of data lines DL, a plurality of gate lines GL intersecting the data lines DL, and pixels arranged in a matrix form.

[0064] The pixel array AA includes a plurality of pixel rows L1 to Ln. Each of the pixel rows L1 to Ln includes a row of pixels arranged along the row direction X in the pixel array AA of the display panel 100. The pixels arranged in one pixel row share the gate line GL. Sub-pixels arranged in the column direction Y along the data line direction share the same data line DL. One horizontal period 1H is a time obtained by dividing one frame period by the total number of the pixel rows L1 to Ln.

[0065] A touch sensor may be provided on the display panel 100. A separate touch sensor may be used to sense a touch input, or a touch input may be sensed through pixels. The touch sensor may be provided as a on-cell type or an in-cell type touch sensor embedded in the pixel array AA on the screen of the display panel.

[0066] The display panel 100 may be implemented as a flexible display panel. The flexible display panel may be made of a plastic OLED panel. An organic film may be provided on the backplane of the plastic OLED panel, and the pixel array AA may be formed on the organic film.

[0067] The backplane of the plastic OLED can be a polyethylene terephthalate (PET) substrate. Alternatively, the backplane of the plastic OLED can be made of any one of acrylonitrile-butadiene-styrene copolymer (ABS), polymethyl methacrylate (PMMA), polyethylene naphthalate (PEN), polycarbonate (PC), polyethersulfone (PES), polyarylate (PAR), polysulfone (PSF), cycloolefin copolymer (COC), triacetyl cellulose (TAC), polyvinyl alcohol (PVA), and polystyrene (PS). However, the present disclosure is not limited thereto. An organic film is formed on the backplane. The pixel array AA and the touch sensor array can be formed on the organic film. The backplane blocks moisture penetration so that the pixel array AA is not exposed to moisture. The organic film can be a thin polyimide (PI) film substrate. A multilayer buffer film can be formed of an insulating material (not shown) on the organic film. Lines can be formed on the organic film to supply power or signals applied to the pixel array AA and the touch sensor array.

[0068] The display panel 100 can include a display area and a non-display area that partially or completely surrounds the display area. The non-display area can be adjacent to the display area and can be provided outside the display area.

[0069] The display area can be an area where pixels P are provided to display an image. A plurality of sub-pixels 101 are the smallest units that constitute the display area, and n sub-pixels 101 form one pixel. Each of the plurality of sub-pixels 101 can emit light having different wavelengths from each other. For example, in order to achieve colors, each pixel can be divided into a red sub-pixel (hereinafter referred to as "R sub-pixel"), a green sub-pixel (hereinafter referred to as "G sub-pixel"), and a blue sub-pixel (hereinafter referred to as "B sub-pixel"). Each pixel can also include a white sub-pixel. The plurality of sub-pixels 101 can be variously modified in terms of color and configuration as needed.

[0070] For example, the plurality of sub-pixels 101 may include a red sub-pixel, a green sub-pixel, and a blue sub-pixel, where the red sub-pixel, the green sub-pixel, and the blue sub-pixel may be arranged in a repeating manner. Alternatively, the plurality of sub-pixels 101 may include a red sub-pixel, a green sub-pixel, a blue sub-pixel, and a white sub-pixel, where the red sub-pixel, the green sub-pixel, the blue sub-pixel, and the white sub-pixel may be arranged in a repeating manner, or the red sub-pixel, the green sub-pixel, the blue sub-pixel, and the white sub-pixel may be arranged in a quadrilateral type. For example, the red sub-pixel, the blue sub-pixel, and the green sub-pixel may be sequentially arranged along the row direction, or the red sub-pixel, the blue sub-pixel, the green sub-pixel, and the white sub-pixel may be sequentially arranged along the row direction. However, in the embodiments of the present disclosure, the color type, the arrangement type, and the arrangement order of the sub-pixels are not limited and may be configured in various forms according to the light-emitting characteristics, the device lifetime, and the device specifications.

[0071] In addition, according to the light-emitting characteristics, the sub-pixels may have different light-emitting areas. For example, the sub-pixel that emits light of a color different from the color of the blue sub-pixel may have a light-emitting area different from the light-emitting area of the blue sub-pixel. For example, the red sub-pixel, the blue sub-pixel, and the green sub-pixel or the red sub-pixel, the blue sub-pixel, the white sub-pixel, and the green sub-pixel may each have a different light-emitting area.

[0072] Each sub-pixel 101 includes a pixel circuit. The pixel circuit is connected to a data line DL and a gate line GL.

[0073] The cross-sectional structure of the display panel 100 may include a circuit layer CIR, a light-emitting element layer EMIL, and a packaging layer ENC stacked on a substrate SUBS, as Figure 2 shown.

[0074] The circuit layer CIR may include a thin film transistor (TFT) array and gate drivers 410 and 420. The TFT array includes pixel circuits connected to wirings such as data lines, gate lines, and power lines. The circuit layer CIR includes a plurality of metal layers and semiconductor material layers, and insulating layers insulating from the metal layers are interposed between the plurality of metal layers. All the transistors formed in the circuit layer CIR may be implemented as n-channel oxide TFTs.

[0075] The light-emitting element layer EMIL may include light-emitting elements driven by the pixel circuits. The light-emitting elements may include light-emitting elements of red sub-pixels, light-emitting elements of green sub-pixels, and light-emitting elements of blue sub-pixels. The light-emitting element layer EMIL may further include light-emitting elements of white sub-pixels. The light-emitting element layer EMIL corresponding to each sub-pixel may have a structure in which a light-emitting element and a color filter are stacked. The light-emitting element EL in the light-emitting element layer EMIL may be covered by a plurality of protective layers including organic films and inorganic films.

[0076] The encapsulation layer ENC covers the light-emitting element layer EMIL to seal the circuit layer CIR and the light-emitting element layer EMIL. The encapsulation layer ENC may also have a multi-insulating film structure in which organic films and inorganic films are alternately laminated. The inorganic film blocks the penetration of moisture and oxygen. The organic film planarizes the surface of the inorganic film. When the organic layer and the inorganic layer are laminated in multiple layers, the movement path of moisture and oxygen becomes longer than that of a single layer, thereby effectively blocking the penetration of moisture and oxygen that affect the light-emitting element layer EMIL.

[0077] The encapsulation layer ENC may include a first encapsulation layer, a second encapsulation layer, and a third encapsulation layer that block the penetration of moisture or oxygen. The first encapsulation layer, the second encapsulation layer, and the third encapsulation layer may be alternately laminated, but the exemplary embodiments of the present disclosure are not limited thereto.

[0078] The encapsulation layer ENC may be formed of a transparent material to transmit the light emitted from the light-emitting layer.

[0079] The first encapsulation layer and the third encapsulation layer may be formed of at least one inorganic material such as silicon nitride (SiNx), silicon oxide (SiOx), and aluminum oxide (AlyOz), but are not limited thereto. The first encapsulation layer and the third encapsulation layer may be formed using a vacuum film-forming method such as chemical vapor deposition (CVD) or atomic layer deposition (ALD), but are not limited thereto.

[0080] The first encapsulation layer and the third encapsulation layer may be formed of at least two layers or more. For example, the first encapsulation layer may be formed with a three-layer structure of silicon oxide (SiOx) / silicon nitride (SiNx) / silicon oxide (SiOx), but is not limited thereto. In addition, the first encapsulation layer may be formed with a four-layer structure of silicon oxide (SiOx) / silicon nitride (SiNx) / silicon oxide (SiOx) / silicon oxide (SiOx), but is not limited thereto.

[0081] The second encapsulation layer may cover foreign materials or particles that may be generated during the manufacturing process. Further, the second encapsulation layer may planarize the surface of the first encapsulation layer. For example, the second encapsulation layer may be a particle covering layer, but is not limited thereto.

[0082] The second encapsulation layer may be an organic material, for example, a polymer such as silicon oxycarbide (SiOCz), epoxy resin, polyimide, polyethylene, or acrylate, but is not limited thereto.

[0083] The second encapsulation layer may be formed of a thermosetting material or a photocuring material cured by heat or light.

[0084] The second encapsulation layer may be formed by various methods such as inkjet coating or slot coating, but is not limited thereto.

[0085] In addition, the encapsulation layer ENC is not limited to three layers. For example, it may include n layers in which an inorganic encapsulation layer and an organic encapsulation layer are alternately stacked (where n is an integer greater than 3).

[0086] A touch sensor layer (not shown) may be formed on the encapsulation layer ENC, and a polarizing plate or a color filter layer may be provided thereon. The touch sensor layer may include a capacitive touch sensor that senses a touch input based on a change in capacitance before and after the touch input. The touch sensor layer may have a metal wiring pattern and an insulating film that form the capacitance of the touch sensor. The insulating film may insulate the regions where the metal wiring patterns intersect and may flatten the surface of the touch sensor layer. The polarizing plate may improve visibility and contrast by converting the polarization of external light reflected by the metal in the touch sensor layer and the circuit layer. The polarizing plate may be implemented as a circular polarizing plate or a polarizing plate in which a linear polarizing plate and a phase retardation film are joined together. A cover glass may be bonded to the polarizing plate. The color filter layer may include red, green, and blue color filters. The color filter layer may also include a black matrix pattern. The color filter layer may replace the polarizing plate by absorbing a part of the wavelength of the light reflected from the circuit layer and the touch sensor layer and may increase the color purity of the image reproduced in the pixel array.

[0087] The power supply unit 140 generates direct current (DC) power required to drive the pixel array of the display panel 100 and the display panel driving unit by using a DC-DC converter. The DC-DC converter may include a charge pump, a regulator, a buck converter, a boost converter, etc. The power supply unit 140 may adjust the level of the input DC voltage applied from a host system (not shown) to generate constant voltages (or DC voltages) such as a gamma reference voltage VGMA, a gate-on voltage VGH and VEH (or VGL and VEL), a gate-off voltage VGL and VEL (or VGH and VEH), a pixel driving voltage EVDD, a low-potential power voltage EVSS, an initialization voltage VINIT, and a reference voltage VREF. The gamma reference voltage VGMA is supplied to the data driver 110. The gate-on voltages VGH and VEH (or VGL and VEL) and the gate-off voltages VGL and VEL (or VGH and VEH) are supplied to the gate driver 120. Constant voltages such as the pixel driving voltage EVDD, the low-potential power voltage EVSS, the initialization voltage VINIT, the reference voltage VREF, etc. are commonly supplied to the pixels.

[0088] The display panel driving unit writes the pixel data of the input image into the pixels of the display panel 100 under the control of the timing controller (TCON) 130.

[0089] The display panel driving unit includes a data driver 110 and a gate driver 120.

[0090] A demultiplexer (DEMUX) may be disposed between the data driver 110 and the data lines DL. The demultiplexer is omitted from Figure 1 . The demultiplexer sequentially connects one channel of the data driver 110 to a plurality of data lines DL, and distributes the data voltage output from one channel of the data driver 110 to the data lines DL in a time division manner, thereby reducing the number of channels of the data driver 110.

[0091] The display panel driving circuit may further include a touch sensor driver for driving a touch sensor. The touch sensor driver is omitted from Figure 1 . In a mobile device, the timing controller 130, the power supply unit 140, the data driver 110, etc. may be integrated into one driving integrated circuit (IC).

[0092] The data driver 110 generates a data voltage Vdata by converting pixel data of an input image received from the timing controller 130 with a gamma compensation voltage in each frame period by using a digital-to-analog converter (DAC). The gamma reference voltage VGMA is divided for each gray level by a voltage divider circuit. The gamma compensation voltage divided from the gamma reference voltage VGMA is supplied to the DAC of the data driver 110. The data voltage Vdata is output through an output buffer in each channel of the data driver 110.

[0093] In the data driver 110, the output buffer included in one channel may be connected to adjacent data lines DL through a demultiplexer array 112 (not shown). The demultiplexer array 112 may be directly formed on the substrate of the display panel 100 or integrated with the data driver 110 into one driving IC.

[0094] The gate driver 120 may be implemented as an in-panel gate (GIP) circuit directly formed on the border BZ area of the display panel 100 together with the TFT array of the pixel array AA. The gate driver 120 sequentially outputs gate signals to the gate lines GL under the control of the timing controller 130. The gate driver 120 may sequentially supply gate signals to the gate lines GL by shifting the gate signals by using a shift register.

[0095] The timing controller 130 receives digital video data DATA of an input image and a timing signal synchronized therewith from a host system (not shown). The timing signal includes a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a main clock CLK, a data enable signal DE, etc. Here, the horizontal synchronization signal is a signal indicating the time taken for one horizontal line of a display screen, and the vertical synchronization signal is a signal indicating the time taken for displaying one frame of the screen. The data enable signal may correspond to a signal indicating a period during which a data voltage is supplied to a pixel. Since the vertical period and the horizontal period can be known by counting the data enable signal DE, the vertical synchronization signal Vsync and the horizontal synchronization signal Hsync can be omitted. The data enable signal DE has a period of one horizontal period (1H).

[0096] The timing controller 130 multiplies the input frame frequency by i and controls the operation timing of the display panel driving circuit at a frame frequency of input frame frequency × i (i is a positive integer greater than 0) Hz. The input frame frequency is 60 Hz in the NTSC (National Television System Committee) scheme and 50 Hz in the PAL (Phase Alternating Line) scheme.

[0097] Based on the timing signals Vsync, Hsync, and DE received from the host system, the timing controller 130 generates a data timing control signal for controlling the operation timing of the data driver 110, a MUX signal for controlling the operation timing of the demultiplexer array 112, and a gate timing control signal for controlling the operation timing of the gate driver 120.

[0098] The voltage level of the gate timing control signal output from the timing controller 130 can be converted into a gate-on voltage VGH and VEH (or VGL and VEL) and a gate-off voltage VGL and VEL (or VGH and VEH) by a level shifter (not shown), and then supplied to the gate driver 120. That is, the level shifter converts the low-level voltage of the gate timing control signal into a gate-off voltage VGL and VEL (or VGH and VEH), and converts the high-level voltage of the gate timing control signal into a gate-on voltage VGH and VEH (or VGL and VEL). The gate timing signal includes a start pulse and a shift clock.

[0099] The host system may include a main board of one of a television system, a set-top box, a navigation system, a personal computer (PC), a home theater system, a vehicle system, and a mobile device system. In this case, the data driver 110, the gate driver 120, the timing controller 130, etc. may be integrated into one driving IC (DIC) in a mobile device or a wearable device.

[0100] Figure 3 is a diagram showing a pixel circuit according to a comparative example,Figure 4 is a diagram showing Figure 3 the driving timing of the pixel circuit shown, and Figure 5 is a diagram for explaining Figure 4 the problems that occur when the pixel circuit

[0101] Referring to Figures 3 to 4 , the pixel circuit according to the comparative example includes a light-emitting element EL, a driving element DT, a plurality of switching elements T1, T2, T3, T4, T5, and T6, and a capacitor Cst. The driving element DT and the switching elements T1, T2, T3, T4, T5, and T6 can be implemented as P-channel LTPS TFTs.

[0102] The pixel circuit is driven in the order of an initialization step Ti, a sampling step Ts, and a light-emitting step Tem.

[0103] The TFTs of the pixel circuit in which all elements are implemented as P-channel LTPS TFTs have a hysteresis characteristic. Due to the hysteresis characteristic, when the data voltage changes from a black gradation to a white gradation, the value of the threshold voltage Vth decreases, resulting in a significant decrease in luminance compared to when the data voltage changes from a white gradation to a white gradation without a change in the threshold voltage, leading to a degradation in FFR performance.

[0104] As Figure 5 shown, when the data voltage changes from a black gradation to a white gradation and from the first frame of the white gradation to the second frame, the amount of change in the threshold voltage at the end of the sampling step Ts is different from the amount of change in the threshold voltage at the start of the light-emitting step Tem, resulting in a peak in the first frame of the white gradation.

[0105] To improve the FFR performance, it is necessary to increase the luminance difference between the first frame and the fourth frame of the white gradation. To this end, the driving element DT must be initialized to a constant voltage before the sampling step in order to suppress the occurrence of hysteresis due to the difference between the previous frame data voltage and the current frame data voltage. That is, in the initialization step, it is necessary to be configured to perform an on-state bias stress (OBS) drive that applies stress to the driving element DT with a constant Vgs voltage. However, in the pixel circuit of the comparative example, the source node of the driving element floats in the initialization step, such that the voltage of the source node changes according to the condition of the previous data voltage. Since there is no separate voltage, control TFT, and timing control for driving the OBS to apply a constant voltage to the source or drain of the driving element in the pixel circuit of the comparative example, it is difficult to improve the first frame response (FFR) performance without an additional configuration for applying the OBS voltage to the pixel circuit.

[0106] Therefore, in the exemplary embodiment, it is intended to improve the FFR performance by implementing OBS driving in the initialization step using a pixel driving voltage or a data voltage, without a separate additional configuration.

[0107] Hereinafter, in a first exemplary embodiment of the present disclosure, OBS driving using a data voltage will be described.

[0108] Figure 6 is a diagram showing a pixel circuit according to a first exemplary embodiment of the present disclosure, Figure 7 is showing Figure 6 a driving timing diagram of the shown pixel circuit, Figure 8A 、 Figure 8B and Figure 8C is a diagram for explaining Figure 7 the operating principle of the pixel circuit, and Figure 9 is a diagram for comparing and explaining simulation results of the pixel circuit according to the first exemplary embodiment.

[0109] Referring to Figure 6 , a pixel circuit according to a first exemplary embodiment of the present disclosure includes a light-emitting element EL, a driving element DT that supplies current to the light-emitting element EL, a plurality of switching elements T1, T2, T3, T4, T5, and T6 that switch a current path connected to the driving element DT, and a capacitor Cst that stores a gate-source voltage of the driving element DT. The driving element DT and the switching elements T1, T2, T3, T4, T5, and T6 can be implemented as P-channel LTPS TFTs.

[0110] The capacitor Cst is connected between a pixel driving voltage line 61 and a second node n2. A first electrode of the capacitor Cst is connected to the pixel driving voltage line 61, and a second electrode is connected to the second node n2. The pixel driving voltage ELVDD is supplied to the pixel circuit through the pixel driving voltage line 61. A first node n1 is connected to a first electrode of the driving element DT, a second electrode of a third switching element T3, and a first electrode of a second switching element T2. The second node n2 is connected to a second electrode of the capacitor Cst, a gate electrode of the driving element DT, a first electrode of a first switching element T1, and a first electrode of a fifth switching element T5.

[0111] The first switching element T1 is turned on according to a gate conduction voltage VGL of a second scan signal SCAN1(n) to connect the gate electrode and the second electrode of the driving element DT. The first switching element T1 includes a gate electrode to which the second scan signal SCAN1(n) is applied, a first electrode connected to the second node n2, and a second electrode connected to a third node n3. The third node n3 is connected to a second electrode of the driving element DT, a second electrode of the first switching element T1, and a first electrode of a fourth switching element T4.

[0112] The second switching element T2 is turned on according to the gate turn-on voltage VGL of the third scan signal SCAN2(n) to apply the data voltage Vdata to the first electrode of the driving element DT. The second switching element T2 includes a gate electrode to which the third scan signal SCAN2(n) is applied, a first electrode connected to the first node n1, and a second electrode connected to the data line 60. The first node n1 is connected to the first electrode of the driving element DT, the first electrode of the second switching element T2, and the second electrode of the third switching element T3.

[0113] The third switching element T3 supplies the pixel driving voltage ELVDD to the first electrode of the driving element DT in response to the EM signal EM(n). The third switching element T3 includes a gate electrode to which the EM signal EM(n) is applied, a first electrode connected to the pixel driving voltage line 61, and a second electrode connected to the first node n1.

[0114] The fourth switching element T4 is turned on according to the gate turn-on voltage VGL of the EM signal EM(n) to connect the second electrode of the driving element DT to the anode of the light-emitting element EL. The fourth switching element T4 includes a gate electrode to which the EM signal EM(n) is applied, a first electrode connected to the third node n3, and a second electrode connected to the fourth node n4. The fourth node n4 is connected to the anode electrode of the light-emitting element EL, the second electrode of the fourth switching element T4, and the second electrode of the sixth switching element T6.

[0115] The fifth switching element T5 is turned on according to the gate turn-on voltage VGL of the first scan signal SCAN1(n - 1) and connects the second node n2 to the first initialization voltage line 63 during the initialization step Ti to initialize the capacitor Cst and the gate of the driving element DT. The fifth switching element T5 includes a gate electrode to which the first scan signal SCAN1(n - 1) is applied, a first electrode connected to the second node n2, and a second electrode connected to the first initialization voltage line 63.

[0116] The sixth switching element T6 is turned on according to the gate turn-on voltage VGL of the third scan signal SCAN2(n) to connect the second initialization voltage line 64 to the anode of the light-emitting element EL during the initialization step Ti. During the initialization step Ti, the anode voltage of the light-emitting element EL is discharged to the second initialization voltage Voi2 through the sixth switching element T6. In this case, the light-emitting element EL does not emit light because the voltage between the anode and the cathode is lower than its threshold voltage. The sixth switching element T6 includes a gate electrode to which the third scan signal SCAN2(n) is applied, a first electrode to which the second initialization voltage line 64 is connected, and a second electrode to which the fourth node n4 is connected.

[0117] The driving element DT drives the light-emitting element EL by adjusting the current flowing through the light-emitting element EL according to the gate-source voltage Vgs. The driving element DT includes a gate electrode connected to the second node n2, a first electrode connected to the first node n1, and a second electrode connected to the third node n3.

[0118] The light-emitting element EL is connected between the fourth node n4 and the low-potential power supply voltage line 62. The light-emitting element EL can be implemented as an OLED. The OLED includes an organic compound layer formed between an anode and a cathode. The organic compound layer may include, but is not limited to, a hole injection layer (HIL), a hole transport layer (HTL), a light-emitting layer (EML), an electron transport layer (ETL), and an electron injection layer (EIL). When a voltage is applied to the anode and cathode of the OLED, holes passing through the hole transport layer (HTL) and electrons passing through the electron transport layer (ETL) move to the light-emitting layer (EML) to form excitons, and thus visible light is emitted from the light-emitting layer (EML).

[0119] As Figure 7 shown, the pixel circuit according to the first exemplary embodiment is driven in the order of the OBS step Tobs, the initialization step Ti, the sampling step Ts, and the light-emitting step Tem.

[0120] In Figure 8A the initialization step Ti, the first switching element T1, the third switching element T3, and the fourth switching element T4 are turned off, and the fifth switching element T5 is turned on by the first scan signal SCAN1(n - 1), so that the voltage of the second node n2 is discharged to the first initialization voltage Vini1, and the sixth switching element T6 is turned on by the third scan signal SCAN2(n), so that the voltage of the fourth node n4 is discharged to the second initialization voltage Vini2. Here, the first initialization voltage Vini1 and the second initialization voltage Vini2 are set such that: Vini1 ≤ Vini2.

[0121] Furthermore, in the OBS step Tobs, the second switching element T2 is turned on by the third scan signal SCAN2(n) to supply the data voltage Vdata(n - 1) applied to the previous pixel line to the first electrode of the driving element DT. For example, the data voltage Vdata(n - 1) can be between 0 and 255 grayscales and can have a value between 2V and 5V.

[0122] In this case, the initialization step Ti is executed at the same timing as the OBS step Tobs. Therefore, the voltage of the second node n2 becomes Vg = Vini1, the voltage of the first node n1 becomes Vdata(n - 1), and thus the source-gate voltage of the driving element becomes Vsg = Vini1 - Vdata(n - 1).

[0123] In Figure 8B During the sampling step Ts, the third switching element T3, the fourth switching element T4, and the fifth switching element T5 are turned off, the first switching element T1 is turned on by the second scan signal SCAN1(n), and the second switching element T2 is turned on by the third scan signal SCAN2(n), so that a data voltage is applied to the first node n1 and the second node n2.

[0124] In this case, the sixth switching element T6 is turned on together with the second switching element T2 by the third scan signal SCAN2(n), so that the second initialization voltage Vini2 is applied to the fourth node n4.

[0125] Therefore, the voltage of the second node n2 becomes Vg = Vdata - |Vth|, and the voltage of the first node n1 becomes Vs = Vdata, so that the source-gate voltage of the driving element becomes Vsg = |Vth|.

[0126] In Figure 8C During the light-emitting step Tem, the first switching element T1, the second switching element T2, the fifth switching element T5, and the sixth switching element T6 are turned off, and the third switching element T3 and the fourth switching element T4 are turned on by the EM signal EM(n), so that current flows through the driving element DT to the light-emitting element EL to emit light. The voltage of the second node n2 becomes Vg = Vdata - |Vth|, and the voltage of the first node n1 becomes Vs = ELVDD, so that the source-gate voltage of the driving element becomes Vsg = ELVDD - Vdata + |Vth|.

[0127] Referring Figure 9 to [reference], the pixel circuit according to the first exemplary embodiment performs the OBS step together with the data voltage in the initialization step, thereby improving the first frame response (FFR) performance. That is, compared with the pixel circuit of the comparative example according to Figure 3 when the data voltage changes from black grayscale to white grayscale, the first frame response (FFR) performance of the pixel circuit according to the first exemplary embodiment is greatly improved.

[0128] As described above, in the first exemplary embodiment of the present disclosure, FFR improvement can be achieved by implementing OBS driving using the data voltage Vdata without a separate voltage, control TFT, and timing control.

[0129] Hereinafter, in the second exemplary embodiment of the present disclosure, OBS driving using a pixel driving voltage will be described.

[0130] Figure 10 FIG. Figure 11 is a diagram showing a pixel circuit according to the second exemplary embodiment of the present disclosure, Figure 10A diagram of the driving timing of the pixel circuit shown Figure 12A and Figure 12B and Figure 12C are diagrams for explaining Figure 11 the operating principle of the pixel circuit, and Figure 13 is a diagram for comparing and explaining the simulation results of the pixel circuit according to the second exemplary embodiment.

[0131] Referring to Figure 10 , the pixel circuit according to the second exemplary embodiment of the present disclosure includes a light-emitting element EL, a driving element DT that supplies current to the light-emitting element EL, a plurality of switching elements T1, T2, T3, T4, T5, and T6 configured to switch a current path connected to the driving element DT, and a capacitor Cst configured to store the gate-source voltage of the driving element DT. The driving element DT and the switching elements T1, T2, T3, T4, T5, and T6 can be implemented as P-channel LTPS TFTs.

[0132] The capacitor Cst is connected between the pixel driving voltage line 61 and the second node n2. The first electrode of the capacitor Cst is connected to the pixel driving voltage line 61, and the second electrode is connected to the second node n2. The second node n2 is connected to the second electrode of the capacitor Cst, the gate electrode of the driving element DT, the first electrode of the first switching element T1, and the first electrode of the fifth switching element T5.

[0133] The first switching element T1 is turned on according to the gate conduction voltage VGL of the second scan signal SCAN(n) to connect the gate electrode of the driving element DT to the second electrode. The first switching element T1 includes a gate electrode to which the second scan signal SCAN(n) is applied, a first electrode connected to the second node n2, and a second electrode connected to the third node n3. The third node n3 connects the second electrode of the driving element DT, the second electrode of the first switching element T1, and the first electrode of the fourth switching element T4.

[0134] The second switching element T2 is turned on according to the gate conduction voltage VGL of the second scan signal SCAN(n) to apply the data voltage Vdata to the first electrode of the driving element DT. The second switching element T2 includes a gate electrode to which the second scan signal SCAN(n) is applied, a first electrode connected to the first node n1, and a second electrode connected to the data line 60. The first node n1 connects the first electrode of the driving element DT, the first electrode of the second switching element T2, and the second electrode of the third switching element T3.

[0135] The third switching element T3 supplies the pixel driving voltage ELVDD to the first node n1 in response to the first EM signal EM(n+2). The third switching element T3 includes a gate electrode to which the first EM signal EM(n+2) is applied, a first electrode connected to the pixel driving voltage line 61, and a second electrode connected to the first node n1.

[0136] The fourth switching element T4 is turned on according to the gate conduction voltage VGL of the second EM signal EM(n) to connect the second electrode of the driving element DT to the anode of the light-emitting element EL. The fourth switching element T4 includes a gate electrode to which the second EM signal EM(n) is applied, a first electrode connected to the third node n3, and a second electrode connected to the fourth node n4. The fourth node n4 is connected to the anode electrode of the light-emitting element EL, the second electrode of the fourth switching element T4, and the second electrode of the sixth switching element T6.

[0137] The fifth switching element T5 is turned on according to the gate conduction voltage VGL of the first scan signal SCAN(n-2) to connect the second node n2 to the first initialization voltage line 63, thereby initializing the capacitor Cst and the gate of the driving element DT during the initialization step Ti. The fifth switching element T5 includes a gate electrode to which the first scan signal SCAN(n-2) is applied, a first electrode to which the second node n2 is connected, and a second electrode to which the first initialization voltage line 63 is connected.

[0138] The sixth switching element T6 is turned on according to the gate conduction voltage VGL of the first scan signal SCAN(n-2) to connect the second initialization voltage line 64 to the anode of the light-emitting element EL during the initialization step Ti. During the initialization step Ti, the anode voltage of the light-emitting element EL is discharged to the second initialization voltage Vini2 through the sixth switching element T6. In this case, the light-emitting element EL does not emit light because the voltage between the anode and the cathode is lower than its threshold voltage. The sixth switching element T6 includes a gate electrode to which the first scan signal SCAN(n-2) is applied, a first electrode connected to the second initialization voltage line 64, and a second electrode connected to the fourth node n4.

[0139] The driving element DT drives the light-emitting element EL by adjusting the current flowing through the light-emitting element EL according to the gate-source voltage Vgs. The driving element DT includes a gate electrode connected to the second node n2, a first electrode connected to the first node n1, and a second electrode connected to the third node n3.

[0140] The light-emitting element EL is connected between the fourth node n4 and the low-potential power voltage line 62. The light-emitting element EL can be implemented as an OLED. The OLED includes an organic compound layer formed between an anode and a cathode. The organic compound layer may include, but is not limited to, a hole injection layer (HIL), a hole transport layer (HTL), a light-emitting layer (EML), an electron transport layer (ETL), and an electron injection layer (EIL). When a voltage is applied to the anode and cathode of the OLED, holes passing through the hole transport layer (HTL) and electrons passing through the electron transport layer (ETL) move to the light-emitting layer (EML) to form excitons, and thus visible light is emitted from the light-emitting layer (EML).

[0141] As Figure 11 shown, the pixel circuit according to the second exemplary embodiment is driven in the order of the first OBS step Tobs1, the second OBS step Tobs2, the initialization step Ti, the sampling step Ts, and the light-emitting step Tem.

[0142] In the first OBS step Tobs1 before the initialization step Ti, the third switching element T3 is turned on by the first EM signal of the (n + 2)-th pixel row to supply the pixel driving voltage ELVDD to the first electrode of the driving element DT.

[0143] In Figure 12A the initialization step Ti, the first switching element T1, the second switching element T2, and the fourth switching element T4 are turned off, and the fifth switching element T5 is turned on, so that the voltage of the second node n2 is discharged to the first initialization voltage Vini1, and the sixth switching element T6 is turned on, so that the voltage of the fourth node n4 is discharged to the second initialization voltage Vini2.

[0144] Meanwhile, in the second OBS step Tobs2, the third switching element T3 is turned on by the first EM signal EM(n + 2) to supply the pixel driving voltage ELVDD to the first electrode of the driving element DT. In this case, the fourth switching element T4 is turned off by the second EM signal EM(n), so that the light-emitting element EL does not emit light through the conduction of the driving element DT.

[0145] In this case, the initialization step Ti is executed at the same timing as the second OBS step Tobs2. Therefore, the voltage of the second node n2 becomes Vg = Vini1, the voltage of the first node n1 becomes Vs = ELVDD, and the source-gate voltage of the driving element becomes Vsg = ELVDD - Vini1.

[0146] In Figure 12BIn the sampling step Ts, the third switching element T3, the fourth switching element T4, the fifth switching element T5, and the sixth switching element T6 are turned off, and the first switching element T1 and the second switching element T2 are turned on by the second scan signal SCAN(n), so that the data voltage is applied to the first node n1. As a result, the voltage of the second node n2 becomes Vg = Vdata - |Vth|, the voltage of the first node n1 becomes Vs = Vdata, and the source-gate voltage of the driving element becomes Vsg = |Vth|.

[0147] In Figure 12C In the light-emitting step Tem, the first switching element T1, the second switching element T2, the fifth switching element T5, and the sixth switching element T6 are turned off, and the fourth switching element T4 is turned on by the second EM signal EM(n), so that current flows through the driving element DT and through the light-emitting element EL to emit light. Therefore, the voltage of the second node n2 becomes Vg = Vdata - |Vth|, the voltage of the first node n1 becomes Vs = ELVDD, and the voltage between the source and the gate of the driving element becomes Vsg = ELVDD - Vdata + |Vth|.

[0148] Reference Figure 13 , the pixel circuit according to the second exemplary embodiment performs the OBS step together with the pixel driving voltage in the initialization step, thereby improving the first frame response (FFR) performance. That is, compared with the pixel circuit of the comparative example according to Figure 3 , when the data voltage changes from black grayscale to white grayscale, the first frame response (FFR) performance of the pixel circuit according to the second exemplary embodiment is greatly improved.

[0149] Thus, in the second exemplary embodiment of the present disclosure, the OBS driving can be realized by using the pixel driving voltage ELVDD to achieve FFR improvement without a separate voltage, a control TFT, and a timing control.

[0150] In addition, when the OBS driving using the pixel driving voltage (ELVDD) is applied to the pixel circuit of the comparative example, FFR improvement is possible, but when black data is applied, black floating occurs, where complete black cannot be displayed. However, in the pixel circuit of the exemplary embodiment, since the third switching element T3 and the fourth switching element T4 are driven separately, that is, not driven by one EM signal but by different EM signals, black floating can be improved.

[0151] Figure 14 FIG. is a diagram showing a pixel circuit according to a third exemplary embodiment of the present disclosure, Figure 15 FIG. is a diagram showing Figure 14 the driving timing of the pixel circuit shown in Figure 16A ,Figure 16B and Figure 16C is a diagram showing Figure 15 the operating principle of the pixel circuit shown.

[0152] Referring to Figure 14 , the pixel circuit according to the third exemplary embodiment of the present disclosure includes a light-emitting element EL, a driving element DT that supplies current to the light-emitting element EL, a plurality of switching elements T1, T2, T3, T4, T5, T6, and T7 that switch a current path connected to the driving element DT, and a capacitor Cst that stores the gate-source voltage of the driving element DT. The driving element DT and the switching elements T1, T2, T3, T4, T5, T6, and T7 can be implemented as P-channel LTPS TFTs.

[0153] The capacitor Cst is connected between a second node n2 and a fifth node n5. A first electrode of the capacitor Cst is connected to the fifth node n5, and a second electrode is connected to the second node n2. The second node n2 is connected to the gate electrode of the driving element DT, the second electrode of the capacitor Cst, and the first electrode of the fifth switching element T5. The fifth node n5 is connected to the second electrode of the seventh switching element T7 and the first electrode of the capacitor Cst.

[0154] The first switching element T1 is turned on according to the gate conduction voltage VGL of the second scan signal SCAN(n) to connect the gate electrode of the driving element DT to the second electrode. The first switching element T1 includes a gate electrode to which the second scan signal SCAN(n) is applied, a first electrode connected to the second node n2, and a second electrode connected to a third node n3. The third node n3 is connected to the second electrode of the driving element DT, the second electrode of the first switching element T1, and the first electrode of the fourth switching element T4.

[0155] The second switching element T2 is turned on according to the gate conduction voltage VGL of the second scan signal SCAN(n) to apply the data voltage Vdata to the first electrode of the driving element DT. The second switching element T2 includes a gate electrode to which the second scan signal SCAN(n) is applied, a first electrode connected to the first node n1, and a second electrode connected to the data line 60. The first node n1 is connected to the first electrode of the driving element DT, the first electrode of the second switching element T2, and the second electrode of the third switching element T3.

[0156] The third switching element T3 supplies the pixel driving voltage ELVDD to the first node n1 in response to the first EM signal EM(n + 2). The third switching element T3 includes a gate electrode to which the first EM signal EM(n + 2) is applied, a first electrode connected to the pixel driving voltage line 61, and a second electrode connected to the first node n1.

[0157] The fourth switching element T4 is turned on according to the gate turn-on voltage VGL of the second EM signal EM(n) to connect the second electrode of the driving element DT to the anode of the light-emitting element EL. The fourth switching element T4 includes a gate electrode to which the second EM signal EM(n) is applied, a first electrode connected to the third node n3, and a second electrode connected to the fourth node n4. The fourth node n4 is connected to the anode of the light-emitting element EL, the second electrode of the fourth switching element T4, and the second electrode of the sixth switching element T6.

[0158] The fifth switching element T5 is turned on according to the gate turn-on voltage VGL of the first scan signal SCAN(n - 2) to connect the second node n2 to the initialization voltage line 65, thereby initializing the capacitor Cst and the gate of the driving element DT during the initialization step Ti. The fifth switching element T5 includes a gate electrode to which the first scan signal SCAN(n - 2) is applied, a first electrode to which the second node n2 is connected, and a second electrode to which the initialization voltage line 65 is connected.

[0159] The sixth switching element T6 is turned on according to the gate turn-on voltage VGL of the second scan signal SCAN(n) to connect the initialization voltage line 65 to the anode of the light-emitting element EL during the initialization step Ti. During the initialization step Ti, the anode voltage of the light-emitting element EL is discharged to the initialization voltage Vini through the sixth switching element T6. In this case, the light-emitting element EL does not emit light because the voltage between the anode and the cathode is lower than its threshold voltage. The sixth switching element T6 includes a gate electrode to which the second scan signal SCAN(n) is applied, a first electrode connected to the initialization voltage line 65, and a second electrode connected to the fourth node n4.

[0160] The seventh switching element T7 supplies the pixel driving voltage ELVDD to the capacitor Cst in response to the second EM signal EM(n). The seventh switching element T7 includes a gate electrode to which the second EM signal EM(n) is applied, a first electrode connected to the pixel driving voltage line 61, and a second electrode connected to the fifth node n5.

[0161] The reference voltage line 66 to which the reference voltage Vref is applied and the control switching element Tsw that applies the reference voltage Vref to the fifth node n5 through the reference voltage line 66 can be further connected to the fifth node n5 of the pixel circuit.

[0162] The control switch element Tsw can be disposed inside the display panel 100 and can be disposed outside the display area. For example, the control switch element Tsw can be disposed in a non-display area outside the display area. For example, the control switch element Tsw can be disposed in a border area outside the display area. The control switch element Tsw can be provided for each pixel row to control for each pixel row, or can be provided to divide the display panel 100 into a plurality of pixel blocks to control for each pixel block.

[0163] The control switch element Tsw can receive a control signal from the timing controller. For example, the timing controller generates and outputs a control signal of a first voltage level, and the level shifter receives the control signal of the first voltage level to generate a control signal of a second voltage level higher than the first voltage level and applies it to the control switch element Tsw.

[0164] The reference voltage Vref applied to the pixel circuit is used to improve the influence of the voltage drop IR of the pixel driving voltage ELVDD in the pixel circuit. That is, the current flowing through the light-emitting element is not IOLED = K(ELVDD - Vdata) 2 , but IOLED = K(Vref - Vdata) 2 . Therefore, in this exemplary embodiment, the reference voltage Vref instead of the pixel driving voltage ELVDD is applied to the fifth node n5 to which the capacitor is connected in the initialization and sampling steps.

[0165] As Figure 15 shown, the pixel circuit according to the third exemplary embodiment is driven in the order of the first OBS step Tobs1, the second OBS step Tobs2, the initialization step Ti, the sampling step Ts, and the light-emitting step Tem.

[0166] In the first OBS step Tobs1 before the initialization step Ti, the first switch element T1, the second switch element T2, the fourth switch element T4, the fifth switch element T5, the sixth switch element T6, and the seventh switch element T7 are turned off, and the third switch element T3 is turned on by the first EM signal EM(n + 2) to supply the pixel driving voltage ELVDD to the first electrode of the driving element DT.

[0167] In Figure 16A the initialization step Ti, the first switch element T1, the second switch element T2, the fourth switch element T4, the sixth switch element T6, and the seventh switch element T7 are turned off, and the fifth switch element T5 is turned on by the first scan signal SCAN(n - 2) so that the voltage of the second node n2 is discharged to the initialization voltage Vini.

[0168] Meanwhile, in the second OBS step Tobs2, the third switching element T3 is turned on by the first EM signal to supply the pixel driving voltage ELVDD to the first electrode of the driving element DT.

[0169] In this case, the initialization step Ti is executed at the same timing as the second OBS step Tobs2. Therefore, the voltage of the second node n2 becomes Vg = Vini, the voltage of the first node n1 becomes Vs = ELVDD, and thus the source-gate voltage of the driving element becomes Vsg = ELVDD - Vini.

[0170] In addition, the control switching element Tsw is turned on so that the reference voltage Vref is supplied to the fifth node n5.

[0171] In Figure 16B the sampling step Ts, the third switching element T3, the fourth switching element T4, the fifth switching element T5, and the seventh switching element T7 are turned off, and the first switching element T1 and the second switching element T2 are turned on by the second scan signal SCAN(n) so that the data voltage Vdata is applied to the first node n1 and the second node n2, and the sixth switching element T6 is turned on to apply the initialization voltage Vini to the fourth node n4. Therefore, the voltage of the second node n2 becomes Vg = Vdata - |Vth|, and the voltage of the first node n1 becomes Vs = Vdata, so that the source-gate voltage of the driving element becomes Vsg = |Vth|.

[0172] In addition, the control switching element Tsw is turned on so that the reference voltage Vref is supplied to the fifth node n5.

[0173] In Figure 16C the light-emitting step Tem, the first switching element T1, the second switching element T2, the fifth switching element T5, and the sixth switching element T6 are turned off, the fourth switching element T4 is turned on by the second EM signal EM(n), and the third switching element T3 is turned on by the first EM signal EM(n + 2) so that current flows through the driving element DT through the light-emitting element EL to emit light. Therefore, the voltage of the second node n2 becomes Vg = Vdata - |Vth|+(ELVDD - Vref), and the voltage of the first node n1 becomes Vs = ELVDD, so that the source-gate voltage of the driving element becomes Vsg = Vref - Vdata+|Vth|.

[0174] At this time, the control switching element Tsw is turned off to cut off the supply of the reference voltage Vref.

[0175] Thus, in the third exemplary embodiment of the present disclosure, OBS driving can be achieved by using the pixel driving voltage ELVDD to improve FFR without a separate voltage, control TFT, and timing control.

[0176] The exemplary embodiments of the present disclosure can also be described as follows:

[0177] According to an exemplary embodiment of the present disclosure, the pixel circuit includes: a driving element including a first electrode connected to a first node, a gate electrode connected to a second node, and a second electrode connected to a third node; a first switching element configured to connect the second node and the third node in response to a first strobe signal; a second switching element configured to apply a data voltage to the first node in response to a second strobe signal; a third switching element configured to connect a pixel driving voltage line to the first node in response to a third strobe signal; a fourth switching element configured to connect the third node to a fourth node in response to the third strobe signal; a fifth switching element configured to apply a first initialization voltage to the second node in response to a fourth strobe signal; a sixth switching element configured to apply a second initialization voltage to the fourth node in response to the second strobe signal; a capacitor connected between the pixel driving voltage line and the second node; and a light-emitting element connected to the fourth node and a low-potential power voltage line.

[0178] The pixel circuit is driven in the order of an initialization step, a turn-on bias stress OBS step, a sampling step, and a light-emitting step. In the initialization step, the fifth switching element is turned on so that the voltage of the second node discharges to the first initialization voltage, and the sixth switching element is turned on so that the voltage of the fourth node discharges to the second initialization voltage. And in the OBS step, the second switching element is turned on so that the data voltage of the previous frame is applied to the first node.

[0179] The first initialization voltage is less than or equal to the second initialization voltage.

[0180] In the sampling step, both the first switching element and the second switching element are turned on so that the data voltage of the current frame is applied to the first node.

[0181] The initialization step, the turn-on bias stress OBS step, the sampling step, and the light-emitting step are performed for the pixel circuit, and the initialization step and the OBS step are performed at the same timing.

[0182] In the initialization step, the OBS step is performed together with a data voltage.

[0183] In the initialization step, the fifth switching element is turned on so that the voltage of the second node is discharged to the first initialization voltage, and the sixth switching element is turned on so that the voltage of the fourth node is discharged to the second initialization voltage, and in the OBS step, the second switching element is turned on so that the data voltage of the previous frame is applied to the first node.

[0184] According to an exemplary embodiment of the present disclosure, the pixel circuit includes: a driving element including a first electrode connected to a first node, a gate electrode connected to a second node, and a second electrode connected to a third node; a first switching element configured to connect the second node and the third node in response to a first strobe signal; a second switching element configured to apply a data voltage to the first node in response to the first strobe signal; a third switching element configured to connect a pixel driving voltage line to the first node in response to a second strobe signal; a fourth switching element configured to connect the third node to a fourth node in response to a third strobe signal; a fifth switching element configured to apply a first initialization voltage to the second node in response to a fourth strobe signal; a capacitor connected between the pixel driving voltage line and the second node; and a light emitting element connected to the fourth node and a low-potential power voltage line.

[0185] The pixel circuit further includes: a sixth switching element configured to apply a second initialization voltage to the fourth node in response to the fourth strobe signal.

[0186] The pixel circuit is driven in the order of a first conduction bias stress OBS step, an initialization step, a second OBS step, a sampling step, and a light emitting step. In the initialization step, the fifth switching element is turned on so that the voltage of the second node is discharged to the first initialization voltage, and the sixth switching element is turned on so that the voltage of the fourth node is discharged to the second initialization voltage, and in the second OBS step, the third switching element is turned on to apply a pixel driving voltage from the pixel driving voltage line to the first node.

[0187] In the first OBS step, the third switching element is turned on to apply a pixel driving voltage from the pixel driving voltage line to the first node.

[0188] The pixel circuit further includes: a sixth switching element that applies the initialization voltage to the fourth node in response to the first strobe signal; and a seventh switching element connected between the pixel driving voltage line and the capacitor and configured to connect the pixel driving voltage line to the fifth node in response to the third strobe signal.

[0189] The pixel circuit is driven in the order of a first conduction bias stress OBS step, an initialization step, a second OBS step, a sampling step, and a light emission step. In the initialization step, the fifth switching element is turned on so that the voltage of the second node discharges to the initialization voltage, and in the second OBS step, the third switching element is turned on to apply the pixel driving voltage from the pixel driving voltage line to the first node.

[0190] In the first OBS step, the third switching element is turned on to apply the pixel driving voltage from the pixel driving voltage line to the first node.

[0191] A first conduction bias stress OBS step, an initialization step, a second OBS step, a sampling step, and a light emission step are performed for the pixel circuit, and the initialization step and the second OBS step are performed at the same timing.

[0192] In the initialization step, the second OBS step is performed together with the pixel driving voltage.

[0193] In the initialization step, the fifth switching element is turned on so that the voltage of the second node discharges to the first initialization voltage, and the sixth switching element is turned on so that the voltage of the fourth node discharges to the second initialization voltage, and in the second OBS step, the third switching element is turned on to apply the pixel driving voltage from the pixel driving voltage line to the first node.

[0194] According to an exemplary embodiment of the present disclosure, the display device includes: a pixel array in which a plurality of data lines, a plurality of gate lines, and a plurality of pixel circuits are arranged; a data driver that outputs data voltages to the plurality of data lines; and a gate driver that outputs gate signals to the plurality of gate lines, wherein each of the pixel circuits includes: a driving element including a first electrode connected to a first node, a gate electrode connected to a second node, and a second electrode connected to a third node; a first switching element configured to connect the second node and the third node in response to a first gate signal; a second switching element configured to apply the data voltage to the first node in response to a second gate signal; a third switching element configured to connect a pixel driving voltage line to the first node in response to a third gate signal; a fourth switching element configured to connect the third node to a fourth node in response to the third gate signal; a fifth switching element configured to apply a first initialization voltage to the second node in response to a fourth gate signal; a sixth switching element configured to apply a second initialization voltage to the fourth node in response to the second gate signal; a capacitor connected between the pixel driving voltage line and the second node; and a light emitting element connected to the fourth node and a low-potential power voltage line.

[0195] The pixel circuit is driven in the order of an initialization step, a turn-on bias stress OBS step, a sampling step, and a light emitting step. In the initialization step, the fifth switching element is turned on so that the voltage of the second node discharges to the first initialization voltage, and the sixth switching element is turned on so that the voltage of the fourth node discharges to the second initialization voltage. And in the OBS step, the second switching element is turned on, and the data voltage of the previous frame is applied to the first node.

[0196] The first initialization voltage is less than or equal to the second initialization voltage.

[0197] In the sampling step, both the first switching element and the second switching element are turned on, and the data voltage of the current frame is applied to the first node.

[0198] The initialization step, the turn-on bias stress OBS step, the sampling step, and the light emitting step are performed for the pixel circuit, and the initialization step and the OBS step are performed at the same timing.

[0199] In the initialization step, the OBS step is performed together with the data voltage.

[0200] In the initialization step, the fifth switching element is turned on to discharge the voltage of the second node to the first initialization voltage, and the sixth switching element is turned on to discharge the voltage of the fourth node to the second initialization voltage. And in the OBS step, the second switching element is turned on to apply the data voltage of the previous frame to the first node.

[0201] According to an exemplary embodiment of the present disclosure, the display device includes: a pixel array in which a plurality of data lines, a plurality of gate lines, and a plurality of pixel circuits are arranged; a data driver that outputs data voltages to the plurality of data lines; and a gate driver that outputs gate signals to the plurality of gate lines. Wherein, each of the pixel circuits includes: a driving element including a first electrode connected to a first node, a gate electrode connected to a second node, and a second electrode connected to a third node; a first switching element configured to connect the second node and the third node in response to a first gate signal; a second switching element configured to apply a data voltage to the first node in response to the first gate signal; a third switching element configured to connect a pixel driving voltage line to the first node in response to a second gate signal; a fourth switching element configured to connect the third node to a fourth node in response to a third gate signal; a fifth switching element configured to apply an initialization voltage to the second node in response to a fourth gate signal; a capacitor connected between the pixel driving voltage line and the second node; and a light emitting element connected to the fourth node and a low-potential power voltage line.

[0202] The display device further includes: a sixth switching element configured to apply a second initialization voltage to the fourth node in response to the fourth gate signal.

[0203] The pixel circuit is driven in the order of a first OBS step, an initialization step, a second OBS step, a sampling step, and a light emitting step. In the initialization step, the fifth switching element is turned on to discharge the voltage of the second node to a first initialization voltage, and the sixth switching element is turned on to discharge the voltage of the fourth node to the second initialization voltage. And in the second OBS step, the third switching element is turned on to apply the pixel driving voltage from the pixel driving voltage line to the first node.

[0204] In the first OBS step, the third switching element is turned on to apply the pixel driving voltage from the pixel driving voltage line to the first node.

[0205] The display device further includes: a sixth switching element that applies the initialization voltage to the fourth node in response to the first strobe signal; and a seventh switching element that is connected between the pixel driving voltage line and the first electrode of the capacitor and is configured to connect the pixel driving voltage line to a fifth node connected to the first electrode of the capacitor in response to the third strobe signal.

[0206] The pixel circuit is driven in the order of a first OBS step, an initialization step, a second OBS step, a sampling step, and a light-emitting step. In the initialization step, the fifth switching element is turned on so that the voltage of the second node is discharged to the initialization voltage, and in the second OBS step, the third switching element is turned on to apply the pixel driving voltage from the pixel driving voltage line to the first node.

[0207] In the first OBS step, the third switching element is turned on to apply the pixel driving voltage from the pixel driving voltage line to the first node.

[0208] A first conduction bias stress OBS step, an initialization step, a second OBS step, a sampling step, and a light-emitting step are performed for the pixel circuit, and the initialization step and the second OBS step are performed at the same timing.

[0209] In the initialization step, the second OBS step is performed together with the pixel driving voltage.

[0210] In the initialization step, the fifth switching element is turned on so that the voltage of the second node is discharged to the first initialization voltage, and the sixth switching element is turned on so that the voltage of the fourth node is discharged to the second initialization voltage. In the second OBS step, the pixel driving voltage from the pixel driving voltage line is applied to the first node.

[0211] The display device further includes: a control switching element provided for at least one pixel line and configured to supply a reference voltage to the pixel circuit in response to a control signal from a timing controller.

[0212] Although example embodiments of the present disclosure have been described in more detail with reference to the accompanying drawings, the present disclosure is not limited thereto and may be embodied in many different forms without departing from the technical concept of the present disclosure. Accordingly, the example embodiments disclosed in the present disclosure are provided for illustrative purposes only and are not intended to limit the technical concept of the present disclosure. The scope of the technical concept of the present disclosure is not limited thereto. Therefore, it should be understood that the above example embodiments are illustrative in all respects and do not limit the present disclosure.

[0213] Cross-reference to related applications

[0214] This application claims the benefit of priority of Korean Patent Application No. 10-2023-0172215, filed on December 1, 2023, the entire contents of which are hereby incorporated herein by reference for all purposes.

Claims

1. A pixel circuit, the pixel circuit comprising: a driving element including a first electrode connected to the first node, a gate electrode connected to the second node, and a second electrode connected to a third node; a first switching element configured to connect the second node and the third node in response to a first gating signal; a second switching element configured to apply a data voltage to the first node in response to a second gating signal; a third switching element configured to connect the pixel driving voltage line to the first node in response to a third gating signal; a fourth switching element configured to connect the third node to a fourth node in response to the third gating signal; a fifth switching element configured to apply a first initialization voltage to the second node in response to a fourth gating signal; a sixth switching element configured to apply a second initialization voltage to the fourth node in response to the second gating signal; a capacitor connected between the pixel driving voltage line and the second node; as well as A light emitting element is connected to the fourth node and a low potential power voltage line.

2. The pixel circuit according to claim 1, wherein: The pixel circuit is driven in the order of an initialization step, an on-bias stress OBS step, a sampling step and a light emitting step, In the initialization step, the fifth switching element is turned on so that the voltage of the second node is discharged to the first initialization voltage, and the sixth switching element is turned on so that the voltage of the fourth node is discharged to the second initialization voltage, In the OBS step, the second switching element is turned on so that the data voltage of the previous frame is applied to the first node, and In the sampling step, both the first switching element and the second switching element are turned on so that a data voltage of a current frame is applied to the first node.

3. A pixel circuit, comprising: a driving element including a first electrode connected to the first node, a gate electrode connected to the second node, and a second electrode connected to a third node; a first switching element configured to connect the second node and the third node in response to a first gating signal; a second switching element configured to apply a data voltage to the first node in response to the first gating signal; a third switching element configured to connect the pixel driving voltage line to the first node in response to a second gating signal; a fourth switching element configured to connect the third node to a fourth node in response to a third gating signal; a fifth switching element configured to apply a first initialization voltage to the second node in response to a fourth gating signal; a capacitor connected between the pixel driving voltage line and the second node; as well as A light emitting element is connected to the fourth node and a low potential power voltage line.

4. The pixel circuit according to claim 3, further comprising: A sixth switching element is configured to apply a second initialization voltage to the fourth node in response to the fourth gating signal.

5. The pixel circuit according to claim 4, wherein: The pixel circuit is driven in the order of a first on-bias stress OBS step, an initialization step, a second OBS step, a sampling step and a light emitting step, In the first OBS step, the third switching element is turned on to apply the pixel driving voltage from the pixel driving voltage line to the first node, In the initialization step, the fifth switching element is turned on so that the voltage of the second node is discharged to the first initialization voltage, and the sixth switching element is turned on so that the voltage of the fourth node is discharged to the second initialization voltage, and In the second OBS step, the third switching element is turned on to apply the pixel driving voltage from the pixel driving voltage line to the first node.

6. The pixel circuit according to claim 3, further comprising: a sixth switching element, the sixth switching element applying the initialization voltage to the fourth node in response to the first gating signal; as well as A seventh switching element is connected between the pixel driving voltage line and the capacitor and is configured to connect the pixel driving voltage line to a fifth node in response to the third gate signal.

7. The pixel circuit according to claim 6, wherein: The pixel circuit is driven in the order of a first on-bias stress OBS step, an initialization step, a second OBS step, a sampling step and a light emitting step, In the first OBS step, the third switching element is turned on to apply the pixel driving voltage from the pixel driving voltage line to the first node, In the initialization step, the fifth switch element is turned on to discharge the voltage of the second node to the initialization voltage, and In the second OBS step, the third switching element is turned on to apply the pixel driving voltage from the pixel driving voltage line to the first node.

8. A display device, comprising: A pixel array, wherein a plurality of data lines, a plurality of gate lines and a plurality of pixel circuits are arranged in the pixel array; a data driver, the data driver outputting data voltages to the plurality of data lines; as well as a gate driver, the gate driver outputting a gate signal to the plurality of gate lines, Wherein, each of the pixel circuits comprises: a driving element including a first electrode connected to the first node, a gate electrode connected to the second node, and a second electrode connected to a third node; a first switching element configured to connect the second node and the third node in response to a first gating signal; a second switching element configured to apply the data voltage to the first node in response to a second gating signal; a third switching element configured to connect the pixel driving voltage line to the first node in response to a third gating signal; a fourth switching element configured to connect the third node to a fourth node in response to the third gating signal; a fifth switching element configured to apply a first initialization voltage to the second node in response to a fourth gating signal; a sixth switching element configured to apply a second initialization voltage to the fourth node in response to the second gating signal; a capacitor connected between the pixel driving voltage line and the second node; and A light emitting element is connected to the fourth node and a low potential power voltage line.

9. A display device, comprising: A pixel array, wherein a plurality of data lines, a plurality of gate lines and a plurality of pixel circuits are arranged in the pixel array; a data driver, the data driver outputting data voltages to the plurality of data lines; as well as a gate driver, the gate driver outputting a gate signal to the plurality of gate lines, Wherein, each of the pixel circuits comprises: a driving element including a first electrode connected to the first node, a gate electrode connected to the second node, and a second electrode connected to a third node; a first switching element configured to connect the second node and the third node in response to a first gating signal; a second switching element configured to apply a data voltage to the first node in response to the first gating signal; a third switching element configured to connect the pixel driving voltage line to the first node in response to a second gating signal; a fourth switching element configured to connect the third node to a fourth node in response to a third gating signal; a fifth switching element configured to apply an initialization voltage to the second node in response to a fourth gating signal; a capacitor connected between the pixel driving voltage line and the second node; and A light emitting element is connected to the fourth node and a low potential power voltage line.

10. The display device according to claim 9, further comprising: A sixth switching element is configured to apply a second initialization voltage to the fourth node in response to the fourth gating signal.

11. The display device according to claim 9, further comprising: a sixth switching element, the sixth switching element applying the initialization voltage to the fourth node in response to the first gating signal; as well as A seventh switching element is connected between the pixel driving voltage line and the first electrode of the capacitor and is configured to connect the pixel driving voltage line to a fifth node connected to the first electrode of the capacitor in response to the third selection signal.

12. The display device according to claim 9, further comprising: A control switch element is provided for at least one pixel line and is configured to supply a reference voltage to the pixel circuit in response to a control signal from a timing controller.

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