Shift register, gate drive circuit and display device

Abstract

The invention provides a shift register, a gate drive circuit and a display device, and belongs to the technical field of display. The shift register comprises a first input sub-circuit, a second input sub-circuit, a first output sub-circuit, a second output sub-circuit, a first cascade sub-circuit and a second cascade sub-circuit, the first input sub-circuit is configured to respond to a first input signal and pre-charge the first pull-up node through a first scanning signal; the first input sub-circuit is configured to respond to a second input signal and pre-charge a second pull-up node through a second scanning signal; the first output sub-circuit is configured to output a third clock signal through a first signal output end in response to the potential of the first pull-up node; the first cascade sub-circuit is configured to output a third clock signal through a first cascade signal end in response to the potential of the first pull-up node; the second output sub-circuit is configured to output a fourth clock signal through a second signal output end in response to the potential of the second pull-up node; and the second cascade sub-circuit is configured to output a fourth clock signal through a second cascade signal end in response to the potential of the second pull-up node.

Description

Technical Field

[0001] The present disclosure belongs to the technical field of display, and particularly relates to a shift register, a gate driving circuit, and a display device. Background Art

[0002] In recent years, flat panel displays, such as thin film transistor liquid crystal display panels (TFT-LCDs) and active matrix organic light emitting diode display panels (AMOLEDs), have been widely used in electronic products such as televisions and mobile phones due to their advantages of light weight, thin thickness, and low power consumption.

[0003] With the development of display technology, high-resolution and narrow-bezel display panels have become a trend of development. For this reason, the gate driver on array (GOA) technology has emerged. The GOA technology directly integrates the gate driving circuit of the display panel on the array substrate to replace the external driving chip, and has the advantages of low cost, few processes, and high production capacity. Among them, the GOA circuit is usually implemented by a shift register, and the shift register converts the clock signal into an on / off voltage and outputs it to each gate line of the display panel respectively. Summary of the Invention

[0004] The present invention aims to solve at least one of the technical problems existing in the prior art, and provides a shift register, a gate driving circuit, and a display device.

[0005] In a first aspect, an embodiment of the present disclosure provides a shift register, which includes a first input sub-circuit, a second input sub-circuit, a first output sub-circuit, a second output sub-circuit, a first cascading sub-circuit, and a second cascading sub-circuit;

[0006] The first input sub-circuit is configured to pre-charge a first pull-up node through a first scan signal in response to a first input signal;

[0007] The first input sub-circuit is configured to pre-charge the second pull-up node through a second scan signal in response to a second input signal;

[0008] The first output sub-circuit is configured to output a third clock signal through a first signal output terminal in response to the potential of the first pull-up node;

[0009] The first cascading sub-circuit is configured to output a third clock signal through a first cascading signal terminal in response to the potential of the first pull-up node;

[0010] A second output sub - circuit, configured to output a fourth clock signal through a second signal output terminal in response to the potential of a second pull - up node;

[0011] A second cascaded sub - circuit, configured to output a fourth clock signal through a second cascaded signal terminal in response to the potential of the second pull - up node.

[0012] Wherein, the shift register further includes:

[0013] A first pull - up control sub - circuit, configured to transmit the first scan signal to the first pull - up node in response to a working level signal to pre - charge the first pull - up node;

[0014] A second pull - up control sub - circuit, configured to transmit the first scan signal to the second pull - up node in response to the working level signal to pre - charge the second pull - up node.

[0015] Wherein, the first pull - up control sub - circuit includes a ninth transistor; a first pole of the ninth transistor is connected to the first pull - up node, a second pole is connected to a pull - up control node, and a control pole is connected to a working level signal terminal; the pull - up control node is a connection node between a first input sub - circuit and the second input sub - circuit.

[0016] Wherein, the second pull - up control sub - circuit includes a fourteenth transistor; a first pole of the fourteenth transistor is connected to the second pull - up node, a second pole is connected to the pull - up control node, and a control pole is connected to the working level signal terminal; the pull - up control node is a connection node between the first input sub - circuit and the second input sub - circuit.

[0017] Wherein, the shift register further includes: a first node control sub - circuit, a second node control sub - circuit, a pull - down control sub - circuit, and a pull - down sub - circuit;

[0018] The first node control sub - circuit is configured to control the potential of a pull - down control node through a first clock signal in response to the first scan signal;

[0019] The second node control sub - circuit is configured to control the potential of the pull - down control node through a second clock signal in response to the second scan signal;

[0020] The pull - down control sub - circuit is configured to control the potential of a pull - down node through a working level signal in response to the potential of the pull - down control node, and control the pull - down node through a non - working level signal in response to the potential of the pull - up control node;

[0021] The pull-down sub-circuit is configured to pull down the potential of the pull-up control node, the output of the first signal output terminal, the output of the second signal output terminal, the output of the first cascaded signal terminal, and the output of the second cascaded signal terminal through the non-operating level signal in response to the potential of the pull-down node.

[0022] Wherein, the first node control sub-circuit includes a fifth transistor; a first pole of the fifth transistor is connected to the first clock signal terminal, a second pole is connected to the pull-down control node, and a control pole is connected to the first scan signal terminal.

[0023] Wherein, the second node control sub-circuit includes a sixth transistor; a first pole of the sixth transistor is connected to the second clock signal terminal, a second pole is connected to the pull-down control node, and a control pole is connected to the second scan signal terminal.

[0024] Wherein, the pull-down control sub-circuit includes an eighth transistor, a tenth transistor, and a second storage capacitor;

[0025] A first pole of the eighth transistor is connected to the pull-down node, a second pole is connected to the non-operating level signal terminal, and a control pole is connected to the pull-up control node; the pull-up control node is a connection node between the first input sub-circuit and the second input sub-circuit;

[0026] A first pole of the tenth transistor is connected to the operating level signal terminal, a second pole is connected to the pull-down node, and a control pole is connected to the pull-down control node;

[0027] A first end of the second storage capacitor is connected to the pull-down node, and a second pole is connected to the non-operating level signal terminal.

[0028] Wherein, the pull-down sub-circuit includes a fourth transistor, a seventh transistor, a thirteenth transistor, a fifteenth transistor, and a seventeenth transistor;

[0029] A first pole of the fourth transistor is connected to the first signal output terminal, a second pole is connected to the non-operating level signal terminal, and a control pole is connected to the pull-down node;

[0030] A first pole of the seventh transistor is connected to the pull-up control node, a second pole is connected to the non-operating level signal terminal, and a control pole is connected to the pull-down node; the pull-up control node is a connection node between the first input sub-circuit and the second input sub-circuit;

[0031] A first pole of the thirteenth transistor is connected to the second signal output terminal, a second pole is connected to the non-operating level signal terminal, and a control pole is connected to the pull-down node;

[0032] A first pole of the fifteenth transistor is connected to the first cascaded signal output terminal, a second pole is connected to the non-operating level signal terminal, and a control pole is connected to the pull-down node;

[0033] A first pole of the seventeenth transistor is connected to a second cascaded signal output terminal, a second pole is connected to the non-operating level signal terminal, and a control pole is connected to the pull-down node.

[0034] Wherein, the shift register further includes:

[0035] A reset sub-circuit configured to respond to a reset signal and reset the pull-up control node through a non-operating level signal; the pull-up control node is a connection node between the first input sub-circuit and the second input sub-circuit.

[0036] Wherein, the reset sub-circuit includes an eleventh transistor; a first pole of the eleventh transistor is connected to the pull-up control node, a second pole is connected to the non-operating level signal terminal, and a control pole is connected to the reset signal terminal.

[0037] Wherein, the first input sub-circuit includes a first transistor; a first pole of the first transistor is connected to a first scan signal terminal, a second pole is connected to the pull-up control node, and a control pole is connected to a first signal input terminal; the pull-up control node is a connection node between the first input sub-circuit and the second input sub-circuit.

[0038] Wherein, the second input sub-circuit includes a second transistor; a first end of the second transistor is connected to a second scan signal terminal, a second pole is connected to the pull-up control node, and a control pole is connected to a second signal input terminal; the pull-up control node is a connection node between the first input sub-circuit and the second input sub-circuit.

[0039] Wherein, the first output sub-circuit includes a third transistor and a first storage capacitor;

[0040] A first pole of the third transistor is connected to a third clock signal terminal, a second pole is connected to a first signal output terminal, and a control pole is connected to the first pull-up node;

[0041] A first end of the first storage capacitor is connected to the first pull-up node, and a second end is connected to the first signal output terminal.

[0042] Wherein, the second output sub-circuit includes a twelfth transistor and a third storage capacitor;

[0043] A first pole of the third transistor is connected to a fourth clock signal terminal, a second pole is connected to a second signal output terminal, and a control pole is connected to the second pull-up node;

[0044] A first end of the third storage capacitor is connected to the second pull-up node, and a second end is connected to the second signal output terminal.

[0045] Among them, the first cascaded sub-circuit includes a fourteenth transistor; a first pole of the fourteenth transistor is connected to a third clock signal terminal, a second pole is connected to a first cascaded signal terminal, and a control pole is connected to the first pull-up node.

[0046] Among them, the first cascaded sub-circuit includes a seventeenth transistor; a first pole of the seventeenth transistor is connected to a fourth clock signal terminal, a second pole is connected to a second cascaded signal terminal, and a control pole is connected to the second pull-up node.

[0047] In a second aspect, an embodiment of the present disclosure further provides a gate driving circuit, which includes a plurality of shift registers, among which, the shift register includes any one of the above-mentioned shift registers.

[0048] Among them, the shift register includes a first node control sub-circuit, a second node control sub-circuit, a pull-down control sub-circuit, and a pull-down sub-circuit; the shift register has a first clock signal terminal, a second clock signal terminal, a third clock signal terminal, and a fourth clock signal terminal;

[0049] The gate driving circuit further includes 6 clock signal lines, namely a first clock signal line, a second clock signal line, a third clock signal line, a fourth clock signal line, a fifth clock signal line, and a sixth clock signal line;

[0050] Except for the last-stage shift register, a first cascaded signal terminal of the current-stage shift register is connected to a first signal input terminal of the next-stage shift register;

[0051] Except for the first-stage shift register, a first cascaded signal terminal of the current-stage shift register is connected to a second signal input terminal of the previous-stage shift register;

[0052] The plurality of shift registers are at least divided into N groups, each group includes 3 arranged in sequence, N≥2, and N is a positive integer;

[0053] For the first shift register in each group, the first clock signal terminal, the second clock signal terminal, the third clock signal terminal, and the fourth clock signal terminal are respectively electrically connected to the sixth clock signal line, the first clock signal line, the second clock signal line, and the third clock signal line;

[0054] For the second shift register in each group, the first clock signal terminal, the second clock signal terminal, the third clock signal terminal, and the fourth clock signal terminal are respectively electrically connected to the second clock signal line, the third clock signal line, the fifth clock signal line, and the sixth clock signal line;

[0055] The first clock signal terminal, the second clock signal terminal, the third clock signal terminal, and the fourth clock signal terminal of the third shift register in each group are respectively electrically connected to the fourth clock signal line, the fifth clock signal line, the first clock signal line, and the second clock signal line.

[0056] Wherein, the shift register includes a first node control sub-circuit, a second node control sub-circuit, a pull-down control sub-circuit, and a pull-down sub-circuit; the shift register has a first clock signal terminal, a second clock signal terminal, a third clock signal terminal, and a fourth clock signal terminal;

[0057] The gate driving circuit further includes six clock signal lines, namely a first clock signal line, a second clock signal line, a third clock signal line, a fourth clock signal line, a fifth clock signal line, and a sixth clock signal line;

[0058] Except for the last-stage shift register, the first cascade signal terminal of the current-stage shift register is connected to the first signal input terminal of the next-stage shift register;

[0059] Except for the first-stage shift register, the first cascade signal terminal of the current-stage shift register is connected to the second signal input terminal of the previous-stage shift register;

[0060] The multiple shift registers are at least divided into N groups, each group includes three arranged in sequence, N≥2, and N is a positive integer;

[0061] The first clock signal terminal, the second clock signal terminal, the third clock signal terminal, and the fourth clock signal terminal of the first shift register in each group are respectively electrically connected to the first clock signal line, the second clock signal line, the third clock signal line, and the fourth clock signal line;

[0062] The first clock signal terminal, the second clock signal terminal, the third clock signal terminal, and the fourth clock signal terminal of the second shift register in each group are respectively electrically connected to the third clock signal line, the fourth clock signal line, the fifth clock signal line, and the sixth clock signal line;

[0063] The first clock signal terminal, the second clock signal terminal, the third clock signal terminal, and the fourth clock signal terminal of the third shift register in each group are respectively electrically connected to the fifth clock signal line, the sixth clock signal line, the first clock signal line, and the second clock signal line.

[0064] Among them, the shift register includes a first node control sub-circuit, a second node control sub-circuit, a pull-down control sub-circuit, and a pull-down sub-circuit; the shift register has a first clock signal terminal, a second clock signal terminal, a third clock signal terminal, and a fourth clock signal terminal;

[0065] The gate driving circuit further includes 8 clock signal lines, namely a first clock signal line, a second clock signal line, a third clock signal line, a fourth clock signal line, a fifth clock signal line, a sixth clock signal line, a seventh clock signal line, and an eighth clock signal line;

[0066] The number of the shift registers is M, and the M shift registers are at least divided into N groups, each group includes 4 arranged in sequence, N≥2, and both M and N are positive integers;

[0067] The first cascade signal terminal of the i-th shift register is connected to the first signal input terminal of the (i + 2)-th shift register; i takes values from 1 to (M - 2);

[0068] The second cascade signal terminal of the j-th shift register is connected to the second signal input terminal of the (j - 2)-th shift register; j takes values from 3 to M;

[0069] The first clock signal terminal, the second clock signal terminal, the third clock signal terminal, and the fourth clock signal terminal of the first shift register in each group are respectively electrically connected to the seventh clock signal line, the eighth clock signal line, the third clock signal line, and the fourth clock signal line;

[0070] The first clock signal terminal, the second clock signal terminal, the third clock signal terminal, and the fourth clock signal terminal of the second shift register in each group are respectively electrically connected to the first clock signal line, the second clock signal line, the fifth clock signal line, and the sixth clock signal line;

[0071] The first clock signal terminal, the second clock signal terminal, the third clock signal terminal, and the fourth clock signal terminal of the third shift register in each group are respectively electrically connected to the third clock signal line, the fourth clock signal line, the seventh clock signal line, and the eighth clock signal line;

[0072] The first clock signal terminal, the second clock signal terminal, the third clock signal terminal, and the fourth clock signal terminal of the fourth shift register in each group are respectively electrically connected to the fifth clock signal line, the sixth clock signal line, the first clock signal line, and the second clock signal line.

[0073] Wherein, the shift register includes a first node control sub-circuit, a second node control sub-circuit, a pull-down control sub-circuit, and a pull-down sub-circuit; the shift register has a first clock signal terminal, a second clock signal terminal, a third clock signal terminal, and a fourth clock signal terminal;

[0074] The gate driving circuit further includes 12 clock signal lines, namely a first clock signal line, a second clock signal line, a third clock signal line, a fourth clock signal line, a fifth clock signal line, a sixth clock signal line, a seventh clock signal line, an eighth clock signal line, a ninth clock signal line, a tenth clock signal line, an eleventh clock signal line, and a twelfth clock signal line;

[0075] The number of the shift registers is M, and the M shift registers are at least divided into N groups, each group includes 6 arranged in sequence, N≥2, and both M and N are positive integers;

[0076] The first cascade signal terminal of the i-th shift register is connected to the first signal input terminal of the (i + 2)-th shift register; i takes values from 1 to (M - 2);

[0077] The second cascade signal terminal of the j-th shift register is connected to the second signal input terminal of the (j - 2)-th shift register; j takes values from 3 to M;

[0078] The first clock signal terminal, the second clock signal terminal, the third clock signal terminal, and the fourth clock signal terminal of the first shift register in each group are respectively electrically connected to the tenth clock signal line, the ninth clock signal line, the third clock signal line, and the fourth clock signal line;

[0079] The first clock signal terminal, the second clock signal terminal, the third clock signal terminal, and the fourth clock signal terminal of the second shift register in each group are respectively electrically connected to the twelfth clock signal line, the eleventh clock signal line, the fifth clock signal line, and the sixth clock signal line;

[0080] The first clock signal terminal, the second clock signal terminal, the third clock signal terminal, and the fourth clock signal terminal of the third shift register in each group are respectively electrically connected to the second clock signal line, the first clock signal line, the seventh clock signal line, and the eighth clock signal line;

[0081] The first clock signal terminal, the second clock signal terminal, the third clock signal terminal, and the fourth clock signal terminal of the fourth shift register in each group are respectively electrically connected to the fourth clock signal line, the third clock signal line, the ninth clock signal line, and the tenth clock signal line;

[0082] The first clock signal terminal, the second clock signal terminal, the third clock signal terminal, and the fourth clock signal terminal of the fifth shift register in each group are respectively electrically connected to the sixth clock signal line, the fifth clock signal line, the eleventh clock signal line, and the twelfth clock signal line;

[0083] The first clock signal terminal, the second clock signal terminal, the third clock signal terminal, and the fourth clock signal terminal of the sixth shift register in each group are respectively electrically connected to the eighth clock signal line, the seventh clock signal line, the first clock signal line, and the second clock signal line.

[0084] Among them, the shift register includes a first node control sub-circuit, a second node control sub-circuit, a pull-down control sub-circuit, and a pull-down sub-circuit; the shift register has a first clock signal terminal, a second clock signal terminal, a third clock signal terminal, and a fourth clock signal terminal;

[0085] The gate driving circuit further includes 12 clock signal lines, namely the first clock signal line, the second clock signal line, the third clock signal line, the fourth clock signal line, the fifth clock signal line, the sixth clock signal line, the seventh clock signal line, the eighth clock signal line, the ninth clock signal line, the tenth clock signal line, the eleventh clock signal line, and the twelfth clock signal line;

[0086] The number of the shift registers is M, and the M shift registers are at least divided into N groups, each group includes 6 arranged in sequence, N≥2, and both M and N are positive integers;

[0087] The second cascade signal terminal of the i-th shift register is connected to the first signal input terminal of the (i + 2)-th shift register; i takes values from 1 to (M - 2);

[0088] The second cascade signal terminal of the j-th shift register is connected to the second signal input terminal of the (j - 2)-th shift register; j takes values from 3 to M;

[0089] The first clock signal terminal, the second clock signal terminal, the third clock signal terminal, and the fourth clock signal terminal of the first shift register in each group are respectively electrically connected to the tenth clock signal line, the ninth clock signal line, the third clock signal line, and the fourth clock signal line;

[0090] The first clock signal terminal, the second clock signal terminal, the third clock signal terminal, and the fourth clock signal terminal of the second shift register in each group are respectively electrically connected to the twelfth clock signal line, the eleventh clock signal line, the fifth clock signal line, and the sixth clock signal line.

[0091] The first clock signal terminal, the second clock signal terminal, the third clock signal terminal, and the fourth clock signal terminal of the third shift register in each group are respectively electrically connected to the second clock signal line, the first clock signal line, the seventh clock signal line, and the eighth clock signal line;

[0092] The first clock signal terminal, the second clock signal terminal, the third clock signal terminal, and the fourth clock signal terminal of the fourth shift register in each group are respectively electrically connected to the fourth clock signal line, the third clock signal line, the ninth clock signal line, and the tenth clock signal line;

[0093] The first clock signal terminal, the second clock signal terminal, the third clock signal terminal, and the fourth clock signal terminal of the fifth shift register in each group are respectively electrically connected to the sixth clock signal line, the fifth clock signal line, the eleventh clock signal line, and the twelfth clock signal line;

[0094] The first clock signal terminal, the second clock signal terminal, the third clock signal terminal, and the fourth clock signal terminal of the sixth shift register in each group are respectively electrically connected to the eighth clock signal line, the seventh clock signal line, the first clock signal line, and the second clock signal line.

[0095] Wherein, the shift register includes a first node control sub - circuit, a second node control sub - circuit, a pull - down control sub - circuit, and a pull - down sub - circuit; the shift register has a first clock signal terminal, a second clock signal terminal, a third clock signal terminal, and a fourth clock signal terminal;

[0096] The gate driving circuit further includes 12 clock signal lines, namely the first clock signal line, the second clock signal line, the third clock signal line, the fourth clock signal line, the fifth clock signal line, the sixth clock signal line, the seventh clock signal line, the eighth clock signal line, the ninth clock signal line, the tenth clock signal line, the eleventh clock signal line, and the twelfth clock signal line;

[0097] The number of the shift registers is M, and M shift registers are at least divided into N groups, each group includes 6 arranged in sequence, N≥2, and both M and N are positive integers;

[0098] The second cascading signal terminal of the i - th shift register is connected to the first signal input terminal of the (i + 2) - th shift register; i takes values from 1 to (M - 2);

[0099] The second cascading signal terminal of the j - th shift register is connected to the second signal input terminal of the (j - 3) - th shift register; j takes values from 4 to M;

[0100] The first clock signal terminal, the second clock signal terminal, the third clock signal terminal, and the fourth clock signal terminal of the first shift register in each group are respectively electrically connected to the tenth clock signal line, the ninth clock signal line, the third clock signal line, and the fourth clock signal line;

[0101] The first clock signal terminal, the second clock signal terminal, the third clock signal terminal, and the fourth clock signal terminal of the second shift register in each group are respectively electrically connected to the twelfth clock signal line, the eleventh clock signal line, the fifth clock signal line, and the sixth clock signal line;

[0102] The first clock signal terminal, the second clock signal terminal, the third clock signal terminal, and the fourth clock signal terminal of the third shift register in each group are respectively electrically connected to the second clock signal line, the first clock signal line, the seventh clock signal line, and the eighth clock signal line;

[0103] The first clock signal terminal, the second clock signal terminal, the third clock signal terminal, and the fourth clock signal terminal of the fourth shift register in each group are respectively electrically connected to the fourth clock signal line, the third clock signal line, the ninth clock signal line, and the tenth clock signal line;

[0104] The first clock signal terminal, the second clock signal terminal, the third clock signal terminal, and the fourth clock signal terminal of the fifth shift register in each group are respectively electrically connected to the sixth clock signal line, the fifth clock signal line, the eleventh clock signal line, and the twelfth clock signal line;

[0105] The first clock signal terminal, the second clock signal terminal, the third clock signal terminal, and the fourth clock signal terminal of the sixth shift register in each group are respectively electrically connected to the eighth clock signal line, the seventh clock signal line, the first clock signal line, and the second clock signal line.

[0106] In a third aspect, an embodiment of the present disclosure provides a display device, which includes the gate driving circuit described in any one of the above.

[0107] Wherein, the display device is a virtual reality display device. Description of the Drawings

[0108] Figure 1 It is a schematic structural diagram of a shift register according to an embodiment of the present disclosure.

[0109] Figure 2 It is a schematic structural diagram of another shift register according to an embodiment of the present disclosure.

[0110] Figure 3 The circuit diagram of the shift register according to the embodiment of the present disclosure.

[0111] Figure 4 The cascade schematic diagram of the gate driving circuit of the first example according to the embodiment of the present disclosure.

[0112] Figure 5 For Figure 4 The output result simulation diagram of the partial shift register driven by the gate.

[0113] Figure 6 The cascade schematic diagram of the gate driving circuit of the second example according to the embodiment of the present disclosure.

[0114] Figure 7 For Figure 6 The output result simulation diagram of the partial shift register driven by the gate.

[0115] Figure 8 The cascade schematic diagram of the gate driving circuit of the third example according to the embodiment of the present disclosure.

[0116] Figure 9 The cascade schematic diagram of the gate driving circuit of the fourth example according to the embodiment of the present disclosure.

[0117] Figure 10 The cascade schematic diagram of the gate driving circuit of the fifth example according to the embodiment of the present disclosure.

[0118] Figure 11 The cascade schematic diagram of the gate driving circuit of the sixth example according to the embodiment of the present disclosure.

[0119] Figure 12 For Figure 11 The output result simulation diagram of the partial shift register driven by the gate. Detailed implementation manners

[0120] To enable those skilled in the art to better understand the technical solutions of the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific implementation manners.

[0121] Unless otherwise defined, technical terms or scientific terms used in this disclosure shall have the ordinary meanings as understood by those of ordinary skill in the art to which this disclosure pertains. The terms "first", "second" and similar words used in this disclosure do not denote any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "a", "an" or "the" do not denote a quantity limitation, but mean that there is at least one. Words such as "comprising" or "including" mean that the elements or objects appearing before this word cover the elements or objects listed after this word and their equivalents, without excluding other elements or objects. Words such as "connected" or "coupled" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. Words such as "upper", "lower", "left" and "right" are only used to indicate relative positional relationships, and when the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0122] As users' demands for narrow borders and high-resolution PPI are increasing, it is necessary to reduce the occupied space of the gate driving circuit so that the area of the display region can be as large as possible. Therefore, a gate driving signal required for outputting two rows of gate lines can be provided by a single shift register. However, with the increase in PPI, the screen resolution is getting higher and higher, the voltage drop of the shift register is getting more and more serious, the 1H (horizontal scan time) is getting shorter and shorter, and the output Tr (rise time) / Tf (fall time) increases. When the shift registers in the gate driving circuit are cascaded, display anomalies will occur after several horizontal scans.

[0123] To address the above technical problems, the following technical solutions are provided in the embodiments of this disclosure. Before describing the technical solutions of the embodiments of this disclosure, it should be noted that the transistors used in the embodiments of this disclosure can all be thin-film transistors, field-effect transistors or other devices with the same characteristics. In this embodiment, the coupling manner of the drain and source of each transistor can be interchanged. Therefore, in the embodiments of this disclosure, the drains and sources of the transistors actually have no difference. Here, it is only to distinguish the two poles of the transistor other than the control pole (i.e., the gate), and one of the poles is called the drain and the other is called the source. The transistors used in the embodiments of this disclosure can be N-type transistors or P-type transistors. In the embodiments of this disclosure, when an N-type transistor is used, its first pole can be the source and its second pole can be the drain. In the following embodiments, the description is made by taking the transistor as an N-type transistor as an example, that is, when the signal of the control pole is at a high level, the transistor is turned on. It can be imagined that when a P-type transistor is used, the timing change of the driving signal needs to be adjusted accordingly. The specific details are not elaborated here, but they should also be within the protection scope of this disclosure. Only N-type transistors are taken as examples in the embodiments of this disclosure.

[0124] In addition, the "operating level signal" involved in the embodiments of the present disclosure refers to the level that can control the conduction of the corresponding transistor, and the "non-operating level signal" refers to the level that can control the cut-off of the corresponding transistor. For an N-type transistor, a high-level signal is an operating level signal, while a low-level signal is a non-operating level signal. In the embodiments of the present disclosure, the specific voltage magnitudes of the "operating level" and the "non-operating level" are not limited.

[0125] In a first aspect, Figure 1 is a schematic structural diagram of a shift register according to an embodiment of the present disclosure; as Figure 1 shown, the embodiments of the present disclosure provide a shift register, which includes a first input sub-circuit 1, a second input sub-circuit 2, a first output sub-circuit 3, a second output sub-circuit 4, a first cascading sub-circuit 5, and a second cascading sub-circuit 6. Among them, the first input sub-circuit 1 is configured to pre-charge a first pull-up node PU1 through a first scan signal in response to a first input signal; the first input sub-circuit 1 is configured to pre-charge a second pull-up node PU2 through a second scan signal in response to a second input signal; the first output sub-circuit 3 is configured to output a third clock signal through a first signal output terminal Output1 in response to the potential of the first pull-up node PU1; the first cascading sub-circuit 5 is configured to output the third clock signal through a first cascading signal terminal Output1' in response to the potential of the first pull-up node PU1; the second output sub-circuit 4 is configured to output a fourth clock signal through a second signal output terminal Output2 in response to the potential of the second pull-up node PU2; the second cascading sub-circuit 6 is configured to output the fourth clock signal through a second cascading signal terminal Output2' in response to the potential of the second pull-up node PU2.

[0126] In the shift register of the embodiments of the present disclosure, while configuring two output sub-circuits, the first output sub-circuit 3 and the second output sub-circuit 4, a first cascading sub-circuit 5 that outputs simultaneously with the first output sub-circuit 3 and outputs the same signal, and a second cascading sub-circuit 6 that outputs simultaneously with the second output sub-circuit 4 and outputs the same signal are configured. When applying the shift register in the embodiments of the present disclosure to a gate driving circuit, the first cascading signal terminal Output1' of the first cascading sub-circuit 5 and the second cascading signal terminal Output2' of the second cascading sub-circuit 6 can be respectively connected to the corresponding cascaded shift registers. The first cascading signal terminal Output1' and the second cascading signal terminal Output2' are not electrically connected to the pixel driving circuit in the display panel, that is, there is no connection to the load. Therefore, there will be no voltage drop during the cascading of the shift registers, and thus the technical problems existing in the existing structure can be effectively improved, and the reliability can be improved.

[0127] In some examples, Figure 3The circuit diagram of the shift register according to the embodiments of the present disclosure; as Figure 3 shown, the first input sub-circuit 1 includes a first transistor T1; the source of the first transistor T1 is connected to the first scan signal terminal CN, the drain of the first transistor T1 is connected to the pull-up control node PUCN, and the gate of the first transistor T1 is connected to the first signal input terminal Input1; the pull-up control node PUCN is the connection node between the first input sub-circuit 1 and the second input sub-circuit 2.

[0128] Among them, the first scan signal may be a forward scan signal, and the forward scan signal and the reverse scan signal are a pair of relative signals. For example, if the forward scan signal represents a progressive scan from the first row to the last row, then the reverse scan signal represents a progressive scan from the last row to the first row. In the embodiments of the present disclosure, only the first scan signal as a forward scan signal is taken as an example.

[0129] Specifically, when scanning forward, the first scan signal written to the first scan signal terminal CN is a high-level signal, and the first input signal written to the first signal input terminal Input1 is a high-level signal. At this time, the first transistor T1 is turned on, the pull-up control node PUCN is written with a high-level signal, and the first pull-up node PU1 and the second pull-up node PU2 are pre-charged.

[0130] In some examples, continue to refer to Figure 3 , the second input sub-circuit 2 includes a second transistor T2; the first end of the second transistor T2 is connected to the second scan signal terminal CNB, the drain of the second transistor T2 is connected to the pull-up control node PUCN, and the gate of the second transistor T2 is connected to the second signal input terminal Input12; the pull-up control node PUCN is the connection node between the first input sub-circuit 1 and the second input sub-circuit 2.

[0131] Among them, when the first scan signal is a forward scan signal, the second scan signal is a reverse scan signal. Specifically, when scanning in reverse, the second scan signal written to the second scan signal terminal CNB is a high-level signal, and the second input signal written to the second signal input terminal Input12 is a high-level signal. At this time, the second transistor T2 is turned on, the pull-up control node PUCN is written with a high-level signal, and the first pull-up node PU1 and the second pull-up node PU2 are pre-charged.

[0132] In some examples, continue to refer to Figure 3, the first output sub - circuit 3 includes: a third transistor T3 and a first storage capacitor C1; wherein, the source of the third transistor T3 is connected to the third clock signal terminal CK3, the drain of the third transistor T3 is connected to the first signal output terminal Output1, and the gate of the third transistor T3 is connected to the first pull - up node PU1; the first end of the first storage capacitor C1 is connected to the first pull - up node PU1, and the second end of the first storage capacitor C1 is connected to the first signal output terminal Output1.

[0133] Specifically, when the first pull - up node PU1 is pre - charged, that is, the first storage capacitor C1 is charged, the first pull - up node PU1 is a high - level signal, the third transistor T3 is turned on, and the first clock signal written by the third clock signal terminal CK3 is output through the first signal output terminal Output1.

[0134] In some examples, continue to refer to Figure 3 , the first cascaded sub - circuit 5 includes a fourteenth transistor T14; the source of the fourteenth transistor T14 is connected to the third clock signal terminal CK3, the drain of the fourteenth transistor T14 is connected to the first cascaded signal terminal Output1', and the gate of the fourteenth transistor T14 is connected to the first pull - up node PU1.

[0135] Specifically, when the first pull - up node PU1 is a high - level signal, the fourteenth transistor T14 is turned on, and the third clock signal written by the third clock signal terminal CK3 is output through the first cascaded signal terminal Output1'. It can be seen that since both the fourteenth transistor T14 and the third transistor T3 are controlled by the potential of the first pull - up node PU1, the outputs of the first cascaded signal output terminal and the first signal output terminal Output1 are synchronous.

[0136] In some examples, continue to refer to Figure 3 , the second output sub - circuit 4 includes a twelfth transistor T12 and a third storage capacitor C3; the source of the third transistor T3 is connected to the fourth clock signal terminal CK4, the drain of the twelfth transistor T12 is connected to the second signal output terminal Output2, and the gate of the twelfth transistor T12 is connected to the second pull - up node PU2; the first end of the third storage capacitor C3 is connected to the second pull - up node PU2, and the second end of the third storage capacitor C3 is connected to the second signal output terminal Output2.

[0137] Specifically, when the first pull - up node PU1 is pre - charged, that is, the third storage capacitor C3 is charged, the second pull - up node PU2 is a high - level signal, the twelfth transistor T12 is turned on, and the fourth clock signal written by the fourth clock signal terminal CK4 is output through the second signal output terminal Output2.

[0138] In some examples, continue to refer toFigure 3 The second cascaded sub-circuit 6 includes a seventeenth transistor T17; the source of the seventeenth transistor T17 is connected to the fourth clock signal terminal CK4, the drain of the seventeenth transistor T17 is connected to the second cascaded signal terminal Output2', and the gate of the seventeenth transistor T17 is connected to the second pull-up node PU2.

[0139] Specifically, when the second pull-up node PU2 is at a high-level signal, the seventeenth transistor T17 is turned on, and the fourth clock signal written by the fourth clock signal terminal CK4 is output through the second cascaded signal terminal Output2'. It can be seen that since both the seventeenth transistor T17 and the twelfth transistor T12 are controlled by the potential of the second pull-up node PU2, the outputs of the second cascaded signal output terminal and the second signal output terminal Output2 are synchronized.

[0140] In some examples, Figure 2 is a schematic structural diagram of another shift register according to an embodiment of the present disclosure; as Figure 2 shown, the shift register according to the embodiment of the present disclosure not only includes the above structure, but may also include: a first pull-up control sub-circuit 7 and a second pull-up control sub-circuit 8; the first pull-up control sub-circuit 7 is configured to transmit a first scan signal to the first pull-up node PU1 in response to a working level signal to pre-charge the first pull-up node PU1; the second pull-up control sub-circuit 8 is configured to transmit the first scan signal to the second pull-up node PU2 in response to the working level signal to pre-charge the second pull-up node PU2.

[0141] In the embodiment of the present disclosure, by providing the first pull-up control sub-circuit 7 and the second pull-up control sub-circuit 8, it is possible to effectively avoid the influence on the first output sub-circuit 3 and the second output sub-circuit 4 when the current flowing through the pull-up control node PUCN is too large.

[0142] In some examples, continue to refer to Figure 3 The first pull-up control sub-circuit 7 includes a ninth transistor T9; the source of the ninth transistor T9 is connected to the first pull-up node PU1, the drain of the ninth transistor T9 is connected to the pull-up control node PUCN, and the gate of the ninth transistor T9 is connected to the high-level signal terminal VGH; the pull-up control node PUCN is a connection node between the first input sub-circuit 1 and the second input sub-circuit 2.

[0143] Specifically, the high-level signal terminal VGH continuously loads a high-level signal, the ninth transistor T9 is always on, and the potential of the pull-up control node PUCN is transmitted to the first pull-up node PU1 through the ninth transistor T9.

[0144] In some examples, continue to refer to Figure 3, the second pull-up control sub-circuit 8 includes a fourteenth transistor T14; the source of the fourteenth transistor T14 is connected to the second pull-up node PU2, the drain of the fourteenth transistor T14 is connected to the pull-up control node PUCN, and the gate of the fourteenth transistor T14 is connected to the high-level signal terminal VGH; the pull-up control node PUCN is the connection node between the first input sub-circuit 1 and the second input sub-circuit 2.

[0145] Specifically, the high-level signal terminal VGH continuously loads a high-level signal, the fourteenth transistor T14 is normally open, and the potential of the pull-up control node PUCN is transmitted to the second pull-up node PU2 through the fourteenth transistor T14.

[0146] In some examples, as Figure 2 shown, the shift register of the embodiments of the present disclosure not only includes the above structures, but may also include a first node control sub-circuit 9, a second node control sub-circuit 10, a pull-down control sub-circuit 11, and a pull-down sub-circuit 12. Among them, the first node control sub-circuit 9 is configured to respond to a first scan signal and control the potential of the pull-down control node PDCN through a first clock signal; the second node control sub-circuit 10 is configured to respond to a second scan signal and control the potential of the pull-down control node PDCN through a second clock signal; the pull-down control sub-circuit 11 is configured to respond to the potential of the pull-down control node PDCN and control the potential of the pull-down node PD through a working level signal, and respond to the potential of the pull-up control node PUCN and control the potential of the pull-down node PD through a non-working level signal; the pull-down sub-circuit 12 is configured to respond to the potential of the pull-down node PD and pull down the potential of the pull-up control node PUCN, the output of the first signal output terminal Output1, the output of the second signal output terminal Output2, the output of the first cascade signal terminal Output1', and the output of the second cascade signal terminal Output2' through a non-working level signal.

[0147] Specifically, continue to refer to Figure 3 , the first node control sub-circuit 9 includes a fifth transistor T5; the source of the fifth transistor T5 is connected to the first clock signal terminal CK1, the drain of the fifth transistor T5 is connected to the pull-down control node PDCN, and the gate of the fifth transistor T5 is connected to the first scan signal terminal CN.

[0148] When scanning forward, a high-level signal is written to the first scan signal terminal CN, the fifth transistor T5 is turned on, and the first clock signal written to the first clock signal terminal CK1 is written to the pull-down control node PDCN.

[0149] Specifically, continue to refer to Figure 3, the second node control sub-circuit 10 includes a sixth transistor T6; the source of the sixth transistor T6 is connected to the second clock signal terminal CK2, the drain of the sixth transistor T6 is connected to the pull-down control node PDCN, and the gate of the sixth transistor T6 is connected to the second scan signal terminal CNB.

[0150] During reverse scanning, a high-level signal is written to the second scan signal terminal, the sixth transistor T6 is turned on, and the second clock signal written to the second clock signal terminal CK2 is written to the pull-down control node PDCN.

[0151] Specifically, continue to refer to Figure 3 , the pull-down control sub-circuit 11 includes an eighth transistor T8, a tenth transistor T10, and a second storage capacitor C2; wherein, the source of the eighth transistor T8 is connected to the pull-down node PD, the drain of the eighth transistor T8 is connected to the low-level signal terminal VGL, and the gate of the eighth transistor T8 is connected to the pull-up control node PUCN; the pull-up control node PUCN is the connection node between the first input sub-circuit 1 and the second input sub-circuit 2; the source of the tenth transistor T10 is connected to the operating level signal terminal, the drain of the tenth transistor T10 is connected to the pull-down node PD, and the gate of the tenth transistor T10 is connected to the pull-down control node PDCN; the first end of the second storage capacitor C2 is connected to the pull-down node PD, and the second end of the second storage capacitor C2 is connected to the low-level signal terminal VGL.

[0152] When the pull-down control node PDCN is a high-level signal, the tenth transistor T10 is turned on, and the potential of the pull-down node PD is pulled up to a high-level signal. When the pull-up control node PUCN is a high-level signal, the eighth transistor T8 is turned on, and the potential of the pull-down node PD is pulled down to a low-level signal.

[0153] Specifically, continue to refer to Figure 3, the pull-down sub-circuit 12 includes a fourth transistor T4, a seventh transistor T7, a thirteenth transistor T13, a fifteenth transistor T15, and a seventeenth transistor T17. The source of the fourth transistor T4 is connected to the first signal output terminal Output1, the drain of the fourth transistor T4 is connected to the low-level signal terminal VGL, and the gate of the fourth transistor T4 is connected to the pull-down node PD. The source of the seventh transistor T7 is connected to the pull-up control node PUCN, the drain of the seventh transistor T7 is connected to the low-level signal terminal VGL, and the gate of the seventh transistor T7 is connected to the pull-down node PD; the pull-up control node PUCN is the connection node between the first input sub-circuit 1 and the second input sub-circuit 2. The source of the thirteenth transistor T13 is connected to the second signal output terminal Output2, the drain of the thirteenth transistor T13 is connected to the low-level signal terminal VGL, and the gate of the thirteenth transistor T13 is connected to the pull-down node PD; the source of the fifteenth transistor T15 is connected to the first cascaded signal output terminal, the drain of the fifteenth transistor T15 is connected to the low-level signal terminal VGL, and the gate of the fifteenth transistor T15 is connected to the pull-down node PD; the source of the seventeenth transistor T17 is connected to the second cascaded signal output terminal, the drain of the seventeenth transistor T17 is connected to the low-level signal terminal VGL, and the gate of the seventeenth transistor T17 is connected to the pull-down node PD.

[0154] When the potential of the pull-down node PD is a high-level signal, for the fourth transistor T4, the seventh transistor T7, the thirteenth transistor T13, the fifteenth transistor T15, and the seventeenth transistor T17, the fourth transistor T4 pulls down the output of the first signal output terminal Output1 through a low-level signal, the seventh transistor T7 pulls down the output of the pull-up control node PUCN through a low-level signal, the thirteenth transistor T13 pulls down the output of the second signal output terminal Output2 through a low-level signal, the fifteenth transistor T15 pulls down the output of the first cascaded signal terminal Output1' through a low-level signal, and the seventeenth transistor T17 pulls down the output of the second cascaded signal terminal Output2' through a low-level signal, thereby reducing the output noise of the pull-up control node PUCN, the first signal output terminal Output1, the second signal output terminal Output2, the first cascaded signal terminal Output1', and the second cascaded signal terminal Output2'.

[0155] In some examples, as Figure 2 shown, the shift register of the embodiments of the present disclosure not only includes the above structure, but may also include: a reset sub-circuit 13 configured to reset the pull-up control node PUCN through a low-level signal in response to a reset signal; the pull-up control node PUCN is the connection node between the first input sub-circuit 1 and the second input sub-circuit 2.

[0156] Specifically, continue to refer to Figure 3, the reset sub-circuit 13 includes an eleventh transistor T11; the source of the eleventh transistor T11 is connected to the pull-up control node PUCN, the drain of the eleventh transistor T11 is connected to the low-level signal terminal VGL, and the gate of the eleventh transistor T11 is connected to the reset signal terminal RESET.

[0157] When a high-level signal is written to the reset signal terminal RESET, the eleventh transistor T11 is turned on, and the low-level signal written through the low-level signal terminal VGL resets the pull-up control node PUCN.

[0158] To make the shift register according to the embodiments of the present disclosure clearer, refer to Figure 2 and 3 As shown, a specific shift register structure is provided below, which includes a first input sub-circuit 1, a second input sub-circuit 2, a first output sub-circuit 3, a second output sub-circuit 4, a first cascading sub-circuit 5, a second cascading sub-circuit 6, a first pull-up control sub-circuit 7, a second pull-up control sub-circuit 8, a first node control sub-circuit 9, a second node control sub-circuit 10, a pull-down control sub-circuit 11, a pull-down sub-circuit 12, and a reset sub-circuit 13.

[0159] Specifically, as Figure 3 shown, the first input sub-circuit 1 includes a first transistor T1; the second input sub-circuit 2 includes a second transistor T2; the first output sub-circuit 3 includes: a third transistor T3 and a first storage capacitor C1; the first cascading sub-circuit 5 includes a fourteenth transistor T14; the second output sub-circuit 4 includes a twelfth transistor T12 and a third storage capacitor C3; the second cascading sub-circuit 6 includes a seventeenth transistor T17; the first pull-up control sub-circuit 7 includes a ninth transistor T9; the second pull-up control sub-circuit 8 includes a fourteenth transistor T14; the first node control sub-circuit 9 includes a fifth transistor T5; the second node control sub-circuit 10 includes a sixth transistor T6; the pull-down control sub-circuit 11 includes an eighth transistor T8, a tenth transistor T10, and a second storage capacitor C2; the pull-down sub-circuit 12 includes a fourth transistor T4, a seventh transistor T7, a thirteenth transistor T13, a fifteenth transistor T15, and a seventeenth transistor T17.

[0160] Further, continue to refer to Figure 3, the source of the first transistor T1 is connected to the first scan signal terminal CN, the drain of the first transistor T1 is connected to the pull-up control node PUCN, and the gate of the first transistor T1 is connected to the first signal input terminal Input1. The first end of the second transistor T2 is connected to the second scan signal terminal CNB, the drain of the second transistor T2 is connected to the pull-up control node PUCN, and the gate of the second transistor T2 is connected to the second signal input terminal Input12. The source of the third transistor T3 is connected to the third clock signal terminal CK3, the drain of the third transistor T3 is connected to the first signal output terminal Output1, and the gate of the third transistor T3 is connected to the first pull-up node PU1; the first end of the first storage capacitor C1 is connected to the first pull-up node PU1, and the second end of the first storage capacitor C1 is connected to the first signal output terminal Output1. The source of the third transistor T3 is connected to the fourth clock signal terminal CK4, the drain of the twelfth transistor T12 is connected to the second signal output terminal Output2, and the gate of the twelfth transistor T12 is connected to the second pull-up node PU2; the first end of the third storage capacitor C3 is connected to the second pull-up node PU2, and the second end of the third storage capacitor C3 is connected to the second signal output terminal Output2. The source of the seventeenth transistor T17 is connected to the fourth clock signal terminal CK4, the drain of the seventeenth transistor T17 is connected to the second cascade signal terminal Output2', and the gate of the seventeenth transistor T17 is connected to the second pull-up node PU2. The source of the ninth transistor T9 is connected to the first pull-up node PU1, the drain of the ninth transistor T9 is connected to the pull-up control node PUCN, and the gate of the ninth transistor T9 is connected to the high-level signal terminal VGH. The source of the fourteenth transistor T14 is connected to the second pull-up node PU2, the drain of the fourteenth transistor T14 is connected to the pull-up control node PUCN, and the gate of the fourteenth transistor T14 is connected to the high-level signal terminal VGH. The source of the fifth transistor T5 is connected to the first clock signal terminal CK1, the drain of the fifth transistor T5 is connected to the pull-down control node PDCN, and the gate of the fifth transistor T5 is connected to the first scan signal terminal CN. The source of the sixth transistor T6 is connected to the second clock signal terminal CK2, the drain of the sixth transistor T6 is connected to the pull-down control node PDCN, and the gate of the sixth transistor T6 is connected to the second scan signal terminal CNB. The source of the eighth transistor T8 is connected to the pull-down node PD, the drain of the eighth transistor T8 is connected to the low-level signal terminal VGL, and the gate of the eighth transistor T8 is connected to the pull-up control node PUCN; the source of the tenth transistor T10 is connected to the operating level signal terminal, the drain of the tenth transistor T10 is connected to the pull-down node PD, and the gate of the tenth transistor T10 is connected to the pull-down control node PDCN; the first end of the second storage capacitor C2 is connected to the pull-down node PD, and the second end of the second storage capacitor C2 is connected to the low-level signal terminal VGL.The source of the fourth transistor T4 is connected to the first signal output terminal Output1, the drain of the fourth transistor T4 is connected to the low-level signal terminal VGL, and the gate of the fourth transistor T4 is connected to the pull-down node PD. The source of the seventh transistor T7 is connected to the pull-up control node PUCN, the drain of the seventh transistor T7 is connected to the low-level signal terminal VGL, and the gate of the seventh transistor T7 is connected to the pull-down node PD; the pull-up control node PUCN is the connection node between the first input sub-circuit 1 and the second input sub-circuit 2. The source of the thirteenth transistor T13 is connected to the second signal output terminal Output2, the drain of the thirteenth transistor T13 is connected to the low-level signal terminal VGL, and the gate of the thirteenth transistor T13 is connected to the pull-down node PD; the source of the fifteenth transistor T15 is connected to the first cascaded signal output terminal, the drain of the fifteenth transistor T15 is connected to the low-level signal terminal VGL, and the gate of the fifteenth transistor T15 is connected to the pull-down node PD; the source of the seventeenth transistor T17 is connected to the second cascaded signal output terminal, the drain of the seventeenth transistor T17 is connected to the low-level signal terminal VGL, and the gate of the seventeenth transistor T17 is connected to the pull-down node PD.

[0161] Only the forward scan is taken as an example below to illustrate the working process of the shift register.

[0162] First stage: A high-level signal is written to the first signal input terminal Input1, a high-level signal is written to the first scan signal terminal CN, the first transistor T1 and the fifth transistor T5 are turned on, the pull-up control node PUCN is charged to a high-level signal, and the first pull-up node PU1 and the twelfth pull-up node are pre-charged through the ninth transistor T9 and the fourteenth transistor T14. A low-level signal is written to the first clock signal terminal CK1, and at this time, the tenth transistor T10 is turned off.

[0163] Second stage: Both the first pull-up node PU1 and the second pull-up node PU2 are charged to a high-level signal. The third transistor T3, the fourteenth transistor T14, the twelfth transistor T12, and the sixteenth transistor T16 are all turned on. When the third clock signal input by the third clock signal is a high-level signal, the first signal output terminal Output1 and the first cascaded signal terminal Output1' synchronously output high-level signals; when the fourth clock signal input by the fourth clock signal terminal CK4 is a high-level signal, the second signal output terminal Output2 and the second cascaded signal terminal Output2' synchronously output high-level signals.

[0164] Third stage: A high-level signal is written to the reset signal terminal RESET, the eleventh transistor T11 is turned on, and the potential of the pull-up node is reset.

[0165] The fourth stage: the first clock signal written into the first clock signal terminal CK1 is a high-level signal, the tenth transistor T10 is turned on, the pull-down node PD is pulled high, the fourth transistor T4, the seventh transistor T7, the thirteenth transistor T13, the fifteenth transistor T15 and the seventeenth transistor T17 are turned on, the fourth transistor T4 pulls down the output of the first signal output terminal Output1 through a low-level signal, the seventh transistor T7 pulls down the output of the pull-up control node PUCN through a low-level signal, the thirteenth transistor T13 pulls down the output of the second signal output terminal Output2 through a low-level signal, the fifteenth transistor T15 pulls down the output of the first cascade signal terminal Output1' through a low-level signal, and the seventeenth transistor T17 pulls down the output of the second cascade signal terminal Output2' through a low-level signal, thereby reducing the output noise of the pull-up control node PUCN, the first signal output terminal Output1, the second signal output terminal Output2, the first cascade signal terminal Output1' and the second cascade signal terminal Output2'.

[0166] In a second aspect, an embodiment of the present disclosure provides a gate drive circuit, which includes a plurality of shift registers, wherein the shift registers include any of the shift registers described above. Of course, the shift registers of the embodiment of the present disclosure also include a clock signal line that provides a clock signal to each clock signal line.

[0167] In order to make the gate drive circuit of the embodiment of the present disclosure clearer, the gate drive circuit including 6, 8, and 12 clock signal lines is used as an example to illustrate the cascade relationship of the gate drive circuit of the embodiment of the present disclosure. Figure 3 The shift register shown is taken as an example, but this does not constitute a limitation on the protection scope of the embodiments of the present disclosure.

[0168] First example: Figure 4 FIG. 4 is a schematic diagram of a cascade connection of a gate driving circuit according to a first example of an embodiment of the present disclosure; Figure 4 As shown, the gate drive circuit includes 6 clock signal lines, namely, the first clock signal line ck1, the second clock signal line ck2, the third clock signal line ck3, the fourth clock signal line, the fifth clock signal line ck5 and the sixth clock signal line ck6. Except for the last stage of the shift register, the first cascade signal terminal Output1' of the shift register of this stage is connected to the first signal input terminal Input1 of the next stage of the shift register; except for the first stage of the shift register, the first cascade signal terminal Output1' of the shift register of this stage is connected to the second signal input terminal Input12 of the previous stage of the shift register. The first signal input terminal Input1 of the first stage of the shift register is respectively connected to the frame start signal line STV.

[0169] Specifically, the multiple shift registers are at least divided into N groups, each group including 3 arranged in sequence, N≥2, and N is a positive integer.

[0170] As Figure 4 shown, the first clock signal terminal CK1, the second clock signal terminal CK2, the third clock signal terminal CK3, and the fourth clock signal terminal CK4 of the first shift register in each group are respectively electrically connected to the sixth clock signal line ck6, the first clock signal line ck1, the second clock signal line ck2, and the third clock signal line ck3; the first clock signal terminal CK1, the second clock signal terminal CK2, the third clock signal terminal CK3, and the fourth clock signal terminal CK4 of the second shift register in each group are respectively electrically connected to the second clock signal line ck2, the third clock signal line ck3, the fifth clock signal line ck5, and the sixth clock signal line ck6; the first clock signal terminal CK1, the second clock signal terminal CK2, the third clock signal terminal CK3, and the fourth clock signal terminal CK4 of the third shift register in each group are respectively electrically connected to the fourth clock signal line ck4, the fifth clock signal line ck5, the first clock signal line ck1, and the second clock signal line ck2.

[0171] The working principle of each stage of the shift register is the same as that of the above example, so it will not be repeated here. Figure 5 For Figure 4 the output result simulation diagram of the partial shift register driven by the gate, as Figure 5 shown, the Tf of the interlaced gate drive signal is consistent, improving the reliability of the gate drive circuit.

[0172] The second example: Figure 6 This is the cascade schematic diagram of the gate drive circuit of the second example of the present disclosure; as Figure 6 shown, the gate drive circuit includes 6 clock signal lines, namely the first clock signal line ck1, the second clock signal line ck2, the third clock signal line ck3, the fourth clock signal line, the fifth clock signal line ck5, and the sixth clock signal line ck6. Except for the last stage of the shift register, the first cascade signal terminal Output1' of the current stage of the shift register is connected to the first signal input terminal Input1 of the next stage of the shift register; except for the first stage of the shift register, the first cascade signal terminal Output1' of the current stage of the shift register is connected to the second signal input terminal Input12 of the previous stage of the shift register. The first signal input terminal Input1 of the first stage of the shift register is respectively connected to the frame start signal line STV.

[0173] The multiple shift registers are at least divided into N groups, each group including 3 arranged in sequence, N≥2, and N is a positive integer.

[0174] The first clock signal terminals CK1, second clock signal terminals CK2, third clock signal terminals CK3, and fourth clock signal terminals CK4 of the first shift register in each group are respectively electrically connected to the first clock signal line ck1, second clock signal line ck2, third clock signal line ck3, and fourth clock signal line ck4; the first clock signal terminals CK1, second clock signal terminals CK2, third clock signal terminals CK3, and fourth clock signal terminals CK4 of the second shift register in each group are respectively electrically connected to the third clock signal line ck3, fourth clock signal line ck4, fifth clock signal line ck5, and sixth clock signal line ck6; the first clock signal terminals CK1, second clock signal terminals CK2, third clock signal terminals CK3, and fourth clock signal terminals CK4 of the third shift register in each group are respectively electrically connected to the fifth clock signal line ck5, sixth clock signal line ck6, first clock signal line ck1, and second clock signal line ck2.

[0175] The working principle of each stage of the shift register is the same as that of the above example, so it will not be repeated here. Figure 7 For Figure 6 The output result simulation diagram of the partial shift register driven by the gate, as Figure 7 shown, the Tf of the interlaced gate drive signal is consistent, improving the reliability of the gate drive circuit.

[0176] The third example: Figure 8 is the cascade schematic diagram of the gate drive circuit of the third example of the present disclosure; as Figure 8 shown, the gate drive circuit includes 8 clock signal lines, which are the first clock signal line ck1, second clock signal line ck2, third clock signal line ck3, fourth clock signal line, fifth clock signal line ck5, sixth clock signal line ck6, seventh clock signal line ck7, and eighth clock signal line ck8.

[0177] The number of shift registers is M, and the M shift registers are at least divided into N groups, each group includes 4 arranged in sequence, N≥2, and both M and N are positive integers.

[0178] The first signal output terminal Output1 of the i-th shift register is connected to the first signal input terminal Input1 of the (i + 2)-th shift register; i takes values from 1 to (M - 2); the second signal output terminal Output2 of the j-th shift register is connected to the second signal input terminal Input12 of the (j - 2)-th shift register; j takes values from 3 to M. The first signal input terminals Input1 of the first-stage and second-stage shift registers are respectively connected to the first frame start signal line and the second frame start signal line.

[0179] The first clock signal terminals CK1, second clock signal terminals CK2, third clock signal terminals CK3, and fourth clock signal terminals CK4 of the first shift register in each group are respectively electrically connected to the seventh clock signal line ck7, eighth clock signal line ck8, third clock signal line ck3, and fourth clock signal line ck4; the first clock signal terminals CK1, second clock signal terminals CK2, third clock signal terminals CK3, and fourth clock signal terminals CK4 of the second shift register in each group are respectively electrically connected to the first clock signal line ck1, second clock signal line ck2, fifth clock signal line ck5, and sixth clock signal line ck6; the first clock signal terminals CK1, second clock signal terminals CK2, third clock signal terminals CK3, and fourth clock signal terminals CK4 of the third shift register in each group are respectively electrically connected to the third clock signal line ck3, fourth clock signal line ck4, seventh clock signal line ck7, and eighth clock signal line ck8; the first clock signal terminals CK1, second clock signal terminals CK2, third clock signal terminals CK3, and fourth clock signal terminals CK4 of the fourth shift register in each group are respectively electrically connected to the fifth clock signal line ck5, sixth clock signal line ck6, first clock signal line ck1, and second clock signal line ck2.

[0180] The working principle of each stage of the shift register is the same as that of the above example, so it will not be repeated here.

[0181] The fourth example: Figure 9 It is a cascade schematic diagram of the gate driving circuit of the fourth example of this disclosure; as Figure 9 shown, the gate driving circuit further includes 12 clock signal lines, which are the first clock signal line ck1, second clock signal line ck2, third clock signal line ck3, fourth clock signal line, fifth clock signal line ck5, sixth clock signal line ck6, seventh clock signal line ck7, eighth clock signal line ck8, ninth clock signal line ck9, tenth clock signal line ck10, eleventh clock signal line ck11, and twelfth clock signal line ck12.

[0182] The number of shift registers is M, and the M shift registers are at least divided into N groups, each group includes 6 arranged in sequence, N≥2, and both M and N are positive integers.

[0183] The first cascaded signal terminal Output1' of the i-th shift register is connected to the first signal input terminal Input1 of the (i + 2)-th shift register; i ranges from 1 to (M - 2); the second cascaded signal terminal Output2' of the j-th shift register is connected to the second signal input terminal Input12 of the (j - 2)-th shift register; j ranges from 3 to M. The first signal input terminals Input1 of the first-stage and second-stage shift registers are respectively connected to the first frame start signal line and the second frame start signal line.

[0184] The first clock signal terminal CK1, the second clock signal terminal CK2, the third clock signal terminal CK3, and the fourth clock signal terminal CK4 of the first shift register in each group are respectively electrically connected to the tenth clock signal line ck10, the ninth clock signal line ck9, the third clock signal line ck3, and the fourth clock signal line ck4;

[0185] The first clock signal terminal CK1, the second clock signal terminal CK2, the third clock signal terminal CK3, and the fourth clock signal terminal CK4 of the second shift register in each group are respectively electrically connected to the twelfth clock signal line ck12, the eleventh clock signal line ck11, the fifth clock signal line ck5, and the sixth clock signal line ck6; the first clock signal terminal CK1, the second clock signal terminal CK2, the third clock signal terminal CK3, and the fourth clock signal terminal CK4 of the third shift register in each group are respectively electrically connected to the second clock signal line ck2, the first clock signal line ck1, the seventh clock signal line ck7, and the eighth clock signal line ck8; the first clock signal terminal CK1, the second clock signal terminal CK2, the third clock signal terminal CK3, and the fourth clock signal terminal CK4 of the fourth shift register in each group are respectively electrically connected to the fourth clock signal line ck4, the third clock signal line ck3, the ninth clock signal line ck9, and the tenth clock signal line ck10; the first clock signal terminal CK1, the second clock signal terminal CK2, the third clock signal terminal CK3, and the fourth clock signal terminal CK4 of the fifth shift register in each group are respectively electrically connected to the sixth clock signal line ck6, the fifth clock signal line ck5, the eleventh clock signal line ck11, and the twelfth clock signal line ck12; the first clock signal terminal CK1, the second clock signal terminal CK2, the third clock signal terminal CK3, and the fourth clock signal terminal CK4 of the sixth shift register in each group are respectively electrically connected to the eighth clock signal line ck8, the seventh clock signal line ck7, the first clock signal line ck1, and the second clock signal line ck2.

[0186] The fifth example: Figure 10 is a cascaded schematic diagram of the gate driving circuit according to the fifth example of the present disclosure; as Figure 10As shown, the gate driving circuit further includes 12 clock signal lines, namely a first clock signal line ck1, a second clock signal line ck2, a third clock signal line ck3, a fourth clock signal line, a fifth clock signal line ck5, a sixth clock signal line ck6, a seventh clock signal line ck7, an eighth clock signal line ck8, a ninth clock signal line ck9, a tenth clock signal line ck10, an eleventh clock signal line ck11, and a twelfth clock signal line ck12.

[0187] The number of shift registers is M, and the M shift registers are at least divided into N groups, each group including 6 arranged in sequence, N≥2, and both M and N are positive integers.

[0188] The second cascading signal terminal Output2' of the i-th shift register is connected to the first signal input terminal Input1 of the (i + 2)-th shift register; i takes values from 1 to (M - 2); the second cascading signal terminal Output2' of the j-th shift register is connected to the second signal input terminal Input12 of the (j - 2)-th shift register; j takes values from 3 to M. The first signal input terminals Input1 of the first-stage and second-stage shift registers are respectively connected to the first frame start signal line and the second frame start signal line.

[0189] The first clock signal terminals CK1, second clock signal terminals CK2, third clock signal terminals CK3, and fourth clock signal terminals CK4 of the first shift register in each group are respectively electrically connected to the tenth clock signal line ck10, ninth clock signal line ck9, third clock signal line ck3, and fourth clock signal line ck4; the first clock signal terminals CK1, second clock signal terminals CK2, third clock signal terminals CK3, and fourth clock signal terminals CK4 of the second shift register in each group are respectively electrically connected to the twelfth clock signal line ck12, eleventh clock signal line ck11, fifth clock signal line ck5, and sixth clock signal line ck6; the first clock signal terminals CK1, second clock signal terminals CK2, third clock signal terminals CK3, and fourth clock signal terminals CK4 of the third shift register in each group are respectively electrically connected to the second clock signal line ck2, first clock signal line ck1, seventh clock signal line ck7, and eighth clock signal line ck8; the first clock signal terminals CK1, second clock signal terminals CK2, third clock signal terminals CK3, and fourth clock signal terminals CK4 of the fourth shift register in each group are respectively electrically connected to the fourth clock signal line ck4, third clock signal line ck3, ninth clock signal line ck9, and tenth clock signal line ck10; the first clock signal terminals CK1, second clock signal terminals CK2, third clock signal terminals CK3, and fourth clock signal terminals CK4 of the fifth shift register in each group are respectively electrically connected to the sixth clock signal line ck6, fifth clock signal line ck5, eleventh clock signal line ck11, and twelfth clock signal line ck12; the first clock signal terminals CK1, second clock signal terminals CK2, third clock signal terminals CK3, and fourth clock signal terminals CK4 of the sixth shift register in each group are respectively electrically connected to the eighth clock signal line ck8, seventh clock signal line ck7, first clock signal line ck1, and second clock signal line ck2.

[0190] Sixth example: Figure 11 It is a cascade schematic diagram of the gate driving circuit according to the sixth example of the present disclosure; as Figure 11 shown, the gate driving circuit further includes 12 clock signal lines, namely the first clock signal line ck1, second clock signal line ck2, third clock signal line ck3, fourth clock signal line, fifth clock signal line ck5, sixth clock signal line ck6, seventh clock signal line ck7, eighth clock signal line ck8, ninth clock signal line ck9, tenth clock signal line ck10, eleventh clock signal line ck11, and twelfth clock signal line ck12.

[0191] The number of shift registers is M, and the M shift registers are at least divided into N groups, with each group including 6 arranged in sequence, N≥2, and both M and N are positive integers.

[0192] The second cascaded signal terminal Output2' of the i-th shift register is connected to the first signal input terminal Input1 of the (i + 2)-th shift register; i ranges from 1 to (M - 2); the second cascaded signal terminal Output2' of the j-th shift register is connected to the second signal input terminal Input12 of the (j - 3)-th shift register; j ranges from 4 to M; the first signal input terminals Input1 of the first-stage and second-stage shift registers are respectively connected to the first frame start signal line and the second frame start signal line.

[0193] The first clock signal terminal CK1, the second clock signal terminal CK2, the third clock signal terminal CK3, and the fourth clock signal terminal CK4 of the first shift register in each group are respectively electrically connected to the tenth clock signal line ck10, the ninth clock signal line ck9, the third clock signal line ck3, and the fourth clock signal line ck4; the first clock signal terminal CK1, the second clock signal terminal CK2, the third clock signal terminal CK3, and the fourth clock signal terminal CK4 of the second shift register in each group are respectively electrically connected to the twelfth clock signal line ck12, the eleventh clock signal line ck11, the fifth clock signal line ck5, and the sixth clock signal line ck6; the first clock signal terminal CK1, the second clock signal terminal CK2, the third clock signal terminal CK3, and the fourth clock signal terminal CK4 of the third shift register in each group are respectively electrically connected to the second clock signal line ck2, the first clock signal line ck1, the seventh clock signal line ck7, and the eighth clock signal line ck8; the first clock signal terminal CK1, the second clock signal terminal CK2, the third clock signal terminal CK3, and the fourth clock signal terminal CK4 of the fourth shift register in each group are respectively electrically connected to the fourth clock signal line ck4, the third clock signal line ck3, the ninth clock signal line ck9, and the tenth clock signal line ck10; the first clock signal terminal CK1, the second clock signal terminal CK2, the third clock signal terminal CK3, and the fourth clock signal terminal CK4 of the fifth shift register in each group are respectively electrically connected to the sixth clock signal line ck6, the fifth clock signal line ck5, the eleventh clock signal line ck11, and the twelfth clock signal line ck12; the first clock signal terminal CK1, the second clock signal terminal CK2, the third clock signal terminal CK3, and the fourth clock signal terminal CK4 of the sixth shift register in each group are respectively electrically connected to the eighth clock signal line ck8, the seventh clock signal line ck7, the first clock signal line ck1, and the second clock signal line ck2.

[0194] The working principle of each stage of the shift register is the same as that of the above example, so it will not be repeated here. Figure 12 For Figure 11 the output result simulation diagram of the partial shift register driven by the gate, as Figure 12 shown, the Tf of the interlaced gate drive signal is consistent, improving the reliability of the gate drive circuit.

[0195] In a third aspect, embodiments of the present disclosure provide a display device, which includes the above-mentioned gate driving circuit. The display device may specifically be a virtual reality display device (VR display device).

[0196] It can be understood that the above embodiments are merely exemplary embodiments adopted to illustrate the principle of the present invention, but the present invention is not limited thereto. For those of ordinary skill in the art, various modifications and improvements can be made without departing from the spirit and essence of the present invention, and these modifications and improvements are also considered within the protection scope of the present invention.

Claims

1. A shift register, comprising a first input sub - circuit, a second input sub - circuit, a first output sub - circuit, a second output sub - circuit, a first cascading sub - circuit, and a second cascading sub - circuit; The first input sub - circuit is configured to pre - charge a first pull - up node through a first scan signal in response to a first input signal; The first input sub - circuit is configured to pre - charge the second pull - up node through a second scan signal in response to a second input signal; The first output sub - circuit is configured to output a third clock signal through a first signal output terminal in response to the potential of the first pull - up node; The first cascading sub - circuit is configured to output a third clock signal through a first cascading signal terminal in response to the potential of the first pull - up node; The second output sub - circuit is configured to output a fourth clock signal through a second signal output terminal in response to the potential of the second pull - up node; The second cascading sub - circuit is configured to output a fourth clock signal through a second cascading signal terminal in response to the potential of the second pull - up node.

2. The shift register according to claim 1, wherein, further comprising: A first pull - up control sub - circuit configured to transmit the first scan signal to the first pull - up node in response to a working level signal to pre - charge the first pull - up node; A second pull - up control sub - circuit configured to transmit the first scan signal to the second pull - up node in response to a working level signal to pre - charge the second pull - up node.

3. The shift register according to claim 2, wherein, The first pull - up control sub - circuit includes a ninth transistor; a first pole of the ninth transistor is connected to the first pull - up node, a second pole is connected to a pull - up control node, and a control pole is connected to a working level signal terminal; the pull - up control node is a connection node between the first input sub - circuit and the second input sub - circuit.

4. The shift register according to claim 2, wherein, The second pull - up control sub - circuit includes a fourteenth transistor; a first pole of the fourteenth transistor is connected to the second pull - up node, a second pole is connected to a pull - up control node, and a control pole is connected to a working level signal terminal; the pull - up control node is a connection node between the first input sub - circuit and the second input sub - circuit.

5. The shift register according to claim 1, wherein, further comprising: a first node control sub - circuit, a second node control sub - circuit, a pull - down control sub - circuit, and a pull - down sub - circuit; The first node control sub - circuit is configured to control the potential of a pull - down control node through a first clock signal in response to the first scan signal; The second node control sub - circuit is configured to control the potential of the pull - down control node through a second clock signal in response to the second scan signal; The pull - down control sub - circuit is configured to control the potential of a pull - down node through a working level signal in response to the potential of the pull - down control node, and to control the pull - down node through a non - working level signal in response to the potential of the pull - up control node; The pull-down sub-circuit is configured to pull down the potential of the pull-up control node, the output of the first signal output terminal, the output of the second signal output terminal, the output of the first cascaded signal terminal, and the output of the second cascaded signal terminal through the non-operating level signal in response to the potential of the pull-down node.

6. The shift register according to claim 5, wherein, the first node control sub-circuit includes a fifth transistor; a first pole of the fifth transistor is connected to the first clock signal terminal, a second pole is connected to the pull-down control node, and a control pole is connected to the first scan signal terminal.

7. The shift register according to claim 5, wherein, the second node control sub-circuit includes a sixth transistor; a first pole of the sixth transistor is connected to the second clock signal terminal, a second pole is connected to the pull-down control node, and a control pole is connected to the second scan signal terminal.

8. The shift register according to claim 5, wherein, the pull-down control sub-circuit includes an eighth transistor, a tenth transistor, and a second storage capacitor; a first pole of the eighth transistor is connected to the pull-down node, a second pole is connected to the non-operating level signal terminal, and a control pole is connected to the pull-up control node; the pull-up control node is a connection node between the first input sub-circuit and the second input sub-circuit; a first pole of the tenth transistor is connected to the operating level signal terminal, a second pole is connected to the pull-down node, and a control pole is connected to the pull-down control node; a first end of the second storage capacitor is connected to the pull-down node, and a second pole is connected to the non-operating level signal terminal.

9. The shift register according to claim 5, wherein, the pull-down sub-circuit includes a fourth transistor, a seventh transistor, a thirteenth transistor, a fifteenth transistor, and a seventeenth transistor; a first pole of the fourth transistor is connected to the first signal output terminal, a second pole is connected to the non-operating level signal terminal, and a control pole is connected to the pull-down node; a first pole of the seventh transistor is connected to the pull-up control node, a second pole is connected to the non-operating level signal terminal, and a control pole is connected to the pull-down node; the pull-up control node is a connection node between the first input sub-circuit and the second input sub-circuit; a first pole of the thirteenth transistor is connected to the second signal output terminal, a second pole is connected to the non-operating level signal terminal, and a control pole is connected to the pull-down node; a first pole of the fifteenth transistor is connected to the first cascaded signal output terminal, a second pole is connected to the non-operating level signal terminal, and a control pole is connected to the pull-down node; a first pole of the seventeenth transistor is connected to the second cascaded signal output terminal, a second pole is connected to the non-operating level signal terminal, and a control pole is connected to the pull-down node.

10. The shift register according to claim 1, wherein, further comprising: a reset sub-circuit configured to reset the pull-up control node through a non-operating level signal in response to a reset signal; the pull-up control node is a connection node between the first input sub-circuit and the second input sub-circuit.

11. The shift register according to claim 10, wherein, The reset sub - circuit includes an eleventh transistor; a first pole of the eleventh transistor is connected to the pull - up control node, a second pole is connected to the non - operating level signal terminal, and a control pole is connected to the reset signal terminal.

12. The shift register according to any one of claims 1 - 11, wherein, The first input sub - circuit includes a first transistor; a first pole of the first transistor is connected to the first scan signal terminal, a second pole is connected to the pull - up control node, and a control pole is connected to the first signal input terminal; the pull - up control node is a connection node between the first input sub - circuit and the second input sub - circuit.

13. The shift register according to any one of claims 1 - 11, wherein, The second input sub - circuit includes a second transistor; a first end of the second transistor is connected to the second scan signal terminal, a second pole is connected to the pull - up control node, and a control pole is connected to the second signal input terminal; the pull - up control node is a connection node between the first input sub - circuit and the second input sub - circuit.

14. The shift register according to any one of claims 1 - 11, wherein, The first output sub - circuit includes a third transistor and a first storage capacitor; A first pole of the third transistor is connected to the third clock signal terminal, a second pole is connected to the first signal output terminal, and a control pole is connected to the first pull - up node; A first end of the first storage capacitor is connected to the first pull - up node, and a second end is connected to the first signal output terminal.

15. The shift register according to any one of claims 1 - 11, wherein, The second output sub - circuit includes a twelfth transistor and a third storage capacitor; A first pole of the third transistor is connected to the fourth clock signal terminal, a second pole is connected to the second signal output terminal, and a control pole is connected to the second pull - up node; A first end of the third storage capacitor is connected to the second pull - up node, and a second end is connected to the second signal output terminal.

16. The shift register according to any one of claims 1 - 11, wherein, The first cascade sub - circuit includes a fourteenth transistor; a first pole of the fourteenth transistor is connected to the third clock signal terminal, a second pole is connected to the first cascade signal terminal, and a control pole is connected to the first pull - up node.

17. The shift register according to any one of claims 1 - 11, wherein, The first cascade sub - circuit includes a seventeenth transistor; a first pole of the seventeenth transistor is connected to the fourth clock signal terminal, a second pole is connected to the second cascade signal terminal, and a control pole is connected to the second pull - up node.

18. A gate driving circuit, which includes a plurality of shift registers, wherein, The shift register includes the shift register according to any one of claims 1 - 17.

19. The gate driving circuit according to claim 18, wherein, The shift register includes a first node control sub - circuit, a second node control sub - circuit, a pull - down control sub - circuit, and a pull - down sub - circuit; the shift register has a first clock signal terminal, a second clock signal terminal, a third clock signal terminal, and a fourth clock signal terminal; The gate driving circuit further includes six clock signal lines, namely a first clock signal line, a second clock signal line, a third clock signal line, a fourth clock signal line, a fifth clock signal line, and a sixth clock signal line; Except for the last-stage shift register, the first cascade signal terminal of the current-stage shift register is connected to the first signal input terminal of the next-stage shift register; Except for the first-stage shift register, the first cascade signal terminal of the current-stage shift register is connected to the second signal input terminal of the previous-stage shift register; The multiple shift registers are at least divided into N groups, each group including three arranged in sequence, N≥2, and N is a positive integer; The first clock signal terminal, the second clock signal terminal, the third clock signal terminal, and the fourth clock signal terminal of the first shift register in each group are respectively electrically connected to the sixth clock signal line, the first clock signal line, the second clock signal line, and the third clock signal line; The first clock signal terminal, the second clock signal terminal, the third clock signal terminal, and the fourth clock signal terminal of the second shift register in each group are respectively electrically connected to the second clock signal line, the third clock signal line, the fifth clock signal line, and the sixth clock signal line; The first clock signal terminal, the second clock signal terminal, the third clock signal terminal, and the fourth clock signal terminal of the third shift register in each group are respectively electrically connected to the fourth clock signal line, the fifth clock signal line, the first clock signal line, and the second clock signal line.

20. The gate driving circuit according to claim 18, wherein, The shift register includes a first node control sub-circuit, a second node control sub-circuit, a pull-down control sub-circuit, and a pull-down sub-circuit; the shift register has a first clock signal terminal, a second clock signal terminal, a third clock signal terminal, and a fourth clock signal terminal; The gate driving circuit further includes six clock signal lines, namely a first clock signal line, a second clock signal line, a third clock signal line, a fourth clock signal line, a fifth clock signal line, and a sixth clock signal line; Except for the last-stage shift register, the first cascade signal terminal of the current-stage shift register is connected to the first signal input terminal of the next-stage shift register; Except for the first-stage shift register, the first cascade signal terminal of the current-stage shift register is connected to the second signal input terminal of the previous-stage shift register; The multiple shift registers are at least divided into N groups, each group including three arranged in sequence, N≥2, and N is a positive integer; The first clock signal terminal, the second clock signal terminal, the third clock signal terminal, and the fourth clock signal terminal of the first shift register in each group are respectively electrically connected to the first clock signal line, the second clock signal line, the third clock signal line, and the fourth clock signal line; The first clock signal terminal, the second clock signal terminal, the third clock signal terminal, and the fourth clock signal terminal of the second shift register in each group are respectively electrically connected to the third clock signal line, the fourth clock signal line, the fifth clock signal line, and the sixth clock signal line; The first clock signal terminal, the second clock signal terminal, the third clock signal terminal, and the fourth clock signal terminal of the third shift register in each group are respectively electrically connected to the fifth clock signal line, the sixth clock signal line, the first clock signal line, and the second clock signal line.

21. The gate driving circuit according to claim 18, wherein, The shift register includes a first node control sub-circuit, a second node control sub-circuit, a pull-down control sub-circuit, and a pull-down sub-circuit; the shift register has a first clock signal terminal, a second clock signal terminal, a third clock signal terminal, and a fourth clock signal terminal; The gate driving circuit further includes 8 clock signal lines, namely the first clock signal line, the second clock signal line, the third clock signal line, the fourth clock signal line, the fifth clock signal line, the sixth clock signal line, the seventh clock signal line, and the eighth clock signal line; The number of the shift registers is M, and the M shift registers are at least divided into N groups, each group includes 4 arranged in sequence, N≥2, and both M and N are positive integers; The first cascade signal terminal of the i-th shift register is connected to the first signal input terminal of the (i + 2)-th shift register; i takes values from 1 to (M - 2); The second cascade signal terminal of the j-th shift register is connected to the second signal input terminal of the (j - 2)-th shift register; j takes values from 3 to M; The first clock signal terminal, the second clock signal terminal, the third clock signal terminal, and the fourth clock signal terminal of the first shift register in each group are respectively electrically connected to the seventh clock signal line, the eighth clock signal line, the third clock signal line, and the fourth clock signal line; The first clock signal terminal, the second clock signal terminal, the third clock signal terminal, and the fourth clock signal terminal of the second shift register in each group are respectively electrically connected to the first clock signal line, the second clock signal line, the fifth clock signal line, and the sixth clock signal line; The first clock signal terminal, the second clock signal terminal, the third clock signal terminal, and the fourth clock signal terminal of the third shift register in each group are respectively electrically connected to the third clock signal line, the fourth clock signal line, the seventh clock signal line, and the eighth clock signal line; The first clock signal terminal, the second clock signal terminal, the third clock signal terminal, and the fourth clock signal terminal of the fourth shift register in each group are respectively electrically connected to the fifth clock signal line, the sixth clock signal line, the first clock signal line, and the second clock signal line.

22. The gate driving circuit according to claim 18, wherein, The shift register includes a first node control sub-circuit, a second node control sub-circuit, a pull-down control sub-circuit, and a pull-down sub-circuit; the shift register has a first clock signal terminal, a second clock signal terminal, a third clock signal terminal, and a fourth clock signal terminal; The gate driving circuit further includes 12 clock signal lines, namely a first clock signal line, a second clock signal line, a third clock signal line, a fourth clock signal line, a fifth clock signal line, a sixth clock signal line, a seventh clock signal line, an eighth clock signal line, a ninth clock signal line, a tenth clock signal line, an eleventh clock signal line, and a twelfth clock signal line; The number of the shift registers is M, and the M shift registers are at least divided into N groups, with each group including 6 arranged in sequence, N≥2, and both M and N are positive integers; The first cascading signal terminal of the i-th shift register is connected to the first signal input terminal of the (i + 2)-th shift register; i takes values from 1 to (M - 2); The second cascading signal terminal of the j-th shift register is connected to the second signal input terminal of the (j - 2)-th shift register; j takes values from 3 to M; The first clock signal terminal, the second clock signal terminal, the third clock signal terminal, and the fourth clock signal terminal of the first shift register in each group are respectively electrically connected to the tenth clock signal line, the ninth clock signal line, the third clock signal line, and the fourth clock signal line; The first clock signal terminal, the second clock signal terminal, the third clock signal terminal, and the fourth clock signal terminal of the second shift register in each group are respectively electrically connected to the twelfth clock signal line, the eleventh clock signal line, the fifth clock signal line, and the sixth clock signal line; The first clock signal terminal, the second clock signal terminal, the third clock signal terminal, and the fourth clock signal terminal of the third shift register in each group are respectively electrically connected to the second clock signal line, the first clock signal line, the seventh clock signal line, and the eighth clock signal line; The first clock signal terminal, the second clock signal terminal, the third clock signal terminal, and the fourth clock signal terminal of the fourth shift register in each group are respectively electrically connected to the fourth clock signal line, the third clock signal line, the ninth clock signal line, and the tenth clock signal line; The first clock signal terminal, the second clock signal terminal, the third clock signal terminal, and the fourth clock signal terminal of the fifth shift register in each group are respectively electrically connected to the sixth clock signal line, the fifth clock signal line, the eleventh clock signal line, and the twelfth clock signal line; The first clock signal terminal, the second clock signal terminal, the third clock signal terminal, and the fourth clock signal terminal of the sixth shift register in each group are respectively electrically connected to the eighth clock signal line, the seventh clock signal line, the first clock signal line, and the second clock signal line.

23. The gate driving circuit according to claim 18, wherein, The shift register includes a first node control sub-circuit, a second node control sub-circuit, a pull-down control sub-circuit, and a pull-down sub-circuit; the shift register has a first clock signal terminal, a second clock signal terminal, a third clock signal terminal, and a fourth clock signal terminal; The gate driving circuit further includes 12 clock signal lines, namely a first clock signal line, a second clock signal line, a third clock signal line, a fourth clock signal line, a fifth clock signal line, a sixth clock signal line, a seventh clock signal line, an eighth clock signal line, a ninth clock signal line, a tenth clock signal line, an eleventh clock signal line, and a twelfth clock signal line; The number of the shift registers is M, and the M shift registers are at least divided into N groups, each group includes 6 arranged in sequence, N≥2, and both M and N are positive integers; The second cascading signal terminal of the i-th shift register is connected to the first signal input terminal of the (i + 2)-th shift register; i takes values from 1 to (M - 2); The second cascading signal terminal of the j-th shift register is connected to the second signal input terminal of the (j - 2)-th shift register; j takes values from 3 to M; The first clock signal terminal, the second clock signal terminal, the third clock signal terminal, and the fourth clock signal terminal of the first shift register in each group are respectively electrically connected to the tenth clock signal line, the ninth clock signal line, the third clock signal line, and the fourth clock signal line; The first clock signal terminal, the second clock signal terminal, the third clock signal terminal, and the fourth clock signal terminal of the second shift register in each group are respectively electrically connected to the twelfth clock signal line, the eleventh clock signal line, the fifth clock signal line, and the sixth clock signal line; The first clock signal terminal, the second clock signal terminal, the third clock signal terminal, and the fourth clock signal terminal of the third shift register in each group are respectively electrically connected to the second clock signal line, the first clock signal line, the seventh clock signal line, and the eighth clock signal line; The first clock signal terminal, the second clock signal terminal, the third clock signal terminal, and the fourth clock signal terminal of the fourth shift register in each group are respectively electrically connected to the fourth clock signal line, the third clock signal line, the ninth clock signal line, and the tenth clock signal line; The first clock signal terminal, the second clock signal terminal, the third clock signal terminal, and the fourth clock signal terminal of the fifth shift register in each group are respectively electrically connected to the sixth clock signal line, the fifth clock signal line, the eleventh clock signal line, and the twelfth clock signal line; The first clock signal terminal, the second clock signal terminal, the third clock signal terminal, and the fourth clock signal terminal of the sixth shift register in each group are respectively electrically connected to the eighth clock signal line, the seventh clock signal line, the first clock signal line, and the second clock signal line.

24. The gate driving circuit according to claim 18, wherein, The shift register includes a first node control sub-circuit, a second node control sub-circuit, a pull-down control sub-circuit, and a pull-down sub-circuit; the shift register has a first clock signal terminal, a second clock signal terminal, a third clock signal terminal, and a fourth clock signal terminal; The gate driving circuit further includes 12 clock signal lines, namely a first clock signal line, a second clock signal line, a third clock signal line, a fourth clock signal line, a fifth clock signal line, a sixth clock signal line, a seventh clock signal line, an eighth clock signal line, a ninth clock signal line, a tenth clock signal line, an eleventh clock signal line, and a twelfth clock signal line; The number of the shift registers is M, and the M shift registers are at least divided into N groups, each group including 6 arranged in sequence, N≥2, and both M and N are positive integers; The second cascading signal terminal of the i-th shift register is connected to the first signal input terminal of the (i + 2)-th shift register; i takes values from 1 to (M - 2); The second cascading signal terminal of the j-th shift register is connected to the second signal input terminal of the (j - 3)-th shift register; j takes values from 4 to M; The first clock signal terminal, the second clock signal terminal, the third clock signal terminal, and the fourth clock signal terminal of the first shift register in each group are respectively electrically connected to the tenth clock signal line, the ninth clock signal line, the third clock signal line, and the fourth clock signal line; The first clock signal terminal, the second clock signal terminal, the third clock signal terminal, and the fourth clock signal terminal of the second shift register in each group are respectively electrically connected to the twelfth clock signal line, the eleventh clock signal line, the fifth clock signal line, and the sixth clock signal line; The first clock signal terminal, the second clock signal terminal, the third clock signal terminal, and the fourth clock signal terminal of the third shift register in each group are respectively electrically connected to the second clock signal line, the first clock signal line, the seventh clock signal line, and the eighth clock signal line; The first clock signal terminal, the second clock signal terminal, the third clock signal terminal, and the fourth clock signal terminal of the fourth shift register in each group are respectively electrically connected to the fourth clock signal line, the third clock signal line, the ninth clock signal line, and the tenth clock signal line; The first clock signal terminal, the second clock signal terminal, the third clock signal terminal, and the fourth clock signal terminal of the fifth shift register in each group are respectively electrically connected to the sixth clock signal line, the fifth clock signal line, the eleventh clock signal line, and the twelfth clock signal line; The first clock signal terminal, the second clock signal terminal, the third clock signal terminal, and the fourth clock signal terminal of the sixth shift register in each group are respectively electrically connected to the eighth clock signal line, the seventh clock signal line, the first clock signal line, and the second clock signal line.

25. A display device, which includes the gate driving circuit according to any one of claims 18-24.

26. The display device according to claim 25, wherein, the display device is a virtual reality display device.

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