Amplification circuit

Abstract

The amplifier circuit includes: a distributor that distributes an input signal into a first signal and a second signal having a phase delayed by 90 DEG from the first signal; a first amplifier which amplifies the first signal and outputs the amplified first signal as a third signal to the first node; a second amplifier which amplifies the second signal and outputs the amplified second signal as a fourth signal to the second node; a first inductor connecting the first node and the second node; a second inductor connecting the first node and the third node; a third inductor connecting a third node to a fourth node for outputting an output signal obtained by combining a fourth signal and a third signal having a phase delayed by 90 DEG from the fourth signal; a fourth inductor connecting the second node and the fourth node; the first capacitor is in shunt connection with the third node; and the second capacitor is connected to the fourth node in a shunt mode, and the inductance of the first inductor and the inductance of the third inductor are larger than the inductance of the second inductor and the inductance of the fourth inductor.

Description

Technical Field

[0001] The present invention relates to an amplifier circuit. Background Art

[0002] As an amplifier circuit for amplifying high-frequency signals such as microwaves, a balanced amplifier is known (for example, Patent Document 1).

[0003] Prior Art Documents

[0004] Patent Documents

[0005] Patent Document 1: Japanese Patent Application Laid-Open No. 2022-506367

[0006] In Patent Document 1, losses are generated by the lines connecting the amplifiers and the coupler. In addition, due to the ground capacitances at the output terminals of Amplifiers 4 and 5, the frequency band is narrowed. Summary of the Invention

[0007] The present disclosure has been made in view of the above problems, and an object thereof is to suppress deterioration of characteristics.

[0008] One embodiment of the present disclosure is an amplifier circuit including: a distributor that distributes an input signal into a first signal and a second signal whose phase is delayed by 90° with respect to the first signal; a first amplifier that amplifies the first signal and outputs the amplified first signal as a third signal to a first node; a second amplifier that amplifies the second signal and outputs the amplified second signal as a fourth signal to a second node; a first inductor that connects the first node and the second node; a second inductor that connects the first node and a third node; a third inductor that connects the third node and a fourth node, wherein the fourth node outputs an output signal obtained by synthesizing the fourth signal and a third signal whose phase is delayed by 90° with respect to the fourth signal; a fourth inductor that connects the second node and the fourth node; a first capacitor that is shunt-connected to the third node; and a second capacitor that is shunt-connected to the fourth node, wherein the inductances of the first inductor and the third inductor are greater than the inductances of the second inductor and the fourth inductor.

[0009] Advantages of the Invention

[0010] According to the present disclosure, deterioration of characteristics can be suppressed. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 is a circuit diagram of the amplifier circuit of Example 1.

[0012] Figure 2 is a circuit diagram of a lumped-parameter type branch-line coupler.

[0013] Figure 3 It is a circuit diagram of a distributed-parameter type branch-line coupler.

[0014] Figure 4 It is a circuit diagram of the amplifier of Comparative Example 1.

[0015] Figure 5 It is a top view showing Mounting Example 1 of the synthesizer and the amplifier of Example 1.

[0016] Figure 6 It is a top view showing Mounting Example 2 of the synthesizer and the amplifier of Example 1.

[0017] Figure 7 It is a circuit diagram of the amplifier of Example 2.

[0018] Figure 8 It is a top view showing the mounting example of the synthesizer and the amplifier of Example 2.

[0019] Figure 9 It is a circuit diagram of the amplifier of Example 3.

[0020] Figure 10 It is a top view showing the mounting example of the synthesizer and the amplifier of Example 3.

[0021] Figure 11 It is a circuit diagram of the amplifier of Example 4.

[0022] Explanation of reference numerals:

[0023] 10 (first amplifier), 12 (second amplifier): amplifier;

[0024] 13, 14, 26: matching circuit;

[0025] 16, 24 (another distributor): distributor;

[0026] 18: synthesizer;

[0027] 20, 37a, 37b: line;

[0028] 22: control amplifier;

[0029] 30, 32a, 32b: substrate;

[0030] 31a, 31b: semiconductor chip;

[0031] 33a, 33b, 34a (first pad), 34b (second pad): pad;

[0032] 36a, 36b, 43a, 43b, 45a, 45b: MIM capacitor;

[0033] 38a, 38b: Patterns;

[0034] 40a, 40b, 40c, 40d, 41a, 41b, 41c, 42a, 42b, 44a, 44b: Bonding lines;

[0035] 46a, 46b, 48a (first reactance element), 48b (second reactance element): Reactance elements;

[0036] 100, 102, 104, 106, 110: Amplifier circuits;

[0037] C1 (first capacitor), C2 (second capacitor): Capacitors;

[0038] Cds1 (first ground capacitance), Cds2 (second ground capacitance): Parasitic capacitances;

[0039] L1 (first inductor), L2 (second inductor), L3 (third inductor), L4 (fourth inductor): Inductors;

[0040] N1 (first node), N2 (second node), N3 (third node), N4 (fourth node): Nodes;

[0041] S1 (first signal), S2 (second signal), S3 (third signal), S4 (fourth signal), S5 (fifth signal), S6 (sixth signal): Signals;

[0042] Si, Sin: Input signals;

[0043] So: Output signal. Detailed implementation manners

[0044] [Description of the embodiments of the present disclosure]

[0045] First, the content of the embodiments of the present disclosure will be listed for description.

[0046] (1) One embodiment of the present disclosure is an amplifier circuit, comprising: a distributor that distributes an input signal into a first signal and a second signal whose phase is delayed by 90° with respect to the first signal; a first amplifier that amplifies the first signal and outputs the amplified first signal as a third signal to a first node; a second amplifier that amplifies the second signal and outputs the amplified second signal as a fourth signal to a second node; a first inductor that connects the first node and the second node; a second inductor that connects the first node and a third node; a third inductor that connects the third node and the fourth node, wherein an output signal obtained by synthesizing the fourth signal and a third signal whose phase is delayed by 90° with respect to the fourth signal is output from the fourth node; a fourth inductor that connects the second node and the fourth node; a first capacitor that is shunt-connected to the third node; and a second capacitor that is shunt-connected to the fourth node, and the inductances of the first inductor and the third inductor are each greater than the inductances of the second inductor and the fourth inductor. Thereby, deterioration of characteristics can be suppressed.

[0047] (2) In the above (1), it may also be that the inductances of the first inductor and the third inductor are each 0.8×√2 or more and 1.2×√2 or less of the inductances of the second inductor and the fourth inductor. Thereby, the first to fourth inductors, the first and second capacitors can function as a branch-line coupler.

[0048] (3) In the above (1) or (2), it may also be that reactance elements are shunt-connected to each of the first node and the second node. Thereby, the first to fourth inductors, the first and second capacitors can function as a branch-line coupler.

[0049] (4) In the above (3), it may also be that when the center frequency of the operating band is set to fo and the reference impedance is set to Zo, the capacitance C0 of the first ground capacitance at the output node of the first amplifier, the second ground capacitance at the output node of the second amplifier, and the capacitances of the first capacitor and the second capacitor is 0.8 times or more and 1.2 times or less of 1 / (2πfo×Zo)+1 / (2πfo×Zo / √2), the inductances of the first inductor and the third inductor are each 0.8 times or more and 1.2 times or less of Zo / (2πfo), and the inductances of the second inductor and the fourth inductor are each 0.8 times or more and 1.2 times or less of Zo / (√2×(2πfo)). Thereby, the amplifier circuit can function as a balanced amplifier.

[0050] (5) In the above (1) or (2), it is also possible to include: a first reactance element shunt-connected to the first node; and a second reactance element shunt-connected to the second node. Thus, the first to fourth inductors, the first and second capacitors, and the first and second reactance elements can function as a branch-line coupler.

[0051] (6) In the above (5), it is also possible that when the center frequency of the operating band is set to fo and the reference impedance is set to Zo, the capacitance C0, which is the capacitance component obtained by combining the first ground capacitance of the output node of the first amplifier and the first reactance element, the capacitance component obtained by combining the second ground capacitance of the output node of the second amplifier and the second reactance element, and the capacitances of the first capacitor and the second capacitor, is 0.8 times or more and 1.2 times or less of 1 / (2πfo×Zo)+1 / (2πfo×Zo / √2), the inductances of the first inductor and the third inductor are 0.8 times or more and 1.2 times or less of Zo / (2πfo), and the inductances of the second inductor and the fourth inductor are 0.8 times or more and 1.2 times or less of Zo / (√2×(2πfo)). Thus, the amplifier circuit can function as a balanced amplifier.

[0052] (7) In any one of the above (1) to (6), it is also possible to include: a first semiconductor chip having the first amplifier and a first pad corresponding to the first node; and a second semiconductor chip having the second amplifier and a second pad corresponding to the second node, wherein the first inductor includes a first bonding wire, and the first end of the first bonding wire is connected to the first pad. Thus, deterioration of characteristics can be suppressed.

[0053] (8) In the above (7), it is also possible that the second end of the first bonding wire is connected to the second pad. Thus, deterioration of characteristics can be suppressed.

[0054] (9) In the above (7), it is also possible that the first inductor includes a second bonding wire, and the first end of the second bonding wire is connected to the second pad. Thus, deterioration of characteristics can be suppressed.

[0055] (10) In any one of the above (7) to (9), it is also possible to include: a third bonding wire connecting the first pad and the first capacitor, and the third bonding wire corresponds to the second inductor; and a fourth bonding wire connecting the second pad and the second capacitor, and the fourth bonding wire corresponds to the fourth inductor. Thus, the second inductor and the fourth inductor can be formed.

[0056] (11) In any one of the above (7) to (10), it is also possible that the first inductor, the second inductor, the third inductor, the fourth inductor, the first capacitor, the second capacitor, the first ground capacitance of the first pad, and the second ground capacitance of the second pad form a branch-line coupler. Thereby, deterioration of the characteristics of the branch-line coupler can be suppressed.

[0057] (12) In any one of the above (1) to (11), it may further include: another distributor that distributes a high-frequency signal into the input signal and a fifth signal; and a control amplifier that amplifies the fifth signal and outputs the amplified fifth signal as a sixth signal. A synthesizer including the first inductor, the second inductor, the third inductor, the fourth inductor, the first capacitor, and the second capacitor uses the sixth signal to modulate the loads of the first amplifier and the second amplifier, synthesizes the third signal, the fourth signal, and the sixth signal, and outputs the synthesized signal as an output signal. Thereby, deterioration of the characteristics can be suppressed.

[0058] [Details of Embodiments of the Present Disclosure]

[0059] Hereinafter, with reference to the drawings, specific examples of the amplifier circuit according to the embodiments of the present disclosure will be described. It should be noted that the present disclosure is not limited to these examples, but is shown by the claims, and is intended to include all modifications within the meaning and scope equivalent to the claims.

[0060] [Example 1]

[0061] Example 1 is an example of a balanced amplifier. Figure 1 is a circuit diagram of the amplifier circuit of Example 1. In Figure 1 , illustration of a bias circuit that supplies a bias voltage to the amplifier 10 and the amplifier 12 is omitted.

[0062] As Figure 1 shown, in the amplifier circuit 100 of Example 1, the amplifier 10 and the amplifier 12 are connected in parallel between the input terminal Tin and the output terminal Tout. A high-frequency signal is input as an input signal Si to the input terminal Tin. When the amplifier circuit 100 is used in a mobile communication base station, the frequency of the high-frequency signal is, for example, 0.5 GHz or more and 10 GHz or less. The distributor 16 distributes the input signal Si input to the input terminal Tin into a signal S1 (first signal) and a signal S2 (second signal). The phase of the signal S2 is delayed by 90° with respect to the signal S1.

[0063] The signal S1 is input to the amplifier 10 through the matching circuit (MN: Matching Network) 13. In all the drawings, the matching circuit is illustrated as MN. The matching circuit 13 matches the impedance of the matching circuit 13 as observed from the distributor 16 with the impedance of the amplifier 10 as observed from the matching circuit 13. The amplifier 10 (first amplifier) amplifies the signal S1 and outputs the amplified signal S1 as the signal S3 (third signal). The signal S3 amplified by the amplifier 10 is input to the node N1.

[0064] The signal S2 is input to the amplifier 12 through the matching circuit 14. The matching circuit 14 matches the impedance of the matching circuit 14 as observed from the distributor 16 with the impedance of the amplifier 12 as observed from the matching circuit 14. The amplifier 12 (second amplifier) amplifies the signal S2 and outputs the amplified signal S2 as the signal S4 (fourth signal). The signal S4 amplified by the amplifier 12 is input to the node N2.

[0065] The amplifier 10 and the amplifier 12 respectively include transistors Q1 and Q2 such as FETs (Field Effect Transistors), for example. In the transistors Q1 and Q2, the source S is grounded, the high-frequency signal is input to the gate G, and the high-frequency signal is output from the drain D. The transistors Q1 and Q2 are, for example, GaN HEMTs (Gallium Nitride High Electron Mobility Transistors) or LDMOS (Laterally Diffused Metal Oxide Semiconductors). Parasitic capacitors Cds1 and Cds2 exist between the drain D and the source S of the transistors Q1 and Q2.

[0066] The synthesizer 18 is a lumped-parameter type branch-line coupler, which has parasitic capacitances Cds1 and Cds2, capacitors C1 and C2, and inductors L1 to L4. The inductor L1 (first inductor) electrically connects the node N1 (first node) and the node N2 (second node). The inductor L2 (second inductor) electrically connects the node N1 and the node N3 (third node). The inductor L3 (third inductor) electrically connects the node N3 and the node N4 (fourth node). The inductor L4 (fourth inductor) electrically connects the node N2 and the node N4. The capacitor C1 (first capacitor) is shunt-connected to the node N3. The capacitor C2 (second capacitor) is shunt-connected to the node N4. The node N3 is grounded via a reference resistor Ro (e.g., 50 Ω). The node N4 is electrically connected to the output terminal Tout. The signal S3 and the signal S4 are synthesized at the node N4, and the synthesized signal is output as an output signal So from the output terminal Tout.

[0067] When the amplifier circuit 100 is a balanced amplifier, the distributor 16 distributes the input signal Si into the signals S1 and S2 such that the amplitudes of the signals S1 and S2 are substantially the same and the phase of the signal S2 at the center frequency fo of the operating frequency band is substantially delayed by 90° with respect to the phase of the signal S1. The synthesizer 18 delays the phase of the signal S3 by 90° and synthesizes it with the signal S4. It should be noted that 90° does not have to be strictly 90°. For example, when converted to the wavelength λ at the center frequency fo of the operating frequency band, it can be, for example, 3λ / 16 or more and 5λ / 16 or less, or 7λ / 32 or more and 9λ / 32 or less. The same applies to the following embodiments. The amplifier circuit 100 can also be an amplifier circuit other than a balanced amplifier.

[0068] [Synthesizer 18]

[0069] First, the lumped-parameter type branch-line coupler will be described. Figure 2 is a circuit diagram of a lumped-parameter type branch-line coupler. As Figure 2 shown, capacitors C3 and C4 are respectively provided to replace Figure 1 the parasitic capacitances Cds1 and Cds2 of the synthesizer 18. The nodes N1 to N4 are electrically connected to the terminals T1 to T4 respectively. A method for determining the values of the capacitors C1 to C4 and the inductors L1 to L4 of the lumped-parameter type branch-line coupler will be described.

[0070] In order to describe the method for determining the values of the capacitors C1 to C4 and the inductors L1 to L4 of the lumped-parameter type branch-line coupler, the distributed-parameter type branch-line coupler will be described. Figure 3 is a circuit diagram of a distributed-parameter type branch-line coupler. As Figure 3As shown, transmission lines TL1, TL2, TL3, and TL4 are respectively connected between node N1 and node N2, between node N1 and node N3, between node N3 and node N4, and between node N2 and node N4. The lengths of transmission lines TL1 to TL4 are λ / 4. The characteristic impedance of transmission lines TL1 and TL3 is Zc1, and the characteristic impedance of transmission lines TL2 and TL4 is Zc2. Assume that signal S01 is input to terminal T1 and signals S03 and S04 are output from terminal T3 and terminal T4. At this time, let the ratio of the amplitudes of signal S03 and signal S04 be represented by S03 - S04 in dB.

[0071] Table 1 is a diagram showing the characteristic impedance Zc1 and characteristic impedance Zc2 for realizing the ratio S03 - S04.

[0072] [Table 1]

[0073]

[0074] In Table 1, the reference impedance Zo is set to 50 Ω. The reference impedance Zo corresponds to the impedance when observing terminals T1, T2, T3, and T4 from the outside. In particular, Figure 1 it is the impedance of observing node N4 from the output terminal Tout to which a load is connected, and is equivalent to the characteristic impedance of the transmission line connecting node N2 and output terminal Tout.

[0075] In Table 1, the values of capacitors C1 to C4 and inductors L1 to L4 in the lumped - parameter type branch - line coupler that achieve the desired S03 - S04 are described. Let the capacitances of capacitors C1 to C4 be C0, the inductances of inductors L1 and L3 be L01, and the inductances of inductors L2 and L4 be L02. Let the center frequency of the operating frequency band be fo. At this time, the capacitance C0, inductance L01, and inductance L02 are determined by the following equations.

[0076] C0 = 1 / (2πfo×Zc1) + 1 / (2πfo×Zc2) (Equation 1)

[0077] L01 = Zc1 / (2πfo) (Equation 2)

[0078] L02 = Zc2 / (2πfo) (Equation 3)

[0079] In Figure 1 when the parasitic capacitances Cds1 and Cds2 satisfy Equation 1, by setting the inductances of inductors L1 to L4 and the capacitances of capacitors C1 and C2 to satisfy Equations 1 to 3, Figure 1 ​Figure 1 In Figure 1 , the synthesizer 18 including the parasitic capacitances Cdsl and Cds2 functions as a lumped-parameter type branch-line coupler. The inductances of the inductors L1 to L4 and the capacitances of the capacitors C1 and C2 may not strictly be set to the values calculated by Expressions 1 to 3. For example, each capacitance C0 of the parasitic capacitance Cds1, the parasitic capacitance Cds2, and the capacitors C1 and C2 may be 0.8 times or more and 1.2 times or less of the value obtained by Expression 1, and may be 0.9 times or more and 1.1 times or less. Each inductance L01 of the inductor L1 and the inductor L3 may be 0.8 times or more and 1.2 times or less of the value obtained by Expression 2, and may be 0.9 times or more and 1.1 times or less. Each inductance L02 of the inductor L2 and the inductor L4 may be 0.8 times or more and 1.2 times or less of the value obtained by Expression 3, and may be 0.9 times or more and 1.1 times or less.

[0080] [Comparative Example 1]

[0081] Figure 4 is the circuit diagram of the amplifier circuit of Comparative Example 1. As Figure 4 shown, in the amplifier circuit 110 of Comparative Example 1, the synthesizer 18 is provided separately from the parasitic capacitances Cds1 and Cds2 of the amplifier 10 and the amplifier 12. The synthesizer 18 is a distributed-parameter type or lumped-parameter type branch-line coupler. Other configurations are the same as those in Embodiment 1.

[0082] In Comparative Example 1, a line 20 such as a bonding wire or a transmission line is provided between the amplifier 10 and the amplifier 12 and the synthesizer 18. The insertion loss increases due to the line 20. In addition, the parasitic capacitances Cds1 and Cds2 are added to the outputs of the amplifier 10 and the amplifier 12. Therefore, it is difficult to achieve broadbanding of the amplifier circuit 110.

[0083] According to Embodiment 1, in Figure 1 , each inductance L01 of the inductor L1 and the inductor L3 is larger than each inductance L02 of the inductor L2 and the inductor L4. Thus, as shown in Table 1, the synthesizer 18 functions as a lumped-parameter type branch-line coupler. The line 20 in Comparative Example 1 becomes at least a part of the inductors L2 and L4 in the synthesizer 18. Therefore, the loss caused by the line 20 can be suppressed. In addition, the parasitic capacitances Cds1 and Cds2 function as the capacitors C3 and C4 of the Figure 2 lumped-parameter type branch-line coupler. Thus, broadbanding can be achieved. As described above, the degradation of characteristics can be suppressed.

[0084] As shown in Table 1, when S03 - S04 = 0 dB is set, Zc2 is approximately Zc1 / √2. Therefore, the inductance L01 of the inductor can be set to be not less than 0.8×√2 times and not more than 1.2×√2 times that of the inductor L02. Thereby, the synthesizer 18 functions as a branch-line coupler.

[0085] No reactive components such as capacitors or inductors are shunt-connected to the node N1 and the node N2. Thus, the parasitic capacitances Cds1 and Cds2 function as the Figure 2 capacitors C3 and C4 respectively. Therefore, the synthesizer 18 functions as a branch-line coupler.

[0086] When the amplifier circuit 100 is a balanced amplifier, S03 - S04 = 0 dB in Table 1. In this case, Zc1 = Zo and Zc2 = Zc / √2. Therefore, according to Formulas 1 to 3, when the parasitic capacitances Cds1 (the first ground capacitance of the output node of the amplifier 10), Cds2 (the second ground capacitance of the output node of the amplifier 12), and the capacitances of the capacitors C1 and C2 are set to C0, C0 can be set to be not less than 0.8 times and not more than 1.2 times of 1 / (2πfo×Zo)+1 / (2πfo×Zo / √2), and can be set to be not less than 0.9 times and not more than 1.1 times. The inductances L01 of the inductors L1 and L3 can be set to be not less than 0.8 times and not more than 1.2 times of Zo / (2πfo), and can be set to be not less than 0.9 times and not more than 1.1 times. The inductances L02 of the inductors L2 and L4 can be set to be not less than 0.8 times and not more than 1.2 times of Zo / (√2×(2πfo)), and can be set to be not less than 0.9 times and not more than 1.1 times.

[0087] It should be noted that when the amplifier circuit 100 is a balanced amplifier, the saturation powers of the amplifiers 10 and 12 are substantially the same. For example, the difference in the saturation powers of the amplifiers 10 and 12 is 1 dB or less or 2 dB or less.

[0088] [Mounting Example 1 of Embodiment 1]

[0089] Figure 5 It is a top view showing Mounting Example 1 of the synthesizer and the amplifier of Embodiment 1. As Figure 5As shown, a semiconductor chip 31a, a semiconductor chip 31b, MIM (Metal Insulator Metal) capacitors 36a, MIM capacitors 36b, lines 37a, and lines 37b are mounted on a substrate 30. The upper surface of the substrate 30 is, for example, a conductor layer to which a reference potential such as a ground potential is supplied. The semiconductor chip 31a includes: a transistor Q1 corresponding to the amplifier 10, a substrate 32a, and pads 33a and 34a provided on the substrate 32a. The semiconductor chip 31b includes: a transistor Q2 corresponding to the amplifier 12, a substrate 32b, and pads 33b and 34b provided on the substrate 32b. The pads 33a and 33b are input pads for inputting a high-frequency signal and are, for example, gate pads. The pads 34a and 34b are output pads for outputting a high-frequency signal and are, for example, drain pads. When the transistors Q1 and Q2 are GaN HEMTs, the substrates 32a and 32b are, for example, silicon carbide substrates, sapphire substrates, or gallium nitride substrates. The pads 33a, 33b, 34a, and 34b are, for example, gold layers, copper layers, or aluminum layers.

[0090] The MIM capacitors 36a and 36b include a lower electrode, an upper electrode, and a dielectric layer sandwiched between the lower electrode and the upper electrode. The lower electrode is electrically connected to the conductor layer on the upper surface of the substrate 30 to which the reference potential is supplied. The lines 37a and 37b are electrically connected to the upper electrodes of the MIM capacitors 36a and 36b, respectively. A dielectric layer is provided between the lines 37a and 37b and the conductor layer to which the reference potential is supplied. The lines 37a and 37b are, for example, transmission lines such as microstrip lines. The characteristic impedance at the center frequency fo of the transmission line formed by the lines 37a and 37b is substantially the reference impedance.

[0091] The pads 34a and 34b are electrically connected by a bonding wire 40a. The pad 34a and the upper electrode of the MIM capacitor 36a are electrically connected by a bonding wire 40b. The upper electrodes of the MIM capacitors 36a and 36b are electrically connected by a bonding wire 40c. The pad 34b and the upper electrode of the MIM capacitor 36b are electrically connected by a bonding wire 40d.

[0092] The semiconductor chips 31a and 31b respectively correspond to Figure 1 the amplifiers 10 and 12. The MIM capacitors 36a and 36b respectively correspond to Figure 1 the capacitors C1 and C2. The bonding wires 40a, 40b, 40c, and 40d respectively correspond to Figure 1 the inductors L1, L2, L3, and L4.

[0093] [Mounting Example 2 of Embodiment 1]

[0094] Figure 6 This is a top view showing Mounting Example 2 of the synthesizer and amplifier of Embodiment 1. As Figure 6 shown, on the substrate 30, there are provided a pattern 38a and a pattern 38b of a conductor. The bonding wire 41a electrically connects the pad 34a and the pattern 38a. The bonding wire 41b electrically connects the pad 34b and the pattern 38b. The bonding wire 41c electrically connects the pattern 38a and the pattern 38b. The bonding wires 41a to 41c, the pattern 38a, and the pattern 38b form an inductor L1. Other configurations are the same as Figure 5 Mounting Example 1, and its description is omitted.

[0095] In Mounting Example 1 and Mounting Example 2 of Embodiment 1, the semiconductor chip 31a (first semiconductor chip) includes an amplifier 10 and a pad 34a (first pad) corresponding to the node N1. The semiconductor chip 31b (second semiconductor chip) includes an amplifier 12 and a pad 34b (second pad) corresponding to the node N2. The inductor L1 includes a bonding wire 40a or a bonding wire 41a (first bonding wire) whose first end is connected to the pad 34a. Thus, the pad 34a can function as the node N1. Therefore, it is possible to suppress the provision of an extra wire such as the wire 20 in Comparative Example 1, and the degradation of characteristics can be suppressed.

[0096] As shown in Mounting Example 1 of Embodiment 1, the second end of the bonding wire 40a is connected to the pad 34b. Thus, the pad 34b can function as the node N2. Therefore, it is possible to suppress the provision of an extra wire such as the wire 20 in Comparative Example 1, and the degradation of characteristics can be suppressed.

[0097] As shown in Mounting Example 2 of Embodiment 1, the inductor L1 includes a bonding wire 41b (second bonding wire) whose first end is connected to the pad 34b. Thus, the pad 34b can function as the node N2. Therefore, it is possible to suppress the provision of an extra wire such as the wire 20 in Comparative Example 1, and the degradation of characteristics can be suppressed.

[0098] The bonding wire 40b (third bonding wire) connects the pad 34a and the capacitor C1, and the bonding wire 40b corresponds to the inductor L2. The bonding wire 40d (fourth bonding wire) connects the pad 34b and the capacitor C2, and the bonding wire 40d corresponds to the inductor L4. Thus, the inductor L2 and the inductor L4 can be respectively formed by the bonding wire 40b and the bonding wire 40d.

[0099] [Embodiment 2]

[0100] Figure 7 This is a circuit diagram of the amplifier circuit of Embodiment 2. As Figure 7As shown, in the amplifier circuit 102 of Embodiment 2, a capacitor C5 is shunt-connected to node N1, and a capacitor C6 is shunt-connected to node N2. Other configurations are the same as those in Embodiment 1, and the description thereof is omitted.

[0101] When the parasitic capacitances Cds1 and Cds2 are smaller than C0 calculated according to Table 1, the capacitances of capacitors C3 and C4 can be set to desired values by providing capacitors C5 and C6. In this case, the capacitances of capacitors C5 and C6 are smaller than the capacitances of capacitors C1 and C2. Figure 3

[0102] [Mounting Example of Embodiment 2]

[0103] Figure 8 is a top view showing a mounting example of the synthesizer and amplifier of Embodiment 2. As Figure 8 shown, MIM capacitors 43a and 43b are provided on a substrate 30. The structures of MIM capacitors 43a and 43b are the same as those of MIM capacitors 36a and 36b. A bonding wire 42a electrically connects a pad 34a to the upper electrode of MIM capacitor 43a. A bonding wire 42b electrically connects a pad 34b to the upper electrode of MIM capacitor 43b. The lower electrodes of MIM capacitors 43a and 43b are electrically connected to a conductor layer to which a reference potential is supplied. Other configurations are the same as Figure 5 those of Mounting Example 1, and the description thereof is omitted.

[0104] MIM capacitors 43a and 43b respectively correspond to Figure 7 capacitors C5 and C6. The bonding wire 42a and MIM capacitor 43a form a conductive reactance element 46a. The bonding wire 42b and MIM capacitor 43b form a conductive reactance element 46b.

[0105] [Embodiment 3]

[0106] Figure 9 is a circuit diagram of the amplifier circuit of Embodiment 3. As Figure 9 shown, in the amplifier circuit 104 of Embodiment 3, an inductor L5 is shunt-connected to node N1, and an inductor L6 is shunt-connected to node N2. A capacitor C01 is electrically connected between the inductor L5 and the ground, and a capacitor C02 is electrically connected between the inductor L6 and the ground. Capacitors C01 and C02 are capacitors for bias voltage cut-off that suppress the flow of bias current to the ground. Other configurations are the same as those in Embodiment 2, and the description thereof is omitted.

[0107] When the parasitic capacitances Cds1 and Cds2 are greater than C0 calculated according to Table 1, by setting the inductors L5 and L6, Figure 2 the capacitances of the capacitors C3 and C4 can be set to desired values.

[0108] [Mounting Example of Embodiment 3]

[0109] Figure 10 is a top view showing a mounting example of the synthesizer and the amplifier of Embodiment 3. As Figure 10 shown, MIM capacitors 45a and 45b are provided on the substrate 30. The structures of the MIM capacitors 45a and 45b are the same as those of the MIM capacitors 36a and 36b. The MIM capacitors 45a and 45b are the capacitor C01 and the capacitor C02, respectively. The bonding wire 44a electrically connects the pad 34a to the upper electrode of the MIM capacitor 45a. The bonding wire 44b electrically connects the pad 34b to the upper electrode of the MIM capacitor 45b. The lower electrodes of the MIM capacitors 45a and 45b are electrically connected to the conductor layer to which the reference potential is supplied. Other configurations are Figure 8 the same as the mounting example of Embodiment 2, and the description thereof is omitted.

[0110] The bonding wires 44a and 44b respectively correspond to Figure 9 the inductors L5 and L6. The bonding wire 44a and the MIM capacitor 45a form an inductive reactance element 48a. The bonding wire 44b and the MIM capacitor 45b form an inductive reactance element 48b.

[0111] According to Embodiment 2 and Embodiment 3, the reactance element 46a or the reactance element 48a (first reactance element) is shunt-connected to the node N1. The reactance element 46b or the reactance element 48b (second reactance element) is shunt-connected to the node N2. Thereby, even when the parasitic capacitances Cds1 and Cds2 are different from the capacitance C0 calculated according to Table 1, Figure 3 the capacitances of the capacitors C3 and C4 can be made close to C0. Thereby, the synthesizer 18 functions as a branch-line coupler.

[0112] The capacitance component obtained by synthesizing the parasitic capacitance Cds1 with the reactance element 46a or the reactance element 48a, the capacitance component obtained by synthesizing the parasitic capacitance Cds2 with the reactance element 46b or the reactance element 48b, and the capacitance C0 of the capacitors C1 and C2 can be set to be not less than 0.8 times and not more than 1.2 times of 1 / (2πfo×Zo)+1 / (2πfo×Zo / √2), and can be set to be not less than 0.9 times and not more than 1.1 times. The inductance L01 of each of the inductors L1 and L3 can be set to be not less than 0.8 times and not more than 1.2 times of Zo / (2πfo), and can be set to be not less than 0.9 times and not more than 1.1 times. The inductance L02 of each of the inductors L2 and L4 can be set to be not less than 0.8 times and not more than 1.2 times of Zo / (√2×(2πfo)), and can be set to be not less than 0.9 times and not more than 1.1 times. Thereby, the amplifier circuits 102 and 104 can be used as a balanced amplifier.

[0113] [Embodiment 4]

[0114] Embodiment 4 is an example of an LMBA (Load Modulated Balanced Amplifier). Figure 11 It is a circuit diagram of the amplifier circuit of Embodiment 4. As Figure 11 shown, in the amplifier circuit 106 of Embodiment 4, a control amplifier 22, an amplifier 10, and an amplifier 12 are connected in parallel between an input terminal Tin and an output terminal Tout. A high-frequency signal is input as an input signal Sin to the input terminal Tin. A distributor 24 (another distributor) distributes the input signal Sin input to the input terminal Tin into a signal S5 (fifth signal) and an input signal Si.

[0115] The signal S5 is input to the control amplifier 22 via a matching circuit 26. The matching circuit 26 matches the impedance of the matching circuit 26 as observed from the distributor 24 with the impedance of the control amplifier 22 as observed from the matching circuit 26. The control amplifier 22 amplifies the signal S5 and outputs the amplified signal as a signal S6 (sixth signal). The signal S6 amplified by the control amplifier 22 is output to a node N3 of a synthesizer 18.

[0116] The input signal Si distributed by the distributor 24 is input to the amplifier circuit 100. Except that the signal S6 is input to the node N3 of the synthesizer 18, the amplifier circuit 100 is the same as the amplifier circuit 100 of Embodiment 1, and its description is omitted.

[0117] The control amplifier 22 is equivalent to the main amplifier of the Doherty amplifier circuit, and the amplifiers 10 and 12 are equivalent to the peak amplifiers of the Doherty amplifier circuit. The control amplifier 22 operates in class AB or class B, and the amplifiers 10 and 12 operate in class C. When the input power of the input signal Sin is small, the control amplifier 22 mainly amplifies the input signal Sin. When the input power increases, in addition to the control amplifier 22, the amplifiers 10 and 12 also amplify the peak of the input signal Sin. Thus, the control amplifier 22 and the amplifiers 10 and 12 amplify the input signal Sin.

[0118] The synthesizer 18 modulates the loads of the amplifiers 10 and 12 using the signal S6, synthesizes the signals S3, S4, and S6, and outputs the synthesized signal as the output signal So. Hereinafter, a specific description will be given.

[0119] When the power of the input signal Si is small and the amplifiers 10 and 12 are not operating, the signal S6 input to the node N3 of the synthesizer 18 is divided into two signals S6 / 2 that are respectively directed to the nodes N1 and N2. The phase of the signal S6 / 2 at the node N2 is delayed by 90° compared to the phase of the signal S6 / 2 at the node N1. The signal S6 / 2 is reflected at the nodes N1 and N2. The signal S6 / 2 is synthesized at the node N4. The phase of the signal S6 / 2 reflected at the node N1 becomes 90° delayed compared to the phase of the signal S6 / 2 reflected at the node N2. Thus, at the node N4, the phases of the two signals S6 / 2 are aligned, and the signal S6 is synthesized. The synthesized signal S6 is output as the output signal So to the output terminal Tout. At this time, the reflection coefficient of the synthesizer 18 as observed from the amplifiers 10 and 12 is approximately 1, and the load impedance of the amplifiers 10 and 12 is substantially high.

[0120] When the power of the input signal Sin is large and the amplifiers 10 and 12 are operating, the phase of the signal S4 is delayed by 90° compared to the phase of the signal S3. The phase of the signal S6 / 2 at the node N2 is delayed by 90° compared to the phase of the signal S6 / 2 at the node N1. The signals S3 + S6 / 2 synthesized at the node N1 and the signal S4 + S6 / 2 synthesized at the node N2 are synthesized at the node N4. The synthesized signal S3 + S4 + S6 is output as the output signal So to the output terminal Tout. At this time, the reflection coefficient of the synthesizer 18 as observed from the amplifiers 10 and 12 is less than 1, and the larger the amplitudes of the signals S3 and S4, the smaller the reflection coefficient. Therefore, the load impedance of the amplifiers 10 and 12 is substantially low. Thus, the synthesizer 18 modulates the load impedance of the synthesizer 18 as observed from the amplifiers 10 and 12 depending on the amplitudes of the signals S3 and S4.

[0121] In a Doherty amplifier circuit, a λ / 4 line is provided as an impedance transformer in a synthesizer that synthesizes a signal amplified by a main amplifier and a signal amplified by a peak amplifier. The λ / 4 line is used to modulate the load impedance of the main amplifier. In this case, when the frequency changes, the electrical length of the λ / 4 line deviates from λ / 4, so it is difficult to widen the operating frequency band. In one example, the relative bandwidth of the synthesizer using the λ / 4 line is about 8%.

[0122] In the LMBA as in Embodiment 4, the synthesizer 18 uses the signal S6 to modulate the loads of the amplifier 10 and the amplifier 12, synthesizes the signal S3, the signal S4, and the signal S6, and outputs the synthesized signal as the output signal So. Thereby, widening of the operating frequency band can be achieved. For example, the relative bandwidth of the 90° coupler is at most 120% in a commercially available 90° hybrid coupler.

[0123] Deterioration of the characteristics of the amplifier circuit 106 can be suppressed by using the amplifier circuits of Embodiments 1 to 3 in the LMBA. The high-frequency characteristics can be improved. In particular, as shown in Comparative Example 1, when the loss of the line 20 is large, the reflection coefficient of the signal S6 / 2 at the nodes N1 and N2 is less than 1. As a result, the loss in the synthesizer 18 becomes large. In Embodiment 4, no redundant line such as the line 20 is provided, so the loss in the synthesizer 18 can be suppressed. It should be noted that in the LMBA or the like, S03 - S04 in Table 1 can also be set to negative or positive values other than 0 dB.

[0124] The embodiments disclosed herein should be considered as illustrative in all respects and not restrictive. The scope of the present disclosure is shown not by the above meaning but by the claims, and is intended to include all modifications within the meaning and scope equivalent to the claims.

Claims

1. An amplifier circuit comprising: a distributor for distributing an input signal into a first signal and a second signal whose phase is delayed by 90° compared with the first signal; a first amplifier, amplifying the first signal, and outputting the amplified first signal as a third signal to a first node; a second amplifier, amplifying the second signal, and outputting the amplified second signal as a fourth signal to a second node; a first inductor connecting the first node and the second node; a second inductor connecting the first node and a third node; a third inductor connecting the third node and a fourth node, wherein the fourth node is for outputting an output signal obtained by synthesizing the fourth signal and the third signal whose phase is delayed by 90° relative to the fourth signal; a fourth inductor connecting the second node and the fourth node; A first capacitor connected in shunt to the third node; and a second capacitor connected in shunt to the fourth node, The inductances of the first inductor and the third inductor are greater than the inductances of the second inductor and the fourth inductor.

2. The amplifier circuit according to claim 1, wherein: The inductance of each of the first inductor and the third inductor is greater than or equal to 0.8×√2 and less than or equal to 1.2×√2 of the inductance of each of the second inductor and the fourth inductor.

3. The amplifier circuit according to claim 1 or 2, wherein: A reactive element is connected to each of the first node and the second node without being branched.

4. The amplifier circuit according to claim 3, wherein: When the center frequency of the operating frequency band is set to fo and the reference impedance is set to Zo, The capacitance C0 of the first grounding capacitance of the output node of the first amplifier, the second grounding capacitance of the output node of the second amplifier, and the capacitances of the first capacitor and the second capacitor is greater than or equal to 0.8 times and less than or equal to 1.2 times 1 / (2πfo×Zo)+1 / (2πfo×Zo / √2), The inductance of each of the first inductor and the third inductor is greater than or equal to 0.8 times and less than or equal to 1.2 times Zo / (2πfo), Each inductance of the second inductor and the fourth inductor is greater than or equal to 0.8 times and less than or equal to 1.2 times Zo / (√2×(2πfo)).

5. The amplifier circuit according to claim 1 or 2, comprising: a first reactance element connected in shunt to the first node; and The second reactance element is connected to the second node in a shunt manner.

6. The amplifier circuit according to claim 5, wherein: When the center frequency of the operating frequency band is set to fo and the reference impedance is set to Zo, The capacitance C0 which is a capacitance component obtained by synthesizing the first ground capacitance of the output node of the first amplifier and the first reactance element, a capacitance component obtained by synthesizing the second ground capacitance of the output node of the second amplifier and the second reactance element, and the capacitance of the first capacitor and the second capacitor is greater than or equal to 0.8 times and less than or equal to 1.2 times 1 / (2πfo×Zo)+1 / (2πfo×Zo / √2), The inductance of each of the first inductor and the third inductor is greater than or equal to 0.8 times and less than or equal to 1.2 times Zo / (2πfo), Each inductance of the second inductor and the fourth inductor is greater than or equal to 0.8 times and less than or equal to 1.2 times Zo / (√2×(2πfo)).

7. The amplifier circuit according to claim 1 or 2, comprising: a first semiconductor chip including the first amplifier and a first pad corresponding to the first node; and A second semiconductor chip includes the second amplifier and a second pad corresponding to the second node. The first inductor includes a first bonding wire, a first end of the first bonding wire being connected to the first pad.

8. The amplifier circuit according to claim 7, wherein: The second end of the first bonding wire is connected to the second pad.

9. The amplifier circuit according to claim 7, wherein: The first inductor includes a second bonding wire having a first end connected to the second pad.

10. The amplifier circuit according to claim 7, comprising: a third bonding wire connecting the first pad to the first capacitor, the third bonding wire corresponding to the second inductor; and A fourth bonding wire connects the second pad and the second capacitor, and the fourth bonding wire corresponds to the fourth inductor.

11. The amplifier circuit according to claim 7, wherein: The first inductor, the second inductor, the third inductor, the fourth inductor, the first capacitor, the second capacitor, a first grounding capacitance of the first pad, and a second grounding capacitance of the second pad form a branch line coupler.

12. The amplifier circuit according to claim 1 or 2, comprising: another distributor that distributes the high-frequency signal into the input signal and a fifth signal; and controlling the amplifier to amplify the fifth signal and output the amplified fifth signal as a sixth signal, A synthesizer including the first inductor, the second inductor, the third inductor, the fourth inductor, the first capacitor, and the second capacitor modulates the loads of the first amplifier and the second amplifier using the sixth signal, synthesizes the third signal, the fourth signal, and the sixth signal, and outputs the synthesized signal as an output signal.

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