Amplification circuit

Abstract

The invention provides an amplifier circuit capable of realizing miniaturization. An amplifier circuit is provided with: a distributor (18) that distributes an input signal into a first signal and a second signal; a first amplifier having a first node to which the first signal is input, amplifying the first signal input to the first node, and outputting the amplified first signal as a third signal; a second amplifier having a second node to which the second signal is input, amplifying the second signal input to the second node, and outputting the amplified second signal as a fourth signal; a path (28) DC connecting the first node and the second node via the distributor; and a synthesizer (20) that synthesizes the third signal and the fourth signal, in which a third node that supplies a bias voltage to the first amplifier and the second amplifier is provided only at one point in the path.

Description

Technical Field

[0001] The present invention relates to an amplifier circuit. Background Art

[0002] As an amplifier circuit for amplifying high-frequency signals such as microwaves, a balanced amplifier is known (for example, Patent Document 1).

[0003] Prior Art Documents

[0004] Patent Documents

[0005] Patent Document 1: Japanese Patent Application Laid-Open No. 2022-506367

[0006] In Patent Document 1, a bias voltage is applied from a voltage source 8 to the input nodes of amplifiers 4 and 5, and a bias voltage is applied from a voltage source 9 to the output nodes of amplifiers 4 and 5. However, a specific method of applying a bias voltage from the voltage source 8 to the input nodes of amplifiers 4 and 5 is not described, and the amplifier circuit may be enlarged. Summary of the Invention

[0007] The present disclosure has been made in view of the above problems, and an object thereof is to achieve miniaturization.

[0008] One embodiment of the present disclosure is an amplifier circuit including: a distributor that distributes an input signal into a first signal and a second signal; a first amplifier having a first node to which the first signal is input, amplifying the first signal input to the first node, and outputting the amplified first signal as a third signal; a second amplifier having a second node to which the second signal is input, amplifying the second signal input to the second node, and outputting the amplified second signal as a fourth signal; a path that directly connects the first node and the second node via the distributor; and a synthesizer that synthesizes the third signal and the fourth signal, and a third node for supplying a bias voltage to the first amplifier and the second amplifier is provided only at one place in the path.

[0009] One embodiment of the present disclosure is an amplifier circuit, comprising: a distributor that distributes an input signal into a first signal and a second signal; a first amplifier having a first node for inputting the first signal, amplifying the first signal input to the first node, and outputting the amplified first signal as a third signal; a second amplifier having a second node for inputting the second signal, amplifying the second signal input to the second node, and outputting the amplified second signal as a fourth signal; a synthesizer that synthesizes the third signal and the fourth signal; a single pad supplied with a bias voltage; a first bias circuit that directly connects the single pad and the first node to suppress leakage of the first signal to the single pad; and a second bias circuit that directly connects the single pad and the second node to suppress leakage of the second signal to the single pad.

[0010] One embodiment of the present disclosure is an amplifier circuit, comprising: a distributor that distributes an input signal into a first signal and a second signal; a first amplifier having a first node for inputting the first signal, amplifying the first signal input to the first node, and outputting the amplified first signal as a third signal; a second amplifier having a second node for inputting the second signal, amplifying the second signal input to the second node, and outputting the amplified second signal as a fourth signal; a synthesizer that synthesizes the third signal and the fourth signal; a single pad supplied with a bias voltage; a first bias circuit that directly connects the single pad and the first node to suppress leakage of the first signal to the single pad; and a second bias circuit that directly connects the first node and the second node to suppress leakage of the first signal to the second node and leakage of the second signal to the first node.

[0011] Advantages of the Invention

[0012] According to the present disclosure, miniaturization can be achieved. Description of the Drawings

[0013] Figure 1 is a circuit diagram of the amplifier circuit of Embodiment 1.

[0014] Figure 2 is a circuit diagram showing Example 1 of the bias circuit in Embodiment 1.

[0015] Figure 3 is a circuit diagram showing Example 2 of the bias circuit in Embodiment 1.

[0016] Figure 4 is a circuit diagram showing Example 3 of the bias circuit in Embodiment 1.

[0017] Figure 5 It is the circuit diagram of Example 1 representing the dispenser in Example 1.

[0018] Figure 6 It is the circuit diagram of Example 2 representing the dispenser in Example 1.

[0019] Figure 7 It is the circuit diagram of Example 3 representing the dispenser in Example 1.

[0020] Figure 8 It is the circuit diagram of the amplifier circuit in Example 1.

[0021] Figure 9 It is the circuit diagram of the amplifier circuit in Comparative Example 1.

[0022] Figure 10 It is the circuit diagram of the amplifier circuit in Example 2.

[0023] Figure 11 It is the circuit diagram of Example 1 representing the bias circuit in Example 2.

[0024] Figure 12 It is the circuit diagram of Example 2 representing the bias circuit in Example 2.

[0025] Figure 13 It is the circuit diagram of Example 3 representing the bias circuit in Example 2.

[0026] Figure 14 It is the circuit diagram of Example 4 representing the dispenser in Example 2.

[0027] Figure 15 It is the circuit diagram of Example 5 representing the dispenser in Example 2.

[0028] Figure 16 It is the circuit diagram of the circuit for simulation.

[0029] Figure 17 It is the diagram representing S21 and S41 in the simulation.

[0030] Figure 18 It is the diagram representing S43 and S23 in the simulation.

[0031] Figure 19 It is the circuit diagram of the amplifier circuit in Example 3.

[0032] Figure 20 It is the circuit diagram of Example 1 representing the bias circuit in Example 3.

[0033] Figure 21 It is the circuit diagram of Example 2 representing the bias circuit in Example 3.

[0034] Figure 22 It is the circuit diagram of the amplifier circuit in Example 4.

[0035] Description of the reference numerals:

[0036] 10 (first amplifier), 11 (second amplifier): amplifiers;

[0037] 12 (first bias circuit), 12a (first bias circuit), 12b (second bias circuit), 12c (second bias circuit), 14, 14a, 14b, 22: bias circuits;

[0038] 13, 13a, 13b, 15, 15a, 15b, 23: pads;

[0039] 16, 17, 26: matching circuits;

[0040] 18, 24 (another distributor): distributors;

[0041] 20: synthesizer;

[0042] 21: control amplifier;

[0043] 27, 28: paths;

[0044] 29: DC path;

[0045] 100, 102, 104, 106, 110: amplifier circuits;

[0046] S1 (first signal), S2 (second signal), S3 (third signal), S4 (fourth signal), S5 (fifth signal), S6 (sixth signal): signals;

[0047] Si: input signal;

[0048] So: output signal;

[0049] N1 (first node), N2 (second node), N5 (third node), N6 (fourth node): nodes;

[0050] C01a (first capacitor), C01b (second capacitor): capacitors. Detailed implementation manners

[0051] [Description of the embodiments of the present disclosure]

[0052] First, the content of the embodiments of the present disclosure will be listed for description.

[0053] (1) One embodiment of the present disclosure is an amplifier circuit, comprising: a distributor that distributes an input signal into a first signal and a second signal; a first amplifier having a first node for inputting the first signal, amplifying the first signal input to the first node, and outputting the amplified first signal as a third signal; a second amplifier having a second node for inputting the second signal, amplifying the second signal input to the second node, and outputting the amplified second signal as a fourth signal; a path that directly connects the first node and the second node via the distributor; and a synthesizer that synthesizes the third signal and the fourth signal. There is only one third node in the path that supplies a bias voltage to the first amplifier and the second amplifier. Thus, the number of pads and the number of bias circuits can be reduced, and therefore the amplifier circuit can be miniaturized.

[0054] (2) In the above (1), it may also comprise: a pad to which the bias voltage is supplied; and a bias circuit that directly connects the pad and the third node to suppress leakage of the first signal and the second signal to the pad. Thus, the number of pads and the number of bias circuits can be reduced, and therefore the amplifier circuit can be miniaturized.

[0055] (3) In the above (1) or (2), it may be that the distributor includes a branch-line coupler, and the branch-line coupler has: a first end for inputting the input signal; a second end for outputting the first signal; a third end located diagonally opposite the first end for outputting the second signal; and a fourth end located diagonally opposite the second end, which is terminated at a reference potential. Thus, the first node and the second node can be directly connected via the distributor.

[0056] (4) In the above (3), it may also comprise: a capacitor, the first end of which is connected to the fourth end of the branch-line coupler; and a resistor, the first end of which is connected to the second end of the capacitor, and the second end of which is connected to the reference potential. Thus, direct current flowing from the path to the reference potential can be suppressed.

[0057] (5) One embodiment of the present disclosure is an amplifier circuit, comprising: a distributor that distributes an input signal into a first signal and a second signal; a first amplifier having a first node for inputting the first signal, amplifying the first signal input to the first node, and outputting the amplified first signal as a third signal; a second amplifier having a second node for inputting the second signal, amplifying the second signal input to the second node, and outputting the amplified second signal as a fourth signal; a synthesizer that synthesizes the third signal and the fourth signal; a single pad supplied with a bias voltage; a first bias circuit that directly connects the single pad and the first node in DC to suppress leakage of the first signal to the single pad; and a second bias circuit that directly connects the single pad and the second node in DC to suppress leakage of the second signal to the single pad. Thereby, the number of pads can be reduced, and thus the amplifier circuit can be miniaturized.

[0058] (6) One embodiment of the present disclosure is an amplifier circuit, comprising: a distributor that distributes an input signal into a first signal and a second signal; a first amplifier having a first node for inputting the first signal, amplifying the first signal input to the first node, and outputting the amplified first signal as a third signal; a second amplifier having a second node for inputting the second signal, amplifying the second signal input to the second node, and outputting the amplified second signal as a fourth signal; a synthesizer that synthesizes the third signal and the fourth signal; a single pad supplied with a bias voltage; a first bias circuit that directly connects the single pad and the first node in DC to suppress leakage of the first signal to the single pad; and a second bias circuit that directly connects the first node and the second node in DC to suppress leakage of the first signal to the second node and leakage of the second signal to the first node. Thereby, the number of pads can be reduced, and thus the amplifier circuit can be miniaturized.

[0059] (7) In the above (5) or (6), it may also be that a first end of the distributor that outputs the first signal and a second end of the distributor that outputs the second signal are directly connected in DC without passing through the distributor. Thereby, the number of pads can be reduced, and thus the amplifier circuit can be miniaturized.

[0060] (8) In the above (5) or (6), it may also be that the first terminal of the distributor that outputs the first signal and the second terminal of the distributor that outputs the second signal are directly connected via the distributor. The amplifier circuit includes: a first capacitor, the first terminal of the first capacitor is connected to the distributor, and the second terminal of the first capacitor is connected to the first node; and a second capacitor, the first terminal of the second capacitor is connected to the distributor, and the second terminal of the second capacitor is connected to the second node. Thereby, the number of pads can be reduced, and thus the amplifier circuit can be miniaturized.

[0061] (9) In any one of the above (1) to (8), it may also include: another distributor that distributes a high-frequency signal into the input signal and a fifth signal; and a control amplifier that amplifies the fifth signal and outputs the amplified fifth signal as a sixth signal. The synthesizer uses the sixth signal to modulate the loads of the first amplifier and the second amplifier, synthesizes the third signal, the fourth signal, and the sixth signal, and outputs the synthesized signal as an output signal. Thereby, broadbanding of the operating frequency band can be achieved.

[0062] (10) In the above (9), it may also include a DC path that directly connects the output node of the first amplifier and the output node of the control amplifier via the synthesizer, and a fourth node that supplies a bias voltage to the first amplifier and the control amplifier is provided only at one place in the DC path. Thereby, the number of pads and the number of bias circuits can be reduced, and thus the amplifier circuit can be miniaturized.

[0063] [Details of Embodiments of the Present Disclosure]

[0064] Hereinafter, with reference to the drawings, specific examples of the amplifier circuit according to the embodiments of the present disclosure will be described. It should be noted that the present disclosure is not limited to these examples, but is shown by the claims, and is intended to include all modifications within the meaning and scope equivalent to the claims.

[0065] [Example 1]

[0066] Example 1 is an example of a balanced amplifier. Figure 1 is the circuit diagram of the amplifier circuit of Example 1. As Figure 1As shown, in the amplifier circuit 100 of Embodiment 1, an amplifier 10 and an amplifier 11 are connected in parallel between an input terminal Tin and an output terminal Tout. A high-frequency signal is input as an input signal Si to the input terminal Tin. When the amplifier circuit 100 is used in a base station for mobile communication, the frequency of the high-frequency signal is, for example, 0.5 GHz or more and 10 GHz or less. A capacitor C01 for DC (Direct Current) cut-off is connected between the input terminal Tin and a distributor 18. The distributor 18 distributes the input signal Si input to the input terminal Tin into a signal S1 (first signal) and a signal S2 (second signal).

[0067] The signal S1 is input to the amplifier 10 through a matching circuit (MN: Matching Network) 16. In all the drawings, the matching circuit is illustrated as MN. The matching circuit 16 matches the impedance of the matching circuit 16 as observed from the distributor 18 with the impedance of the amplifier 10 as observed from the matching circuit 16. The amplifier 10 (first amplifier) has a node N1 (first node) and a node N3. The amplifier 10 amplifies the signal S1 input to the node N1, and outputs the amplified signal S1 as a signal S3 (third signal) to the node N3. The signal S3 amplified by the amplifier 10 is input to a synthesizer 20.

[0068] The signal S2 is input to the amplifier 11 through a matching circuit 17. The matching circuit 17 matches the impedance of the matching circuit 17 as observed from the distributor 18 with the impedance of the amplifier 11 as observed from the matching circuit 17. The amplifier 11 (second amplifier) has a node N2 (second node) and a node N4. The amplifier 11 amplifies the signal S2 input to the node N2, and outputs the amplified signal S2 as a signal S4 (fourth signal) to the node N4. The signal S4 amplified by the amplifier 11 is input to the synthesizer 20.

[0069] The synthesizer 20 synthesizes the signal S3 and the signal S4, and outputs the synthesized signal as an output signal So to the output terminal Tout. A capacitor C02 for DC cut-off is connected between the synthesizer 20 and the output terminal Tout.

[0070] A path 28 directly connects the node N1 and the node N2 through the matching circuit 16, the matching circuit 17, and the distributor 18. Thus, the node N1 and the node N2 are directly short-circuited, and are substantially at the same potential in DC. A path 27 directly connects the node N3 and the node N4 through the synthesizer 20. Thus, the node N3 and the node N4 are directly short-circuited, and are substantially at the same potential in DC.

[0071] A bias circuit (BC: Bias Circuit) 12 is connected between a node N5 within a path 28 and a pad 13. The pad 13 is a pad that supplies an input bias voltage to nodes N1 and N2 which are input nodes of an amplifier 10 and an amplifier 11. The bias circuit 12 connects the pad 13 and the node N5 in a DC manner, suppressing leakage of a signal S1 flowing through the node N5 to the pad 13. The nodes N1 and N2 are connected in a DC manner through the path 28. Therefore, substantially the same input bias voltage is applied to the nodes N1 and N2. The bias circuit 12 may be connected to any part within the path 28.

[0072] A bias circuit 14 is connected between a node N6 within a path 27 and a pad 15. The pad 15 is a pad that supplies an output bias voltage to nodes N3 and N4 which are output nodes of the amplifier 10 and the amplifier 11. The bias circuit 14 connects the pad 15 and the node N6 in a DC manner, suppressing leakage of a signal S3 flowing through the node N6 to the pad 15. The nodes N3 and N4 are connected in a DC manner through the path 27. Therefore, substantially the same output bias voltage is applied to the nodes N3 and N4.

[0073] A matching circuit or a higher harmonic processing circuit may be connected between the node N3 and a synthesizer 20. A matching circuit or a higher harmonic processing circuit may be connected between the node N4 and the synthesizer 20. The matching circuit is a circuit that matches the impedance of the matching circuit as observed from the node N3 or the node N4 with the impedance of the synthesizer 20 as observed from the matching circuit. The higher harmonic processing circuit is a circuit that reflects higher harmonic signals within the signal S3 or the signal S4 to the node N3 or the node N4. When the operating frequency band of the amplifier circuit 100 is set as a fundamental wave, the higher harmonic signals are, for example, second harmonic waves or third harmonic waves.

[0074] The amplifier 10 and the amplifier 11 are, for example, FETs (Field Effect Transistors), with the source grounded, a high-frequency signal input to the gate, and a high-frequency signal output from the drain. The FETs are, for example, GaN HEMTs (Gallium Nitride High Electron Mobility Transistors) or LDMOSs (Laterally Diffused Metal Oxide Semiconductors). Multistage FETs may be provided respectively in the amplifier 10 and the amplifier 11. When the amplifier 10 and the amplifier 11 are FETs, the bias voltages supplied to the pad 13 and the pad 15 are a gate bias voltage and a drain bias voltage respectively.

[0075] When the amplifier circuit 100 is a balanced amplifier, the distributor 18 distributes the input signal Si into signals S1 and S2 such that the amplitudes of signal S1 and signal S2 are substantially the same, and the phase of signal S2 at the center frequency fo of the operating frequency band is approximately 90° delayed from the phase of signal S1. The synthesizer 20 delays the phase of signal S3 by 90° and synthesizes it with signal S4. The amplifier circuit 100 can also be an amplifier circuit other than a balanced amplifier.

[0076] [Examples of Bias Circuits]

[0077] Figures 2 to 4 are circuit diagrams showing Examples 1 to 3 of the bias circuit in Embodiment 1. As Figure 2 shown, in Example 1, the bias circuit 12 includes a transmission line TL1 and a capacitor C1. The first end of the transmission line TL1 is electrically connected to the node N5, and the second end of the transmission line TL1 is electrically connected to the pad 13. The transmission line TL1 is a λ / 4 transmission line. The electrical length of the λ / 4 transmission line is, for example, λ / 4. Here, λ is the wavelength at the center frequency fo of the operating frequency band of the amplifier circuit 100. The electrical length of the λ / 4 transmission line may not be strictly λ / 4, and for example, it may be 3λ / 16 or more and 5λ / 16 or less, or it may be 7λ / 32 or more and 9λ / 32 or less. The same applies to the following embodiments. A capacitor C1 is shunt-connected to the node between the transmission line TL1 and the pad 13. Thereby, the bias voltage supplied to the pad 13 is supplied to the node N5, and signals S1 or S2 passing through the node N5 are less likely to leak to the pad 13.

[0078] As Figure 3 shown, in Example 2, an inductor L1 is used instead of Figure 2 the transmission line TL1. In Figure 3 Example 2, signals S1 or S2 passing through the node N5 are also less likely to leak to the pad 13 by appropriately setting the inductance of the inductor L1 and the capacitance of the capacitor C1.

[0079] As Figure 4 shown, in Example 3, it is an example using a CRLH (Composite Right / Left Handed) line. A transmission line TL2 and an inductor L2 are connected in series between the node N5 and the pad 13. A capacitor C2 is shunt-connected to the node between the inductor L2 and the pad 13. A capacitor C3 and a capacitor C4 are connected in series between the node between the transmission line TL2 and the inductor L2 and the ground. An inductor L3 is shunt-connected to the node between the capacitor C3 and the capacitor C4. In Figure 4In Example 3, the inductances of inductor L2 and inductor L3 and the capacitances of capacitors C2 to C4 are appropriately set so that signal S1 or signal S2 passing through node N5 is less likely to leak to pad 13. A CRLH line other than the circuit of Figure 4 can also be used.

[0080] [Examples of Dividers]

[0081] Figures 5 to 7 are circuit diagrams showing Examples 1 to 3 of the divider in Embodiment 1. As Figure 5 shown, in Example 1, the divider 18 uses a Wilkinson divider. The Wilkinson divider 18a includes a transmission line TL11, a transmission line TL12, and a resistor R11. The transmission line TL11 is connected between terminal T1 and terminal T2, and the transmission line TL12 is connected between terminal T1 and terminal T3. The transmission lines TL11 and TL12 are λ / 4 transmission lines. The resistance value of the resistor R11 is, for example, twice the reference impedance. A transmission line TL13 is connected between the transmission line TL12 and terminal T3. The transmission line TL13 is a λ / 4 transmission line. The Wilkinson divider divides the input signal Si input to terminal T1 into signals S1 and S2 with the same amplitude, and the transmission line TL13 delays the phase of signal S2 at the center frequency fo by approximately 90° compared to the phase of signal S1. Terminals T2 and T3 are connected directly in DC via the transmission lines TL11 to TL13. Note that 90° does not have to be strictly 90°, for example, in terms of the wavelength λ, it can be, for example, 3λ / 16 or more and 5λ / 16 or less, or it can be 7λ / 32 or more and 9λ / 32 or less. The same applies to the following embodiments.

[0082] As Figure 6 shown, in Example 2, the divider 18 uses a distributed parameter type branch line coupler as a 90° coupler. A transmission line TL21 is connected between terminal T1 and terminal T2. A transmission line TL22 is connected between terminal T2 and terminal T3. A transmission line TL23 is connected between terminal T3 and terminal T4. A transmission line TL24 is connected between terminal T4 and terminal T1. The transmission lines TL21 to TL24 are λ / 4 transmission lines. The input signal Si input to terminal T1 is divided into signals S1 and S2 and output from terminals T2 and T3, respectively. The phase of signal S2 at the center frequency fo is delayed by approximately 90° compared to the phase of signal S1. Terminal T4 is connected to the reference potential via a reference impedance (for example, 50 Ω), for example. Terminals T2 and T3 are connected directly in DC via the transmission lines TL21 to TL24.

[0083] As Figure 7As shown, in Example 3, the distributor 18 uses a lumped-parameter type branch-line coupler. An inductor L11 is connected between terminals T1 and T2. An inductor L12 is connected between terminals T2 and T3. An inductor L13 is connected between terminals T3 and T4. An inductor L14 is connected between terminals T4 and T1. The node between inductor L14 and inductor L11 is grounded via a capacitor C11. The node between inductor L11 and inductor L12 is grounded via a capacitor C12. The node between inductor L12 and inductor L13 is grounded via a capacitor C13. The node between inductor L13 and inductor L14 is grounded via a capacitor C14. By appropriately setting the inductances of inductors L11 to L14 and the capacitances of capacitors C11 to C14, the input signal Si input to terminal T1 is roughly equally divided into signal S1 and signal S2, which are output from terminals T2 and T3 respectively, and the phase of signal S2 at the center frequency fo is roughly delayed by 90° compared to the phase of signal S1. Terminal T4 is connected to a reference potential via a reference impedance, for example. Terminals T2 and T3 are connected DC via inductors L11 to L14.

[0084] The matching circuits 16 and 17 are passive circuits including inductors and capacitors. Capacitors are not connected in series in the paths through which signal S1 and signal S2 flow respectively. Thus, terminal T2 is connected DC to node N1, and terminal T3 is connected DC to node N2. The matching circuits 16 and 17 are, for example, circuits formed by combining inductors connected in series, a π-type circuit of the CLC structure, a T-type circuit of the LCL structure, an L-type circuit of the LC structure, or these circuits.

[0085] [Example of an amplifier circuit using a 90° coupler]

[0086] Figure 8 is a circuit diagram of the amplifier circuit of Example 1, and is an example of using a Figure 6 90° coupler for the distributor 18 and the synthesizer 20. As Figure 8As shown, the terminal T1 of the distributor 18 is connected to the input terminal Tin via the capacitor C01 for DC cut-off. The terminal T2 of the distributor 18 is connected to the node N1 via the matching circuit 16. The terminal T3 of the distributor 18 is connected to the node N2 via the matching circuit 17. The terminal T4 of the distributor 18 forms a termination via the capacitor C03 for DC cut-off and the resistor R01. The terminal T1 of the synthesizer 20 is electrically connected to the node N3. The terminal T2 of the synthesizer 20 forms a termination via the capacitor C04 for DC cut-off and the resistor R02. The terminal T3 of the synthesizer 20 is connected to the output terminal Tout via the capacitor C02 for DC cut-off. The terminal T4 of the synthesizer 20 is connected to the node N4. The resistance values of the resistor R01 and the resistor R02 are the reference impedance (e.g., 50 Ω). At the synthesizer 20, the phase of the signal S3 at the center frequency fo is approximately delayed by 90° with respect to the phase of the signal S4, and the signals S3 and S4 input to the terminals T1 and T4 are synthesized into the output signal So.

[0087] The path 28 DC-connects between the node N1 and the node N2 via the distributor 18. Therefore, the bias circuit 12 can be connected to the amplifier 10 and the amplifier 11 at the node N5 at any position on the path 28 to apply substantially the same input bias voltage. The path 27 DC-connects between the node N3 and the node N4 via the synthesizer 20. Therefore, the bias circuit 14 can be connected to the amplifier 10 and the amplifier 11 at the node N6 at any position on the path 27 to apply substantially the same output bias voltage. The capacitor C01 can be used to suppress the DC current from flowing to the input terminal Tin due to the input bias voltage. The capacitor C02 can be used to suppress the DC current from flowing to the output terminal Tout due to the output bias voltage. The capacitors C03 and C04 can be used to suppress the DC current from flowing to the resistor R01 and the resistor R02.

[0088] [Comparative Example 1]

[0089] Figure 9 is the circuit diagram of the amplifier circuit of Comparative Example 1. As Figure 9As shown, in the amplifier circuit 110 of Comparative Example 1, capacitors C01a and C01b for DC cut-off are respectively connected between the distributor 18 and nodes N1 and N2. Capacitors C02a and C02b for DC cut-off are respectively connected between the synthesizer 20 and nodes N3 and N4. A pad 13a is connected to a node N5a between the node N1 and the capacitor C01a via a bias circuit 12a, and a pad 13b is connected to a node N5b between the node N2 and the capacitor C01b via a bias circuit 12b. A pad 15a is connected to a node N6a between the node N3 and the capacitor C02a via a bias circuit 14a, and a pad 15b is connected to a node N6b between the node N4 and the capacitor C02b via a bias circuit 14b.

[0090] In Comparative Example 1, the node N1 and the node N2 are not connected directly in DC, and the node N3 and the node N4 are not connected directly in DC. Therefore, the pad 13a and the pad 13b are respectively connected to the node N5a and the node N5b via the bias circuit 12a and the bias circuit 12b. The pad 15a and the pad 15b are respectively connected to the node N6a and the node N6b via the bias circuit 14a and the bias circuit 14b. Thus, two pads 13a and 13b, two bias circuits 12a and 12b, two pads 15a and 15b, and two bias circuits 14a and 14b are provided, so that the amplifier circuit 110 becomes large-sized.

[0091] As an amplifier circuit in which an amplifier is connected in parallel between an input terminal Tin and an output terminal Tout, a Doherty amplifier circuit is known. In the Doherty amplifier circuit, the main amplifier operates in class A or AB, and the peak amplifier operates in class C. Therefore, the input bias voltages of the main amplifier and the peak amplifier are different. Therefore, a bias circuit for applying an input bias voltage to the main amplifier and a bias circuit for applying an input bias voltage to the peak amplifier are respectively provided. However, when the input bias voltages of the amplifier 10 and the amplifier 11 can be made the same as those shown in Embodiment 1 and Comparative Example 1, when two pads 13a and 13b and two bias circuits 12a and 12b are provided as shown in Comparative Example 1, the amplifier circuit becomes large-sized.

[0092] The pad 13 is a metal layer such as a copper layer, a gold layer, or an aluminum layer provided on a dielectric substrate. A bonding wire or a bump or the like is bonded to the pad 13. Therefore, the size of the pad 13 is 50 μm × 50 μm or more, and as an example, it is 100 μm × 100 μm, which is very large. Therefore, when two pads 13a and 13b are provided as shown in Comparative Example 1, the amplifier circuit becomes large-sized.

[0093] [Description of Embodiment 1]

[0094] According to Embodiment 1, in path 28 that directly connects node N1 and node N2, node N5 (the third node) for supplying input bias voltages to amplifier 10 and amplifier 11 is provided only at one location. Thereby, one bias circuit 12 and one pad 13 can be used to supply input bias voltages to amplifier 10 and amplifier 11. Therefore, amplifier circuit 100 can be miniaturized. Note that in Figure 1 and Figure 8 , node N5 is provided between splitter 18 and node N1, but it may also be provided between splitter 18 and node N2.

[0095] Bias circuit 12 directly connects pad 13 and node N5, suppressing leakage of signal S1 and signal S2 to pad 13. In this way, the number of pads 13 and bias circuits 12 can be reduced, and amplifier circuit 100 can be miniaturized. For example, the absolute value of the impedance (such as the resistance value) under direct current between pad 13 and node N5 is smaller than the absolute value of the impedance at the center frequency fo of the operating frequency band between pad 13 and node N5, for example, 1 / 10 times or less, 1 / 100 times or less, 1 / 1000 times or less. In addition, the leakage from node N5 to pad 13 at the center frequency fo is -20 dB or less, -40 dB or less, -60 dB or less. The same applies to the bias circuits in the following embodiments.

[0096] As Figure 8 shown, a branch-line coupler is used as splitter 18. Input signal Si is input to terminal T1 (the first terminal) of the branch-line coupler. Signal S1 is output from terminal T2 (the second terminal). Terminal T3 (the third terminal) is located diagonally opposite terminal T1, and signal S2 is output from terminal T3. Terminal T4 (the fourth terminal) is located diagonally opposite terminal T2, and a termination is formed at the reference potential. Thereby, node N1 and node N2 are connected via splitter 18 through direct-current path 28.

[0097] The first terminal of capacitor C03 is connected to terminal T4. The first terminal of resistor R01 is connected to the second terminal of capacitor C03, and the second terminal of resistor R01 is connected to the reference potential. Thereby, direct-current flowing from path 28 to the reference potential via resistor R01 can be suppressed. The resistance value of resistor R01 is the reference impedance (such as 50 Ω). The resistance value of resistor R01 may not be strictly the reference impedance, for example, it may be 0.8 times or more and 1.2 times or less of the reference impedance.

[0098] [Embodiment 2]

[0099] Figure 10 is the circuit diagram of the amplifier circuit of Embodiment 2. As Figure 10As shown, in the amplifier circuit 102 of Embodiment 2, a node N5a is provided between node N1 and terminal T2, and a node N5b is provided between node N2 and terminal T3. A capacitor C01a for DC cut-off is provided between node N5a and terminal T2, and a capacitor C01b for DC cut-off is provided between node N5b and terminal T3.

[0100] A bias circuit 12a is provided between node N5a and node N7, and a bias circuit 12b is provided between node N5b and node N7. A pad 13 is electrically connected to node N7. The bias circuit 12a connects the pad 13 and node N5a in DC, suppressing the leakage of the signal S1 flowing through node N5a to the pad 13 and node N5b. The bias circuit 12b connects the pad 13 and node N5b in DC, suppressing the leakage of the signal S2 flowing through node N5b to the pad 13 and node N5a. Other circuit structures are the same as those of Embodiment 1 Figure 1 and the description thereof is omitted.

[0101] [Examples of Bias Circuits]

[0102] Figures 11 to 13 are circuit diagrams showing Examples 1 to 3 of the bias circuit in Embodiment 2. As Figure 11 shown, in Example 1, the bias circuit 12a and the bias circuit 12b have the same circuit structure as the Figure 2 bias circuit 12. In the bias circuit 12a and the bias circuit 12b, the first ends of the transmission lines TL1 are respectively connected to node N5a and node N5b, and the second end of the transmission line TL1 is connected to node N7. The capacitor C1 is shunt-connected to the node between node N7 and the transmission line TL1. Thus, the bias voltage supplied to the pad 13 is supplied to node N5a and node N5b, and the signal S1 passing through node N5a and the signal S2 passing through node N5b are not easily leaked to the pad 13.

[0103] As Figure 12 shown, in Example 2, the bias circuit 12a and the bias circuit 12b have the same circuit structure as the Figure 3 bias circuit 12. In the bias circuit 12a and the bias circuit 12b, an inductor L1 is used instead of the Figure 11 transmission line TL1. In Figure 12 Example 2, the signal S1 passing through node N5a and the signal S2 passing through node N5b are also not easily leaked to the pad 13 by appropriately setting the inductance of the inductor L1 and the capacitance of the capacitor C1.

[0104] As Figure 13 shown, in Example 3, the bias circuit 12a and the bias circuit 12b have the same circuit structure as the Figure 4 bias circuit 12. In Figure 13In Example 3, the inductances of inductor L2 and inductor L3 and the capacitances of capacitors C2 to C4 are appropriately set so that the signal S1 passing through node N5a and the signal S2 passing through node N5b are less likely to leak to pad 13. A CRLH line other than the circuit of Figure 13 can also be used.

[0105] [Examples of Dividers]

[0106] Figure 14 and Figure 15 are circuit diagrams showing Example 4 and Example 5 of the divider in Embodiment 2. As Figure 14 shown, in Example 4, the divider 18 is a distributed coupling type coupler that electromagnetically couples transmission line TL41 and transmission line TL42. The input signal Si input to terminal T1 is divided into signal S1 and signal S2 and output to terminal T2 and terminal T3, respectively. Terminal T4 is connected to the reference potential via a reference impedance, for example. The phase of signal S2 at the center frequency fo is approximately 90° delayed from the phase of signal S1. The ratio of the amplitudes of signal S1 and signal S2 can be appropriately set by appropriately setting the coupling coefficient between transmission line TL41 and transmission line TL42.

[0107] As Figure 15 shown, in Example 5, the divider 18 is a closely wound coil coupler that electromagnetically couples inductor L21 and inductor L22. The input signal Si input to terminal T1 is divided into signal S1 and signal S2, and the phase of signal S2 at the center frequency fo is approximately 90° delayed from the phase of signal S1. The ratio of the amplitudes of signal S1 and signal S2 can be appropriately set by appropriately setting the inductances of inductor L21 and inductor L22 and the coupling coefficient between inductor L21 and inductor L22. Terminal T4 is connected to the reference potential via a reference impedance, for example.

[0108] According to Embodiment 2, the pad 13 supplied with the bias voltage is a single pad 13. The bias circuit 12a (first bias circuit) connects the single pad 13 to node N1 in a DC manner, suppressing the leakage of signal S1 to the single pad 13. The bias circuit 12b (second bias circuit) connects the single pad 13 to node N2 in a DC manner, suppressing the leakage of signal S2 to the single pad 13. Thus, compared with Figure 9 Comparative Example 1, the number of pads 13 can be set to one. As a result, the amplifier circuit 102 can be miniaturized.

[0109] When using Figure 14 Example 4 or Figure 15 Example 5 of the divider as Figure 10 the divider 18, terminals T2 and T3 are not connected in a DC manner via the divider 18. Therefore, as in Embodiment 1, it is difficult to make the bias circuit 12 into one. Therefore, use as inFigures 11 to 13 As described in Figures 11 to 13 , there is a single pad 13, a bias circuit 12a, and a bias circuit 12b. Thus, compared with Comparative Example 1, the number of pads 13 can be set to one, and the amplifier circuit 102 can be miniaturized. When using Figure 14 Example 4 of Figure 15 or Example 5 of

[0110] as the distributor 18, the DC-blocking capacitor may not be provided between the distributor 18 and the nodes N1 and N2, but between the input terminal Tin and the distributor 18. Figures 5 to 7 Examples 1 to 3 of the circuit structure described in Figure 10 can also be used as the distributor 18 of Figure 10 . As shown in Figures 11 to 13 , the first end of the capacitor C01a (first capacitor) is connected to the distributor 18, and the second end of the capacitor C01a is connected to the node N1. The first end of the capacitor C01b (second capacitor) is connected to the distributor 18, and the second end of the capacitor C01b is connected to the node N2. In this case, the nodes N1 and N2 are DC-isolated. Thus, as described in

[0111] [Simulation]

[0112] In Embodiment 2, the through characteristics of the nodes N5a and N5b and the isolation characteristics between the nodes N5a and N5b were simulated.

[0113] Figure 16 is the circuit diagram of the circuit for simulation. As shown in Figure 16 , a node N5a is provided in the path between the ports P1 and P2. A node N5b is provided in the path between the ports P3 and P4. A bias circuit 12a and a transmission line TL4 are connected in series between the node N5a and the node N7. A bias circuit 12b and a transmission line TL5 are connected in series between the node N5b and the node N7. The circuit structures of the bias circuit 12a and the bias circuit 12b are the same as those of Figure 11 Example 1. A transmission line TL3 is provided between the node N7 and the power supply B. The transmission lines TL3 to TL5 are equivalent to the lines that electrically connect the node N7 to the power supply B, the bias circuit 12a, and the bias circuit 12b, respectively.

[0114] The characteristic impedance of the transmission lines TL1 and TL3 - TL5 at 3.5 GHz is set to 80 Ω respectively. The electrical length of the transmission line TL1 at 3.5 GHz is converted into a phase of 90°, and the electrical lengths of the transmission lines TL3 - TL5 at 3.5 GHz are converted into phases of 5° respectively. The capacitance of the capacitor C1 is set to 100 pF, and the DC bias voltage supplied by the power source B is set to -2.6 V. The ports P1 - P4 are terminated at 50 Ω.

[0115] Figure 17 It is a diagram showing S21 and S41 in the simulation. Figure 18 It is a diagram showing S43 and S23 in the simulation. S21, S41, S43, and S23 correspond to the S - parameters between the respective ports. In Figure 17 and Figure 18 , the absolute values of S21, S41, S43, and S23 are expressed in dB. S21 represents the transmission characteristic from port P1 to port P2, S41 represents the isolation characteristic from port P1 to port P4, S43 represents the transmission characteristic from port P3 to port P4, and S23 represents the isolation characteristic from port P3 to port P2. The frequency fo corresponding to the center frequency of the operating frequency band of the amplifier circuit is 3.5 GHz.

[0116] As Figure 17 and Figure 18 show, S21 and S43 at the frequency fo are approximately 0 dB, and there is almost no loss of the signals S1 and S2 at the nodes N5a and N5b. At 7 GHz, S21 and S43 become extremely small because the electrical length of the transmission line TL1 at 7 GHz is equivalent to 1 / 2 of the wavelength. S41 and S23 at the frequency fo are approximately -80 dB or less, and the isolation characteristics are good.

[0117] As in the above simulation, in Embodiment 2, it is possible to suppress the loss of the signals S1 and S2 at the nodes N5a and N5b, and suppress the leakage of the signal S1 to the node N5a and the leakage of the signal S2 to the node N5b.

[0118] [Embodiment 3]

[0119] Figure 19 It is a circuit diagram of the amplifier circuit of Embodiment 3. As Figure 19As shown, in the amplifier circuit 104 of Embodiment 3, a bias circuit 12 is provided between the pad 13 and the node N5a, and a bias circuit 12c is provided between the node N5a and the node N5b. The bias circuit 12 connects the pad 13 and the node N5a in a DC manner, suppressing the leakage of the signal S1 flowing through the node N5a to the pad 13. The bias circuit 12c connects the node N5a and the node N5b in a DC manner, suppressing the leakage of the signal S1 flowing through the node N5a to the node N5b and suppressing the leakage of the signal S2 flowing through the node N5b to the node N5a. The other circuit structures are the same as those of Embodiment 2 Figure 10 and their description is omitted.

[0120] [Examples of Bias Circuits]

[0121] Figures 20 to 21 are circuit diagrams showing Example 1 and Example 2 of the bias circuit in Embodiment 3. As Figure 20 shown, in Example 1, the bias circuit 12 has the same circuit structure as the Figure 2 bias circuit 12. The bias circuit 12 supplies the bias voltage supplied to the pad 13 to the node N5a and suppresses the leakage of the signal S1 passing through the node N5a to the pad 13.

[0122] In the bias circuit 12c, the first end of the transmission line TL1a is electrically connected to the node N5a, and the second end of the transmission line TL1a is connected to the node N8. The first end of the transmission line TL1b is electrically connected to the node N5b, and the second end of the transmission line TL1b is connected to the node N8. The capacitor C1 is shunt-connected to the node N8. The transmission line TL1a and the transmission line TL1b are λ / 4 transmission lines. The bias circuit 12c supplies the bias voltage supplied to the node N5a to the node N5b, suppressing the leakage of the signal S1 passing through the node N5a to the node N5b and suppressing the leakage of the signal S2 passing through the node N5b to the node N5a.

[0123] As Figure 21 shown, in Example 2, inductors L1, L1a, and L1b are used respectively instead of the Figure 20 transmission lines TL1, TL1a, and TL1b. By appropriately setting the inductances of the inductors L1, L1a, and L1b and the capacitance of the capacitor C1, the signal S1 passing through the node N5a is less likely to leak to the pad 13 and the node N5b, and the signal S2 passing through the node N5b is less likely to leak to the node N5a. The bias circuit 12 and the bias circuit 12c may also include CRLH lines.

[0124] According to Embodiment 3, the pad 13 to which the bias voltage is supplied is a single pad 13. The bias circuit 12 (first bias circuit) connects the single pad 13 to the node N1 in a DC manner, suppressing the leakage of the signal S1 to the single pad 13. The bias circuit 12c (second bias circuit) connects the node N1 to the node N2 in a DC manner, suppressing the leakage of the signal S1 to the node N2 and suppressing the leakage of the signal S2 to the node N1. Thus, compared with Figure 9 Comparative Example 1, the number of pads 13 can be set to one. Thus, the amplifier circuit 104 can be miniaturized.

[0125] It is also possible to use Figure 14 Example 4 of Figure 15 and the distributor of Example 5 of Figure 10 as the distributor 18 of Embodiment 2 and Figure 19 of Embodiment 3. In this case, the terminal T2 and the terminal T3 are connected to each other in a DC manner without passing through the distributor 18. Therefore, as shown in Embodiment 1, it is difficult to make the bias circuit 12 into one. Therefore, use a single pad 13, a bias circuit 12, and a bias circuit 12c as described in Figure 20 and Figure 21 . Thus, compared with Comparative Example 1, the number of pads can be set to one, and the amplifier circuit 104 can be miniaturized.

[0126] It is also possible to use the distributors of Examples 1 to 3 having the circuit structure described in Figures 5 to 7 as the distributor 18 of Embodiment 2 and Figure 10 and Embodiment 3 of Figure 19 . In this case, when capacitors C01a and C01b are provided as shown in Figure 19 , the node N1 and the node N2 are separated from each other in a DC manner. Therefore, use a single pad 13, a bias circuit 12, and a bias circuit 12c as described in Figure 20 and Figure 21 . Thus, compared with Comparative Example 1, the number of pads can be set to one, and the amplifier circuit 104 can be miniaturized.

[0127] [Embodiment 4]

[0128] Embodiment 4 is an example of an LMBA (Load Modulated Balanced Amplifier). Figure 22 is the circuit diagram of the amplifier circuit of Embodiment 4. As shown in Figure 22As shown, in the amplifier circuit 106 of Embodiment 4, a control amplifier 21, an amplifier 10, and an amplifier 11 are connected in parallel between an input terminal Tin and an output terminal Tout. A high-frequency signal is input as an input signal Sin to the input terminal Tin. A distributor 24 (another distributor) distributes the input signal Sin input to the input terminal Tin into a signal S5 (fifth signal) and an input signal Si.

[0129] The signal S5 is input to the control amplifier 21 via a matching circuit 26 and a capacitor C05. The matching circuit 26 matches the impedance of the matching circuit 26 observed from the distributor 24 with the impedance of the control amplifier 21 observed from the matching circuit 26. The capacitor C05 is a DC cut-off capacitor. The control amplifier 21 amplifies the signal S5 and outputs the amplified signal as a signal S6 (sixth signal). The signal S6 amplified by the control amplifier 21 is input to the terminal T2 of the synthesizer 20.

[0130] A bias circuit 22 is provided between a node N9 between the control amplifier 21 and the capacitor C05 and a pad 23. The pad 23 is a pad for supplying an input bias voltage to the input node of the control amplifier 21. The bias circuit 22 connects the pad 23 and the node N9 in DC, suppressing the leakage of the signal S5 flowing through the node N9 to the pad 23.

[0131] A bias circuit 14 is provided between a node N6 between the control amplifier 21 and the terminal T2 of the synthesizer 20 and a pad 15. The pad 15 is a pad for supplying an output bias voltage to the output nodes of the control amplifier 21, the amplifier 10, and the amplifier 11. The bias circuit 14 connects the pad 15 and the node N6 in DC, suppressing the leakage of the signal S6 flowing through the node N5 to the pad 15.

[0132] The input signal Si distributed by the distributor 24 is input to the amplifier circuit 100. Except for the points that the bias circuit 14 and the pad 15 are not provided, and the synthesizer 20 is Figure 5 a 90° coupler and the signal S6 is input to the terminal T2 of the synthesizer 20, the amplifier circuit 100 is the same as the amplifier circuit 100 of Embodiment 1, and its description is omitted.

[0133] The control amplifier 21 corresponds to the main amplifier of a Doherty amplifier circuit, and the amplifiers 10 and 11 correspond to the peak amplifiers of a Doherty amplifier circuit. The control amplifier 21 operates in class AB or class B, and the amplifiers 10 and 11 operate in class C. When the input power of the input signal Sin is small, the control amplifier 21 mainly amplifies the input signal Sin. When the input power increases, in addition to the control amplifier 21, the amplifiers 10 and 11 also amplify the peak of the input signal Sin. Thus, the control amplifier 21, the amplifiers 10, and the amplifier 11 amplify the input signal Sin.

[0134] When the power of the input signal Si is small and the amplifiers 10 and 11 are not operating, the signal S6 input to terminal T2 of the synthesizer 20 is divided into two, with signals S6 / 2 directed towards terminal T1 and terminal T4 respectively. The phase of the signal S6 / 2 at terminal T4 is delayed by 90° compared to the phase of the signal S6 / 2 at terminal T1. The signal S6 / 2 is reflected at terminals T1 and T4. The signal S6 / 2 is combined at terminal T3. The phase of the signal S6 / 2 reflected at terminal T1 becomes delayed by 90° compared to the phase of the signal S6 / 2 reflected at terminal T4. Thus, at terminal T3, the phases of the two signals S6 / 2 are aligned and the signal S6 is combined. The combined signal S6 is output as the output signal So to the output terminal Tout. At this time, the reflection coefficient of the synthesizer 20 as observed from the amplifiers 10 and 11 is close to 1, and the load impedance of the amplifiers 10 and 11 is substantially high.

[0135] When the power of the input signal Sin is large and the amplifiers 10 and 11 are operating, the phase of the signal S4 is delayed by 90° compared to the phase of the signal S3. The phase of the signal S6 / 2 at terminal T4 is delayed by 90° compared to the phase of the signal S6 / 2 at terminal T1. The signal S3 + S6 / 2 combined at terminal T1 and the signal S4 + S6 / 2 combined at terminal T4 are combined at terminal T3. The combined signal S3 + S4 + S6 is output as the output signal So to the output terminal Tout. At this time, the reflection coefficient of the synthesizer 20 as observed from the amplifiers 10 and 11 is less than 1, and the larger the amplitudes of the signals S3 and S4, the smaller the reflection coefficient. Therefore, the load impedance of the amplifiers 10 and 11 is substantially low. Thus, the synthesizer 20 modulates the load impedance of the synthesizer 20 as observed from the amplifiers 10 and 11 depending on the amplitudes of the signals S3 and S4.

[0136] In a Doherty amplifier circuit, a λ / 4 line is provided as an impedance transformer in a synthesizer that combines a signal amplified by a main amplifier and a signal amplified by a peak amplifier. The λ / 4 line is used to modulate the load impedance of the main amplifier. In this case, when the frequency changes, the electrical length of the λ / 4 line deviates from λ / 4, and thus it is difficult to widen the operating bandwidth. In one example, the relative bandwidth of a synthesizer using a λ / 4 line is about 8%.

[0137] In the LMBA as in Embodiment 4, the synthesizer 20 uses the signal S6 to modulate the loads of the amplifiers 10 and 11, combines the signals S3, S4, and S6, and outputs the combined signal as the output signal So. Thereby, widening of the operating bandwidth can be achieved. For example, the relative bandwidth of a 90° coupler is at most 120% in a commercially available 90° hybrid coupler.

[0138] In the LMBA, the input bias voltage of amplifier 10 and the input bias voltage of amplifier 11 can be made substantially the same. Therefore, the amplifier circuit 106 can be miniaturized by using the amplifier circuits of Embodiments 1 to 3 for the amplifier circuit including amplifier 10 and amplifier 11.

[0139] The DC path 29 directly connects the node N3 of amplifier 10 and the output node of the control amplifier 21 via the synthesizer 20. Only one node N6 (the fourth node) for supplying the bias voltage to amplifier 10 and the control amplifier 21 is provided in the DC path 29. Thus, the pads 15 and the bias circuit 14 for applying the output bias voltage to amplifier 10 and the control amplifier 21 can be one each. Therefore, the amplifier circuit 106 can be miniaturized.

[0140] The DC path 29 may also directly connect the node N3 and the node N4 to the output node of the control amplifier 21 via the synthesizer 20. Only one node N6 for supplying the bias voltage to amplifier 10, amplifier 11, and the control amplifier 21 may be provided in the DC path 29. Thus, the pads 15 and the bias circuit 14 for applying the output bias voltage to amplifier 10, amplifier 11, and the control amplifier 21 can be one each. Therefore, the amplifier circuit 106 can be miniaturized.

[0141] The embodiments disclosed herein should be considered illustrative in all respects and not restrictive. The scope of the present disclosure is shown not by the above description but by the claims, and is intended to include all modifications within the meaning and scope equivalent to the claims.

Claims

1. An amplifier circuit, comprising: a distributor, distributing an input signal into a first signal and a second signal; a first amplifier having a first node for inputting the first signal, amplifying the first signal inputted to the first node, and outputting the amplified first signal as a third signal; a second amplifier having a second node for inputting the second signal, amplifying the second signal inputted to the second node, and outputting the amplified second signal as a fourth signal; a path, connecting the first node and the second node in direct current via the distributor; as well as a synthesizer, synthesizing the third signal and the fourth signal, A third node for supplying a bias voltage to the first amplifier and the second amplifier is provided at only one location in the path.

2. The amplifier circuit according to claim 1, comprising: a pad supplied with the bias voltage; and The bias circuit connects the pad to the third node in a direct current manner to suppress leakage of the first signal and the second signal to the pad.

3. The amplifier circuit according to claim 1 or 2, wherein: The distributor includes a branch line coupler, which has: a first end for inputting the input signal; a second end for outputting the first signal; a third end, located diagonally opposite the first end, for outputting the second signal; and a fourth end, located diagonally opposite the second end, forming a terminal at a reference potential.

4. The amplifier circuit according to claim 3, comprising: a capacitor, a first end of the capacitor being connected to the fourth end of the branch line coupler; and A resistor, wherein a first end of the resistor is connected to the second end of the capacitor, and a second end of the resistor is connected to the reference potential.

5. An amplifier circuit comprising: a distributor, distributing an input signal into a first signal and a second signal; a first amplifier having a first node for inputting the first signal, amplifying the first signal inputted to the first node, and outputting the amplified first signal as a third signal; a second amplifier having a second node for inputting the second signal, amplifying the second signal inputted to the second node, and outputting the amplified second signal as a fourth signal; a synthesizer, synthesizing the third signal and the fourth signal; A single pad, supplied with a bias voltage; a first bias circuit, connecting the single pad to the first node in direct current to suppress leakage of the first signal to the single pad; as well as The second bias circuit connects the single pad to the second node in a direct current manner to suppress leakage of the second signal to the single pad.

6. An amplifier circuit comprising: a distributor, distributing an input signal into a first signal and a second signal; a first amplifier having a first node for inputting the first signal, amplifying the first signal inputted to the first node, and outputting the amplified first signal as a third signal; a second amplifier having a second node for inputting the second signal, amplifying the second signal inputted to the second node, and outputting the amplified second signal as a fourth signal; a synthesizer, synthesizing the third signal and the fourth signal; A single pad, supplied with a bias voltage; a first bias circuit, connecting the single pad to the first node in direct current to suppress leakage of the first signal to the single pad; as well as The second bias circuit connects the first node and the second node in direct current, and suppresses leakage of the first signal to the second node and leakage of the second signal to the first node.

7. The amplifier circuit according to claim 5 or 6, wherein: A first end of the distributor that outputs the first signal and a second end of the distributor that outputs the second signal are connected in direct current without passing through the distributor.

8. The amplifier circuit according to claim 5 or 6, wherein: A first end of the distributor outputting the first signal and a second end of the distributor outputting the second signal are connected in direct current via the distributor. The amplifier circuit has: a first capacitor, wherein a first end of the first capacitor is connected to the distributor, and a second end of the first capacitor is connected to the first node; as well as A second capacitor, wherein a first end of the second capacitor is connected to the distributor, and a second end of the second capacitor is connected to the second node.

9. The amplifier circuit according to claim 1, comprising: another distributor that distributes the high-frequency signal into the input signal and a fifth signal; and controlling the amplifier to amplify the fifth signal and output the amplified fifth signal as a sixth signal, The synthesizer modulates the loads of the first amplifier and the second amplifier using the sixth signal, synthesizes the third signal, the fourth signal, and the sixth signal, and outputs the synthesized signal as an output signal.

10. The amplifier circuit according to claim 9, A direct current path is provided, wherein the direct current path connects the output node of the first amplifier and the output node of the control amplifier in direct current via the combiner, A fourth node for supplying a bias voltage to the first amplifier and the control amplifier is provided at only one location in the DC path.

11. The amplifier circuit according to claim 5, comprising: another distributor that distributes the high-frequency signal into the input signal and a fifth signal; and controlling the amplifier to amplify the fifth signal and output the amplified fifth signal as a sixth signal, The synthesizer modulates the loads of the first amplifier and the second amplifier using the sixth signal, synthesizes the third signal, the fourth signal, and the sixth signal, and outputs the synthesized signal as an output signal.

12. The amplifier circuit according to claim 11, A direct current path is provided, wherein the direct current path connects the output node of the first amplifier and the output node of the control amplifier in direct current via the combiner, A fourth node for supplying a bias voltage to the first amplifier and the control amplifier is provided at only one location in the DC path.

13. The amplifier circuit according to claim 6, comprising: another distributor that distributes the high-frequency signal into the input signal and a fifth signal; and controlling the amplifier to amplify the fifth signal and output the amplified fifth signal as a sixth signal, The synthesizer modulates the loads of the first amplifier and the second amplifier using the sixth signal, synthesizes the third signal, the fourth signal, and the sixth signal, and outputs the synthesized signal as an output signal.

14. The amplifier circuit according to claim 13, A direct current path is provided, wherein the direct current path connects the output node of the first amplifier and the output node of the control amplifier in direct current via the combiner, A fourth node for supplying a bias voltage to the first amplifier and the control amplifier is provided at only one location in the DC path.

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