Array substrate and display device

Abstract

An array substrate and a display device. The array substrate comprises a substrate, a transistor, a data line and a first electrode; at least one transistor comprises an active layer and a gate electrode, the active layer comprises a channel region, a first region and a second region, and the channel region overlaps with the gate electrode in the orthographic projection of the substrate; the array substrate further comprises a gate insulating layer, the gate insulating layer is located on the side of the active layer away from the substrate, and the part of the surface of the gate insulating layer close to the substrate is in contact with the part of the surface of the active layer away from the substrate; the gate insulating layer has a plurality of via holes, at least one data line is electrically connected to the first region through one via hole, and at least one first electrode is electrically connected to the second region through another via hole; the via hole has oppositely arranged top and bottom ends, and the bottom end is closer to the active layer than the top end; the bottom end is between the minimum interval and the boundary of the channel region in the orthographic projection of the substrate, and the minimum interval is greater than 2.5 microns, which can solve the problem of unstable performance of the existing transistor.

Description

Technical Field

[0001] This article relates to, but is not limited to, the field of display technology, and in particular to an array substrate and a display device. Background Technology

[0002] Liquid crystal displays (LCDs) are a common type of display. An LCD uses two polarizing materials with a liquid crystal solution (liquid crystal) between them. When a voltage is applied to the two polarizing materials, the liquid crystal deflects. By controlling the applied voltage, the degree of liquid crystal deflection can be adjusted, thus controlling the brightness and display of the screen. Currently, LCDs are being developed towards being lighter, thinner, shorter, and smaller.

[0003] Currently, existing LCD screens suffer from unstable transistor performance, leading to a decline in display quality. Summary of the Invention

[0004] This disclosure provides an array substrate and a display device that can solve the problems of unstable transistor performance and degraded display quality in existing display devices.

[0005] On one hand, this disclosure provides an array substrate, including a substrate, at least one transistor disposed on the substrate, at least one data line disposed on the substrate, and at least one first electrode disposed on the substrate; the at least one transistor includes an active layer and a gate, the active layer includes a channel region and a first region and a second region located on opposite sides of the channel region, the channel region and the gate overlapping in the orthographic projection on the substrate;

[0006] In a plane perpendicular to the array substrate, the array substrate further includes a gate insulating layer, the gate insulating layer being located on the side of the active layer away from the substrate, and a portion of the surface of the gate insulating layer near the substrate being in contact with a portion of the surface of the active layer away from the substrate;

[0007] The gate insulating layer has a plurality of vias, and the at least one data line is electrically connected to the first region via one of the vias, and the at least one first electrode is electrically connected to the second region via another of the vias; the vias have a top end and a bottom end disposed opposite to each other, and the bottom end is closer to the active layer than the top end; there is a minimum gap between the bottom end and the boundary between the orthographic projection of the substrate and the orthographic projection of the channel region on the substrate, the minimum gap being greater than 2.5 micrometers.

[0008] In some exemplary embodiments, the diameter of the bottom end of the via with the minimum spacing is greater than or equal to 1.5 micrometers and less than or equal to 2.0 micrometers.

[0009] In some exemplary embodiments, the aperture of the top end of the via with the minimum spacing is greater than or equal to 1.5 micrometers and less than or equal to 2.0 micrometers, and the aperture of the top end of the same via is greater than the aperture of the bottom end.

[0010] In some exemplary embodiments, the minimum interval is greater than or equal to 3.0 micrometers and less than or equal to 5.0 micrometers.

[0011] In some exemplary embodiments, in a plane perpendicular to the array substrate, the array substrate further includes a first conductive layer and a second conductive layer; the first conductive layer is located on the side of the active layer closer to the substrate, and the second conductive layer is located on the side of the active layer away from the substrate; the first conductive layer includes the at least one data line, and the second conductive layer includes at least one gate.

[0012] In some exemplary embodiments, the second conductive layer further includes at least one pixel connection electrode, at least a portion of which is located within the via and is in contact with the active layer; a portion of the at least one first electrode is electrically connected to the pixel connection electrode.

[0013] In some exemplary embodiments, in a plane perpendicular to the array substrate, the array substrate further includes a transition layer located on the side of the second conductive layer away from the substrate; the transition layer includes at least one pixel connection electrode, at least a portion of the at least one pixel connection electrode being located within the via and the at least a portion being in contact with the active layer; a portion of the at least one first electrode is electrically connected to the pixel connection electrode.

[0014] In some exemplary embodiments, the second conductive layer further includes at least one data connection electrode, a portion of which is located within the via and contacts a portion of the surface of the active layer away from the substrate; the at least one data connection electrode contacts a portion of the surface of the at least one data line away from the substrate.

[0015] In some exemplary embodiments, the at least one data line includes a first top surface and a first bottom surface disposed opposite to each other, and a first side surface connecting the first top surface and the first bottom surface; the first top surface is farther away from the substrate than the first bottom surface; the data connection electrode is in contact with the first top surface and also in contact with the first side surface.

[0016] In some exemplary embodiments, the first region includes a second top surface and a second bottom surface disposed opposite to each other, and a second side surface connecting the second top surface and the second bottom surface; the second top surface is farther away from the substrate than the second bottom surface; the data connection electrode is in contact with the second top surface and also in contact with the second side surface.

[0017] In some exemplary embodiments, the array substrate further includes at least one gate line, the gate and the gate line are in the same layer and are an integral structure interconnected; the at least one gate line extends along a first direction and the at least one data line extends along a second direction, wherein the first direction and the second direction intersect.

[0018] In some exemplary embodiments, the gate line includes a first extension and a second extension connected to each other; the first extension extends along a first direction, the second extension includes a first end and a second end disposed opposite to each other, the first end of the second extension is connected to the first extension, and the second end of the second extension extends along a second direction; wherein a portion of the second extension serves as the gate.

[0019] In some exemplary embodiments, the dimension of the second extension in the orthographic projection onto the substrate along the second direction is greater than 0 micrometers and equal to or less than 5.0 micrometers.

[0020] In some exemplary embodiments, the gate line further includes a third extension; the third extension includes a first end and a second end disposed opposite to each other, the first end of the third extension is connected to the first extension, and the second end of the third extension extends in the opposite direction to the second direction; wherein the size of the second extension in the orthographic projection on the substrate along the second direction is greater than 0 micrometers and equal to or less than 5.0 micrometers, and the size of the third extension in the orthographic projection on the substrate along the second direction is greater than 0 micrometers and equal to or less than 5.0 micrometers.

[0021] In some exemplary embodiments, the gate line is a straight line extending along the first direction.

[0022] On the other hand, this disclosure provides a display device including an array substrate, a counter substrate, and a liquid crystal layer as described in any of the above embodiments; the array substrate and the counter substrate are disposed opposite to each other, and the liquid crystal layer is located between the array substrate and the counter substrate.

[0023] Other features and advantages of this disclosure will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing the disclosure. Other advantages of this disclosure may be realized and obtained by means of the methods described in the description and the accompanying drawings. Attached Figure Description

[0024] The accompanying drawings are used to provide an understanding of the technical solutions of this disclosure and form part of the specification. They are used together with the embodiments of this disclosure to explain the technical solutions of this disclosure and do not constitute a limitation on the technical solutions of this disclosure.

[0025] Figure 1 This is a partial cross-sectional schematic diagram of an array substrate;

[0026] Figure 2 The current-voltage test curves of the transistor under different voltage differences;

[0027] Figure 3 This is a front view schematic diagram of an array substrate according to an embodiment of the present disclosure;

[0028] Figure 4A This is a partial top view of an array substrate according to an embodiment of the present disclosure;

[0029] Figure 4B This is a partial cross-sectional schematic diagram of an array substrate according to an embodiment of the present disclosure;

[0030] Figure 5A This is a planar schematic diagram of an array substrate after the first conductive layer pattern has been formed according to an embodiment of the present disclosure;

[0031] Figure 5B This is a cross-sectional schematic diagram of an array substrate after the first conductive layer pattern has been formed according to an embodiment of the present disclosure;

[0032] Figure 6A This is a planar schematic diagram of an array substrate after a semiconductor layer pattern has been formed, according to an embodiment of the present disclosure.

[0033] Figure 6B This is a cross-sectional view of an array substrate after a semiconductor layer pattern has been formed, according to an embodiment of the present disclosure.

[0034] Figure 7A This is a planar schematic diagram of an embodiment of the present disclosure after the formation of the initial pattern of the second insulating layer on the array substrate;

[0035] Figure 7B This is a schematic cross-sectional view of an array substrate after the initial pattern of the second insulating layer has been formed, according to an embodiment of the present disclosure.

[0036] Figure 8A This is a planar schematic diagram of an embodiment of the present disclosure after the formation of the second conductive layer pattern on the array substrate;

[0037] Figure 8B This is a cross-sectional schematic diagram of an array substrate after the second conductive layer pattern has been formed according to an embodiment of the present disclosure;

[0038] Figure 9A This is a planar schematic diagram of an embodiment of the present disclosure after the formation of a fourth insulating layer pattern on the array substrate;

[0039] Figure 9B This is a cross-sectional schematic diagram of an array substrate after a fourth insulating layer pattern has been formed, according to an embodiment of the present disclosure.

[0040] Figure 10A This is a planar schematic diagram of an array substrate after the third conductive layer pattern has been formed according to an embodiment of the present disclosure;

[0041] Figure 10B This is a cross-sectional schematic diagram of an array substrate after the formation of the third conductive layer pattern according to an embodiment of the present disclosure;

[0042] Figure 11A This is a planar schematic diagram of an embodiment of the present disclosure after the formation of the fifth insulating layer pattern on the array substrate;

[0043] Figure 11B This is a schematic cross-sectional view of an array substrate after the fifth insulating layer pattern has been formed according to an embodiment of the present disclosure;

[0044] Figure 12A This is a planar schematic diagram of an embodiment of the present disclosure after the formation of the fourth conductive layer pattern on the array substrate;

[0045] Figure 12B This is a cross-sectional schematic diagram of an array substrate after the fourth conductive layer pattern has been formed according to an embodiment of the present disclosure;

[0046] Figure 13A This is a partial top view of an array substrate according to another embodiment of the present disclosure;

[0047] Figure 13B This is a partial cross-sectional schematic diagram of an array substrate according to another embodiment of the present disclosure;

[0048] Figure 14A This is a partial top view of an array substrate according to yet another embodiment of the present disclosure;

[0049] Figure 14B This is a partial cross-sectional schematic diagram of an array substrate according to yet another embodiment of the present disclosure;

[0050] Figure 15A This is a plan view of the array substrate after the second insulating layer pattern has been formed, according to another embodiment of the present disclosure;

[0051] Figure 15B This is a cross-sectional schematic diagram of the array substrate after the second insulating layer pattern has been formed, according to another embodiment of this disclosure;

[0052] Figure 16A This is a planar schematic diagram of the array substrate after the second conductive layer pattern has been formed, according to another embodiment of this disclosure;

[0053] Figure 16B This is a cross-sectional schematic diagram of an array substrate after the formation of the second conductive layer pattern according to another embodiment of the present disclosure;

[0054] Figure 17A This is a planar schematic diagram of the array substrate after the third conductive layer pattern has been formed, according to another embodiment of this disclosure;

[0055] Figure 17B This is a cross-sectional schematic diagram of an array substrate after the formation of a third conductive layer pattern according to another embodiment of the present disclosure;

[0056] Figure 18A This is a plan view of the array substrate after the fourth insulating layer pattern has been formed according to another embodiment of the present disclosure;

[0057] Figure 18B This is a cross-sectional schematic diagram of the array substrate after the fourth insulating layer pattern has been formed, according to another embodiment of this disclosure;

[0058] Figure 19A This is a planar schematic diagram of the array substrate after the fifth insulating layer pattern has been formed, according to yet another embodiment of this disclosure;

[0059] Figure 19B This is a cross-sectional schematic diagram of the array substrate after the fifth insulating layer pattern has been formed according to another embodiment of this disclosure;

[0060] Figure 20A This is a planar schematic diagram of the array substrate after the fourth conductive layer pattern has been formed, according to another embodiment of this disclosure;

[0061] Figure 20B This is a cross-sectional schematic diagram of an array substrate after the fourth conductive layer pattern has been formed in yet another embodiment of the present disclosure;

[0062] Figure 21A This is a partial top view of an array substrate according to another embodiment of the present disclosure;

[0063] Figure 21B This is a partial cross-sectional schematic diagram of an array substrate according to another embodiment of the present disclosure;

[0064] Figure 22A This is a plan view of the array substrate after the third insulating layer pattern has been formed according to another embodiment of the present disclosure;

[0065] Figure 22B This is a cross-sectional schematic diagram of the array substrate after the third insulating layer pattern has been formed according to another embodiment of the present disclosure;

[0066] Figure 23A This is a planar schematic diagram of the array substrate after the transition layer pattern has been formed according to another embodiment of the present disclosure;

[0067] Figure 23B This is a cross-sectional view of the array substrate after the transition layer pattern has been formed according to another embodiment of the present disclosure;

[0068] Figure 24AThis is a planar schematic diagram of the array substrate after the third conductive layer pattern has been formed according to another embodiment of the present disclosure;

[0069] Figure 24B This is a cross-sectional schematic diagram of the array substrate after the third conductive layer pattern has been formed according to another embodiment of the present disclosure;

[0070] Figure 25A This is a plan view of the array substrate after the fifth insulating layer pattern has been formed according to another embodiment of the present disclosure;

[0071] Figure 25B This is a cross-sectional schematic diagram of the array substrate after the fifth insulating layer pattern has been formed according to another embodiment of the present disclosure;

[0072] Figure 26A This is a planar schematic diagram of the array substrate after the fourth conductive layer pattern has been formed according to another embodiment of the present disclosure;

[0073] Figure 26B This is a cross-sectional schematic diagram of the array substrate after the fourth conductive layer pattern has been formed according to another embodiment of the present disclosure;

[0074] Figure 27 This is a cross-sectional schematic diagram of a display device according to an embodiment of the present disclosure.

[0075] Figure label:

[0076] 100 - Pixel electrode, D - Via, 200 - Channel area;

[0077] GL - gate line, GL-1 - first extension, GL-2 - second extension, GL-3 - third extension, DL - data line, DL-1 - first top surface, DL-2 - first bottom surface, DL-3 - first side surface, 10 - pixel electrode, 10-1 - connector, 10-2 - comb teeth, 11 - first insulating layer, 11-1 - first insulating film, 12 - second insulating layer, 12-1 - initial pattern of the second insulating layer, 13 - third insulating layer, 13-1 - third insulating film, 14 - fourth insulating layer, 14-1 - fourth insulating film, 15 - fifth insulating layer, 16 - active layer, 16-1 - first region, 1 6a-Second top surface, 16b-Second bottom surface, 16c-Second side surface, 16-2-Second region, 16-3-Channel region, 161-First extension segment, 162-Second extension segment, 163-Third extension segment, 164-Fourth extension segment, 17-Data connection electrode, 18-Gate, 19-Common electrode, 20-Transistor, 21-Pixel connection electrode, 30-Substrate; KK1-Bottom end, KK2-Top end, 40-Boundary, K1-First via, K2-Second via, K3-Third via, K4-Fourth via, K5-Fifth via, K6-Sixth via, K7-Seventh via, K8-Eighth via;

[0078] 1-Opposing substrate, 2-Liquid crystal layer, 3-Black matrix, 4-Color filter layer, 5-Array substrate. Detailed Implementation

[0079] The embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. The implementation can be carried out in many different forms. Those skilled in the art will readily understand that the methods and content can be changed to one or more forms without departing from the spirit and scope of this disclosure. Therefore, this disclosure should not be construed as limited to the content described in the following embodiments. Without conflict, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other.

[0080] In the accompanying drawings, the size of one or more constituent elements, the thickness of layers, or areas are sometimes exaggerated for clarity. Therefore, this disclosure is not necessarily limited to these dimensions, and the shapes and sizes of the components in the drawings do not reflect true proportions. Furthermore, the drawings schematically illustrate ideal examples, and this disclosure is not limited to the shapes or values ​​shown in the drawings.

[0081] The ordinal numbers such as "first," "second," and "third" in this disclosure are used to avoid confusion among the constituent elements, not to limit the quantity. "Multiple" in this disclosure includes two or more quantities.

[0082] In this disclosure, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification of the specification, and does not imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately changed depending on the direction in which the constituent elements are described. Therefore, the description is not limited to the terms used in the specification and may be appropriately replaced as appropriate.

[0083] In this disclosure, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linkage" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection or an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the meaning of these terms in this disclosure as appropriate.

[0084] In this disclosure, a transistor is a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain) and the source electrode (source electrode terminal, source region, or source), and current can flow through the drain electrode, the channel region, and the source electrode. In this disclosure, the channel region refers to the region through which current primarily flows.

[0085] In this disclosure, the first electrode can be the drain electrode and the second electrode can be the source electrode, or vice versa. In cases where transistors with opposite polarities are used or the current direction changes during circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Therefore, in this disclosure, the "source electrode" and the "drain electrode" can be interchanged.

[0086] In this disclosure, "electrical connection" includes the situation where constituent elements are connected together by a component having a certain electrical function. There are no particular limitations on the "component having a certain electrical function," as long as it enables the transmission and reception of electrical signals between the connected constituent elements. Examples of "component having a certain electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components having one or more functions.

[0087] In this disclosure, "parallel" refers to a state in which the angle formed by two straight lines is greater than or equal to -10° and less than 10°, and therefore can include a state in which the angle is greater than or equal to -5° and less than 5°. Furthermore, "perpendicular" refers to a state in which the angle formed by two straight lines is greater than or equal to 80° and less than 100°, and therefore can include a state in which the angle is greater than or equal to 85° and less than 95°.

[0088] In this disclosure, the terms "film" and "layer" can be interchanged. For example, sometimes "conductive layer" can be replaced with "conductive film". Similarly, sometimes "insulating film" can be replaced with "insulating layer".

[0089] In this disclosure, “about” means a value that is not strictly limited and allows for process and measurement errors.

[0090] Figure 1 This is a partial cross-sectional schematic diagram of an array substrate, such as... Figure 1 As shown, the pixel electrode 100 on the array substrate is electrically connected to the active layer of the transistor via via D, as... Figure 1As shown, the active layer includes a channel region 200. During the actual fabrication of the array substrate, etching the vias D generates a large number of free electrons. Some of these free electrons overcome the barrier and reach the channel region 200 of the active layer, causing the channel region 200 to become conductive. This results in a large on-state current in the transistors, affecting their performance and reducing the reliability of the display product. Figure 2 As shown, the current-voltage test curves of transistors under several different voltage differences are illustrated. Curve ① shows the current-voltage (IV) characteristic curve of the transistor under a voltage difference of 0.1V, curve ② shows the current-voltage (IV) characteristic curve of the transistor under a voltage difference of 5.1V, curve ③ shows the current-voltage (IV) characteristic curve of the transistor under a voltage difference of 10.1V, and curve ④ shows the current-voltage (IV) characteristic curve of the transistor under a voltage difference of 15.1V.

[0091] This disclosure provides an array substrate, the array substrate including a substrate, at least one transistor disposed on the substrate, at least one data line disposed on the substrate, and at least one first electrode disposed on the substrate; the at least one transistor includes an active layer and a gate, the active layer includes a channel region and a first region and a second region located on opposite sides of the channel region, the channel region and the gate overlapping in orthographic projection on the substrate;

[0092] In a plane perpendicular to the array substrate, the array substrate further includes a gate insulating layer, the gate insulating layer being located on the side of the active layer away from the substrate, and a portion of the surface of the gate insulating layer near the substrate being in contact with a portion of the surface of the active layer away from the substrate;

[0093] The gate insulating layer has a plurality of vias, and the at least one data line is electrically connected to the first region via one of the vias, and the at least one first electrode is electrically connected to the second region via another of the vias; the vias have a top end and a bottom end disposed opposite to each other, and the bottom end is closer to the active layer than the top end; there is a minimum gap between the bottom end and the boundary between the orthographic projection of the substrate and the orthographic projection of the channel region on the substrate, the minimum gap being greater than 2.5 micrometers.

[0094] The array substrate provided in this embodiment of the present disclosure, by defining the interval between the bottom end of the via and the boundary of the channel region of the active layer in the orthogonal projection of the substrate plane, can prevent free electrons generated during the etching process of the via from crossing the barrier and reaching the channel region of the active layer, can prevent the channel region from becoming conductive, can ensure the performance of the transistor, and can improve the reliability of the transistor.

[0095] Figure 3This is a front view schematic diagram of an array substrate according to an embodiment of the present disclosure. Figure 3 As shown, the array substrate may include a display area AA and a border area BB located on at least one side of the display area AA. The border area BB may include a first border area B1 located on one side of the display area AA and a second border area B2 located on the remaining sides of the display area AA. For example, the first border area B1 may include the bottom border of the array substrate, and the second border area B2 may include the top border, left border, and right border of the array substrate.

[0096] In one exemplary embodiment, such as Figure 3 As shown, the display area AA may include multiple data lines DL and multiple gate lines GL disposed on a substrate. The multiple gate lines GL may extend along a first direction X and be arranged sequentially along a second direction Y different from the first direction X. The multiple data lines DL may extend along the second direction Y and be arranged sequentially along the first direction X. The first direction X and the second direction Y may intersect; for example, the first direction X may be perpendicular to the second direction Y. The multiple data lines DL and the multiple gate lines GL may be located in different film layers; for example, the multiple data lines DL may be located on the side of the multiple gate lines GL closer to the substrate.

[0097] In one exemplary embodiment, such as Figure 3 As shown, multiple data lines DL and multiple gate lines GL can intersect to form multiple sub-pixel regions. The area defined by the intersection of adjacent data lines DL and adjacent gate lines GL can be a sub-pixel region. A sub-pixel region can include an open area and a non-open area surrounding the open area. The non-open area can be an area obscured by the black matrix of the opposing substrate of the array substrate, and the open area can be an area not obscured by the black matrix of the opposing substrate. All gate lines GL can be located within the non-open area. The array substrate of this disclosure embodiment can be used to implement a display function, and the open area of ​​each sub-pixel region can be configured for display. The non-open area can surround the open area and not be displayed. However, this disclosure embodiment is not limited in this respect. In some examples, the array substrate can be used to implement other functions.

[0098] In one exemplary embodiment, the display area AA may include a plurality of pixel units disposed on a substrate. At least one pixel unit may include three sub-pixels (e.g., a first sub-pixel, a second sub-pixel, and a third sub-pixel arranged sequentially along a first direction X). The three sub-pixels of the pixel unit may, for example, be a blue sub-pixel, a red sub-pixel, and a green sub-pixel, and the three sub-pixels may be arranged sequentially in the order of blue sub-pixel, red sub-pixel, and green sub-pixel. Figure 3 As shown, at least one sub-pixel may include: a pixel electrode 10 and a common electrode ( Figure 3(Not shown), and the orthographic projections of the pixel electrode 10 and the common electrode of the sub-pixel on the substrate may partially overlap. The common electrode of multiple sub-pixels in the display area AA can be a single structure. For example, the common electrode may be located on the side of the pixel electrode 10 closer to the substrate. The sub-pixel may also include a transistor 20. The transistor 20 may be located near the intersection of the data line DL and the gate line GL. The transistor 20 may include a gate, a first electrode, and a second electrode. The gate may be electrically connected to the gate line GL, the first electrode of the transistor 20 may be electrically connected to the data line DL, and the second electrode may be electrically connected to the pixel electrode 10 of a sub-pixel. The transistor 20 may be configured to provide the data signal transmitted by the data line DL to the pixel electrode 10 under the control of the gate line GL.

[0099] In one exemplary embodiment, the second bezel region B2 may include at least a gate driving circuit (e.g., including multiple cascaded shift registers), which may be electrically connected to multiple gate lines GL in the display region AA. The gate driving circuit may also include transistors. The structure of the transistors located in the second bezel region B2 may be the same as or different from the structure of the transistors located in the display region AA.

[0100] Liquid crystal display devices have various display modes, such as ADS (Advanced Super Dimension Switch) mode, TN (twisted nematic) mode, and VA (Vertical Alignment) mode. In ADS mode, both the pixel electrode and the common electrode are located on one side of the array substrate. In TN and VA modes, the pixel electrode and the common electrode are respectively located on opposite sides of the liquid crystal layer, with the pixel electrode on one side of the array substrate and the common electrode on the opposite substrate side.

[0101] The working principle of ADS mode is that liquid crystal molecules lie in a plane parallel to the glass substrate. Without voltage, light passing through the lower polarizer forms linearly polarized light parallel to the short axis of the liquid crystal molecules. The polarization direction cannot rotate, therefore it is absorbed by the upper polarizer and cannot escape. When a voltage is applied, a lateral electric field is formed on both sides of the liquid crystal, and the liquid crystal molecules align along the direction of the electric field. Light passing through the lower polarizer and the liquid crystal layer becomes elliptically polarized and can pass through the upper polarizer and escape.

[0102] The working principle of TN mode is as follows: In the absence of voltage, liquid crystal molecules are twisted and aligned at 90° under the action of the alignment film. Light passes through the lower polarizer and the liquid crystal molecules and is emitted from the upper polarizer. When voltage is applied, except for the liquid crystal near the upper and lower alignment films, most of the other liquid crystal molecules are vertically aligned. Light passing through the lower polarizer passes through the liquid crystal layer without deflection. Because it is parallel to the polarization axis of the upper polarizer, the light is absorbed and cannot be emitted.

[0103] The working principle of VA mode is that the liquid crystal molecules are aligned vertically to the glass substrate. When there is no voltage, the light passes through the lower polarizer and forms linearly polarized light parallel to the short axis of the liquid crystal molecules. The polarization direction cannot be rotated, so it is absorbed by the upper polarizer and cannot be emitted. When a voltage is applied, the liquid crystal molecules deflect along the direction of the electric field. The light passes through the lower polarizer and the liquid crystal layer and becomes elliptically polarized, allowing it to pass through the upper polarizer and be emitted.

[0104] The structure of the array substrate is described below using the ADS mode array substrate structure as an example.

[0105] Figure 4A This is a partial top view of an array substrate according to an embodiment of the present disclosure. Figure 4B This is a partial cross-sectional schematic diagram of an array substrate according to an embodiment of the present disclosure. Figure 4B for Figure 4A A cross-sectional view of the section marked AA. (See diagram below.) Figure 4A As shown, only one pixel unit is illustrated as an example, and one pixel unit may include three sub-pixels. The three sub-pixels can be a first sub-pixel, a second sub-pixel, and a third sub-pixel arranged sequentially along the first direction X. For example, the first sub-pixel can be a blue sub-pixel, the second sub-pixel can be a red sub-pixel, and the third sub-pixel can be a green sub-pixel. In this embodiment of the present disclosure, i can be a positive integer greater than or equal to 1, and j can be a positive integer greater than or equal to 2.

[0106] In this embodiment of the disclosure, the direction perpendicular to the array substrate is defined as the third direction Z, which can also be referred to as the thickness direction of the array substrate. Figure 4B As shown, in a plane perpendicular to the array substrate, the array substrate may include a substrate 30, and a first conductive layer, a semiconductor layer, a second conductive layer, a third conductive layer, and a fourth conductive layer sequentially disposed on one side of the substrate 30. The array substrate may also include a first insulating layer 11 located between the first conductive layer and the semiconductor layer, a second insulating layer 12 located between the semiconductor layer and the second conductive layer, a third insulating layer 13 and a fourth insulating layer 14 located between the second conductive layer and the third conductive layer, and a fifth insulating layer 15 located between the third conductive layer and the fourth conductive layer. In embodiments of this disclosure, the first insulating layer may also be referred to as a buffer layer, the second insulating layer may also be referred to as a gate insulating (GI) layer, the third insulating layer may also be referred to as a first passivation (PVX1) layer, the fourth insulating layer may also be referred to as a planarization (PLN) layer, and the fifth insulating layer may also be referred to as a second passivation (PVX2) layer.

[0107] like Figure 4BAs shown, the first conductive layer may include multiple data lines DL. In one example, the first conductive layer may also include multiple light-shielding blocks, which can prevent light from shining from one side of the substrate 30 onto the transistor 20, thereby improving the performance of the transistor. Setting the light-shielding blocks and data lines in the same layer structure can reduce the number of film layers in the array substrate, simplify the fabrication process of the array substrate, and reduce the manufacturing cost of the array substrate.

[0108] like Figure 4B As shown, the semiconductor layer may include an active layer 16 comprising multiple transistors 20. The active layer 16 may include a channel region 16-3, a first region 16-1, and a second region 16-2 located on opposite sides of the channel region 16-3. For example, during the fabrication of the array substrate, a portion of the active layer 16 may be locally conductiveized to form the first region 16-1 and the second region 16-2. The first region 16-1 of the active layer 16 can be used as the first electrode of a transistor, and the second region 16-2 of the active layer 16 can be used as the second electrode of a transistor. By locally conductiveizing the active layer to form the first and second electrodes of the transistors, the area of ​​the transistor gate can be reduced, avoiding the gate's influence on the aperture ratio of the display area, thus improving the aperture ratio of the display area.

[0109] like Figure 4B As shown, the second conductive layer may include a plurality of data connection electrodes 17, which can be electrically connected to the data line DL and the active layer 16 respectively via vias located in the insulating layer. The orthographic projections of the data connection electrodes 17 onto the plane of the array substrate and the orthographic projections of the data line DL onto the plane of the array substrate may at least partially overlap. The orthographic projections of the data connection electrodes 17 onto the plane of the array substrate and the orthographic projections of the active layer 16 onto the plane of the array substrate may also partially overlap.

[0110] like Figure 4B As shown, the data line DL may include a first top surface DL-1 and a first bottom surface DL-2 disposed opposite to each other, and a first side surface DL-3 connecting the first top surface DL-1 and the first bottom surface DL-2. The first top surface DL-1 is farther from the substrate 30 than the first bottom surface DL-2. Figure 4BAs shown, the orthographic projection of the data connection electrode 17 onto the plane of the array substrate and the orthographic projection of the first top surface DL-1 onto the plane of the array substrate can at least partially overlap, and the orthographic projection of the data connection electrode 17 onto the plane of the array substrate and the orthographic projection of the first side surface DL-3 onto the plane of the array substrate can at least partially overlap. That is, the data connection electrode 17 is in contact with both the first top surface DL-1 and the first side surface DL-3 of the data line DL. This increases the contact area between the data connection electrode 17 and the data line DL without increasing the line width of the data line DL, thereby improving the reliability of the electrical connection between the two.

[0111] like Figure 4B As shown, the first region 16-1 may include a second top surface 16a and a second bottom surface 16b disposed opposite each other, and a second side surface 16c connecting the second top surface 16a and the second bottom surface 16b. The second top surface 16a is farther from the substrate 30 than the second bottom surface 16b. Figure 4B As shown, the orthographic projection of the data connection electrode 17 onto the plane of the array substrate and the orthographic projection of the second top surface 16a onto the plane of the array substrate can at least partially overlap, and the orthographic projection of the data connection electrode 17 onto the plane of the array substrate and the orthographic projection of the second side surface 16c onto the plane of the array substrate can at least partially overlap. That is, the data connection electrode 17 is in contact with both the second top surface 16a and the second side surface 16c of the first region 16-1. This increases the contact area between the data connection electrode 17 and the first region 16-1 without increasing the size of the first region 16-1, thus improving the reliability of the electrical connection between the two. Figure 4B As shown, the second conductive layer may further include multiple gates 18 of multiple transistors 20. The orthographic projection of the gate 18 onto the plane of the array substrate and the orthographic projection of the channel region 16-3 onto the plane of the array substrate may at least partially overlap. The gate can block at least part of the light from affecting the channel region, thereby improving the performance of the transistor.

[0112] like Figure 4B As shown, the third conductive layer may include multiple common electrodes 19, and the fourth conductive layer may include multiple pixel electrodes 10. The orthographic projections of the common electrodes 19 onto the plane of the array substrate and the orthographic projections of the pixel electrodes 10 onto the plane of the array substrate may partially overlap. In this embodiment, a pixel electrode may also be referred to as a first electrode of a sub-pixel, and a common electrode may also be referred to as a second electrode of a sub-pixel. Alternatively, a pixel electrode may also be referred to as a second electrode of a sub-pixel, and a common electrode may also be referred to as a first electrode of a sub-pixel.

[0113] In one exemplary embodiment, such as Figure 4BAs shown, the second insulating layer 12 has multiple vias, and the data line DL is electrically connected to the first region 16-1 via one via, and the pixel electrode 10 is electrically connected to the second region 16-2 via another via. Each via has a top end KK2 and a bottom end KK1 disposed opposite to each other, and the bottom end KK1 is closer to the active layer 16 than the top end KK2. There is a minimum gap between the orthographic projection of the bottom end KK1 onto the plane of the array substrate and the orthographic projection boundary of the channel region 16-3 onto the plane of the array substrate, and the minimum gap is greater than 2.5 micrometers.

[0114] In an exemplary embodiment, there is a minimum gap between the orthographic projection of the bottom end KK1 onto the plane of the array substrate and the orthographic projection boundary of the channel region 16-3 onto the plane of the array substrate. The minimum gap is greater than or equal to 3.0 micrometers and less than or equal to 5.0 micrometers. In this embodiment, limiting the minimum gap to greater than 3.0 micrometers is to avoid transistor defects, and limiting the minimum gap to less than 5.0 micrometers is to ensure that the transistor ratio is not too large, thereby ensuring aperture ratio and transmittance, and improving the resolution of the display device.

[0115] In an exemplary embodiment, there is a minimum gap between the orthographic projection of the bottom end KK1 onto the plane of the array substrate and the orthographic projection boundary of the channel region 16-3 onto the plane of the array substrate. The aperture of the bottom end KK1 of the via with the minimum gap is greater than or equal to 1.5 micrometers and less than or equal to 2.0 micrometers.

[0116] In an exemplary embodiment, there is a minimum gap between the orthographic projection of the bottom end KK1 onto the plane of the array substrate and the orthographic projection boundary of the channel region 16-3 onto the plane of the array substrate. The aperture of the top end KK2 of the via with the minimum gap is greater than or equal to 1.5 micrometers and less than or equal to 2.0 micrometers, and the aperture of the top end KK2 of the same via is greater than the aperture of the bottom end KK1.

[0117] In one exemplary embodiment, the substrate 30 may be a transparent substrate. For example, the substrate 30 may be a rigid substrate or a flexible substrate. For example, the material of a rigid substrate may include, but is not limited to, one or more of glass and quartz. The material of a flexible substrate may include, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fibers. However, the embodiments disclosed herein are not limited in this respect.

[0118] In an exemplary embodiment, the materials of the first conductive layer, the second conductive layer, and the third conductive layer can be metallic materials, such as any one or more of molybdenum (Mo), aluminum (Al), copper (Cu), and titanium (Ti). Alternatively, the materials of the first conductive layer, the second conductive layer, and the third conductive layer can be alloys of metallic materials such as molybdenum (Mo), aluminum (Al), copper (Cu), and titanium (Ti), for example, aluminum-neodymium alloy (AlNd), molybdenum-niobium alloy (MoNb), or molybdenum-nickel-titanium alloy (MoNiTi). The first conductive layer, the second conductive layer, and the third conductive layer can be a single-layer structure or a multi-layer composite structure, such as Ti / Al / Ti, Mo / Nb / Cu, MoNiTi / Cu, MoNb / Cu / MoNiTi, or MoNiTi / Cu / MoNiTi, etc.

[0119] In an exemplary embodiment, the material of the fourth conductive layer can be a transparent conductive oxide material, which may include indium tin oxide (ITO) or indium zinc oxide (IZO). For example, the fourth conductive layer can be a single-layer structure or a multi-layer composite structure, such as ITO / Al / ITO.

[0120] In an exemplary embodiment, the materials of the first insulating layer 11, the second insulating layer 12, the third insulating layer 13, and the fifth insulating layer 15 can be inorganic materials. Examples of inorganic materials include silicon oxynitride (SiO2). x N y ) or silicon nitride (SiN) x ) or silicon oxide (SiO) x One or more of the following: ) The first insulating layer 11, the second insulating layer 12, the third insulating layer 13, and the fifth insulating layer 15 can be a single layer, a multi-layer, or a composite layer structure.

[0121] In an exemplary embodiment, the material of the fourth insulating layer 14 can be an organic material. Examples of organic materials include any one or more of epoxy resin, phenolic resin, urea-formaldehyde resin, melamine-formaldehyde resin, furan resin, silicone resin, polyester resin, polyamide resin, acrylic resin, polyurethane, vinyl resin, hydrocarbon resin, and polyether resin. The fourth insulating layer 14 can be a single layer, multiple layers, or a composite layer structure. In embodiments of this disclosure, providing an organic insulating layer can reduce crosstalk between the gate and the common electrode.

[0122] In an exemplary embodiment, the active layer 16 may include two or more sub-active layers. For example, the active layer may include two sub-active layers, or the active layer may include three sub-active layers, etc. The materials of each sub-active layer in the two or more sub-active layers may be the same or different.

[0123] In one exemplary embodiment, the semiconductor layer material may include one or more of the following: indium gallium zinc oxide (IGZO), zinc oxynitride (ZnON), indium zinc tin oxide (IZTO), indium gallium tin oxide (IGTO), indium gallium zinc tin oxide (IGZTO), and indium gallium zinc y oxide (IGZYO, where Y represents tin doping). In one example, the semiconductor layer material may be various materials such as amorphous silicon (a-Si), polycrystalline silicon (p-Si), hexathiophene, and polythiophene. The array substrate provided in this embodiment is suitable for transistors manufactured based on oxide technology, silicon technology, and organic technology.

[0124] The structure of the array substrate is illustrated below through an example of the fabrication process of the array substrate. The "patterning process" described in the embodiments of this disclosure includes processes such as photoresist coating, mask exposure, development, etching, and photoresist stripping for metallic, inorganic, or transparent conductive materials; and for organic materials, it includes processes such as organic material coating, mask exposure, and development. The deposition process can employ any one or more of sputtering, evaporation, and chemical vapor deposition; the coating process can employ any one or more of spraying, spin coating, and inkjet printing; and the etching process can employ any one or more of dry etching and wet etching. This disclosure does not limit the specific processes. A "thin film" refers to a thin film of a certain material fabricated on a substrate using deposition, coating, or other processes. If the "thin film" does not require a patterning process during the entire fabrication process, it can also be called a "layer." If the "thin film" requires a patterning process during the entire fabrication process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern." The "A and B co-layer structure" described in this disclosure refers to A and B being formed through the same patterning process.

[0125] The fabrication process of the array substrate may include the following steps, using only a partial segment of a transistor and a data line as an example:

[0126] (11) Forming a first conductive layer pattern. Forming the first conductive layer pattern may include: depositing a first conductive thin film on one side of the substrate 30, and patterning the first conductive thin film using a patterning process to form a first conductive layer pattern located on one side of the substrate 30. The first conductive layer may include multiple data lines DL, such as... Figure 5A and Figure 5B As shown, Figure 5B for Figure 5A Cross-sectional view along the BB direction.

[0127] like Figure 5A As shown, the orthographic projection of the data line DL onto the plane of the array substrate can be a line extending along the second direction Y.

[0128] (12) Forming a semiconductor layer pattern. Forming a semiconductor layer pattern may include: sequentially depositing a first insulating film 11-1 and a semiconductor film on one side of the substrate 30 on which the aforementioned pattern is formed; and patterning the semiconductor film using a patterning process to form a semiconductor layer pattern located on the side of the first insulating film 11-1 away from the substrate 30. The semiconductor layer may include the active layer 16 of a transistor, such as... Figure 6A and Figure 6B As shown, Figure 6B for Figure 6A Cross-sectional view along the BB direction.

[0129] like Figure 6A As shown, the active layer 16 may include a first extension segment 161, a second extension segment 162, a third extension segment 163, and a fourth extension segment 164 connected sequentially. The first extension segment 161 may include a first end and a second end disposed opposite to each other, and the second end of the first extension segment 161 may extend along a first direction X. The first end of the second extension segment 162 may be connected to the second end of the first extension segment 161, and the second end of the second extension segment 162 may extend along a direction different from both the first direction X and the second direction Y, extending in the opposite direction to the second direction Y. The first end of the third extension segment 163 may be connected to the second end of the second extension segment 162, and the second end of the third extension segment 163 extends along the first direction X. The first end of the fourth extension segment 164 may be connected to the second end of the third extension segment 163, and the second end of the fourth extension segment 164 may extend along a direction different from both the first direction X and the second direction Y, extending in the direction of extension of the second direction Y.

[0130] like Figure 6B As shown, forming the semiconductor layer pattern may further include using a mask to partially conductor-encode the active layer 16, so that portions of the active layer 16 respectively form a first region 16-1 and a second region 16-2. The first region 16-1 of the active layer 16 can be used as the first electrode of a transistor, and the second region 16-2 of the active layer 16 can be used as the second electrode of a transistor.

[0131] like Figure 6A As shown, the channel region 16-3 of the active layer 16 has a boundary 40 in the orthogonal projection onto the substrate. The boundary 40 can be irregular or other shapes.

[0132] (13) Forming an initial pattern for the second insulating layer. Forming an initial pattern for the second insulating layer may include: depositing a second insulating film on one side of the substrate 30 on which the aforementioned pattern is formed, and patterning the second insulating film using a patterning process to form an initial pattern 12-1 of the second insulating layer located on the side of the semiconductor layer away from the substrate 30 and a first insulating layer pattern located on the side away from the substrate 30, such as... Figure 7A and Figure 7B As shown, Figure 7B for Figure 7A Cross-sectional view along the BB direction.

[0133] like Figure 7A As shown, the initial pattern 12-1 of the second insulating layer may include multiple vias, and the multiple vias may include at least one first via K1. Both the first insulating film and the second insulating film within the first via K1 are etched away. The orthographic projection of the first via K1 onto the plane of the array substrate may at least partially overlap with the orthographic projection of the active layer 16 onto the plane of the array substrate and the orthographic projection of the data line DL onto the plane of the array substrate. The first via K1 exposes a portion of the surface of the active layer 16 away from the substrate 30, and also exposes a portion of the surface of the data line DL away from the substrate 30. The first via K1 is configured such that subsequently formed data connection electrodes are electrically connected to both the active layer 16 and the data line DL via the via, thereby electrically connecting the active layer 16 to the data line DL via the data connection electrodes.

[0134] In some exemplary embodiments, the first via K1 can be a circular hole, an elliptical hole, a rectangular hole, or a hexagonal hole, etc.

[0135] In some exemplary embodiments, such as Figure 7A As shown, there is a gap L1 between the orthographic projection of the bottom end KK1 of the first via K1 onto the plane of the array substrate and the boundary 40 of the orthographic projection of the channel region 16-3 onto the plane of the array substrate. The gap L1 can be greater than 2.5 micrometers. By limiting this gap L1, free electrons generated by etching the via can be prevented from crossing the barrier and reaching the channel region 16-3 of the active layer, thus preventing the channel region 16-3 from becoming conductive and improving the reliability of the transistor.

[0136] (14) Forming a second conductive layer pattern. Forming the second conductive layer pattern may include: depositing a second conductive film on one side of the substrate 30 on which the aforementioned pattern is formed, and patterning the second conductive film by a patterning process to form a second conductive layer pattern located on the side of the initial pattern 12-1 of the second insulating layer away from the substrate 30. The second conductive layer may include a plurality of data connection electrodes 17, a plurality of gate electrodes 18, and a plurality of gate lines GL, such as Figure 8A and Figure 8B As shown, Figure 8B for Figure 8A Cross-sectional view along the BB direction.

[0137] like Figure 8AAs shown, the orthographic projection of the data connection electrode 17 onto the plane of the array substrate can be rectangular. The orthographic projection of the data connection electrode 17 onto the plane of the array substrate and the orthographic projection of the first via K1 onto the plane of the array substrate may at least partially overlap. For example, the orthographic projection of the data connection electrode 17 onto the plane of the array substrate may include the orthographic projection of the first via K1 onto the plane of the array substrate. The data connection electrode 17 is electrically connected to the active layer 16 and the data line DL via the first via K1.

[0138] like Figure 8A As shown, the orthographic projection of the gate line GL onto the plane of the array substrate can be a straight line extending along the first direction X. The gate 18 and the gate line GL can be an integral structure connected to each other, that is, a portion of the gate line GL can serve as the gate 18. For example, the portion where the orthographic projection of the gate line GL onto the plane of the array substrate overlaps with the orthographic projection of the channel region of the active layer 16 onto the plane of the array substrate can serve as the gate 18.

[0139] (15) Forming a fourth insulating layer pattern. Forming the fourth insulating layer pattern may include: sequentially depositing a third insulating film and a fourth insulating film on one side of the substrate 30 on which the aforementioned pattern is formed, and patterning the fourth insulating film using a patterning process to form a third insulating layer pattern, a fourth insulating layer pattern, and a second insulating layer pattern located on the side of the second conductive layer away from the substrate 30, such as... Figure 9A and Figure 9B As shown, Figure 9B for Figure 9A Cross-sectional view along the BB direction.

[0140] like Figure 9A As shown, the fourth insulating layer 14 may include a plurality of vias, and the plurality of vias may include at least one second via K2. The fourth insulating film, the third insulating film, and the second insulating film within the second via K2 are all etched away, exposing a portion of the surface of the active layer 16 away from the substrate 30. The second via K2 is configured such that a subsequently formed pixel electrode is electrically connected to the active layer 16 via the via.

[0141] In some exemplary embodiments, the second via K2 can be a circular hole, an elliptical hole, a rectangular hole, or a hexagonal hole, etc.

[0142] In some exemplary embodiments, such as Figure 9AAs shown, there is a gap L2 between the orthographic projection of the bottom end KK1 of the second via K2 onto the plane of the array substrate and the boundary 40 of the orthographic projection of the channel region 16-3 onto the plane of the array substrate. The gap L2 can be greater than 2.5 micrometers. By limiting this gap L2, free electrons generated by etching the via can be prevented from crossing the barrier and reaching the channel region 16-3 of the active layer, thus preventing the channel region 16-3 from becoming conductive and improving the reliability of the transistor.

[0143] (16) Forming a third conductive layer pattern. Forming the third conductive layer pattern may include: depositing a third conductive film on one side of the substrate 30 on which the aforementioned pattern is formed, and patterning the third conductive film using a patterning process to form a third conductive layer pattern located on the side of the fourth insulating layer 14 away from the substrate 30. The third conductive layer may include multiple common electrodes 19, such as... Figure 10A and Figure 10B As shown, Figure 10B for Figure 10A Cross-sectional view along the BB direction.

[0144] like Figure 10A As shown, the orthographic projection of the common electrode 19 onto the plane of the array substrate can be a rectangle, etc.

[0145] (17) Forming a fifth insulating layer pattern. Forming a fifth insulating layer pattern may include: depositing a fifth insulating film on one side of the substrate 30 on which the aforementioned pattern is formed, and patterning the fifth insulating film using a patterning process to form a fifth insulating layer pattern located on the side of the third conductive layer away from the substrate 30, such as... Figure 11A and Figure 11B As shown, Figure 11B for Figure 11A Cross-sectional view along the BB direction.

[0146] like Figure 11A As shown, the fifth insulating layer 15 may include a plurality of vias, and the plurality of vias may include at least one third via K3. The orthographic projection of the third via K3 onto the plane of the array substrate may at least partially overlap with the orthographic projection of the second via K2 onto the plane of the array substrate. For example, the orthographic projection of the third via K3 onto the plane of the array substrate may include the orthographic projection of the second via K2 onto the plane of the array substrate. The third via K3 is configured such that the pixel electrode subsequently formed is electrically connected to the active layer 16 via the via.

[0147] In some exemplary embodiments, the third via K3 can be a circular hole, an elliptical hole, a rectangular hole, or a hexagonal hole, etc.

[0148] (18) Forming a fourth conductive layer pattern. Forming the fourth conductive layer pattern may include: depositing a fourth conductive film on one side of the substrate 30 on which the aforementioned pattern is formed, and patterning the fourth conductive film using a patterning process to form a fourth conductive layer pattern located on the side of the fifth insulating layer 15 away from the substrate 30. The fourth conductive layer may include multiple pixel electrodes 10, such as... Figure 12A and Figure 12B As shown, Figure 12B for Figure 12A Cross-sectional view along the BB direction.

[0149] like Figure 12A As shown, the pixel electrode 10 may include a connecting portion 10-1 and a plurality of comb portions 10-2. The main body of the connecting portion 10-1 may be rectangular in shape and extend along a first direction X. The comb portions 10-2 may be strip-shaped and extend along a second direction Y. The first end of the comb portion 10-2 may be connected to the connecting portion 10-1, and the second end of the comb portion 10-2 may extend along the second direction Y. The plurality of comb portions 10-2 may be arranged at intervals along the first direction X. For example, the plurality of comb portions 10-2 may be arranged at equal intervals along the first direction X.

[0150] like Figure 12A As shown, the orthographic projection of the pixel electrode 10 onto the plane of the array substrate and the orthographic projection of the common electrode 19 onto the plane of the array substrate may partially overlap.

[0151] like Figure 12B As shown, the pixel electrode 10 can be electrically connected to the active layer 16 via the third via K3 and the second via K2.

[0152] Figure 13A This is a partial top view of an array substrate according to another embodiment of the present disclosure. Figure 13B This is a partial cross-sectional schematic diagram of an array substrate according to another embodiment of the present disclosure. Figure 13B for Figure 13A A cross-sectional view along the CC direction. (See attached image.) Figure 13A , Figure 13B As shown, in a plane perpendicular to the array substrate, the array substrate may include a substrate 30, and a first conductive layer, a semiconductor layer, a second conductive layer, a third conductive layer, and a fourth conductive layer sequentially disposed on one side of the substrate 30. The array substrate may also include a first insulating layer 11 located between the first conductive layer and the semiconductor layer, a second insulating layer 12 located between the semiconductor layer and the second conductive layer, a third insulating layer 13 and a fourth insulating layer 14 located between the second conductive layer and the third conductive layer, and a fifth insulating layer 15 located between the third conductive layer and the fourth conductive layer. The main structure of the array substrate in this exemplary embodiment can be referred to the description of the foregoing embodiments, with the main difference being that... Figure 13AAs shown, the gate line GL may include a first extension GL-1, a second extension GL-2, and a third extension GL-3. The first extension GL-1 may be a straight line extending along a first direction X. The second extension GL-2 may include two oppositely positioned ends; the first end of the second extension GL-2 may be connected to the first extension GL-1, and the second end of the second extension GL-2 may extend along a second direction Y. The third extension GL-3 may include two oppositely positioned ends; the first end of the third extension GL-3 may be connected to the first extension GL-1, and the second end of the third extension GL-3 may extend in the opposite direction of the second direction Y. For example, the second extension GL-2 and the third extension GL-3 may be symmetrically arranged about the first extension GL-1.

[0153] In some possible exemplary embodiments, a portion of the second extension GL-2 may serve as the gate 18. The size of the orthographic projection of the second extension GL-2 onto the plane of the array substrate along the second direction Y may be greater than 0 micrometers and less than or equal to 5.0 micrometers. The size of the orthographic projection of the third extension GL-3 onto the plane of the array substrate along the second direction Y may be greater than 0 micrometers and less than or equal to 5.0 micrometers. For example, the size of the orthographic projection of the second extension GL-2 onto the plane of the array substrate along the second direction Y may be equal to the size of the orthographic projection of the third extension GL-3 onto the plane of the array substrate along the second direction Y. Alternatively, the size of the orthographic projection of the second extension GL-2 onto the plane of the array substrate along the second direction Y may be greater than the size of the orthographic projection of the third extension GL-3 onto the plane of the array substrate along the second direction Y. Alternatively, the size of the orthographic projection of the second extension GL-2 onto the plane of the array substrate along the second direction Y may be less than the size of the orthographic projection of the third extension GL-3 onto the plane of the array substrate along the second direction Y.

[0154] Figure 14A This is a partial top view of an array substrate according to yet another embodiment of the present disclosure. Figure 14B This is a partial cross-sectional schematic diagram of an array substrate according to yet another embodiment of the present disclosure. Figure 14B for Figure 14A A cross-sectional view along the DD direction. (See attached image.) Figure 14A , Figure 14BAs shown, the array substrate may include a substrate 30, and a first conductive layer, a semiconductor layer, a second conductive layer, a third conductive layer, and a fourth conductive layer sequentially disposed on one side of the substrate 30. The array substrate may further include a first insulating layer 11 located between the first conductive layer and the semiconductor layer, a second insulating layer 12 located between the semiconductor layer and the second conductive layer, a third insulating layer 13 and a fourth insulating layer 14 located between the second conductive layer and the third conductive layer, and a fifth insulating layer 15 located between the third conductive layer and the fourth conductive layer. The main structure of the array substrate in this exemplary embodiment can be referred to the description of the foregoing embodiments, with the main difference being that... Figure 14B As shown, the array substrate may further include multiple pixel connection electrodes 21. The pixel connection electrodes 21 may be located in the second conductive layer, and the pixel electrode 10 may be electrically connected to the active layer 16 via the pixel connection electrodes 21. By using the pixel connection electrodes 21, the aperture of the vias on the second insulating layer used to achieve the electrical connection between the pixel electrode 10 and the active layer 16 can be reduced. This can prevent free electrons generated by etching the vias from crossing the barrier and reaching the channel region 16-3 of the active layer, thus preventing the channel region 16-3 from becoming conductive and improving the reliability of the transistor.

[0155] The fabrication process of the array substrate may include the following steps, using only a partial segment of a transistor and a data line as an example:

[0156] (21) The first conductive layer pattern and the semiconductor layer pattern are formed sequentially. The preparation steps can be referred to the description of the foregoing embodiment, and will not be elaborated here.

[0157] (22) Forming a second insulating layer pattern. Forming the second insulating layer pattern may include: depositing a second insulating film on one side of the substrate 30 on which the aforementioned pattern is formed, and patterning the second insulating film using a patterning process to form a second insulating layer pattern on the side of the semiconductor layer away from the substrate 30 and a first insulating layer pattern on the side away from the substrate 30, such as... Figure 15A and Figure 15B As shown, Figure 15B for Figure 15A Cross-sectional view along the DD direction.

[0158] like Figure 15AAs shown, the second insulating layer 12 may include multiple vias, including at least one first via K1 and at least one fourth via K4. Both the first and second insulating films within the first via K1 are etched away, and the second insulating film within the fourth via K4 is also etched away. The orthographic projection of the first via K1 onto the plane of the array substrate may at least partially overlap with the orthographic projections of the active layer 16 and the data line DL onto the plane of the array substrate. The first via K1 exposes a portion of the surface of the active layer 16 away from the substrate 30, and also exposes a portion of the surface of the data line DL away from the substrate 30. The first via K1 is configured such that subsequently formed data connection electrodes are electrically connected to both the active layer 16 and the data line DL via the via, thereby electrically connecting the active layer 16 to the data line DL via the data connection electrodes. The orthographic projection of the fourth via K4 onto the plane of the array substrate and the orthographic projection of the active layer 16 onto the plane of the array substrate may at least partially overlap, and the fourth via K4 exposes a portion of the surface of the active layer 16 away from the substrate 30. The fourth via K4 is configured such that the pixel connection electrode formed subsequently is electrically connected to the active layer 16 through the via.

[0159] In some exemplary embodiments, the first via K1 can be a circular hole, an elliptical hole, a rectangular hole, or a hexagonal hole, etc.

[0160] In some exemplary embodiments, the aperture of the bottom end KK1 of the fourth via K4 can range from 1.5 micrometers to 2.0 micrometers. For example, the aperture of the bottom end KK1 of the fourth via K4 can be 1.6 micrometers, or the aperture of the bottom end KK1 of the fourth via K4 can be 1.8 micrometers, etc. The fourth via K4 can be a circular hole, an elliptical hole, a rectangular hole, or a hexagonal hole, etc.

[0161] In some exemplary embodiments, such as Figure 15A As shown, there is a gap L1 between the orthographic projection of the bottom end KK1 of the first via K1 onto the plane of the array substrate and the boundary 40 of the orthographic projection of the channel region 16-3 onto the plane of the array substrate. The gap L1 can be greater than 2.5 micrometers. By limiting this gap L1, free electrons generated by etching the via can be prevented from crossing the barrier and reaching the channel region 16-3 of the active layer, thus preventing the channel region 16-3 from becoming conductive and improving the reliability of the transistor.

[0162] In some exemplary embodiments, such as Figure 15AAs shown, there is a gap L4 between the orthographic projection of the bottom end KK1 of the fourth via K4 onto the plane of the array substrate and the boundary 40 of the orthographic projection of the channel region 16-3 onto the plane of the array substrate. The gap L4 can be greater than 2.5 micrometers. By limiting this gap L4, free electrons generated by etching the via can be prevented from crossing the barrier and reaching the channel region 16-3 of the active layer, thus preventing the channel region 16-3 from becoming conductive and improving the reliability of the transistor.

[0163] (23) Forming a second conductive layer pattern. Forming the second conductive layer pattern may include: depositing a second conductive film on one side of the substrate 30 on which the aforementioned pattern is formed, and patterning the second conductive film using a patterning process to form a second conductive layer pattern located on the side of the second insulating layer 12 away from the substrate 30. The second conductive layer may include multiple data connection electrodes 17, multiple gate electrodes 18, multiple gate lines GL, and multiple pixel connection electrodes 21, such as... Figure 16A and Figure 16B As shown, Figure 16B for Figure 16A A cross-sectional view along the DD direction. In this embodiment, the aperture of the fourth via K4 can be reduced by using the pixel connection electrode 21. Without changing the overall layout of the array substrate, the reduction in the aperture of the fourth via K4 increases the spacing between the fourth via K4 and the boundary of the channel region 16-3. This prevents free electrons generated by etching the fourth via from crossing the barrier and reaching the channel region 16-3 of the active layer, thus preventing the channel region 16-3 from becoming conductive and improving the reliability of the transistor.

[0164] like Figure 16A As shown, the gate line GL may include a first extension GL-1 and a second extension GL-2 connected to each other. The first extension GL-1 may be a straight line extending along a first direction X. The second extension GL-2 may include a first end and a second end disposed opposite to each other. The first end of the second extension GL-2 may be connected to the first extension GL-1, and the second end of the second extension GL-2 may extend along a second direction Y.

[0165] like Figure 16A As shown, the orthographic projection of the pixel connection electrode 21 onto the plane of the array substrate can be a rectangle, etc. The orthographic projection of the pixel connection electrode 21 onto the plane of the array substrate and the orthographic projection of the fourth via K4 onto the plane of the array substrate may at least partially overlap. For example, the orthographic projection of the pixel connection electrode 21 onto the plane of the array substrate may include the orthographic projection of the fourth via K4 onto the plane of the array substrate. The pixel connection electrode 21 can be electrically connected to the active layer 16 via the fourth via K4, and the pixel connection electrode 21 is configured to be electrically connected to a subsequently formed pixel electrode, which can be electrically connected to the active layer 16 via the pixel connection electrode 21.

[0166] (24) Forming a third conductive layer pattern. Forming the third conductive layer pattern may include: sequentially depositing a third insulating film 13-1, a fourth insulating film 14-1, and a third conductive film on one side of the substrate 30 on which the aforementioned pattern is formed; patterning the third conductive film using a patterning process to form a third conductive layer pattern located on the side of the fourth insulating film 14-1 away from the substrate 30; the third conductive layer may include a common electrode 19, such as... Figure 17A and Figure 17B As shown, Figure 17B for Figure 17A Cross-sectional view along the DD direction.

[0167] (25) Forming a fourth insulating layer pattern. Forming a fourth insulating layer pattern may include: patterning the fourth insulating film through a patterning process, so that the fourth insulating film 14-1 forms a fourth insulating layer 14 and the third insulating film 13-1 forms a third insulating layer 13, such as... Figure 18A and Figure 18B As shown, Figure 18B for Figure 18A Cross-sectional view along the DD direction.

[0168] like Figure 18A As shown, the fourth insulating layer 14 may include a plurality of vias, at least one of which is a fifth via K5. Both the fourth and third insulating films within the fifth via K5 are etched away, exposing at least a portion of the surface of the pixel connection electrode 21 on the side away from the substrate 30. The orthographic projection of the fifth via K5 onto the plane of the array substrate may at least partially overlap with the orthographic projection of the pixel connection electrode 21 onto the plane of the array substrate; for example, the orthographic projection of the fifth via K5 onto the plane of the array substrate may lie within the orthographic projection of the pixel connection electrode 21 onto the plane of the array substrate. The fifth via K5 is configured such that a subsequently formed pixel electrode is electrically connected to the active layer 16 via this via.

[0169] like Figure 18A As shown, the fifth via K5 can be a circular hole, an elliptical hole, a rectangular hole, or a hexagonal hole, etc.

[0170] (26) Forming a fifth insulating layer pattern. Forming a fifth insulating layer pattern may include: depositing a fifth insulating film on one side of the substrate 30 on which the aforementioned pattern is formed, and patterning the fifth insulating film using a patterning process to form a fifth insulating layer pattern located on the side of the third conductive layer away from the substrate 30, such as... Figure 19A and Figure 19B As shown, Figure 19B for Figure 19A Cross-sectional view along the DD direction.

[0171] like Figure 19A As shown, the fifth insulating layer 15 may include a plurality of vias, at least one of which is a sixth via K6, within which the fifth insulating film is etched away. The orthographic projection of the sixth via K6 onto the plane of the array substrate at least partially overlaps with the orthographic projection of the fifth via K5 onto the plane of the array substrate. For example, the orthographic projection of the sixth via K6 onto the plane of the array substrate may include the orthographic projection of the fifth via K5 onto the plane of the array substrate, and the sixth via K6 is connected to the fifth via K5, exposing at least a portion of the surface of the pixel connection electrode 21 on the side away from the substrate 30. The sixth via K6 is configured such that a subsequently formed pixel electrode is electrically connected to the active layer 16 via this via.

[0172] (27) Forming a fourth conductive layer pattern. Forming the fourth conductive layer pattern may include: depositing a fourth conductive film on one side of the substrate 30 on which the aforementioned pattern is formed, and patterning the fourth conductive film using a patterning process to form a fourth conductive layer pattern located on the side of the fifth insulating layer 15 away from the substrate 30. The fourth conductive layer may include multiple pixel electrodes 10, such as... Figure 20A and Figure 20B As shown, Figure 20B for Figure 20A Cross-sectional view along the DD direction.

[0173] like Figure 20A As shown, the pixel electrode 10 may include a connecting portion 10-1 and a plurality of comb portions 10-2. The main body of the connecting portion 10-1 may be rectangular in shape and extend along a first direction X. The comb portions 10-2 may be strip-shaped and extend along a second direction Y. The first end of the comb portion 10-2 may be connected to the connecting portion 10-1, and the second end of the comb portion 10-2 may extend along the second direction Y. The plurality of comb portions 10-2 may be arranged at intervals along the first direction X. For example, the plurality of comb portions 10-2 may be arranged at equal intervals along the first direction X.

[0174] Figure 21A This is a partial top view of an array substrate according to another embodiment of the present disclosure. Figure 21B This is a partial cross-sectional schematic diagram of an array substrate according to another embodiment of the present disclosure. Figure 21B for Figure 21A A cross-sectional view along the EE direction. (See attached image.) Figure 21A , Figure 21BAs shown, the array substrate may include a substrate 30 and a first conductive layer, a semiconductor layer, a second conductive layer, a transition layer, a third conductive layer, and a fourth conductive layer sequentially disposed on one side of the substrate 30. The array substrate may also include a first insulating layer 11 located between the first conductive layer and the semiconductor layer, a second insulating layer 12 located between the semiconductor layer and the second conductive layer, a third insulating layer 13 located between the second conductive layer and the transition layer, a fourth insulating layer 14 located between the transition layer and the third conductive layer, and a fifth insulating layer 15 located between the third conductive layer and the fourth conductive layer. The main structure of the array substrate in this exemplary embodiment can be referred to the description of the foregoing embodiments, with the main difference being that... Figure 21B As shown, the array substrate may further include multiple pixel connection electrodes 21. The pixel connection electrodes 21 may be located in the transition layer, and the pixel electrode 10 may be electrically connected to the active layer 16 via the pixel connection electrodes 21. By using the pixel connection electrodes 21, the aperture of the vias on the second insulating layer used to achieve the electrical connection between the pixel electrode 10 and the active layer 16 can be reduced. This can prevent free electrons generated by etching the vias from crossing the barrier and reaching the channel region 16-3 of the active layer, thus preventing the channel region 16-3 from becoming conductive and improving the reliability of the transistor.

[0175] The fabrication process of the array substrate may include the following steps, using only a partial segment of a transistor and a data line as an example:

[0176] (31) The first conductive layer pattern, the semiconductor layer pattern, the initial pattern of the second insulating layer and the second conductive layer pattern are formed sequentially. The preparation steps can be referred to the description of the foregoing embodiments, and will not be elaborated here.

[0177] (32) Forming a third insulating layer pattern. Forming the third insulating layer pattern may include: depositing a third insulating film on one side of the substrate 30 on which the aforementioned pattern is formed, and patterning the third insulating film by a patterning process to form a third insulating layer pattern located on the side of the second conductive layer away from the substrate 30, and a second insulating layer pattern located on the side of the semiconductor layer away from the substrate 30, such as... Figure 22A and Figure 22B As shown, Figure 22B for Figure 22A Cross-sectional view along the EE direction.

[0178] like Figure 22AAs shown, the third insulating layer 13 may include a plurality of vias, at least one of which is a seventh via K7. The orthographic projection of the seventh via K7 onto the plane of the array substrate may at least partially overlap with the orthographic projection of the active layer 16 onto the plane of the array substrate. For example, the orthographic projection of the seventh via K7 onto the plane of the array substrate may lie within the orthographic projection of the active layer 16 onto the plane of the array substrate. Both the third insulating film and the second insulating film within the seventh via K7 are etched away, exposing at least a portion of the surface of the active layer 16 on the side away from the substrate 30. The seventh via K7 is configured such that subsequently formed pixel connection electrodes are electrically connected to the active layer 16 via this via.

[0179] In some exemplary embodiments, the seventh via K7 can be a circular hole, an elliptical hole, a rectangular hole, or a hexagonal hole, etc.

[0180] In some exemplary embodiments, such as Figure 22A As shown, there is a gap L7 between the orthographic projection of the bottom end KK1 of the seventh via K7 onto the plane of the array substrate and the boundary 40 of the orthographic projection of the channel region 16-3 onto the plane of the array substrate. The gap L7 can be greater than 2.5 micrometers. By limiting this gap L7, free electrons generated by etching the via can be prevented from crossing the barrier and reaching the channel region 16-3 of the active layer, thus preventing the channel region 16-3 from becoming conductive and improving the reliability of the transistor.

[0181] (33) Forming a transition layer pattern. Forming the transition layer pattern may include: depositing a conductive thin film on one side of the substrate 30 on which the aforementioned pattern is formed, and patterning the conductive thin film using a patterning process to form a transition layer pattern located on the side of the third insulating layer 13 away from the substrate 30. The transition layer may include multiple pixel connection electrodes 21, such as... Figure 23A and Figure 23B As shown, Figure 23B for Figure 23A Cross-sectional view along the EE direction.

[0182] like Figure 23A As shown, the orthographic projection of the pixel connection electrode 21 onto the plane of the array substrate can be rectangular. The orthographic projection of the pixel connection electrode 21 onto the plane of the array substrate and the orthographic projection of the seventh via K7 onto the plane of the array substrate can at least partially overlap. For example, the orthographic projection of the pixel connection electrode 21 onto the plane of the array substrate may include the orthographic projection of the seventh via K7 onto the plane of the array substrate. The pixel connection electrode 21 can be electrically connected to the active layer 16 via the seventh via K7.

[0183] In an exemplary embodiment, the transition layer can be made of a metallic material, such as any one or more of molybdenum (Mo), aluminum (Al), copper (Cu), and titanium (Ti). Alternatively, the transition layer can be an alloy of molybdenum (Mo), aluminum (Al), copper (Cu), and titanium (Ti), such as aluminum-neodymium alloy (AlNd), molybdenum-niobium alloy (MoNb), or molybdenum-nickel-titanium alloy (MoNiTi). The transition layer can be a single-layer structure or a multi-layer composite structure, such as Ti / Al / Ti, Mo / Nb / Cu, MoNiTi / Cu, MoNb / Cu / MoNiTi, or MoNiTi / Cu / MoNiTi, etc.

[0184] (34) Forming a third conductive layer pattern. Forming the third conductive layer pattern may include: sequentially depositing a fourth insulating film 14-1 and a third conductive film on one side of the substrate 30 on which the aforementioned pattern is formed; and patterning the third conductive film using a patterning process to form a third conductive layer pattern located on the side of the fourth insulating film 14-1 away from the substrate 30. The third conductive layer may include a common electrode 19, such as... Figure 24A and Figure 24B As shown, Figure 24B for Figure 24A Cross-sectional view along the EE direction.

[0185] (35) Forming a fifth insulating layer pattern. Forming the fifth insulating layer pattern may include: depositing a fifth insulating film on one side of the substrate 30 on which the aforementioned pattern is formed, and patterning the fifth insulating film using a patterning process to form a fifth insulating layer pattern and a fourth insulating layer pattern located on the side of the third conductive layer away from the substrate 30, such as... Figure 25A and Figure 25B As shown, Figure 25B for Figure 25A Cross-sectional view along the EE direction.

[0186] like Figure 25A As shown, the fifth insulating layer 15 may include a plurality of vias, and the plurality of vias may include at least one eighth via K8. The orthographic projection of the eighth via K8 onto the plane of the array substrate overlaps at least partially with the orthographic projection of the pixel connection electrode 21 onto the plane of the array substrate. For example, the orthographic projection of the eighth via K8 onto the plane of the array substrate may be located within the orthographic projection of the pixel connection electrode 21 onto the plane of the array substrate. The fifth insulating film and the fourth insulating film located within the eighth via K8 are both etched away, and the eighth via K8 exposes at least a portion of the surface of the pixel connection electrode 21 away from the substrate 30. The eighth via K8 is configured such that the subsequently formed pixel electrode is electrically connected to the pixel connection electrode 21 via the via, thereby realizing the electrical connection between the pixel electrode and the active layer.

[0187] In some exemplary embodiments, the eighth via K8 can be a circular hole, an elliptical hole, a rectangular hole, or a hexagonal hole, etc.

[0188] (36) Forming a fourth conductive layer pattern. Forming the fourth conductive layer pattern may include: depositing a fourth conductive film on one side of the substrate 30 on which the aforementioned pattern is formed, and patterning the fourth conductive film using a patterning process to form a fourth conductive layer pattern located on the side of the fifth insulating layer 15 away from the substrate 30. The fourth conductive layer may include multiple pixel electrodes 10, such as... Figure 26A and Figure 26B As shown, Figure 26B for Figure 26A A cross-sectional view along the EE direction. (See attached image.) Figure 26B As shown, the pixel electrode 10 can be electrically connected to the pixel connection electrode 21 via the eighth via K8. The structure of the pixel electrode 10 can be referred to the description of the aforementioned exemplary embodiments, and will not be repeated here.

[0189] Figure 27 This is a cross-sectional schematic diagram of a display device according to an embodiment of the present disclosure. Figure 27 As shown, one embodiment of this disclosure also provides a display device. Taking the display device as an example, which can implement ADS (Advanced Super Dimension Switch) mode, the display device may include an array substrate 5, which may be the array substrate provided in any of the foregoing embodiments.

[0190] The display device may further include a counter substrate 1 and a liquid crystal layer 2 disposed between an array substrate 5 and the counter substrate 1. The pixel electrodes and common electrodes included in the array substrate 5 can be configured to generate an electric field that controls the deflection of liquid crystal molecules in the liquid crystal layer 2. Figure 27 As shown, the liquid crystal molecules in the liquid crystal layer 2 can be arranged horizontally on the array substrate 5. In this embodiment, the horizontal direction is parallel to the plane where the array substrate 5 is located.

[0191] In one exemplary embodiment, such as Figure 27 As shown, the opposing substrate 1 may include a substrate, and a black matrix 3 and a color filter layer 4 disposed on the substrate. However, the embodiments disclosed herein are not limited thereto.

[0192] In one exemplary embodiment, the width of the black matrix 3 can be approximately twice the width of the gate line.

[0193] This disclosure also provides a display device. The display device includes the array substrate described in any of the foregoing embodiments. The display device can be any product or component with display function, such as a liquid crystal panel, electronic paper, mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator. This disclosure is not limited in this respect.

[0194] While the embodiments disclosed in this invention have been described above, the content is merely for the purpose of facilitating understanding of the invention and is not intended to limit the invention. It should be noted that the above embodiments or implementation methods are merely exemplary and not restrictive. Therefore, this disclosure is not limited to the content specifically shown and described herein. Various modifications, substitutions, or omissions can be made to the form and details of the implementation without departing from the scope of this disclosure.

Claims

1. An array substrate, characterized in that, The device includes a substrate, at least one transistor disposed on the substrate, at least one data line disposed on the substrate, and at least one first electrode disposed on the substrate; the at least one transistor includes an active layer and a gate, the active layer includes a channel region and a first region and a second region located on opposite sides of the channel region, the channel region and the gate overlapping in orthographic projection on the substrate; In a plane perpendicular to the array substrate, the array substrate further includes a gate insulating layer, the gate insulating layer being located on the side of the active layer away from the substrate, and a portion of the surface of the gate insulating layer near the substrate being in contact with a portion of the surface of the active layer away from the substrate; The gate insulating layer has a plurality of vias, and the at least one data line is electrically connected to the first region via one of the vias, and the at least one first electrode is electrically connected to the second region via another of the vias; the vias have a top end and a bottom end disposed opposite to each other, and the bottom end is closer to the active layer than the top end; there is a minimum gap between the bottom end and the boundary of the channel region in the orthographic projection of the substrate and the orthographic projection of the substrate, the minimum gap being greater than 2.5 micrometers; In a plane perpendicular to the array substrate, the array substrate further includes a first conductive layer and a second conductive layer; the first conductive layer is located on the side of the active layer closer to the substrate, and the second conductive layer is located on the side of the active layer away from the substrate; the first conductive layer includes the at least one data line, and the second conductive layer includes at least one gate; the second conductive layer further includes at least one pixel connection electrode, at least a portion of the at least one pixel connection electrode is located within the via, and the at least a portion is in contact with the active layer; A portion of the at least one first electrode is electrically connected to the pixel connection electrode; Alternatively, in a plane perpendicular to the array substrate, the array substrate further includes a transition layer located on the side of the second conductive layer away from the substrate; The transition layer includes at least one pixel connection electrode, at least a portion of which is located within the via and is in contact with the active layer; A portion of the at least one first electrode is electrically connected to the pixel connection electrode.

2. The array substrate as described in claim 1, characterized in that, The diameter of the bottom end of the via with the minimum spacing is greater than or equal to 1.5 micrometers and less than or equal to 2.0 micrometers.

3. The array substrate as described in claim 2, characterized in that, The diameter of the top of the via with the minimum spacing is greater than or equal to 1.5 micrometers and less than or equal to 2.0 micrometers, and the diameter of the top of the same via is greater than the diameter of the bottom.

4. The array substrate as described in claim 1, characterized in that, The minimum interval is greater than or equal to 3.0 micrometers and less than or equal to 5.0 micrometers.

5. The array substrate as described in claim 1, characterized in that, The second conductive layer further includes at least one data connection electrode, a portion of which is located within the via and contacts a portion of the surface of the active layer away from the substrate; the at least one data connection electrode contacts a portion of the surface of the at least one data line away from the substrate.

6. The array substrate as described in claim 5, characterized in that, The at least one data line includes a first top surface and a first bottom surface disposed opposite to each other, and a first side surface connecting the first top surface and the first bottom surface; the first top surface is farther away from the substrate than the first bottom surface; the data connection electrode is in contact with the first top surface and also in contact with the first side surface.

7. The array substrate as described in claim 5, characterized in that, The first region includes a second top surface and a second bottom surface disposed opposite to each other, and a second side surface connecting the second top surface and the second bottom surface; the second top surface is farther away from the substrate than the second bottom surface; the data connection electrode is in contact with the second top surface and also in contact with the second side surface.

8. The array substrate as described in any one of claims 1 to 7, characterized in that, The array substrate further includes at least one gate line, the gate and the gate line are in the same layer and are an integral structure connected to each other; the at least one gate line extends along a first direction and the at least one data line extends along a second direction, wherein the first direction and the second direction intersect.

9. The array substrate as described in claim 8, characterized in that, The gate line includes a first extension and a second extension connected to each other; the first extension extends along the first direction, and the second extension includes a first end and a second end disposed opposite to each other, the first end of the second extension is connected to the first extension, and the second end of the second extension extends along the second direction; wherein a portion of the second extension serves as the gate.

10. The array substrate as claimed in claim 9, characterized in that, The second extension has a dimension greater than 0 micrometers and equal to or less than 5.0 micrometers in the orthogonal projection of the substrate along the second direction.

11. The array substrate as claimed in claim 9, characterized in that, The gate line further includes a third extension; the third extension includes a first end and a second end disposed opposite to each other, the first end of the third extension is connected to the first extension, and the second end of the third extension extends in the opposite direction to the second direction; wherein, the size of the second extension in the orthographic projection on the substrate along the second direction is greater than 0 micrometers and equal to or less than 5.0 micrometers, and the size of the third extension in the orthographic projection on the substrate along the second direction is greater than 0 micrometers and equal to or less than 5.0 micrometers.

12. The array substrate as claimed in claim 8, characterized in that, The grid line is a straight line extending along the first direction.

13. A display device, characterized in that, It includes an array substrate, a counter substrate, and a liquid crystal layer as described in any one of claims 1 to 12; the array substrate and the counter substrate are disposed opposite to each other, and the liquid crystal layer is located between the array substrate and the counter substrate.

Images