N-type TOPCon battery and preparation method thereof

Abstract

The embodiment of the invention provides an N-type TOPCon battery and a preparation method thereof, and the N-type TOPCon battery provided by the embodiment of the invention comprises an N-type silicon substrate, and a tunneling oxide layer, a polycrystalline silicon transition layer, a mask oxide layer, a phosphorus-doped polycrystalline silicon layer and an electrode which are sequentially deposited on the back surface of the silicon substrate, wherein a polycrystalline silicon transition layer and a mask oxide layer are additionally arranged between the tunneling oxide layer and the phosphorus-doped polycrystalline silicon layer, and the mask oxide layer is used as a first barrier for hindering the propulsion process of phosphorus atoms, so that the doping concentration of the phosphorus atoms in the polycrystalline silicon transition layer is relatively low; and the tunneling oxide layer serving as a second barrier in the process of hindering phosphorus atom propulsion is combined, so that the number of phosphorus atoms in the silicon substrate can be effectively reduced while the doping concentration of the phosphorus atoms in the phosphorus-doped polycrystalline silicon layer is increased, and the open voltage and the photoelectric conversion efficiency of the cell are further improved.

Description

Technical Field

[0001] The present invention relates to the technical field of crystalline silicon solar cell manufacturing, and particularly to an N-type TOPCon cell and a preparation method thereof. Background Art

[0002] Currently, N-type TOPCon cells in crystalline silicon solar cells are widely used due to their advantages such as small attenuation, obvious overall efficiency and power generation advantages of the cells.

[0003] In order to effectively reduce surface recombination and metal contact recombination, a passivation contact structure composed of a tunneling oxide layer and a phosphorus-doped polysilicon layer is provided on the back surface of the N-type TOPCon cell. Among them, the tunneling oxide layer, as a phosphorus atom diffusion barrier layer, can prevent phosphorus atoms from diffusing into the silicon substrate, ensuring that the cell has a high open-circuit voltage and photoelectric conversion efficiency.

[0004] However, in existing N-type TOPCon cells, the tunneling oxide layer has poor tolerance to the doping concentration of phosphorus atoms. A higher back surface phosphorus atom concentration will increase the damage of phosphorus atoms to the tunneling oxide layer, resulting in an increase in the number of phosphorus atoms diffusing into the back surface silicon substrate, leading to a decrease in the open-circuit voltage of the cell, affecting the passivation effect of the back field, and reducing the contact resistivity between the back silver paste and the silicon wafer, thereby reducing the photoelectric conversion efficiency of the cell. Summary of the Invention

[0005] The technical problem to be solved by the present invention is to provide an N-type TOPCon cell and a preparation method thereof, so as to solve the problem that the passivation contact structure in existing N-type TOPCon cells has poor tolerance to the doping concentration of phosphorus atoms and cannot effectively improve the open-circuit voltage and photoelectric conversion efficiency of the cell by increasing the phosphorus atom doping concentration.

[0006] To solve the above problems, the present invention is realized by the following technical solutions:

[0007] The present invention provides an N-type TOPCon cell, which includes an N-type silicon substrate and a tunneling oxide layer, a polysilicon transition layer, a mask oxide layer, a phosphorus-doped polysilicon layer and an electrode sequentially deposited on the back surface of the silicon substrate.

[0008] Further, in the N-type TOPCon cell, the doping concentration of phosphorus atoms in the phosphorus-doped polysilicon layer is 8E20 - 10E20 / cm 3 .

[0009] Further, in the N-type TOPCon cell, the mask oxide layer includes a silicon dioxide layer with a thickness of 0.5 - 1.0 nm.

[0010] Further, in the N-type TOPCon cell, the doping concentration of phosphorus atoms in the polysilicon transition layer is 2E20 - 3E20 / cm 3 .

[0011] Further, in the N-type TOPCon cell, the thickness of the polysilicon transition layer is 10 - 20 nm.

[0012] Further, in the N-type TOPCon cell, the tunneling oxide layer includes a silicon dioxide layer with a thickness of 1.5 - 3 nm, and / or the thickness of the phosphorus-doped polysilicon layer is 90 - 110 nm.

[0013] The present invention also provides a method for manufacturing an N-type TOPCon cell, which includes:

[0014] After texturing, boron doping, and removing the boron-silicate glass layer on the back of the N-type silicon wafer in sequence, a tunneling oxide layer, a polysilicon transition layer, a masking oxide layer, and a polysilicon passivation layer are formed on the back in sequence;

[0015] Phosphorus doping is performed on the polysilicon passivation layer to form a doped polysilicon layer;

[0016] The phosphorus-silicate glass layer on the front, the deposited polysilicon layer on the front, the boron-silicate glass layer on the front, and the phosphorus-phosphorus-silicate glass layer on the back are removed in sequence;

[0017] After removing the phosphorus-silicate glass layer on the back, a passivation film layer, a front antireflection film layer, a back antireflection film layer, and electrodes are formed on the silicon wafer in sequence.

[0018] Further, in the method for manufacturing the N-type TOPCon cell, forming the tunneling oxide layer, the polysilicon transition layer, the masking oxide layer, and the polysilicon passivation layer on the back in sequence includes:

[0019] Forming a silicon dioxide layer with a thickness of 1.5 - 3 nm on the back as the tunneling oxide layer;

[0020] Forming a polysilicon layer with a thickness of 10 - 20 nm on the surface of the tunneling oxide layer as the polysilicon transition layer;

[0021] Forming a silicon dioxide layer with a thickness of 0.5 - 1.0 nm on the surface of the polysilicon transition layer as the masking oxide layer;

[0022] Forming a polysilicon layer with a thickness of 90 - 110 nm on the surface of the masking oxide layer as the polysilicon passivation layer.

[0023] Further, in the method for manufacturing the N-type TOPCon cell, phosphorus doping is performed on the polysilicon passivation layer to form a doped polysilicon layer, which includes:

[0024] At a temperature of 785 - 805 °C, with the flow rate of POCl 3 being 1300 - 1700 sccm / min, the oxygen flow rate being 500 - 700 sccm / min, and the pressure being 120 - 180 mbar, deposit for 14 - 20 min, and then raise the temperature of the silicon wafer to 895 - 920 °C for high-temperature drive treatment for 20 - 35 min to obtain a phosphorus-doped polysilicon layer.

[0025] Furthermore, in the preparation method of the N-type TOPCon battery, sequentially removing the phosphorus-silicate glass layer on the front side, the overplated polysilicon layer on the front side, the boron-silicate glass layer on the front side, and the phosphorus-silicate glass layer on the back side includes:

[0026] Performing chain pickling on the front side of the silicon wafer to remove the phosphorus-silicate glass layer on the front side;

[0027] Performing alkali etching treatment on the front side of the silicon wafer to remove the overplated polysilicon layer on the front side;

[0028] Performing chain pickling on the front side and the back side of the silicon wafer, the boron-silicate glass layer on the front side and the phosphorus-silicate glass layer on the back side.

[0029] Compared with the prior art, the embodiments of the present invention include the following advantages:

[0030] In the embodiments of the present invention, the provided N-type TOPCon battery includes an N-type silicon substrate and a tunneling oxide layer, a polysilicon transition layer, a mask oxide layer, a phosphorus-doped polysilicon layer, and an electrode sequentially deposited on the back side of the silicon substrate; wherein, a polysilicon transition layer and a mask oxide layer are additionally provided between the tunneling oxide layer and the phosphorus-doped polysilicon layer, and the mask oxide layer is used as the first barrier during the process of hindering the advancement of phosphorus atoms, so that the doping concentration of phosphorus atoms in the polysilicon transition layer is relatively low. Combining with the tunneling oxide layer as the second barrier during the process of hindering the advancement of phosphorus atoms, it is thus possible to effectively reduce the number of phosphorus atoms in the silicon matrix while increasing the doping concentration of phosphorus atoms in the phosphorus-doped polysilicon layer, thereby further improving the open voltage and photoelectric conversion efficiency of the battery.

[0031] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit this application. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 is a schematic structural diagram of an N-type TOPCon battery provided by an embodiment of the present invention;

[0033] Figure 2 is a flowchart of a preparation method of an N-type TOPCon battery provided by an embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0034] To make the above objects, features, and advantages of the present invention more apparent and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0035] The applicant of the present invention has found that when preparing an N-type TOPCon battery, it is necessary to prepare an ultra-thin silicon dioxide layer on the back of the battery as a tunneling oxide layer, and then deposit a phosphorus-doped polysilicon thin layer as a back-field polysilicon passivation layer. The two together form a passivated contact structure to effectively reduce surface recombination and metal contact recombination. Among them, the tunneling oxide layer serves as a barrier layer to prevent the advancement of phosphorus atoms, blocking the advancement of phosphorus atoms into the silicon substrate, thereby reducing the number of phosphorus atoms in the silicon substrate, reducing the back-surface impurity recombination, and improving the open-circuit voltage of the cell; in addition, under the action of the energy band barrier of the back-field polysilicon passivation layer, the tunneling oxide layer acts as an insulating layer to prevent minority carriers from passing through the oxide layer to reach the back of the silicon wafer, and allows majority carriers to reach the back of the silicon wafer through the channels of the silicon-oxygen bond breakage gaps (pinholes), thereby improving the collection ability of majority carriers in the cell and improving the efficiency of the cell.

[0036] However, in existing N-type TOPCon batteries, the tunneling oxide layer has poor tolerance to the doping concentration of phosphorus atoms. A higher back-surface phosphorus atom concentration will increase the damage of phosphorus atoms to the tunneling oxide layer, resulting in an increase in the number of phosphorus atoms diffusing into the back-surface silicon substrate, leading to a decrease in the open-circuit voltage of the cell, a weaker passivation effect of the back field, a decrease in the contact resistivity between the back silver paste and the silicon wafer, and a decrease in the photoelectric conversion efficiency of the cell.

[0037] An embodiment of the present invention provides an N-type TOPCon battery to solve the above problems, which includes an N-type silicon substrate 11 and a tunneling oxide layer 12, a polysilicon transition layer 13, a mask oxide layer 14, a phosphorus-doped polysilicon layer 15, and an electrode 16 sequentially deposited on the back of the silicon substrate 11.

[0038] Among them, a polysilicon transition layer and a mask oxide layer are additionally provided between the tunneling oxide layer and the phosphorus-doped polysilicon layer. The mask oxide layer is used as the first barrier in the process of preventing the advancement of phosphorus atoms, so that the doping concentration of phosphorus atoms in the polysilicon transition layer is relatively low. Combined with the tunneling oxide layer as the second barrier in the process of preventing the advancement of phosphorus atoms, it is possible to effectively reduce the number of phosphorus atoms in the silicon substrate while increasing the phosphorus atom doping concentration in the phosphorus-doped polysilicon layer, thereby further improving the open-circuit voltage and photoelectric conversion efficiency of the cell.

[0039] Optionally, in the N-type TOPCon cell provided in the embodiment of the present invention, the tunneling oxide layer includes a silicon dioxide layer with a thickness of 1.5 to 3 nm, that is, a silicon dioxide thin film layer with a thickness of 1.5 to 3 nm is first grown on the back of the silicon substrate as the tunneling oxide layer of the topcon core structure. For example, the thickness of the silicon dioxide layer can be one of 1.5 nm, 2 nm, 2.5 nm, 3 nm, or any two of them.

[0040] In the embodiment of the present invention, the phosphorus-doped polysilicon layer is not only used for back field passivation, but also directly makes ohmic contact with the printed silver paste. Among them, due to the barrier effect of the tunnel oxide layer and the mask oxide layer, the opening voltage is adjusted by the phosphorus diffusion process to greatly increase the doping concentration of phosphorus atoms in the phosphorus-doped polysilicon layer, which can not only improve the passivation effect, but also effectively reduce the contact resistivity with the silver paste, improve the ohmic contact, and reduce the lateral thin layer transmission loss of the carrier, thereby improving the efficiency of the battery cell.

[0041] Optionally, in one embodiment, the doping concentration of phosphorus atoms in the phosphorus-doped polysilicon layer is 8E20-10E20 / cm 3 For example, the doping concentration of phosphorus atoms in the phosphorus-doped polysilicon layer may be 8E20 / cm 3 、8.5E20 / cm 3 、9E20 / cm 3 , 9.5E20, 10E20 / cm 3 The range value of one or both of them.

[0042] Optionally, in one embodiment, the thickness of the phosphorus-doped polysilicon layer is 90-110 nm, which can reduce parasitic absorption while ensuring the passivation effect. For example, the thickness of the phosphorus-doped polysilicon layer is in the range of one or any two of 90 nm, 95 nm, 100 nm, 105 nm, and 110 nm.

[0043] In the embodiment of the present invention, the mask oxide layer includes a silicon dioxide layer with a thickness of 0.5 to 1.0 nm. By growing an ultra-thin silicon dioxide layer with a thickness of 0.5 to 1.0 nm outside the polysilicon transition layer as a mask layer, and when the phosphorus diffusion is advanced at a temperature above 900°C to form a phosphorus-doped polysilicon layer, the Si-O bonds in the mask layer are broken and fail, thereby realizing the first barrier layer to block the advancement of phosphorus atoms, which can effectively reduce the advancement of phosphorus atoms to the polysilicon transition layer, so that the tunnel oxide layer is used as the second barrier layer to block the advancement of phosphorus ions, and the pressure of blocking the advancement of phosphorus ions can be greatly alleviated, thereby effectively reducing the number of phosphorus atoms in the silicon substrate.

[0044] In the embodiments of the present invention, under the action of the mask oxide layer to block the phosphorus ion propulsion, the doping concentration of phosphorus atoms in the polysilicon transition layer is sharply reduced. Optionally, in one embodiment, the doping concentration of phosphorus atoms in the polysilicon transition layer is 2E20 - 3E20 / cm 3 . Exemplarily, the doping concentration of phosphorus atoms in the polysilicon transition layer can be 2E20 / cm 3 , 2.5E20 / cm 3 , 3E20 / cm 3 or the range value of any two of them.

[0045] Optionally, in one embodiment, the thickness of the polysilicon transition layer is 10 - 20 nm. That is, outside the tunneling oxide layer, a polysilicon layer with a thickness of 10 - 20 nm is grown as a passivation transition layer. Under the action of the mask oxide layer to block the phosphorus atom propulsion, a polysilicon layer with this thickness can effectively receive the phosphorus atoms passing through the transition mask oxide layer and keep the doping concentration of phosphorus atoms at 2E20 - 3E20 / cm 3 . Exemplarily, the thickness of the polysilicon transition layer is one of 10 nm, 11 nm, 12 nm, 13 nm, 14 nm, 15 nm, 16 nm, 17 nm, 18 nm, 19 nm, 20 nm or the range value of any two of them.

[0046] In practical applications, the N-type TOPCon battery provided by the embodiments of the present invention further includes a boron diffusion layer (not shown) disposed on the front surface of the N-type silicon substrate.

[0047] In practical applications, the open-circuit voltage of the N-type TOPCon battery provided by the embodiments of the present invention is increased by 1.4 mV, the fill factor is increased by 0.33%, and the photoelectric conversion efficiency is increased by 0.14%.

[0048] Among them, part of the electrode 16 is not covered with the phosphorus-doped polysilicon layer 15.

[0049] The N-type TOPCon battery provided by the embodiments of the present invention further includes a passivation film layer 17 and a first antireflection film layer 18 sequentially disposed on the front surface of the silicon substrate 11. Among them, the passivation film layer 17 is located between the silicon substrate 11 and the first antireflection film layer 18, that is, the passivation film layer is close to the silicon substrate 11. Through the above settings, the reflectivity of incident light on the front surface of the battery can be effectively reduced, thereby improving the absorption of light by the film layer.

[0050] Among them, the boron diffusion layer is located between the silicon substrate and the passivation film layer 17 on the front surface.

[0051] In practical applications, the film thickness of the first anti-reflection film layer 18 is controlled within 70 - 84 nm. Exemplarily, the film thickness of the first anti-reflection film layer 18 is one of 70 nm, 72 nm, 76 nm, 78 nm, 80 nm, 84 nm or a range value between any two of them.

[0052] Optionally, in one embodiment, the above-mentioned first anti-reflection film layer 18 includes a silicon nitride layer, and the refractive index of the first anti-reflection film layer 18 is between 1.98 - 2.1; the above-mentioned passivation film layer 17 is an alumina film layer, and the thickness is 2.5 - 5 nm. Exemplarily, the thickness of the passivation film layer is one of 2.5 nm, 3 nm, 3.5 nm, 4 nm, 4.5 nm, 5 nm or a range value between any two of them.

[0053] The N-type TOPCon battery provided by the embodiment of the present invention further includes a second anti-reflection film layer 19 disposed on the surface of the phosphorus-doped polysilicon layer 15, which is used to reduce the reflectivity of incident light on the back surface of the battery, thereby improving the absorption of light by the film layer.

[0054] Optionally, in one embodiment, the above-mentioned second anti-reflection film layer 19 includes a silicon nitride layer, and the refractive index of the second anti-reflection film layer 19 is between 1.98 - 2.1.

[0055] In practical applications, the film thickness of the second anti-reflection film layer 19 is controlled within 75 - 90 nm. Exemplarily, the film thickness of the second anti-reflection film layer 19 is one of 75 nm, 76 nm, 78 nm, 80 nm, 84 nm, 86 nm, 88 nm, 90 nm or a range value between any two of them.

[0056] The above-mentioned electrode 16 includes a negative electrode 161 on the back surface of the silicon substrate and a positive electrode 162 on the front surface. The negative electrode 161 specifically includes a back surface main grid electrode and a back surface sub-grid electrode, both of which can be silver electrodes. The positive electrode 162 can be a silver-aluminum electrode.

[0057] In addition, the N-type TOPCon battery provided by the embodiment of the present invention further includes a front surface main grid electrode and a front surface sub-grid electrode deposited on the front surface of the N-type silicon substrate 11; among them, the front surface main grid electrode can be a silver electrode, and the front surface sub-grid electrode is a silver-aluminum paste electrode.

[0058] In the N-type TOPCon battery provided by the embodiment of the present invention, the two oxide layers hinder the diffusion of phosphorus atoms into the interior of the silicon matrix, reduce impurity recombination, improve the open voltage of the battery chip, and the mask oxide layer has a thickness of less than 1 nm and breaks and fails under high-temperature phosphorus diffusion above 900 °C, so the structure of the finished battery chip is not affected; in addition, due to the two-oxide layer structure, the back surface is not easily penetrated by phosphorus atoms, and the surface phosphorus atom concentration can be increased from 5.5E20 / cm 3 to 8.5E20 / cm 3, reducing the lateral transmission loss of carriers, improving the ohmic contact with the silver paste, and improving the filling of the battery cell.

[0059] The present invention also provides a method for preparing an N-type TOPCon battery. Figure 2 As shown, it includes steps 201 to 204:

[0060] Step 201, after the N-type silicon wafer is textured and boron doped in sequence and the borosilicate glass layer on the back is removed, a tunneling oxide layer, a polysilicon transition layer, a mask oxide layer, and a polysilicon passivation layer are formed in sequence on the back;

[0061] Step 202, phosphorus-doping the polysilicon passivation layer to form a phosphorus-doped polysilicon layer;

[0062] Step 203, sequentially removing the front phosphosilicate glass layer, the front coated polysilicon layer, the front borosilicate glass layer and the back phosphosilicate glass layer;

[0063] Step 204: after removing the phosphosilicate glass layer on the back side, a passivation film layer, a front anti-reflection film layer, a back anti-reflection film layer and an electrode are sequentially formed on the silicon wafer.

[0064] The preparation method of the N-type TOPCon battery provided in the embodiment of the present invention is to additionally grow a polysilicon transition layer and a mask oxide layer between the tunneling oxide layer and the phosphorus-doped polysilicon layer, and use the mask oxide layer as the first barrier to hinder the advancement of phosphorus atoms, so that the doping concentration of phosphorus atoms in the polysilicon transition layer is low, and then combine the tunneling oxide layer as the second barrier to hinder the advancement of phosphorus atoms; in addition, because the Si-O bond of the mask oxide layer breaks and fails when the phosphorus is diffused at a temperature above 900°C, the additionally set mask oxide layer will not affect the structure of the finished battery cell, and thus can effectively reduce the number of phosphorus atoms in the silicon substrate while increasing the doping concentration of phosphorus atoms in the phosphorus-doped polysilicon layer, thereby further improving the battery's opening voltage and photoelectric conversion efficiency.

[0065] In the above step 201, N-type virgin silicon of a certain size is selected for double-sided texturing treatment, that is, the preparation of a double-sided pyramid structure is carried out to ensure that the surface reflectivity of the texture is between 9% and 10%, for example, 9.4%; among them, the N-type virgin silicon can specifically be a silicon wafer of 182mm×182mm. Optionally, the virgin silicon wafer is subjected to double-sided texturing treatment with a texturing solution at 75-85°C. Among them, by volume, the above texturing solution includes 16-24 parts of a KOH solution with a mass percentage of 45%, 3-6 parts of a texturing additive, and 450-500 parts of water. Among them, the texturing additive includes a surfactant with a mass percentage of 2-3%, a defoaming agent with a mass percentage of 1-3%, a nucleating agent with a mass percentage of 1-1.5%, sodium benzoate with a mass percentage of 4-6%, and water with a mass percentage of 86.5-90%. The surfactant can be sodium lauryl polyoxyethylene ether sulfate or triglyceride, the defoaming agent can be polyoxypropylene glycerol ether or polyoxypropylene glycerol ether, and the nucleating agent can be sodium citrate.

[0066] In the above step 201, the textured silicon wafer is sent into a furnace tube for boron doping to prepare a PN junction and make the surface boron doping concentration reach 8E18-2E19 atoms / cm3, and the diffusion junction depth reach between 0.6 and 1.2 um.

[0067] Exemplarily, the textured silicon wafer is diffused. First, it is deposited for 10-15 minutes under the conditions of a temperature of 830-870°C, a BCl 3 flow rate of 180-220 sccm / min, an oxygen flow rate of 700-900 sccm / min, a nitrogen flow rate of 1500-3000 sccm / min, and a pressure of 120-180 mbar. Then the silicon wafer is heated to 1030-1050°C and treated for 50-80 minutes at a pressure of 700-950 mbar and an oxygen flow rate of 15000-20000 sccm / min to complete boron doping.

[0068] In the above step 201, removing the boron-silicate glass layer on the back includes:

[0069] The back side of the boron-doped silicon wafer is subjected to chain pickling and alkaline polishing treatment. Among them, by volume, the chain pickling solution includes 500 - 600 parts of hydrofluoric acid with a mass percentage of 49% and 50 - 100 parts of water. The temperature of the above alkaline polishing treatment is 70 - 80 °C, and the alkaline polishing solution includes 19 - 26 parts of KOH solution with a mass percentage of 45%, 3 - 6 parts of alkaline polishing additive, and 450 - 500 parts of water. Among them, the alkaline polishing additive includes a surfactant with a mass percentage of 2 - 3%, a defoaming agent with a mass percentage of 2 - 3%, an antifoaming agent with a mass percentage of 2 - 4%, glucose with a mass percentage of 2 - 3%, sodium polystyrene sulfonate with a mass percentage of 2 - 3%, and water with a mass percentage of 80 - 85%. The surfactant can be sodium lauryl polyoxyethylene ether sulfate or triglyceride, the defoaming agent can be polyoxypropylene glycerol ether or polyoxypropylene glycerol ether, and the antifoaming agent can be polydimethylsiloxane.

[0070] In the above step 201, the N-type silicon wafer after forming the PN junction is subjected to Low Pressure Chemical Vapor Deposition (LPCVD). First, an ultrathin silicon dioxide layer is formed on the back side of the N-type silicon wafer as the ultrathin tunneling oxide layer. Then, a polysilicon transition layer with a thickness that can meet the transition passivation effect is prepared on both sides. Then, another ultrathin silicon dioxide layer is formed as the mask oxide layer. Then, a polysilicon layer with a thickness that can meet the passivation effect is prepared on both sides as the polysilicon passivation layer. Among them, because preparing the polysilicon layer on both sides is beneficial for subsequent removal of the polysilicon layer on the front side, and it is not easy to appear in two extreme situations of excessive removal or insufficient removal, and the yield is better controlled.

[0071] Optionally, forming the tunneling oxide layer, polysilicon transition layer, mask oxide layer, and polysilicon passivation layer on the back side in sequence includes:

[0072] Forming a silicon dioxide layer with a thickness of 1.5 - 3 nm on the back side as the tunneling oxide layer;

[0073] Forming a polysilicon layer with a thickness of 10 - 20 nm on the surface of the tunneling oxide layer as the polysilicon transition layer;

[0074] Forming a silicon dioxide layer with a thickness of 0.5 - 1.0 nm on the surface of the polysilicon transition layer as the mask oxide layer;

[0075] Forming a polysilicon layer with a thickness of 90 - 110 nm on the surface of the mask oxide layer as the polysilicon passivation layer.

[0076] In this embodiment, the N-type silicon wafer after forming the PN junction is subjected to Low Pressure Chemical Vapor Deposition (LPCVD), and under the conditions of an oxygen amount of 250 - 350 L, a temperature of 600 - 640 °C, and a pressure of 650 - 900 mbar for 15 - 30 min, a silicon dioxide layer with a thickness of 1.5 - 3 nm can be formed on the back surface as the tunneling oxide layer. Among them, the flow rate of oxygen introduced is 40 L / min.

[0077] In this embodiment, after forming the tunneling oxide layer, under the conditions of a temperature of 600 - 630 °C and a pressure of 25 - 30 mbar, silane with a flow rate of 800 - 1200 sccm is introduced and lasts for 120 - 180 s, and a polysilicon layer with a thickness capable of meeting the passivation effect is prepared on both sides or one side as the above-mentioned polysilicon transition layer; the thickness can specifically be 10 - 20 nm.

[0078] In this embodiment, after forming the polysilicon transition layer, under the conditions of an oxygen amount of 100 - 200 L, a temperature of 580 - 610 °C, and a pressure of 400 - 600 mbar for 5 - 15 min, a silicon dioxide layer with a thickness of 0.5 - 1.0 nm can be formed on the back surface as the mask oxide layer. Among them, the flow rate of oxygen introduced is 40 L / min, and the introduction time is 2.5 - 5 min.

[0079] In this embodiment, after forming the mask oxide layer, under the conditions of a temperature of 600 - 630 °C and a pressure of 25 - 30 mbar, silane with a flow rate of 800 - 1200 sccm is introduced and lasts for 1400 - 1800 s, and a polysilicon layer with a thickness capable of meeting the passivation effect is prepared on both sides or one side as the above-mentioned polysilicon passivation layer; the thickness can specifically be 90 - 110 nm.

[0080] Optionally, in one embodiment, in step 202 above, phosphorus doping is performed on the polysilicon passivation layer to form a phosphorus-doped polysilicon layer, including:

[0081] At a temperature of 785 - 805 °C, the flow rate of POCl 3 is 1300 - 1700 sccm / min, the oxygen flow rate is 500 - 700 sccm / min, and under the condition of a pressure of 120 - 180 mbar, deposition is carried out for 14 - 20 min, and then the silicon wafer is heated to 895 - 920 °C for high-temperature drive-in treatment for 20 - 35 min to obtain a phosphorus-doped polysilicon layer.

[0082] In this embodiment, by at a temperature of 785 - 805 °C, POCl 3Deposit for 14 - 20 minutes under the conditions that the flow rate is 1300 - 1700 sccm / min, the oxygen flow rate is 500 - 700 sccm / min, and the pressure is 120 - 180 mbar. Then heat the silicon wafer to 895 - 920 °C for high-temperature promotion treatment for 20 - 35 minutes, and high-concentration doping of the polysilicon passivation layer can be completed to obtain a phosphorus-doped polysilicon layer with a phosphorus atom doping concentration of 8E20 - 10E20 / cm 3 of the phosphorus-doped polysilicon layer.

[0083] Optionally, in one embodiment, step 203 above includes:

[0084] Perform chain pickling on the front side of the silicon wafer to remove the phosphosilicate glass layer on the front side;

[0085] After removing the phosphosilicate glass layer on the front side, perform alkali etching treatment on the front side of the silicon wafer to remove the polycrystalline silicon layer deposited on the side;

[0086] After removing the polycrystalline silicon layer deposited on the front side, perform chain pickling on the front and back sides of the silicon wafer to remove the borosilicate glass layer on the front side and the phosphosilicate glass layer on the back side.

[0087] In this embodiment, the front side of the silicon wafer with completed phosphorus doping faces the chain pickling to remove the phosphosilicate glass layer on the front side. Among them, the pickling solution in the chain pickling can be hydrofluoric acid with a mass percentage of 8 - 15%.

[0088] In this embodiment, after removing the phosphosilicate glass layer on the front side, continue with alkali etching treatment to remove the polycrystalline silicon layer deposited on the front side. Among them, by volume, the above alkali etching solution includes 16 - 24 parts of a 45% KOH solution by mass, 3 - 7 parts of an etching additive, and 400 - 500 parts of water. Among them, the etching additive includes a surfactant with a mass percentage of 1 - 2%, a defoaming agent with a mass percentage of 2 - 3%, an antifoaming agent with a mass percentage of 1 - 3%, glucose with a mass percentage of 2 - 4%, sodium dodecyl sulfate with a mass percentage of 1 - 3%, and water with a mass percentage of 80 - 85%. The surfactant can be sodium lauryl polyoxyethylene sulfate or triglyceride, the defoaming agent can be oxypropylene glycerol ether or oxypropylene glycerol ether, and the antifoaming agent can be octylphenol polyoxyethylene ether.

[0089] In this embodiment, because when boron doping is performed on the silicon wafer, a borosilicate glass layer is also formed on its front side, which can protect the internal texture from damage by alkali polishing or alkali etching treatment. Therefore, after removing the polycrystalline silicon layer deposited on the front side, chain pickling is used to remove the borosilicate glass layer on the front side of the silicon wafer; in addition, a phosphosilicate glass layer is also formed on the back side of the silicon wafer during the process of phosphorus doping, and it also needs to be removed by chain pickling after removing the polycrystalline silicon layer deposited on the front side. Among them, the pickling solution in the chain pickling can be hydrofluoric acid with a mass percentage of 25 - 40%.

[0090] In the above step 204, an aluminum oxide film layer is deposited on the front side or both the front and back sides of the product by Atomic Layer Deposition (ALD) process as a passivation layer to form field passivation. Among them, the thickness of the aluminum oxide film layer can be 2.5 - 5 nm;

[0091] After forming the aluminum oxide film layer, a silicon nitride layer is first deposited on the front side of the battery, with a comprehensive refractive index between 1.98 and 2.1, and the film thickness is controlled between 70 and 84 nm; then a silicon nitride layer is deposited on the back side, with a comprehensive refractive index between 1.98 and 2.1, and the film thickness is controlled between 75 and 90 nm; then positive and negative metal electrodes are prepared through printing and sintering. Among them, silver paste is used for the main grids on both the front and back sides, silver-aluminum paste is used for the sub-grids on the front side, and silver paste is used for the sub-grids on the back side. The sintering temperature is 780 - 840 °C, the time is 40 - 70 S, and the total consumption is controlled between 90 and 200 mg.

[0092] The present invention will be described in detail below through embodiments.

[0093] Embodiment 1

[0094] (1) Select an N-type silicon wafer with a size of 182 mm × 182 mm, and perform double-sided texturing treatment on the original silicon wafer with a texturing solution at 77 °C. Among them, by volume, the above texturing solution includes 20 parts of a KOH solution with a mass percentage of 45%, 4.3 parts of a texturing additive, and 460 parts of water. Among them, the texturing additive includes a surfactant with a mass percentage of 3%, a defoaming agent with a mass percentage of 1.8%, a nucleating agent with a mass percentage of 1.2%, sodium benzoate with a mass percentage of 5.0%, and water with a mass percentage of 89%. The surfactant is sodium lauryl polyoxyethylene ether sulfate, the defoaming agent is oxypropylene glycerol ether, and the nucleating agent is sodium citrate;

[0095] (2) Feed the textured silicon wafer into the furnace tube, and deposit for 10 min under the conditions of a temperature of 850 °C, a BCl 3 flow rate of 190 sccm / min, an oxygen flow rate of 750 sccm / min, a nitrogen flow rate of 2000 sccm / min, and a pressure of 150 mbar. Then raise the temperature of the silicon wafer to 1045 °C and treat for 60 min at a pressure of 800 mbar and an oxygen flow rate of 18000 sccm / min to complete boron doping;

[0096] (3) Carry out chain pickling on the back side of the boron-doped silicon wafer and perform alkaline polishing treatment to remove the boron-silicate glass layer on the back side. Among them, by volume, the chain pickling solution includes 550 parts of hydrofluoric acid with a mass percentage of 49% and 50 parts of water; the temperature of the above alkaline polishing treatment is 75 °C, and the alkaline polishing solution includes 22 parts of KOH solution with a mass percentage of 45%, 4 parts of alkaline polishing additive, and 470 parts of water. Among them, the alkaline polishing additive includes a surfactant with a mass percentage of 3%, a defoaming agent with a mass percentage of 2.2%, an antifoaming agent with a mass percentage of 3%, glucose with a mass percentage of 2.5%, sodium polystyrene sulfonate with a mass percentage of 2%, and water with a mass percentage of 85%. The surfactant is sodium lauryl polyoxyethylene ether sulfate, the defoaming agent can be oxypropylene glycerol ether, and the antifoaming agent is polydimethylsiloxane;

[0097] (4) Carry out Low Pressure Chemical Vapor Deposition (LPCVD) on the boron-doped N-type silicon wafer, and introduce 300 L of oxygen at a flow rate of 40 L / min, and act for 20 min at a temperature of 610 °C and a pressure of 800 mbar, then a silicon dioxide layer with a thickness of 2.2 nm can be formed on the back side as the tunneling oxide layer;

[0098] (5) After forming the tunneling oxide layer, at a temperature of 615 °C and a pressure of 26 mbar, introduce silane with a flow rate of 950 sccm and continue for 150 s to prepare a polysilicon layer with a thickness of 10 nm as the above polysilicon transition layer;

[0099] (6) After forming the polysilicon transition layer, introduce 150 L of oxygen at a flow rate of 40 L / min, and act for 8 min at a temperature of 585 °C and a pressure of 500 mbar, then a silicon dioxide layer with a thickness of 0.8 nm can be formed on the back side as the mask oxide layer;

[0100] (7) After forming the mask oxide layer, at a temperature of 615 °C and a pressure of 26 mbar, introduce silane with a flow rate of 1050 sccm and continue for 1600 s to prepare a polysilicon layer with a thickness of 110 nm as the above polysilicon passivation layer;

[0101] (8) Place the silicon wafer at a temperature of 795 °C, with a flow rate of POCl 3 of 1450 sccm / min, an oxygen flow rate of 600 sccm / min, and a pressure of 160 mbar, deposit for 18 min, and then raise the temperature of the silicon wafer to 910 °C for high-temperature drive-in treatment for 25 min to complete high-concentration doping of the polysilicon passivation layer and obtain a phosphorus-doped polysilicon layer;

[0102] (9) Orient the silicon wafer with the phosphorus-doped side facing up, and subject it to chain pickling to remove the phosphosilicate glass layer on the front side. In the chain pickling process, the pickling solution is hydrofluoric acid with a mass percentage of 10%.

[0103] (10) After removing the phosphosilicate glass layer on the front side, perform an alkaline etching treatment on the silicon wafer to remove the polysilicon layer deposited on the front side. By volume, the above alkaline etching solution includes 18 parts of a KOH solution with a mass percentage of 45%, 4.5 parts of an etching additive, and 450 parts of water. The etching additive includes a surfactant with a mass percentage of 1 - 2%, a defoaming agent with a mass percentage of 2 - 3%, an antifoaming agent with a mass percentage of 1 - 3%, glucose with a mass percentage of 2 - 4%, sodium dodecyl sulfate with a mass percentage of 1 - 3%, and water with a mass percentage of 80 - 85%. The surfactant is sodium lauryl polyoxyethylene ether sulfate, the defoaming agent is oxypropylene glycerol ether, and the antifoaming agent is octylphenol polyoxyethylene ether.

[0104] (11) Subject the silicon wafer to the ALD process to deposit an aluminum oxide film layer on both sides, with a thickness maintained at 3.5 nm.

[0105] (12) Deposit a silicon nitride layer with a thickness of 76 nm on the front side; deposit a silicon nitride layer with a thickness of 80 nm on the back side.

[0106] (13) Prepare the front and back metal electrodes. Use silver paste for the front and back main grids, silver-aluminum paste for the front sub-grid, and silver paste for the back sub-grid, and then sinter at 810 °C for 50 s.

[0107] Repeat the above Example 1 to produce 4500 N-type TOPCon cells. Conduct electrical performance tests on each cell and calculate the average value. The results are shown in Table 1.

[0108] Comparative Example 1

[0109] (1) Select an N-type silicon wafer with a size of 182 mm × 182 mm, and perform double-sided texturing treatment on the original silicon wafer with the texturing solution at 77 °C. By volume, the above texturing solution includes 20 parts of a KOH solution with a mass percentage of 45%, 4.3 parts of a texturing additive, and 460 parts of water. The texturing additive includes a surfactant with a mass percentage of 3%, a defoaming agent with a mass percentage of 1.8%, a nucleating agent with a mass percentage of 1.2%, sodium benzoate with a mass percentage of 5%, and water with a mass percentage of 89%. The surfactant is sodium lauryl polyoxyethylene ether sulfate, the defoaming agent is oxypropylene glycerol ether, and the nucleating agent is sodium citrate.

[0110] (2) Feed the textured silicon wafer into the furnace tube, and at a temperature of 850 °C, BCl 3Deposit for 10 min under the conditions of a flow rate of 190 sccm / min, an oxygen flow rate of 750 sccm / min, a nitrogen flow rate of 2000 sccm / min, and a pressure of 150 mbar. Then, heat the silicon wafer to 1045 °C and treat it at a pressure of 800 mbar and an oxygen flow rate of 18000 sccm / min for 60 min to complete boron doping;

[0111] (3) Perform chain pickling on the back side of the boron-doped silicon wafer and perform alkali polishing treatment to remove the boron-silicate glass layer on the back side. Among them, by volume, the chain pickling solution includes 550 parts of hydrofluoric acid with a mass percentage of 49% and 50 parts of water; the temperature of the above alkali polishing treatment is 75 °C, and the alkali polishing solution includes 22 parts of KOH solution with a mass percentage of 45%, 4 parts of alkali polishing additive, and 470 parts of water. Among them, the alkali polishing additive includes a surfactant with a mass percentage of 3%, a defoaming agent with a mass percentage of 2.2%, an antifoaming agent with a mass percentage of 3%, glucose with a mass percentage of 2.5%, sodium polystyrene sulfonate with a mass percentage of 2.2%, and water with a mass percentage of 85%. The surfactant is sodium lauryl polyoxyethylene ether sulfate, the defoaming agent is oxypropylene glycerol ether, and the antifoaming agent is polydimethylsiloxane;

[0112] (4) Perform Low Pressure Chemical Vapor Deposition (LPCVD) on the boron-doped N-type silicon wafer, introduce 300 L of oxygen at a flow rate of 40 L / min, and act at a temperature of 610 °C and a pressure of 800 mbar for 20 min to form a silicon dioxide layer with a thickness of 2.5 nm on the back side as the tunneling oxide layer;

[0113] (5) After forming the tunneling oxide layer, at a temperature of 615 °C and a pressure of 28 mbar, introduce silane with a flow rate of 1100 sccm and continue for 1850 s to prepare a polysilicon layer with a thickness of 125 nm as the polysilicon passivation layer;

[0114] (6) Place the silicon wafer at a temperature of 790 °C, POCl 3 Deposit for 16 min under the conditions of a flow rate of 1300 sccm / min, an oxygen flow rate of 650 sccm / min, and a pressure of 150 mbar. Then, heat the silicon wafer to 880 °C and perform a high-temperature drive-in treatment for 30 min to complete high-concentration doping of the polysilicon passivation layer to obtain a phosphorus-doped polysilicon layer;

[0115] (7) Face the front side of the silicon wafer that has completed phosphorus doping and perform chain pickling to remove the phosphorus-silicate glass layer on the front side. Among them, the pickling solution in the chain pickling uses hydrofluoric acid with a mass percentage of 9%;

[0116] (8), After removing the phosphosilicate glass layer on the front side, the silicon wafer is subjected to alkali etching treatment to remove the polysilicon layer plated around the front side. Among them, by volume, the above alkali etching solution includes 17 parts of a KOH solution with a mass percentage of 45%, 4 parts of an etching additive, and 450 parts of water. Among them, the etching additive includes a surfactant with a mass percentage of 1.8%, a defoaming agent with a mass percentage of 2.6%, an antifoaming agent with a mass percentage of 2.2%, glucose with a mass percentage of 3.0%, sodium dodecyl sulfate with a mass percentage of 1.5%, and water with a mass percentage of 85%. The surfactant is sodium lauryl polyoxyethylene ether sulfate, the defoaming agent is oxypropylene glycerol ether, and the antifoaming agent is octylphenol polyoxyethylene ether;

[0117] (9), The silicon wafer is subjected to the ALD process to deposit aluminum oxide film layers on both sides, with a thickness of 3.5 nm;

[0118] (10), Deposit a silicon nitride layer with a thickness of 76 nm on the front side; deposit a silicon nitride layer with a thickness of 80 nm on the back side;

[0119] (11), Prepare the front and back metal electrodes. The front and back main grids use silver paste, the front sub-grid uses silver-aluminum paste, and the back sub-grid uses silver paste, and then sinter at 810 °C for 50 s.

[0120] Repeat the above Comparative Example 1 to prepare 3700 N-type TOPCon cells, perform electrical performance tests on each cell and calculate the average value, and the results are shown in Table 1.

[0121] Table 1

[0122] Experiment Qty Eta(%) Uoc(mv) Isc(A) FF(%) Example 1 4500 25.65 726.3 13.9020 84.63 Comparative Example 1 3700 25.51 724.9 13.9013 84.30

[0123] Experiments show that for the N-type TOPCon cells provided in the embodiments of the present invention, by additionally growing a polysilicon transition layer and a mask oxide layer between the tunneling oxide layer and the phosphorus-doped polysilicon layer, and using the mask oxide layer as the first barrier to hinder the advancement of phosphorus atoms, the open-circuit voltage is increased by 1.4 mV, the fill factor is increased by 0.33%, and the photoelectric conversion efficiency is increased by 0.14%.

[0124] In summary, in this embodiment, the provided N-type TOPCon cell includes an N-type silicon substrate and a tunneling oxide layer, a polysilicon transition layer, a masking oxide layer, a phosphorus-doped polysilicon layer, and an electrode that are sequentially deposited on the back surface of the silicon substrate. Among them, a polysilicon transition layer and a masking oxide layer are additionally provided between the tunneling oxide layer and the phosphorus-doped polysilicon layer. The masking oxide layer is used as the first barrier during the process of hindering the advancement of phosphorus atoms, so that the doping concentration of phosphorus atoms in the polysilicon transition layer is relatively low. Combined with the tunneling oxide layer, which serves as the second barrier during the process of hindering the advancement of phosphorus atoms, it is thus possible to increase the doping concentration of phosphorus atoms in the phosphorus-doped polysilicon layer while effectively reducing the number of phosphorus atoms in the silicon matrix, thereby further improving the open-circuit voltage and photoelectric conversion efficiency of the cell.

[0125] Although the preferred embodiments of the embodiments of the present invention have been described, those skilled in the art can make additional changes and modifications once they learn the basic creative concepts. Therefore, the claims are intended to be construed as including the preferred embodiments and all changes and modifications that fall within the scope of the embodiments of the present invention.

[0126] The above provides a detailed introduction to an N-type TOPCon cell and its preparation method provided by the present invention. Specific examples are used in this article to elaborate on the principle and implementation manner of the present invention. The description of the above embodiments is only used to help understand the method and its core idea of the present invention; at the same time, for those of ordinary skill in the art, according to the idea of the present invention, there will be changes in the specific implementation manner and application scope. In summary, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. An N-type TOPCon cell, characterized in that, it includes an N-type silicon substrate and a tunneling oxide layer, a polysilicon transition layer, a mask oxide layer, a phosphorus-doped polysilicon layer, and an electrode that are sequentially deposited on the back surface of the silicon substrate.

2. The N-type TOPCon cell according to claim 1, characterized in that, The doping concentration of phosphorus atoms in the phosphorus-doped polysilicon layer is 8E20 to 10E20 / cm 3 .

3. The N-type TOPCon cell according to claim 1, characterized in that, the mask oxide layer includes a silicon dioxide layer with a thickness of 0.5 - 1.0 nm.

4. The N-type TOPCon cell according to claim 1, characterized in that, The doping concentration of phosphorus atoms in the polysilicon transition layer is 2E20 to 3E20 / cm 3 .

5. The N-type TOPCon cell according to claim 1, characterized in that, the thickness of the polysilicon transition layer is 10 - 20 nm.

6. The N-type TOPCon cell according to claim 1, characterized in that, the tunneling oxide layer includes a silicon dioxide layer with a thickness of 1.5 - 3 nm, and / or the thickness of the phosphorus-doped polysilicon layer is 90 - 110 nm.

7. A method for manufacturing an N-type TOPCon cell, characterized in that, it includes: after texturing, boron doping, and removing the boron-silicon glass layer on the back surface of an N-type silicon wafer in sequence, a tunneling oxide layer, a polysilicon transition layer, a mask oxide layer, and a polysilicon passivation layer are formed on the back surface in sequence; phosphorus doping is performed on the polysilicon passivation layer to form a phosphorus-doped polysilicon layer; the phosphorus-silicon glass layer on the front surface, the over-deposited polysilicon layer on the front surface, the boron-silicon glass layer on the front surface, and the phosphorus-silicon glass layer on the back surface are removed in sequence; after removing the phosphorus-silicon glass layer on the back surface, a passivation film layer, a front anti-reflection film layer, a back anti-reflection film layer, and an electrode are formed on the silicon wafer in sequence.

8. The manufacturing method according to claim 7, characterized in that, forming a tunneling oxide layer, a polysilicon transition layer, a mask oxide layer, and a polysilicon passivation layer on the back surface in sequence includes: forming a silicon dioxide layer with a thickness of 1.5 - 3 nm on the back surface as the tunneling oxide layer; forming a polysilicon layer with a thickness of 10 - 20 nm on the surface of the tunneling oxide layer as the polysilicon transition layer; forming a silicon dioxide layer with a thickness of 0.5 - 1.0 nm on the surface of the polysilicon transition layer as the mask oxide layer; forming a polysilicon layer with a thickness of 90 - 110 nm on the surface of the mask oxide layer as the polysilicon passivation layer.

9. The manufacturing method according to claim 7, characterized in that, phosphorus doping is performed on the polysilicon passivation layer to form a phosphorus-doped polysilicon layer, including: Deposit for 14 - 20 min under the conditions of a temperature of 785 - 805 °C, a flow rate of POCl 3 of 1300 - 1700 sccm / min, an oxygen flow rate of 500 - 700 sccm / min, and a pressure of 120 - 180 mbar. Then, heat the silicon wafer to 895 - 920 °C for high-temperature drive-in treatment for 20 - 35 min to obtain a phosphorus-doped polysilicon layer.

10. The manufacturing method according to claim 7, characterized in that, removing the phosphorus-silicon glass layer on the front surface, the over-deposited polysilicon layer on the front surface, the boron-silicon glass layer on the front surface, and the phosphorus-silicon glass layer on the back surface in sequence includes: performing chain pickling on the front surface of the silicon wafer to remove the phosphorus-silicon glass layer on the front surface; after removing the phosphorus-silicon glass layer on the front surface, performing alkali etching treatment on the front surface of the silicon wafer to remove the over-deposited polysilicon layer on the front surface; after removing the over-deposited polysilicon layer on the front surface, performing chain pickling on the front surface and the back surface of the silicon wafer to remove the boron-silicon glass layer on the front surface and the phosphorus-silicon glass layer on the back surface.

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