Display substrate and preparation method thereof, display panel and display device

Abstract

The invention discloses a display substrate and a preparation method thereof, a display panel and a display device. The display substrate comprises a substrate, and a driving circuit layer and a conductive layer which are sequentially arranged on the substrate; the driving circuit layer comprises a plurality of pixel driving circuits; the conductive layer comprises a plurality of bonding pad groups arranged in an array and at least one power transmission line, each bonding pad group comprises three bonding pads, a single bonding pad is connected with a single pixel driving circuit, and the single bonding pad is configured to be connected with a first pole pin of a single light-emitting device; the power transmission line is configured to be connected with the second pole pin of the light-emitting device so as to transmit the first level signal to the light-emitting device.

Description

Technical Field

[0001] This application relates to, but is not limited to, display technologies, and particularly to a display substrate, a method for manufacturing the same, a display panel, and a display device. Background Art

[0002] The technology of Light Emitting Diode (LED) has developed for nearly thirty years. From the initial solid-state lighting power source to the backlight source in the display field and then to the LED display screen, it provides a solid foundation for its wider applications. Among them, with the development of chip manufacturing and packaging technologies, Mini Light Emitting Diode (Mini LED) display and Micro Light Emitting Diode (Micro LED) display have gradually become a hot spot in display panels and can be applied in fields such as AR / VR, TV, and outdoor displays.

[0003] MIP (Micro / Mini LED in Package) packaging technology is a new packaging technology based on Mini Light Emitting Diode or Micro Light Emitting Diode. By separately packaging a large-area integral display panel, it realizes the organic combination of light-emitting diodes and discrete devices. The MIP packaging technology has advantages such as light mixing, high uniformity, no Mura effect, etc., and does not require high-cost repair. It can directly perform test sorting, which can reduce the difficulty of point measurement sorting and lower production costs. Moreover, the MIP packaging technology can package smaller-sized LED chips, and the size of the lamp beads used and the gap between the lamp beads can be smaller, which helps to improve the pixel density of the display panel and enhance the display effect. The display substrate adopting the MIP display solution is increasingly favored by users.

[0004] It is found by the inventors of this application that currently, there are few designs of display substrates that can implement the MIP display solution. Summary of the Invention

[0005] The present disclosure provides a display substrate, a method for manufacturing the same, a display panel, and a display device, which can be used to solve the problem that there are few designs of display substrates that can implement the MIP display solution.

[0006] In a first aspect, an embodiment of the present disclosure provides a display substrate, including: a substrate, a driving circuit layer, and a conductive layer sequentially disposed on the substrate; the driving circuit layer includes a plurality of pixel driving circuits; the conductive layer includes a plurality of pad groups arranged in an array and at least one power transmission line, each pad group includes three pads, a single pad is connected to a single pixel driving circuit, and a single pad is configured to be connected to a first pole pin of a single light-emitting device; the power transmission line is configured to be connected to a second pole pin of the light-emitting device to transmit a first-level signal to the light-emitting device.

[0007] In an exemplary embodiment, the plurality of pad groups include a plurality of rows of pad groups extending in a first direction and a plurality of columns of pad groups extending in a second direction, and the first direction and the second direction intersect; in a plane parallel to the display substrate, the display substrate includes a plurality of first display regions, the first display regions extend in the first direction, and a single first display region includes a single row of the pad groups.

[0008] In an exemplary embodiment, the conductive layer further includes a plurality of pairs of fifth pads and sixth pads, and the sixth pads are connected to the power transmission line; in a plane parallel to the display substrate, the display substrate further includes a plurality of second display regions, the second display regions extend in the first direction, and a single second display region includes a plurality of groups of the fifth pads and the sixth pads extending in the first direction; the first display regions and the second display regions are alternately arranged in the second direction.

[0009] In an exemplary embodiment, a single pad group includes a first pad, a second pad, and a third pad, and the first pad, the second pad, and the third pad are arranged in a "pin" shape; the first pad is configured to be connected to a first light-emitting device, the second pad is configured to be connected to a second light-emitting device, and the third pad is configured to be connected to a third light-emitting device.

[0010] In an exemplary embodiment, in the second direction, a single group of the fifth pads and the sixth pads is arranged in pairs with a single pad group; the fifth pad is configured to be connected to a first pole pin of a fourth light-emitting device, and the sixth pad is configured to be connected to a second pole pin of the fourth light-emitting device; the color of the first light-emitting device is the same as the color of the fourth light-emitting device.

[0011] In an exemplary embodiment, the paired first pads are connected to each other, or the pixel driving circuit of the paired first pads is connected to the fifth pads.

[0012] In an exemplary embodiment, a protective layer is further included, and the protective layer is disposed on a side of the conductive layer away from the substrate; the protective layer includes a plurality of vias, and surfaces of the first pad, the second pad, the third pad, the fifth pad, the sixth pad, and at least one power transmission line are respectively exposed by the plurality of vias.

[0013] In an exemplary embodiment, the fifth pad is connected to the corresponding pixel driving circuit, a single set of the fifth pad and the sixth pad is connected to a single light-emitting device, the fifth pad is configured to be connected to a first pole pin of the light-emitting device, and the sixth pad is configured to be connected to a second pole pin of the light-emitting device.

[0014] In an exemplary embodiment, colors of the light-emitting devices connected within a single second display area are the same, and colors of the light-emitting devices connected in adjacent second display areas are different.

[0015] In an exemplary embodiment, a plurality of light-emitting devices of different colors are connected within a single second display area, and the light-emitting devices of different colors are alternately arranged in sequence; in the second direction, colors of a plurality of the light-emitting devices in the same column are the same.

[0016] In an exemplary embodiment, a plurality of light-emitting devices of different colors are connected within a single second display area, and the light-emitting devices of different colors are alternately arranged in sequence; in the same column along the second direction, the light-emitting devices of different colors are alternately arranged in sequence.

[0017] In an exemplary embodiment, a protective layer is further included, and the protective layer is disposed on a side of the conductive layer away from the substrate; the protective layer includes a plurality of vias, and surfaces of the fifth pad, the sixth pad, and at least one power transmission line are respectively exposed by the plurality of vias.

[0018] In a second aspect, an embodiment of the present disclosure provides a method for manufacturing a display substrate, including: forming a driving circuit layer on a substrate, the driving circuit layer including a plurality of pixel driving circuits; forming a conductive layer on the driving circuit layer; the conductive layer includes a plurality of pad groups arranged in an array and at least one power transmission line, each pad group includes three pads, a single pad is connected to a single pixel driving circuit, and a single pad is configured to be connected to a first pole pin of a single light-emitting device; the power transmission line is configured to be connected to a second pole pin of the light-emitting device to transmit a first level signal to the light-emitting device.

[0019] In a third aspect, an embodiment of the present disclosure provides a display panel, including the display substrate as described above.

[0020] Fourthly, an embodiment of the present disclosure provides a display device, including the display panel as described above.

[0021] For the display substrate proposed by the embodiment of the present disclosure, by dividing a plurality of pad groups on the display substrate, and using three pads provided in each pad group to be respectively connected to the first pole pins of different light-emitting devices, and using a power transmission line to be connected to the second pole pins of the light-emitting devices, it is possible to package three light-emitting devices connected within a single pad group by using the MIP packaging technology, thereby implementing the MIP display solution. The problem that there are few designs of display substrates capable of implementing the MIP display solution is solved.

[0022] Other aspects can be understood after reading and understanding the drawings and the detailed description. Description of the Drawings

[0023] The drawings are used to provide an understanding of the technical solutions of the present disclosure, and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solutions of the present disclosure, and do not constitute a limitation to the technical solutions of the present disclosure.

[0024] Figure 1 It is a schematic structural diagram of a display panel;

[0025] Figure 2 It is a schematic plan view of a display panel;

[0026] Figure 3 It is a schematic equivalent circuit diagram of a pixel driving circuit;

[0027] Figure 4 It is a schematic plan view of a display substrate in an exemplary embodiment;

[0028] Figure 5 It is a schematic plan view of a display substrate in another exemplary embodiment;

[0029] Figure 6 For Figure 5 a cross-sectional view of the display substrate in along the A-A direction;

[0030] Figure 7 For Figure 5 a plan view of the display panel formed by the display substrate in ;

[0031] Figure 8 It is a schematic plan view of a display panel in another exemplary embodiment;

[0032] Figure 9 It is a schematic plan view of a display panel in another exemplary embodiment;

[0033] Figure 10 It is a schematic plan view of a display panel in another exemplary embodiment. Detailed implementation manners

[0034] The present disclosure describes multiple embodiments, but the description is exemplary rather than restrictive, and it will be apparent to those of ordinary skill in the art that there can be more embodiments and implementation solutions within the scope covered by the embodiments described in the present disclosure. Although many possible combinations of features are shown in the drawings and discussed in the detailed implementation manners, many other combination ways of the disclosed features are also possible. Unless specifically restricted, any feature or element of any embodiment can be combined with any other feature or element in any other embodiment, or can replace any other feature or element in any other embodiment.

[0035] The present disclosure includes and contemplates combinations with features and elements known to those of ordinary skill in the art. The embodiments, features, and elements already disclosed in the present disclosure can also be combined with any conventional features or elements to form unique inventive solutions defined by the claims. Any feature or element of any embodiment can also be combined with features or elements from other inventive solutions to form another unique inventive solution defined by the claims. Therefore, it should be understood that any feature shown and / or discussed in the present disclosure can be implemented alone or in any suitable combination. Therefore, the embodiments are not subject to other limitations except those made according to the appended claims and their equivalents. In addition, various modifications and changes can be made within the scope of protection of the appended claims.

[0036] In addition, when describing representative embodiments, the specification may have presented the method and / or process as a specific sequence of steps. However, to the extent that the method or process does not depend on the specific sequence of steps described herein, the method or process should not be limited to the specific sequence of steps described. As will be understood by those of ordinary skill in the art, other step sequences are possible. Therefore, the specific sequence of steps set forth in the specification should not be construed as a limitation on the claims. In addition, the claims directed to the method and / or process should not be limited to performing their steps in the order written, and those skilled in the art can easily understand that these orders can be varied and still remain within the spirit and scope of the embodiments of the present disclosure.

[0037] In the drawings, sometimes for clarity, the sizes of one or more constituent elements, the thicknesses of layers, or regions are exaggerated. In addition, the drawings schematically show ideal examples, and one aspect of the present disclosure is not limited to the shapes, values, etc. shown in the drawings.

[0038] The ordinal numbers such as "first", "second", "third", etc. in this specification are set to avoid confusion of components, rather than to limit the quantity. "Plurality" in the present disclosure means two or more quantities.

[0039] In this specification, for convenience, terms indicating orientation or positional relationship such as "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. are used to describe the positional relationship of components with reference to the accompanying drawings. This is only for the convenience of describing this specification and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation on the present disclosure. The positional relationship of components changes appropriately according to the direction of the described components. Therefore, it is not limited to the terms described in the specification and can be replaced appropriately according to the circumstances.

[0040] In this specification, unless otherwise clearly defined and limited, the terms "mounted", "connected", and "coupled" shall be understood in a broad sense. For example, it may be a fixed connection, a detachable connection, or an integral connection; it may be a mechanical connection or an electrical connection; it may be directly connected, or indirectly connected through an intermediate member, or the internal communication of two elements. For those of ordinary skill in the art, the meanings of the above terms in the present disclosure can be understood according to the circumstances.

[0041] In this specification, a transistor refers to an element including at least three terminals: a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain) and the source electrode (source electrode terminal, source region, or source), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region where current mainly flows.

[0042] In this specification, the first pole of the transistor can be the drain electrode, and the second pole of the transistor can be the source electrode, or the first pole of the transistor can be the source electrode, and the second pole of the transistor can be the drain electrode. In the case of using transistors with opposite polarities or when the current direction changes during circuit operation, etc., the functions of the "source electrode" and "drain electrode" sometimes swap. Therefore, in this specification, the "source electrode" and "drain electrode" can be swapped with each other, and the "source terminal" and "drain terminal" can be swapped with each other.

[0043] In this specification, "connection" includes cases where constituent elements are connected together through elements having a certain electrical effect. The "elements having a certain electrical effect" are not particularly limited as long as they can transmit electrical signals between the constituent elements to be connected. Examples of the "elements having a certain electrical effect" include not only electrodes and wirings, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.

[0044] In this specification, "parallel" means a state where the angle formed by two straight lines is -10° or more and 10° or less. Therefore, it also includes a state where the angle is -5° or more and 5° or less. In addition, "perpendicular" means a state where the angle formed by two straight lines is 80° or more and 100° or less. Therefore, it also includes a state where the angle is 85° or more and 95° or less.

[0045] In this specification, "film" and "layer" can be interchanged. For example, sometimes "conductive layer" can be changed to "conductive film". Similarly, sometimes "insulating film" can be changed to "insulating layer".

[0046] In this disclosure, "thickness" and "height" refer to the vertical distance between the surface on the side away from the substrate and the surface on the side close to the substrate of the film layer.

[0047] Triangles, rectangles, trapezoids, pentagons, hexagons, etc. in this specification are not strictly defined and can be approximate triangles, rectangles, trapezoids, pentagons, hexagons, etc. There can be some small deformations caused by tolerances, and there can be chamfers, arc edges, and deformations, etc.

[0048] "About" in this disclosure means not strictly defining the boundary and allowing values within the process and measurement error range.

[0049] Embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.

[0050] Figure 1 It is a schematic structural diagram of a display panel, such as Figure 1As shown, in a plane perpendicular to the display panel, the display panel may at least include a driving circuit layer 20 disposed on a substrate 10 and a light-emitting structure layer 30 disposed on a side of the driving circuit layer 20 away from the substrate 10. In a plane parallel to the display panel, the driving circuit layer 20 may include a plurality of circuit units, and at least one circuit unit may include a pixel driving circuit and a plurality of signal lines connected to the pixel driving circuit. The pixel driving circuit is configured to receive a data voltage under the control of the signal lines and output a corresponding current. The light-emitting structure layer 30 may include a plurality of light-emitting units, and at least one light-emitting unit may include a light-emitting diode 40. The light-emitting diodes 40 in the plurality of light-emitting units are correspondingly connected to the pixel driving circuits in the plurality of circuit units. The light-emitting diode 40 is configured to emit light with a corresponding brightness under the drive of the current output by the corresponding pixel driving circuit.

[0051] In an exemplary embodiment, the circuit unit referred to in the present disclosure refers to a region divided according to the pixel driving circuit, and the light-emitting unit referred to in the present disclosure refers to a region divided according to the light-emitting diode. In an exemplary embodiment, the positions of the light-emitting unit and the circuit unit may be corresponding, or the positions of the light-emitting unit and the circuit unit may not be corresponding. The present disclosure does not make a limitation here.

[0052] In an exemplary embodiment, the light-emitting diode 40 may be a submillimeter light-emitting diode Mini LED or a micro light-emitting diode Micro LED.

[0053] Figure 2 is a schematic plan view of a display panel. As Figure 2 shown, in a plane parallel to the display panel, the display panel may include a first sub-pixel P1 that emits first-color light, a second sub-pixel P2 that emits second-color light, and a third sub-pixel P3 that emits third-color light. In an exemplary embodiment, each sub-pixel may include a circuit unit and a light-emitting unit. The first sub-pixel P1 may include a first circuit unit and a first light-emitting unit. The first light-emitting unit may at least include a first light-emitting diode that emits first-color light. The first circuit unit may at least include a first pixel driving circuit connected to the first light-emitting diode. The second sub-pixel P2 may include a second circuit unit and a second light-emitting unit. The second light-emitting unit may at least include a second light-emitting diode that emits second-color light. The second circuit unit may at least include a second pixel driving circuit connected to the second light-emitting diode. The third sub-pixel P3 may include a third circuit unit and a third light-emitting unit. The third light-emitting unit may at least include a third light-emitting diode that emits third-color light. The third circuit unit may at least include a third pixel driving circuit connected to the third light-emitting diode.

[0054] In an exemplary embodiment, the first sub-pixel P1 may be a red (R) sub-pixel that emits red light, the second sub-pixel P2 may be a green sub-pixel (G) that emits green light, and the third sub-pixel P3 may be a blue (B) sub-pixel that emits blue light. The R sub-pixel, G sub-pixel, and B sub-pixel may form a pixel unit P. In an exemplary embodiment, the three sub-pixels in the pixel unit P may be arranged in a horizontal side-by-side, vertical side-by-side, or triangular pattern, etc., and the present disclosure does not limit this here.

[0055] In an exemplary embodiment, the pixel unit P may include four sub-pixels, and the four sub-pixels may be arranged in a horizontal side-by-side, vertical side-by-side, square, or diamond pattern, etc., and the present disclosure does not limit this here.

[0056] Figure 3 It is a schematic equivalent circuit diagram of a pixel driving circuit. In an exemplary embodiment, the pixel driving circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, or 7T1C structure or other pixel circuits, not limited to Figure 3 the pixel circuit structure shown. As Figure 3 shown, the pixel driving circuit may include seven transistors (the first transistor T1 to the seventh transistor T7) and one storage capacitor C. The pixel driving circuit is connected to seven signal lines (data signal line D, first scan signal line S1, second scan signal line S2, light-emitting signal line E, initial signal line INIT, first power supply line VDD, and second power supply line VSS).

[0057] In an exemplary embodiment, the pixel driving circuit may include a first node N1, a second node N2, and a third node N3. Among them, the first node N1 is respectively connected to the first pole of the third transistor T3, the second pole of the fourth transistor T4, and the second pole of the fifth transistor T5. The second node N2 is respectively connected to the second pole of the first transistor, the first pole of the second transistor T2, the control pole of the third transistor T3, and the second end of the storage capacitor C. The third node N3 is respectively connected to the second pole of the second transistor T2, the second pole of the third transistor T3, and the first pole of the sixth transistor T6.

[0058] In an exemplary embodiment, the first end of the storage capacitor C is connected to the first power supply line VDD, and the second end of the storage capacitor C is connected to the second node N2, that is, the second end of the storage capacitor C is connected to the control pole of the third transistor T3.

[0059] The control electrode of the first transistor T1 is connected to the second scan signal line S2, the first electrode of the first transistor T1 is connected to the initial signal line INIT, and the second electrode of the first transistor is connected to the second node N2. When a conductive-level scan signal is applied to the second scan signal line S2, the first transistor T1 transfers an initialization voltage to the control electrode of the third transistor T3 to initialize the electric charge amount at the control electrode of the third transistor T3.

[0060] The control electrode of the second transistor T2 is connected to the first scan signal line S1, the first electrode of the second transistor T2 is connected to the second node N2, and the second electrode of the second transistor T2 is connected to the third node N3. When a conductive-level scan signal is applied to the first scan signal line S1, the second transistor T2 connects the control electrode and the second electrode of the third transistor T3.

[0061] The control electrode of the third transistor T3 is connected to the second node N2, that is, the control electrode of the third transistor T3 is connected to the second end of the storage capacitor C. The first electrode of the third transistor T3 is connected to the first node N1, and the second electrode of the third transistor T3 is connected to the third node N3. The third transistor T3 can be referred to as a driving transistor. The third transistor T3 determines the amount of driving current flowing between the first power supply line VDD and the second power supply line VSS according to the potential difference between its control electrode and the first electrode.

[0062] The control electrode of the fourth transistor T4 is connected to the first scan signal line S1, the first electrode of the fourth transistor T4 is connected to the data signal line D, and the second electrode of the fourth transistor T4 is connected to the first node N1. When a conductive-level scan signal is applied to the first scan signal line S1, the fourth transistor T4 inputs the data voltage of the data signal line D into the pixel driving circuit.

[0063] The control electrode of the fifth transistor T5 is connected to the light-emitting signal line E, the first electrode of the fifth transistor T5 is connected to the first power supply line VDD, and the second electrode of the fifth transistor T5 is connected to the first node N1. The control electrode of the sixth transistor T6 is connected to the light-emitting signal line E, the first electrode of the sixth transistor T6 is connected to the third node N3, and the second electrode of the sixth transistor T6 is connected to the first electrode of the light-emitting device. When a conductive-level light-emitting signal is applied to the light-emitting signal line E, the fifth transistor T5 and the sixth transistor T6 cause the light-emitting device to emit light by forming a driving current path between the first power supply line VDD and the second power supply line VSS.

[0064] The control electrode of the seventh transistor T7 is connected to the second scan signal line S2, the first electrode of the seventh transistor T7 is connected to the initial signal line INIT, and the second electrode of the seventh transistor T7 is connected to the first electrode of the light-emitting device. When a conduction-level scan signal is applied to the second scan signal line S2, the seventh transistor T7 transfers an initialization voltage to the first electrode of the light-emitting device to initialize the electric charge accumulated in the first electrode of the light-emitting device or release the electric charge accumulated in the first electrode of the light-emitting device.

[0065] In an exemplary embodiment, the light-emitting device may be an LED.

[0066] In an exemplary embodiment, the second electrode of the light-emitting device is connected to the second power supply line VSS, the signal of the second power supply line VSS is a low-level signal, and the signal of the first power supply line VDD is a continuously provided high-level signal. The first scan signal line S1 is a scan signal line in the pixel driving circuit of the current display row, and the second scan signal line S2 is a scan signal line in the pixel driving circuit of the previous display row. That is, for the nth display row, the first scan signal line S1 is S(n), and the second scan signal line S2 is S(n - 1). The second scan signal line S2 of the current display row and the first scan signal line S1 in the pixel driving circuit of the previous display row are the same signal line, which can reduce the signal lines of the display panel and achieve a narrow bezel of the display panel.

[0067] In an exemplary embodiment, the first transistor T1 to the seventh transistor T7 may be P-type transistors, or may be N-type transistors. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the process difficulty of the display panel, and improve the yield of the product. In some possible implementation manners, the first transistor T1 to the seventh transistor T7 may include P-type transistors and N-type transistors.

[0068] In an exemplary embodiment, the first transistor T1 to the seventh transistor T7 may adopt low-temperature polycrystalline silicon thin-film transistors, or may adopt oxide thin-film transistors, or may adopt low-temperature polycrystalline silicon thin-film transistors and oxide thin-film transistors. The active layer of the low-temperature polycrystalline silicon thin-film transistor uses low-temperature poly-silicon (LTPS for short), and the active layer of the oxide thin-film transistor uses oxide semiconductor (Oxide). The low-temperature polycrystalline silicon thin-film transistor has advantages such as high mobility and fast charging, and the oxide thin-film transistor has advantages such as low leakage current. Integrating the low-temperature polycrystalline silicon thin-film transistor and the oxide thin-film transistor on a display substrate to form a low-temperature polycrystalline oxide (LTPO) display substrate can utilize the advantages of both, can achieve low-frequency driving, can reduce power consumption, and can improve display quality.

[0069] An embodiment of the present disclosure provides a display substrate, including: a substrate, a driving circuit layer, and a conductive layer sequentially disposed on the substrate; the driving circuit layer includes a plurality of pixel driving circuits; the conductive layer includes a plurality of pad groups arranged in an array and at least one power transmission line, each pad group includes three pads, a single pad is connected to a single pixel driving circuit, and a single pad is configured to be connected to a first pole pin of a single light-emitting device; the power transmission line is configured to be connected to a second pole pin of the light-emitting device to transmit a first-level signal to the light-emitting device.

[0070] In the display substrate provided by the embodiment of the present disclosure, by dividing a plurality of pad groups on the display substrate, using three pads provided in the pad group to be respectively connected to the first pole pins of different light-emitting devices, and using the power transmission line to be connected to the second pole pins of the light-emitting devices, it is possible to package three light-emitting devices connected within a single pad group by using the MIP packaging technology, thereby implementing the MIP display solution.

[0071] In an exemplary embodiment, the plurality of pad groups include a plurality of pad group rows extending in a first direction and a plurality of pad group columns extending in a second direction, and the first direction and the second direction intersect; in a plane parallel to the display substrate, the display substrate includes a plurality of first display regions, the first display regions extend in the first direction, and a single first display region includes a single pad group row.

[0072] In an exemplary embodiment, the conductive layer further includes a plurality of pairs of fifth pads and sixth pads, the sixth pads are connected to the power transmission line; in a plane parallel to the display substrate, the display substrate further includes a plurality of second display regions, the second display regions extend in the first direction, and a single second display region includes a plurality of groups of the fifth pads and the sixth pads extending in the first direction; the first display regions and the second display regions are alternately arranged in the second direction.

[0073] In an exemplary embodiment, a single pad group includes a first pad, a second pad, and a third pad, and the first pad, the second pad, and the third pad are arranged in a "pin" shape; the first pad is configured to be connected to a first light-emitting device, the second pad is configured to be connected to a second light-emitting device, and the third pad is configured to be connected to a third light-emitting device.

[0074] In an exemplary embodiment, in the second direction, a single set of the fifth pad and the sixth pad are arranged in pairs with a single one of the pads; the fifth pad is configured to be connected to a first pole pin of a fourth light-emitting device, and the sixth pad is configured to be connected to a second pole pin of the fourth light-emitting device; the color of the first light-emitting device is the same as the color of the fourth light-emitting device.

[0075] In this embodiment, the color of the first light-emitting device is the same as the color of the fourth light-emitting device, and the fourth light-emitting device can perform light-emitting compensation on the first light-emitting device, thereby improving the display effect.

[0076] In an exemplary embodiment, the first pad and the fifth pad arranged in pairs are connected to each other, or the pixel driving circuit of the first pad arranged in pairs is connected to the fifth pad.

[0077] In this embodiment, the first pad and the fifth pad share the same pixel driving circuit, which can save the layout space of the pixel driving circuits in the driving circuit layer.

[0078] In an exemplary embodiment, a protective layer is further included, and the protective layer is disposed on a side of the conductive layer away from the substrate; the protective layer includes a plurality of vias, and the surfaces of the first pad, the second pad, the third pad, the fifth pad, the sixth pad, and at least one of the power transmission lines are respectively exposed by the plurality of vias.

[0079] In an exemplary embodiment, the fifth pad is connected to the corresponding pixel driving circuit, a single set of the fifth pad and the sixth pad are connected to a single light-emitting device, the fifth pad is configured to be connected to a first pole pin of the light-emitting device, and the sixth pad is configured to be connected to a second pole pin of the light-emitting device.

[0080] In this embodiment, the fifth pad in the second display area is connected to its own pixel driving circuit, and can emit light independently. Based on the MIP display scheme, a display scheme using the light-emitting devices in the second display area for display can be supported, so that the display substrate can support two different display schemes.

[0081] In an exemplary embodiment, the colors of the light-emitting devices connected in a single second display area are the same, and the colors of the light-emitting devices connected in adjacent second display areas are different.

[0082] In an exemplary embodiment, a single second display area is connected with a plurality of light-emitting devices of different colors, and the light-emitting devices of different colors are arranged alternately in sequence; in the second direction, the colors of a plurality of the light-emitting devices in the same column are the same.

[0083] In an exemplary embodiment, a plurality of light-emitting devices of different colors are connected within a single second display area, and the light-emitting devices of different colors are arranged alternately in sequence; within the same column along the second direction, the light-emitting devices of different colors are arranged alternately in sequence.

[0084] In an exemplary embodiment, it further includes a protective layer, and the protective layer is disposed on a side of the conductive layer away from the substrate; the protective layer includes a plurality of vias, and the plurality of vias respectively expose the surfaces of the fifth pad, the sixth pad, and at least one power transmission line.

[0085] Figure 4 It is a schematic plan view of a display substrate in an exemplary embodiment. As Figure 4 shown, within a plane parallel to the display substrate, the display substrate includes a plurality of pad groups arranged in an array. The plurality of pad groups arranged in an array include a plurality of rows of pad groups extending along a first direction X and a plurality of columns of pad groups extending along a second direction Y. The first direction X and the second direction Y intersect. Among them, each pad group includes a first pad 61, a second pad 62, and a third pad 63 arranged in a "pin" shape. The first pad 61, the second pad 62, and the third pad 63 are respectively connected to their corresponding pixel driving circuits. The display substrate further includes at least one power transmission line 70. The power transmission line 70 can be configured to transmit a first-level signal, and the first-level signal can be a low-level signal. For example, the power transmission line 70 can be a second power supply line, or can be configured to be connected to the second power supply line. In an exemplary embodiment, the light-emitting device can include two pins (a first pole pin and a second pole pin). The first pole pin can be, for example, a positive pole pin, and the second pole pin can be, for example, a negative pole pin. When installing the light-emitting device subsequently, the first pad 61 can be connected to the first pole pin of the first light-emitting device, the second pad 62 can be connected to the first pole pin of the second light-emitting device, the third pad 63 can be connected to the first pole pin of the third light-emitting device, and the second pole pins of the plurality of light-emitting devices can be respectively connected to the power transmission line 70. The three pads within a single pad group can be respectively connected to light-emitting devices of three different colors. For example, the first light-emitting device can be a blue light-emitting device, the second light-emitting device can be a green light-emitting device, and the third light-emitting device can be a red light-emitting device.

[0086] In an exemplary embodiment, the first light-emitting device, the second light-emitting device, and the third light-emitting device can be sub-millimeter light-emitting diodes or micro light-emitting diodes, and the three light-emitting devices connected to a single pad group can be packaged using MIP packaging technology.

[0087] In an exemplary embodiment, as Figure 4As shown, the display substrate may include a plurality of power transmission lines 70 whose main bodies extend along the second direction Y. The plurality of power transmission lines 70 may be disposed on both sides of the pad group along the first direction X to facilitate subsequent connection to the second pole pins of the light-emitting devices. In other embodiments, some of the plurality of power transmission lines 70 may be arranged to extend along the first direction X, and the remaining power transmission lines 70 of the plurality of power transmission lines 70 may be arranged to extend along the second direction Y. The plurality of power transmission lines 70 extending in different directions may intersect with each other to form a grid-like low-potential signal transmission structure, which helps to reduce the voltage drop during signal transmission. The number, arrangement, and connection relationship of the power transmission lines 70 may be set as needed, and the present disclosure does not limit this.

[0088] In an exemplary embodiment, as Figure 4 shown, a single pad group may further include a fourth pad 64. The first pad 61, the second pad 62, the third pad 63, and the fourth pad 64 within a single pad group may be arranged in an array. The fourth pad 64 may be connected to the power transmission line 70, or the fourth pad 64 and the power transmission line 70 may be set as an integrally connected structure. By providing the fourth pad 64, it is convenient to arrange the light-emitting devices within a single pad group subsequently.

[0089] In an exemplary embodiment, as Figure 4 shown, within a single pad group, the second pad 62 may be located on one side of the first pad 61 along the first direction X, the fourth pad 64 may be located on one side of the first pad 61 along the second direction Y, the third pad 63 may be located on one side of the second pad 62 along the second direction Y, and may be located on one side of the fourth pad 64 along the first direction X. The present disclosure does not limit this.

[0090] Figure 5 It is a schematic plan view of a display substrate in yet another exemplary embodiment. Figure 5 Compared with Figure 4 , the difference is that a plurality of pairs of fifth pads 65 and sixth pads 66 are added, and the remaining structures may refer to the description of Figure 4 , and will not be elaborated here.

[0091] As Figure 5As shown, the display substrate may include a plurality of first display regions C1 and a plurality of second display regions C2. The first display regions C1 may extend along a first direction X, and a single first display region C1 may include a single row of pad groups; the second display regions C2 may extend along the first direction X, and a single second display region C2 may include multiple sets of fifth pads 65 and sixth pads 66 arranged in pairs, and the multiple sets of fifth pads 65 and sixth pads 66 may be arranged in sequence along the first direction X. In the second direction Y, the first display regions C1 and the second display regions C2 may be alternately arranged with each other, and a single pair of the fifth pad 65 and the sixth pad 66 in the second display region C2 may be correspondingly arranged with a single pad group in an adjacent first display region C1. In a plane parallel to the display substrate, the multiple sets of fifth pads 65 and sixth pads 66 of the multiple second display regions C2 may be arranged in an array. In the second direction Y, a single set of the fifth pad 65 and the sixth pad 66 may be spaced apart within a single column of pad groups, and a single pad group may be arranged in pairs with an adjacent single set of the fifth pad 65 and the sixth pad 66.

[0092] In an exemplary embodiment, the sixth pad 66 may be located on one side of the fifth pad 65 along the first direction X. The sixth pad 66 may be connected to the power transmission line 70, or the sixth pad 66 and the power transmission line 70 may be provided as an integrally connected structure. The present disclosure does not limit this.

[0093] In an exemplary embodiment, when installing the light-emitting device subsequently, the fifth pad 65 may be connected to the first pole pin of the fourth light-emitting device, and the sixth pad 66 may be connected to the second pole pin of the fourth light-emitting device. The fourth light-emitting device may be arranged close to the first light-emitting device, and the fourth light-emitting device may be provided as a blue light-emitting device. Thus, during normal display, the fourth light-emitting device may perform brightness compensation on the first light-emitting device, which helps to improve the display defect caused by blue light attenuation. In this embodiment, by setting both the first display region C1 and the second display region C2 of the display substrate to perform display, and connecting the blue light-emitting device by using the pads provided in the second display region C2, it is possible to adopt MIP packaging for the first light-emitting device, the second light-emitting device, and the third light-emitting device, or it is possible to adopt MIP packaging for the first light-emitting device, the second light-emitting device, the third light-emitting device, and the fourth light-emitting device, realizing the MIP display scheme, which helps to increase the number of sub-pixels of the display panel and can improve the display defect caused by blue light attenuation. In other embodiments, the first light-emitting device and the fourth light-emitting device may be light-emitting devices of other colors. The present disclosure does not limit this.

[0094] In an exemplary embodiment, as Figure 5As shown, when the fourth light-emitting device is set as a blue light-emitting device, the fifth pad 65 and the adjacent first pad 61 can be set to be connected to each other, so that the fourth light-emitting device and the first light-emitting device can work synchronously, realizing light emission compensation for the blue light-emitting device. In other embodiments, the fifth pad 65 and the pixel driving circuit corresponding to the adjacent first pad 61 can also be set to be connected, and the present disclosure does not limit this.

[0095] In an exemplary embodiment, the fifth pad 65 can be connected to the pixel driving circuit corresponding to itself, and the sixth pad 66 can be connected to the power transmission line 70, so that the light-emitting device connected to the fifth pad 65 and the sixth pad 66 can emit light independently. When installing the light-emitting device subsequently, the light-emitting device can be installed only at the fifth pad 65 and the sixth pad 66, and no light-emitting device is installed in the first display area C1, and a display panel with a larger sub-pixel pitch can be obtained. The display panel of this display solution can be applicable to application scenarios where the distance between the observer and the display panel is relatively far, or application scenarios with low requirements for picture clarity. In this embodiment, by setting to use the second display area C2 of the display substrate for display and not using the first display area C1 for display, the application scenarios of the display substrate are expanded, and the pads that normally work on the display substrate and the positions for connecting the light-emitting devices can be selected according to actual needs, and the present disclosure does not limit this.

[0096] In an exemplary embodiment, the pads in a single second display area C2 can be configured to be connected to light-emitting devices of the same color, and the pads in the second display areas C2 adjacent in the second direction Y can be configured to be connected to light-emitting devices of different colors. For example, along the second direction Y, red light-emitting devices, green light-emitting devices, and blue light-emitting devices can be periodically arranged in multiple second display areas C2, and the present disclosure does not limit the color arrangement of the light-emitting devices in the multiple second display areas C2.

[0097] In an exemplary embodiment, the pads in a single second display area C2 can be configured to be connected to multiple different-color light-emitting devices. For example, along the first direction X, red light-emitting devices, green light-emitting devices, and blue light-emitting devices can be periodically arranged in a single second display area C2, so that different-color sub-pixels can be provided in a single second display area C2 of the display panel. Along the second direction Y, multiple sub-pixels in the same column can be set to the same color, or, along the second direction Y, the sub-pixels in the same column can be set to be arranged alternately in different colors. The present disclosure does not limit the color arrangement of the light-emitting devices in a single second display area C2 and the different color arrangements of the light-emitting devices in the same column.

[0098] Figure 6 For Figure 5The schematic cross-sectional view of the display substrate along the A-A direction is shown. As Figure 6 shown, in a plane perpendicular to the display substrate, the display substrate includes a substrate 10, a driving structure layer 20 disposed on the substrate 10, and a conductive layer disposed on a side of the driving structure layer 20 away from the substrate 10. The driving structure layer 20 may include a power line 11, and the power line 11 may include at least one of a first power line and a second power line. The first power line may be connected to a source electrode or a drain electrode of a corresponding transistor in the pixel driving circuit. The second power line may be connected to a power transmission line 70 through a transfer electrode 21, so as to provide a first level signal to the light-emitting device through the power transmission line 70. The driving structure layer 20 may further include a first transistor, and the first transistor may include a bottom gate electrode 12, a first active layer 14, a first gate electrode 16, a first source electrode 18, and a first drain electrode 19. The first transistor may be, for example, a driving transistor. A plurality of insulating layers are further disposed between the respective film layers of the first transistor, including a first insulating layer 13, a second insulating layer 15, and a third insulating layer 17. In an exemplary embodiment, the power line 11 may be disposed on the same layer as the bottom gate electrode 12, or the power line 11 may be disposed on a side of any insulating layer away from the substrate 10. The first power line and the second power line may be disposed on different layers. For example, the second power line may be disposed in the conductive layer, and the present disclosure does not limit this. The conductive layer may include a plurality of pads and a power transmission line 70. The pads may be connected to a corresponding pixel driving circuit, for example, may be connected to a drain electrode of a driving transistor in the pixel driving circuit. A planarization layer 22 and a fourth insulating layer 23 may be sequentially disposed between the conductive layer and the driving structure layer 20.

[0099] In an exemplary embodiment, a fifth insulating layer 31 and a black matrix layer 32 may be further sequentially disposed on a side of the conductive layer away from the substrate 10. Through holes are formed in the fifth insulating layer 31 and the black matrix layer 32, and the through holes may expose the pads and the power transmission line 70 located in the metal layer, so as to facilitate subsequent connection to the light-emitting device.

[0100] In an exemplary embodiment, a protective layer 33 may be further disposed on a side of the black matrix layer 32 away from the substrate 10. Through holes are formed in the protective layer 33, and the through holes may expose the power transmission line 70 and at least a part of the pads located in the metal layer, so as to facilitate subsequent connection to the light-emitting device.

[0101] In an exemplary embodiment, in combination with Figure 5As shown, the pads of the metal layer may include a first pad 61, a second pad 62, a third pad 63, a fifth pad 65, and a sixth pad 66, and the sixth pad 66 may be connected to the power transmission line 70. The vias of the protective layer 33 may expose the surfaces of the first pad 61, the second pad 62, the third pad 63, the fifth pad 65, the sixth pad 66, and the power transmission line 70. The first pad 61 and the fifth pad 65 may be connected to each other or set as an integral structure, so that the fifth pad 65 and the first pad 61 may share the same pixel driving circuit, and the subsequently installed fourth light-emitting device may emit light synchronously with the first light-emitting device, which can not only achieve light-emitting compensation for the first light-emitting device, but also save the layout space of the pixel driving circuit.

[0102] In an exemplary embodiment, the pads of the metal layer may include a first pad 61, a second pad 62, a third pad 63, a fifth pad 65, and a sixth pad 66. The first pad 61 and the fifth pad 65 may be independent of each other, and the fifth pad 65 may be connected to its corresponding pixel driving circuit, so that the light-emitting devices connected to the fifth pad 65 and the sixth pad 66 may emit light independently. The vias of the protective layer 33 may only expose the surfaces of the fifth pad 65, the sixth pad 66, and the power transmission line 70. When installing the light-emitting device subsequently, the light-emitting device may be installed only at the fifth pad 65 and the sixth pad 66, and no light-emitting device may be installed in the first display area C1, and a display panel with a larger sub-pixel pitch may be obtained. By controlling the positions of the vias of the protective layer 33, different display schemes of the display substrate may be controlled.

[0103] The preparation process of the display substrate will be described by way of example below. The "patterning process" as mentioned in the present disclosure, for metal materials, inorganic materials or transparent conductive materials, includes processes such as coating photoresist, mask exposure, development, etching, and photoresist stripping. For organic materials, it includes processes such as coating organic materials, mask exposure, and development. Deposition can be carried out by any one or more of sputtering, evaporation, and chemical vapor deposition. Coating can be carried out by any one or more of spraying, spin coating, and inkjet printing. Etching can be carried out by any one or more of dry etching and wet etching. The present disclosure does not make any limitations. A "thin film" refers to a thin film made of a certain material on a substrate by using deposition, coating, or other processes. If the "thin film" does not require a patterning process during the entire manufacturing process, the "thin film" can also be referred to as a "layer". If the "thin film" requires a patterning process during the entire manufacturing process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern". The statement "A and B are arranged in the same layer" as mentioned in the present disclosure means that A and B are formed simultaneously through the same patterning process. The "thickness" of the film layer is the dimension of the film layer in the direction perpendicular to the display backplane. In the exemplary embodiments of the present disclosure, the statement "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A includes the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0104] In an exemplary embodiment, Figure 6 the preparation process of the shown display substrate may include the following steps.

[0105] (1) Form a driving circuit layer pattern. In an exemplary embodiment, forming a driving circuit layer pattern may include:

[0106] Deposit a first conductive thin film on the substrate 10, and pattern the first conductive thin film through a patterning process to form a first conductive layer pattern. The first conductive layer pattern may at least include a power line 11 and a bottom gate electrode 12.

[0107] In an exemplary embodiment, the bottom gate electrode 12 can be used as a gate electrode of a first transistor to be formed later and also has the function of shielding light for the first transistor. In an exemplary embodiment, the first transistor may be a driving transistor.

[0108] In an exemplary embodiment, the orthographic projection of the power line 11 on the substrate and the orthographic projection of the bottom gate electrode 12 on the substrate may be isolated from each other.

[0109] In an exemplary embodiment, the power supply line 11 may include a first power supply line; alternatively, the power supply line 11 may include a second power supply line; or, the power supply line 11 may include a first power supply line and a second power supply line, and the first power supply line and the second power supply line are arranged at intervals from each other.

[0110] Subsequently, a first insulating film and a semiconductor film are sequentially deposited, and the semiconductor film is patterned through a patterning process to form a first insulating layer 13 covering the power supply line 11 and the bottom gate electrode 12, and a semiconductor layer pattern disposed on the first insulating layer 13. The semiconductor layer pattern may at least include a first active layer 14, and the orthographic projection of the first active layer 14 on the substrate may be located within the range of the orthographic projection of the bottom gate electrode 12 on the substrate. The first insulating layer 13 may be referred to as a buffer layer.

[0111] Subsequently, a second insulating film and a second conductive film are sequentially deposited, and the second conductive film is patterned through a patterning process to form a second insulating layer 15 covering the semiconductor layer pattern, and a second conductive layer pattern disposed on the second insulating layer 15. The second conductive layer pattern may at least include a first gate electrode 16. The first gate electrode 16 may serve as the top gate electrode of the first transistor, and the orthographic projection of the first gate electrode 16 on the substrate may be located within the range of the orthographic projection of the first active layer 14 on the substrate. The second insulating layer 15 may be referred to as a gate insulation (GI) layer.

[0112] Subsequently, a third insulating film is deposited, and the third insulating film is patterned through a patterning process to form a third insulating layer 17 pattern covering the second conductive layer pattern. The third insulating layer 17 may include a plurality of openings. The plurality of openings may include contact holes and two active vias. The contact holes may expose the surface of the power supply line 11, and the two active vias may respectively expose both ends of the first active layer 14. The third insulating layer 17 may be referred to as an interlayer dielectric (ILD) layer.

[0113] Subsequently, a third conductive film is deposited, and the third conductive film is patterned through a patterning process to form a third conductive layer pattern on the third insulating layer. The third conductive layer pattern at least includes: a first source electrode 18, a first drain electrode 19, and a transfer electrode 21. In an exemplary embodiment, the power supply line 11 may include a second power supply line, the transfer electrode 21 may be connected to the second power supply line through a contact hole, and the first source electrode 18 and the first drain electrode 19 may be respectively connected to the first active layer 14 through the first active vias.

[0114] In an exemplary embodiment, the first power line (not shown) may be connected to the source electrode or drain electrode of the corresponding transistor in the pixel driving circuit. The bottom gate electrode 12, the first active layer 14, the first gate electrode 16, the first source electrode 18 and the first drain electrode 19 may constitute a first transistor, and the orthographic projection of the bottom gate electrode 12 on the substrate may cover the orthographic projection of the first active layer 14, the first gate electrode 16, the first source electrode 18 and the first drain electrode 19 on the substrate, thereby shading the first transistor. The first transistor may be a thin film transistor (TFT).

[0115] At this point, the pattern of the driving circuit layer 20 is prepared. In an exemplary embodiment, the driving circuit layer 20 of each sub-pixel may include a plurality of transistors and storage capacitors constituting a pixel driving circuit.

[0116] In an exemplary embodiment, the substrate may be a rigid substrate or a flexible substrate. The rigid substrate may be made of materials such as glass or quartz, and the flexible substrate may be made of materials such as polyimide (PI). The flexible substrate may be a single-layer structure or a laminated structure consisting of an inorganic material layer and a flexible material layer, which is not limited in the present disclosure.

[0117] In an exemplary embodiment, the first insulating layer, the second insulating layer, and the third insulating layer may be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be a single layer, a multilayer, or a composite layer. The first conductive layer, the second conductive layer, and the third conductive layer may be made of metal materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti), and molybdenum (Mo), or alloy materials of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), and may be a single layer structure, or a multilayer composite structure, such as Ti / Al / Ti, etc. The semiconductor layer may be made of amorphous indium gallium zinc oxide material (a-IGZO), zinc oxynitride (ZnON), and indium zinc tin oxide (IZTO), which is not limited in the present disclosure.

[0118] (2) Forming a planarization layer and a fourth insulating layer pattern. In an exemplary embodiment, forming a planarization layer and a fourth insulating layer pattern may include:

[0119] A planar layer film is coated on the substrate forming the aforementioned pattern, and the planar layer film is patterned through a patterning process to form a planar layer 22 pattern covering the third conductive layer pattern. The planar layer 22 may include multiple openings, and the multiple openings may respectively expose the surface of the transfer electrode 21 and the surface of the first drain electrode 19.

[0120] Subsequently, a fourth insulating film is deposited and patterned through a patterning process to form a pattern of a fourth insulating layer 23 covering the flat layer pattern. The fourth insulating layer 23 may include a plurality of openings, and the plurality of openings may respectively expose the surfaces of the via electrode 21 and the first drain electrode 19. The plurality of openings located in the fourth insulating layer 23 may communicate with the plurality of openings located in the flat layer 22. The fourth insulating layer 23 may be referred to as a passivation (PVX) layer.

[0121] In an exemplary embodiment, the fourth insulating layer may be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be a single layer, a multi-layer, or a composite layer. The first conductive layer, the second conductive layer, and the third conductive layer may be made of a metal material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti), and molybdenum (Mo), or an alloy material of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), and may be a single-layer structure or a multi-layer composite structure, such as Ti / Al / Ti, etc.

[0122] (3) Form a conductive layer pattern. In an exemplary embodiment, forming the conductive layer pattern may include:

[0123] Deposit a fourth conductive film on the substrate on which the foregoing pattern is formed and pattern the fourth conductive film through a patterning process to form a conductive layer pattern, which may at least include a plurality of pads and a power transmission line 70.

[0124] In an exemplary embodiment, the power transmission line 70 may be connected to the second power supply line through the openings in the fourth insulating layer and the flat layer and the via electrode 21, thereby realizing the connection with the second power supply line.

[0125] In an exemplary embodiment, the conductive layer pattern may include a plurality of pad groups arranged in an array. In a plane parallel to the display substrate, the display substrate includes a plurality of first display regions sequentially arranged in a second direction. A single first display region may include a single row of pad groups extending in a first direction. Each pad group may include a first pad 61, a second pad 62, and a third pad 63 arranged in a “pin” shape. The first pad 61, the second pad 62, and the third pad 63 may be connected to the first drain electrodes 19 of their respective first transistors through openings in the fourth insulating layer and the planarization layer, thereby enabling the first pad 61, the second pad 62, and the third pad 63 to be respectively connected to their corresponding pixel driving circuits. When installing the light-emitting devices subsequently, the first pad 61 may be connected to the first pole pin of the first light-emitting device, the second pad 62 may be connected to the first pole pin of the second light-emitting device, and the third pad 63 may be connected to the first pole pin of the third light-emitting device. The second pole pins of the plurality of light-emitting devices may be respectively connected to the power transmission line 70. The first light-emitting device may be a blue light-emitting device, the second light-emitting device may be a green light-emitting device, and the third light-emitting device may be a red light-emitting device.

[0126] In an exemplary embodiment, in a plane parallel to the display substrate, the display substrate further includes a plurality of second display regions extending in a second direction. The plurality of first display regions and the plurality of second display regions may be alternately arranged in sequence in the second direction. The conductive layer pattern may further include a plurality of fifth pads 65 and a plurality of sixth pads 66. The sixth pads 66 may be connected to the power transmission line 70. A single second display region may include multiple pairs of fifth pads 65 and sixth pads 66 extending in the second direction. When installing the light-emitting devices subsequently, the fifth pad 65 may be connected to the first pole pin of the fourth light-emitting device, and the sixth pad 66 may be connected to the second pole pin of the fourth light-emitting device.

[0127] In an exemplary embodiment, as Figure 6 shown, a single pad group may be arranged in pairs with an adjacent single group of fifth pads 65 and sixth pads 66. The first pad 61 and the fifth pad 65 may be set as an integrally connected structure. The fourth light-emitting device may be a blue light-emitting device, which can not only implement the MIP display scheme subsequently but also improve the display defects caused by blue light attenuation.

[0128] In other embodiments, the fifth pad 65 may be directly connected to the first drain electrode 19 through an opening, and the present disclosure does not limit this. In other embodiments, the first pad 61 and the fifth pad 65 may be set to be independent of each other, and the fifth pad 65 may be connected to the pixel driving circuit corresponding to itself, and the present disclosure does not limit this.

[0129] (4) Form a fifth insulating layer pattern and a black matrix layer pattern. In an exemplary embodiment, forming the fifth insulating layer pattern and the black matrix layer pattern may include:

[0130] Deposit a fifth insulating thin film on the substrate on which the foregoing pattern is formed, pattern the fifth insulating thin film through a patterning process to form a pattern of the fifth insulating layer 31. The pattern of the fifth insulating layer 31 may at least include a plurality of openings, and the plurality of openings may respectively expose the surfaces of the first pad 61, the second pad 62, the third pad 63, the fifth pad 65, the sixth pad 66, and the power transmission line 70, thereby facilitating subsequent connection to corresponding light-emitting devices. The fifth insulating layer 31 may protect the conductive layer and prevent metal oxidation and corrosion.

[0131] Subsequently, form a pattern of a black matrix (BM) layer 32 on the pattern of the fifth insulating layer. The black matrix layer 32 may expose the plurality of openings located in the fifth insulating layer 31. The black matrix layer 32 may block the metal on one side of the substrate, reduce the reflection of the display substrate, and help improve the display effect of the display substrate.

[0132] (5) Form a protective layer pattern. In an exemplary embodiment, forming the protective layer pattern may include:

[0133] Coat a protective layer thin film on the substrate on which the foregoing pattern is formed, pattern the protective layer thin film through a patterning process to form a pattern of an overcoat (OC) layer 33. The protective layer 33 may include a plurality of openings. The protective layer 33 may protect the metal film layer and the black matrix layer 32 and prevent the film layer from being scratched.

[0134] In an exemplary embodiment, as Figure 6 shown, the openings of the protective layer 33 may expose the surfaces of the first pad 61, the second pad 62, the third pad 63, the fifth pad 65, the sixth pad 66, and the power transmission line 70, so that when a light-emitting device is subsequently installed, the fourth light-emitting device may be used to perform light emission compensation on the first light-emitting device.

[0135] In an exemplary embodiment, the openings of the protective layer 33 may only expose the surfaces of the fifth pad 65, the sixth pad 66, and the power transmission line 70. The fifth pad 65 may be connected to a pixel driving circuit corresponding to itself, and the sixth pad 66 may be connected to the power transmission line 70. When a light-emitting device is subsequently installed, no light-emitting device is installed at the first pad 61, the second pad 62, and the third pad 63, and light-emitting devices are only installed at the fifth pad 65 and the sixth pad 66, so that a display panel with a larger sub-pixel pitch can be obtained to adapt to different application scenarios.

[0136] So far, as Figure 6The shown display substrate is prepared. The design details of the display substrate can be designed according to actual needs, so as to implement different display schemes.

[0137] Subsequently, the corresponding display device can be continuously installed on the display substrate to form a display panel.

[0138] The embodiment of the present disclosure also provides a method for preparing a display substrate, including: forming a driving circuit layer on a substrate, the driving circuit layer including a plurality of pixel driving circuits; forming a conductive layer on the driving circuit layer; the conductive layer includes a plurality of pad groups arranged in an array and at least one power transmission line, each pad group includes three pads, a single pad is connected to a single pixel driving circuit, and the pad is configured to be connected to the first pole pin of the light-emitting device; the power transmission line is configured to be connected to the second pole pin of the light-emitting device to transmit a first-level signal to the light-emitting device.

[0139] The method for preparing a display substrate provided by the embodiment of the present disclosure can be applied to form a display substrate for a MIP display scheme.

[0140] The embodiment of the present disclosure also provides a display panel, including a plurality of light-emitting devices and the display substrate described in any one of the above embodiments.

[0141] Figure 7 For Figure 5 the planar schematic diagram of the display panel after forming the display substrate in Figure 7 As shown, the display panel includes a first light-emitting device 71, a second light-emitting device 72, a third light-emitting device 73, and a fourth light-emitting device 74. Among them, the first light-emitting device 71 can be connected to the first pad 61 and the fourth pad 64, the second light-emitting device 72 can be connected to the second pad 62 and the adjacent power transmission line 70, the third light-emitting device 73 can be connected to the third pad 63 and the adjacent power transmission line 70, and the fourth light-emitting device 74 can be connected to the fifth pad 65 and the sixth pad 66. In an exemplary embodiment, the first light-emitting device 71 and the fourth light-emitting device 74 can be blue light-emitting devices, the second light-emitting device 72 can be a green light-emitting device, and the third light-emitting device 73 can be a red light-emitting device. The present disclosure does not limit this.

[0142] The display panel provided in this embodiment can share a pixel driving circuit by arranging the fourth light-emitting device 74 close to the first light-emitting device 71. The fourth light-emitting device 74 can supplement the brightness of the first light-emitting device 71, which helps to improve the display defect caused by blue light attenuation. Moreover, the first light-emitting device 71, the second light-emitting device 72, and the third light-emitting device 73 of a single pad group can adopt the MIP packaging technology, or the first light-emitting device 71, the second light-emitting device 72, the third light-emitting device 73, and the corresponding fourth light-emitting device 74 of a single pad group can adopt the MIP packaging technology. Thus, more sub-pixels can be arranged in a single display panel, which helps to improve the resolution of the display panel.

[0143] Figure 8 It is a plan view of the display panel in another exemplary embodiment. As Figure 8 shown, the protective layer 33 can cover multiple pad groups, only exposing the fifth pad 65 and the sixth pad 66. The fifth pad 65 and the first pad 61 are independently arranged, and the fifth pad 65 is connected to its corresponding pixel driving circuit. The fifth pad 65 and the sixth pad 66 in a single second display area can be connected to the corresponding light-emitting devices, so that a display panel with a larger sub-pixel pitch can be obtained, expanding the application scenarios of the display panel. When forming the display substrate, only by controlling the opening positions on the protective layer 33, the display panels of different display schemes in Figure 7 or Figure 8 can be formed. Moreover, this kind of display substrate does not need to add new processes or steps during preparation, which is convenient for preparation.

[0144] In the exemplary embodiment, light-emitting devices of the same color can be arranged in a single second display area, and light-emitting devices of different colors can be arranged in adjacent second display areas. As Figure 8 shown, the fifth light-emitting device 75, the sixth light-emitting device 76, and the seventh light-emitting device 77 can be alternately arranged in multiple second display areas. The fifth light-emitting device 75 can be a blue light-emitting device, the sixth light-emitting device 76 can be a red light-emitting device, and the seventh light-emitting device 77 can be a green light-emitting device. The present disclosure does not limit this.

[0145] Figure 9 It is a plan view of the display panel in another exemplary embodiment. Figure 9 and Figure 8 differ in the arrangement manner of the light-emitting devices, and the remaining structures can refer to the description in Figure 8 , which will not be elaborated here. As Figure 9As shown, within a single second display area, the fifth light-emitting device 75, the sixth light-emitting device 76, and the seventh light-emitting device 77 may be alternately arranged along the first direction X. In the second direction Y, the light-emitting devices of the same column of sub-pixels may be set to the same color, and the present disclosure does not limit this.

[0146] Figure 10 It is a schematic plan view of a display panel in yet another exemplary embodiment. Figure 10 and Figure 9 The difference lies in the arrangement manner of the light-emitting devices, and the remaining structures may refer to the description in Figure 9 and will not be elaborated here. As Figure 10 shown, within a single second display area, the fifth light-emitting device 75, the sixth light-emitting device 76, and the seventh light-emitting device 77 may be alternately arranged along the first direction X. In the second direction Y, the light-emitting devices of the same column of sub-pixels may be alternately arranged with different colors.

[0147] Figure 8 The distance between adjacent sub-pixels of the same color located in different sub-pixel rows in Figure 7 is approximately 3 times the distance between sub-pixels of the same color in Figure 9 The distance between adjacent sub-pixels of the same color within the same sub-pixel row in Figure 7 is approximately 3 times the distance between sub-pixels of the same color in Figure 10 The distance between adjacent sub-pixels of the same color within the same sub-pixel row, and the distance between adjacent sub-pixels of the same color located in different sub-pixel rows in Figure 7 is approximately 3 times the distance between sub-pixels of the same color in Figures 8 to 10 The size of the light-emitting device adopted in Figure 7 may be greater than or equal to the size of the light-emitting device in Figure 7 Compared with the display panel in Figures 8 to 10 the display panel in Figure 7 has fewer sub-pixels and is applicable to scenarios where the distance between the observer and the display panel is relatively far, or scenarios with low requirements for picture clarity. Figures 8 to 10 The display schemes of

[0148] Both may adopt the display substrate in the above-mentioned embodiments. The display substrate provided in the above-mentioned embodiments of the present disclosure can support two different display schemes, without the need to increase the preparation steps and processes, without increasing the production cost, and is easy to promote and use.

[0149] Although the embodiments disclosed in the present invention are as described above, the content described is only an embodiment adopted for the convenience of understanding the present invention and is not intended to limit the present invention. Any person skilled in the art within the scope of the present invention may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope disclosed in the present invention. However, the scope of patent protection of the present invention shall still be subject to the scope defined by the appended claims.

Claims

1. A display substrate, characterized in that, comprising: a substrate and a driving circuit layer and a conductive layer sequentially disposed on the substrate; the driving circuit layer includes a plurality of pixel driving circuits; the conductive layer includes a plurality of pad groups arranged in an array and at least one power transmission line, each pad group includes three pads, a single pad is connected to a single pixel driving circuit, and a single pad is configured to be connected to a first pole pin of a single light-emitting device; the power transmission line is configured to be connected to a second pole pin of the light-emitting device to transmit a first level signal to the light-emitting device.

2. The display substrate according to claim 1, characterized in that, the plurality of pad groups include a plurality of pad group rows extending in a first direction and a plurality of pad group columns extending in a second direction, the first direction and the second direction intersect; in a plane parallel to the display substrate, the display substrate includes a plurality of first display regions, the first display regions extend in the first direction, and a single first display region includes a single pad group row.

3. The display substrate according to claim 2, characterized in that, the conductive layer further includes a plurality of pairs of fifth pads and sixth pads, the sixth pads are connected to the power transmission line; in a plane parallel to the display substrate, the display substrate further includes a plurality of second display regions, the second display regions extend in the first direction, and a single second display region includes a plurality of groups of the fifth pads and the sixth pads extending in the first direction; the first display regions and the second display regions are alternately arranged in the second direction.

4. The display substrate according to claim 3, characterized in that, a single pad group includes a first pad, a second pad and a third pad, the first pad, the second pad and the third pad are arranged in a "pin" shape; the first pad is configured to be connected to a first light-emitting device, the second pad is configured to be connected to a second light-emitting device, and the third pad is configured to be connected to a third light-emitting device.

5. The display substrate according to claim 4, characterized in that, in the second direction, a single group of the fifth pads and the sixth pads are arranged in pairs with a single pad group; the fifth pad is configured to be connected to a first pole pin of a fourth light-emitting device, the sixth pad is configured to be connected to a second pole pin of the fourth light-emitting device; the color of the first light-emitting device is the same as the color of the fourth light-emitting device.

6. The display substrate according to claim 5, characterized in that, the paired first pads are connected to each other, or the pixel driving circuits of the paired first pads are connected to the fifth pads.

7. The display substrate according to claim 6, characterized in that, further comprising a protective layer, the protective layer is disposed on a side of the conductive layer away from the substrate; the protective layer includes a plurality of vias, and the plurality of vias respectively expose surfaces of the first pad, the second pad, the third pad, the fifth pad, the sixth pad and at least one power transmission line.

8. The display substrate according to claim 3, wherein, the fifth pad is connected to the corresponding pixel driving circuit, a single set of the fifth pad and the sixth pad are connected to a single light-emitting device, the fifth pad is configured to be connected to the first pole pin of the light-emitting device, and the sixth pad is configured to be connected to the second pole pin of the light-emitting device.

9. The display substrate according to claim 8, wherein, the light-emitting devices connected within a single second display area have the same color, and the light-emitting devices connected within adjacent second display areas have different colors.

10. The display substrate according to claim 8, wherein, a single second display area is connected with light-emitting devices of multiple different colors, and the light-emitting devices of different colors are arranged alternately in sequence; in the second direction, the light-emitting devices in the same column have the same color.

11. The display substrate according to claim 8, wherein, a single second display area is connected with light-emitting devices of multiple different colors, and the light-emitting devices of different colors are arranged alternately in sequence; in the same column along the second direction, the light-emitting devices of different colors are arranged alternately in sequence.

12. The display substrate according to claim 11, wherein, it further includes a protective layer, and the protective layer is disposed on a side of the conductive layer away from the substrate; the protective layer includes a plurality of vias, and the plurality of vias respectively expose the surfaces of the fifth pad, the sixth pad, and at least one power transmission line.

13. A method for manufacturing a display substrate, wherein, it includes: forming a driving circuit layer on a substrate, and the driving circuit layer includes a plurality of pixel driving circuits; forming a conductive layer on the driving circuit layer; the conductive layer includes a plurality of pad groups arranged in an array and at least one power transmission line, each pad group includes three pads, a single pad is connected to a single pixel driving circuit, and a single pad is configured to be connected to the first pole pin of a single light-emitting device; the power transmission line is configured to be connected to the second pole pin of the light-emitting device to transmit a first level signal to the light-emitting device.

14. A display panel, wherein, it includes a plurality of light-emitting devices and the display substrate according to any one of claims 1 to 12.

15. A display device, wherein, it includes the display panel according to claim 14.

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