Display panel and display device

Abstract

The invention provides a display panel and a display device.The display panel comprises a first area and a second area, the first area is located on the side, close to the edge of the display panel, of the second area, the display panel comprises a substrate, a lead-out wire and a conductive pad, and the lead-out wire is located on one side of the substrate and located in the first area; the lead-out wire comprises a first lead-out wire, a second lead-out wire and a resistor connecting structure located between the first lead-out wire and the second lead-out wire, the conductive pad is located on one side of the substrate and located on different layers from the resistor connecting structure, and the conductive pad is overlapped with the first lead-out wire and / or the second lead-out wire in the direction perpendicular to the plane where the substrate is located. In this way, when static electricity exists on the edge of the display panel and forms a path in the lead-out wire, the static electricity is easily released to the conductive pads on the two sides of the resistor connecting structure, the static electricity is isolated on the conductive pads, electric signal connection is guaranteed, and meanwhile electrostatic protection of the display panel is achieved.

Description

Technical Field

[0001] The present invention relates to the field of display technologies, and particularly to a display panel and a display device. Background Art

[0002] In the field of display technologies, static electricity may damage the components in the display screen, affecting the display performance of the display device. With the development of display technologies, narrow bezel displays and ultra-narrow bezel displays have gradually become the mainstream displays. However, in narrow bezel display panels and ultra-narrow bezel display panels, static electricity is more likely to enter the interior of the display panel to damage the components. This is because in such display panels, in addition to meeting the conventional design requirements for display, the lead requirements for testing also need to be considered. The leads are usually arranged in the peripheral area of the display panel, and static electricity may reach the interior of the display panel through the leads.

[0003] Therefore, in the process of the development of display technologies, a reliable electrostatic protection structure needs to be provided to solve the electrostatic problem of the display panel. Summary of the Invention

[0004] In view of this, the purpose of the present application is to provide a display panel and a display device, which provide a reliable electrostatic protection structure to solve the electrostatic problem of the display panel.

[0005] An embodiment of the present application provides a display panel, including a first region and a second region. The first region is located on one side of the second region close to the edge of the display panel. The display panel includes:

[0006] A substrate;

[0007] A lead wire on one side of the substrate and located in the first region. The lead wire includes a first lead wire, a second lead wire, and a resistance connection structure located between the first lead wire and the second lead wire;

[0008] A conductive pad on one side of the substrate and in a different layer from the resistance connection structure. In a direction perpendicular to the plane where the substrate is located, the conductive pad overlaps with the first lead wire and / or the second lead wire. An embodiment of the present application provides a display device, including the display panel described in the above embodiment.

[0009] Embodiments of the present application provide a display panel and a display device. The display panel includes a first region and a second region. The first region is located on one side of the second region close to the edge of the display panel. The display panel includes a substrate, a lead wire, and a conductive pad. The lead wire is located on one side of the substrate and in the first region. The lead wire includes a first lead wire, a second lead wire, and a resistance connection structure located between the first lead wire and the second lead wire. The conductive pad is located on one side of the substrate and is in a different layer from the resistance connection structure. In the direction perpendicular to the plane where the substrate is located, the conductive pad overlaps with the first lead wire and / or the second lead wire. Electrostatic accumulation is likely to occur on both sides of the resistance connection structure for electrostatic discharge. In this way, when there is static electricity at the edge of the display panel, during the process of the static electricity forming a path in the lead wire, the static electricity is easily discharged to the conductive pad on both sides of the resistance connection structure, and the static electricity is isolated on the conductive pad, realizing the directional release of static electricity and preventing the static electricity from affecting the inside of the display panel, achieving the electrostatic protection of the display panel while ensuring the electrical signal connection. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0011] Figure 1 FIG. shows a schematic diagram of a display panel provided by an embodiment of the present application;

[0012] Figure 2 is a schematic diagram of another display panel provided by an embodiment of the present application;

[0013] Figure 3 For Figure 1 And Figure 2 a detailed schematic diagram of a partial area in;

[0014] Figure 4 For Figure 3 a cross-sectional schematic diagram along the AA direction in;

[0015] Figure 5 is a same-layer comparison diagram of the first region and the second region provided by an embodiment of the present application;

[0016] Figure 6 For Figure 1 And Figure 2 another detailed schematic diagram of a partial area in;

[0017] Figure 7 For Figure 6 a cross-sectional schematic diagram along the AA direction in;

[0018] Figure 8 Another same - layer comparison diagram of the first region and the second region provided by the embodiments of the present application;

[0019] Figure 9 is Figure 1 with Figure 2 Another detailed schematic diagram of a local region in

[0020] Figure 10 is Figure 1 with Figure 2 Another detailed schematic diagram of a local region in

[0021] Figure 11 is Figure 1 with Figure 2 Another detailed schematic diagram of a local region in

[0022] Figure 12 is Figure 1 with Figure 2 Another detailed schematic diagram of a local region in

[0023] Figure 13 is Figure 1 with Figure 2 Another detailed schematic diagram of a local region in

[0024] Figure 14 A schematic plan view of a display device provided by the embodiments of the present application;

[0025] Figure 15 A schematic diagram of a tiled display device provided by the embodiments of the present application. Detailed implementation manners

[0026] To make the above - mentioned objects, features, and advantages of the present application more obvious and understandable, the following will describe the detailed implementation manners of the present application in conjunction with the accompanying drawings.

[0027] In the following description, many specific details are set forth to facilitate a full understanding of the present application. However, the present application may also be implemented in other ways different from those described herein. Those skilled in the art can make similar extensions without departing from the connotation of the present application. Therefore, the present application is not limited by the specific embodiments disclosed below.

[0028] It should be understood that the term “and / or” used herein is merely a description of the association relationship between associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist simultaneously, and B exists alone. In addition, the character “ / ” herein generally represents an “or” relationship between the associated objects before and after.

[0029] Secondly, this application will be described in detail with reference to the schematic diagrams. When describing the embodiments of this application in detail, for the convenience of explanation, the cross-sectional views showing the device structure will be enlarged locally not in accordance with the general scale, and the schematic diagrams are only examples and should not limit the scope of protection of this application herein. In addition, in actual production, three-dimensional spatial dimensions including length, width, and depth should be included.

[0030] To better understand the technical solutions and technical effects of this application, specific embodiments will be described in detail below with reference to the accompanying drawings.

[0031] The display panel provided by the embodiments of this application is applied to a display device and can be used as a substrate for controlling pixel light emission in the display device.

[0032] The display panel may include light-emitting elements in the pixels. For example, the display panel may be a display panel including organic light-emitting diodes (OLEDs); the display panel may also be combined with the light-emitting elements in the pixels by means such as plugging, welding, and bonding. For example, the display panel may be combined with light-emitting elements such as mini light-emitting diodes (Mini-LEDs) and micro light-emitting diodes (Micro-LEDs). In addition, the display panel may also be applied to display devices such as liquid crystal displays (LCDs) and electrophoretic displays (EPDs) that achieve display by regulating the optical path of light. At this time, the display panel can separately regulate the optical paths of light in different pixels. This application does not make any limitations in this regard.

[0033] Figure 1 FIG. is a schematic diagram of a display panel provided by an embodiment of this application. Figure 2 FIG. is a schematic diagram of another display panel provided by an embodiment of this application.

[0034] As Figure 1 and Figure 2 shown, the display panel 01 includes a first region R1 and a second region R2, and the first region R1 is located on the side of the second region R2 close to the edge of the display panel 01. The lead wire 10 is located on one side of the substrate 30 and in the first region R1, that is, the lead wire 10 is located in the region close to the edge in the display panel 01.

[0035] The display panel 01 may be a narrow-frame display panel 01, in which case the first region R1 is a frame region for setting peripheral circuits and peripheral wiring, and the second region R2 is a display region for performing luminous display. The display panel 01 may also be a frameless display panel 01 or an extremely narrow-frame display panel 01, in which case both the first region R1 and the second region R2 are regions for performing luminous display, and the first region R1 is closer to the edge of the display panel 01 than the second region R2. In a display panel 01 with a narrow frame, frameless frame, or extremely narrow frame, the display area is closer to the edge, resulting in prominent electrostatic problems. In particular, if lead wires for testing the display panel 01 are provided in the peripheral region of the display panel 01, it is likely to further increase the risk of electrostatics.

[0036] The display panel 01 includes a signal line 40 to be tested, and the signal line 40 to be tested is usually located in the second region R2. The signal line 40 to be tested is connected to the lead-out wire 10, and the signal line 40 to be tested and the lead-out wire 10 can be arranged in different layers and connected through a switching electrode block (not shown). The signal line 40 to be tested includes at least one of a first signal line, a second signal line and a third signal line, the first signal line is used to transmit a pulse signal, the second signal line is used to transmit a data voltage, and the third signal line is used to transmit a fixed voltage signal; the first lead-out wire is connected to the signal line 40 to be tested, and the second lead-out wire extends to the edge of the display panel 01. During the test of the display panel 01, the lead-out wire 10 can be used to electrically connect to an external test fixture, so that the signal line 40 to be tested is electrically connected to the external test fixture, so that the signal verification of the signal line 40 to be tested is performed using the external test fixture to achieve the performance test of the display panel 01.

[0037] For example, the first signal line is a shift register that transmits a clock signal, and / or the first signal line is a multiplexer that transmits a clock signal, etc. For example, the second signal line is a pixel drive circuit that transmits a data voltage, or a pixel switch transistor that transmits a data voltage, etc. For example, the third signal line is a shift register that transmits a power supply voltage, and / or the third signal line is a pixel circuit that transmits a power supply voltage, a reset voltage, etc.

[0038] Specifically, the surface of the display panel 01 where the lead wire 10 is led out is defined as the front surface of the display panel 01. Before testing the display panel 01, a test connection line connected to the lead wire 10 can be formed. The test connection line extends from the second lead wire through the side wall of the display panel 01 to the other surface (i.e., the back surface) of the display panel 01, so as to connect an external test fixture from the back surface. The test connection line is fabricated after the laminated film layers are prepared on the substrate 30 using semiconductor processes. Before fabricating the test connection line, the initially obtained display panel 01 needs to be edge-ground, so that the edges of the substrate 30 and the multiple stacked film layers prepared using semiconductor processes form edges with chamfers. When fabricating the test connection line, the continuity and fabrication yield of the test connection line at the position of the display panel 01 can be ensured; in addition, the display panel 01 can have a narrower border.

[0039] However, during the edge-grinding process, static electricity will be generated due to the friction between tools such as grinding rods or grinding wheels and the display panel 01. In addition, the substrate in the display panel 01 can be a glass substrate, and during the edge-grinding process, the glass substrate is more likely to generate static electricity. This static electricity will be introduced into the interior of the display panel 01, causing damage to the devices in the display panel 01 and resulting in a loss of process yield.

[0040] After the edge-grinding process, at least part of the edge of the lead wire 10 away from the second region R2 coincides with the edge of the initially obtained display panel 01. That is to say, during the edge-grinding process, at least part of the edge of the lead wire 10 is exposed at the edge position of the display panel 01. During the edge-grinding process, static electricity will be generated during the grinding of the lead wire 10, and at least part of the static electricity generated by structures such as the glass substrate will also be introduced into the lead wire 10.

[0041] In the embodiment of the present application, the first region R1 can at least partially surround the second region R2. For example, as Figure 1 and Figure 2 shown, the first region R1 surrounds the second region R2. The arrangement directions of the second region R2 and part of the first region R1 are different from the arrangement directions of the second region R2 and another part of the first region R1. For example, as Figure 1 and Figure 2 shown, the arrangement directions of the second region R2 and the first regions R1 on the left and right sides are parallel to the row direction, and the arrangement directions of the second region R2 and the first regions R1 on the upper and lower sides are parallel to the column direction.

[0042] Specifically, the first region R1 may include a first sub-region and a second sub-region. The first sub-region and the second region R2 are arranged along the first pixel arrangement direction X1, and the second sub-region and the second region R2 are arranged along the second pixel arrangement direction X2. The first pixel arrangement direction X1 and the second pixel arrangement direction X2 intersect, for example, they may be perpendicular. At least one of the first sub-region and the second sub-region includes the lead wire 10. For example, if the first pixel arrangement direction is horizontal and the second pixel arrangement direction is vertical, the first sub-region may be located on the left or right side of the second region R2, and the second sub-region may be located on the upper or lower side of the second region R2. In this way, the lead wire 10 can be located on at least one of the upper side, lower side, left side, and right side of the second region R2.

[0043] In specific implementation, the lead wire 10 is located in the first sub-region or the second sub-region. Specifically, the lead wire 10 is relatively concentratedly arranged in the first sub-region or the second sub-region on the same side of the second region R2; or, the lead wire 10 may be located in the first sub-region and the second sub-region, that is, the lead wire 10 is dispersedly arranged in the first region R1 on different sides of the second region R2. The transfer electrode block connecting the lead wire 10 and the signal line 40 to be measured can be in the same first region as the lead wire 10 or in different first regions. When it is in different first regions, the lead wire 10 can be connected to the transfer electrode block through an inter-region connection wire.

[0044] Among them, dispersedly arranging the lead wire 10 in the first region R1 on different sides of the second region R2 can reduce the wiring difficulty of the lead wire 10; and can reduce the quantity density of the lead wire 10 within one first region R1, so as to reduce the difficulty of its electrical connection with the external test fixture and improve the accuracy of its electrical connection with the external test fixture.

[0045] The extending direction of the lead wire 10 can be substantially parallel to the arrangement direction of the second region R2 and the first region R1 to which the lead wire 10 belongs. If the lead wire 10 belongs to the first sub-region, the extending direction of the lead wire 10 is substantially parallel to the horizontal direction. If the lead wire 10 belongs to the second sub-region, the extending direction of the lead wire 10 is substantially parallel to the vertical direction.

[0046] Figure 3 、 Figure 6 、 Figures 9 - 13 are Figure 1 multiple detailed schematic diagrams of the local region in Figure 2 ; Figure 4 is Figure 3 the cross-sectional schematic diagram along the AA direction in Figure 7 ; Figure 6 is Figure 5 and Figure 8Multiple in-layer comparison diagrams of the first region and the second region provided by the embodiments of the present application. The display panel 01 includes a substrate 30, lead wires 10, and conductive pads 20.

[0047] In the embodiments of the present application, the lead wire 10 includes a first lead wire 11, a second lead wire 12, and a resistance connection structure 13 located between the first lead wire 11 and the second lead wire 12. Both the conductive pad 20 and the lead wire 10 can conduct electricity. The conductive pad 20 is located on one side of the substrate 30 and is in a different layer from the resistance connection structure 13. In the direction perpendicular to the plane where the substrate 30 is located, the conductive pad 20 overlaps with the first lead wire 11 and / or the second lead wire 12. Electrostatic accumulation is likely to occur on both sides of the resistance connection structure 13 for electrostatic discharge. Thus, when there is static electricity at the edge of the display panel 01, during the process of the static electricity forming a path in the lead wire 10, the static electricity is easily discharged to the conductive pad 20 on both sides of the resistance connection structure 13, and the static electricity is isolated on the conductive pad 20, realizing the directional release of static electricity and preventing the static electricity from affecting the inside of the display panel 01, achieving the electrostatic protection of the display panel 01 while ensuring the electrical signal connection.

[0048] In this embodiment, the conductive pads are also dispersedly arranged in different first regions R1 where the lead wire 10 is located. Therefore, the lead wires 10 dispersedly arranged in the first regions R1 on different sides of the second region R2 can all have corresponding locations for electrostatic discharge.

[0049] In the embodiments of the present application, the display panel 01 may further include an insulating layer 3B, and the insulating layer 3B is located between the conductive pad 20 and the first lead wire 11, and between the conductive pad 20 and the second lead wire 12. In this way, the static electricity can break through the insulating layer 3B from the resistance connection structure 13 and thus discharge to the conductive pad 20. There is a phenomenon similar to climbing at the side wall position of the conductive pad 20 in the insulating layer 3B. The main structural manifestations of the insulating layer 3B include that the thickness of the part of the insulating layer 3B located at the side wall position and near the side wall position of the conductive pad 20 is reduced. For example, compared with the thickness of the insulating layer 3B at a flat position, the thickness of the part of the insulating layer 3B located at the side wall of the conductive pad 20 is reduced, and the thickness of the part of the insulating layer 3B located near the edge of the upper surface of the conductive pad 20 is also reduced. The places where the thickness of the insulating layer 3B is reduced at the side wall position and near the side wall position of the conductive pad 20 are called weak points, and it is easy to be broken through at this position to achieve discharge. The insulating layer 3B is an inorganic material film layer.

[0050] In the embodiment of the present application, the resistance of the resistance connection structure 13 per unit length is greater than that of the first lead wire 11 or the second lead wire 12 per unit length. That is to say, the resistance connection structure 13 is provided to increase the resistance of the lead wire 10. And because the resistance of the position where the resistance connection structure 13 is located is greater, a resistance area is formed. When static electricity is introduced from the outside of the display panel 01, charge enrichment is formed at both ends of the resistance area, serving as a weak area and thus making it easier to release static electricity, thereby playing a role in static protection.

[0051] As a possible implementation manner, referring to Figure 3 , Figure 4 , Figure 5 and Figure 11 shown, when the lead conductor extends in the first direction, the length of the resistance connection structure 13 in the second direction is less than that of the first lead wire 11 or the second lead wire 12, that is, the width of the resistance connection structure 13 is less than that of the first lead wire 11 and the second lead wire 12, making the resistance at the resistance connection structure 13 relatively large, which is equivalent to a necking design for the lead wire 10. Referring to Figure 3 shown, such a necking position forms a region with a relatively large resistance, and static charge aggregation regions are formed on both sides of it, so that it is easy to release static electricity to the conductive pad 20, playing a role in static protection.

[0052] Among them, in the direction from both ends of the resistance connection structure 13 to the center, its length in the second direction can gradually decrease, and it can have a fixed length in the central region. Or, the resistance connection structure 13 has the same length in the second direction as a whole, so that there is a length change at the connection of the resistance connection structure 13 with the first lead wire 11 and the second lead wire 12.

[0053] In addition, the resistance connection structure 13 and the first lead wire 11 and / or the second lead wire 12 can be arranged in the same layer. Referring to Figure 3 shown, this simplifies the difficulty of layer design and saves the design space of other layers; of course, the resistance connection structure 13 and the first lead wire 11 can be arranged in different layers, which is beneficial to improving the static electricity release effect.

[0054] As another possible implementation manner, referring to Figures 6 - 10 , Figures 12 - 13 shown, the first lead wire 11 and the second lead wire 12 can be arranged in the same layer, and the resistance connection structure 13 and the first lead wire 11 can be in different layers. In this way, the length of the resistance connection structure 13 in the current flow direction is greater than the distance between the first lead wire 11 and the second lead wire 12, making the resistance at the resistance connection structure 13 relatively large, and thus it is easy to release static electricity.

[0055] Specifically, the resistor connection structure 13 includes a connection wire 131 that is located on a different layer from the first lead wire 11; one end of the connection wire 131 is connected to the end of the first lead wire 11 through a first via 132, and the other end of the connection wire 131 is connected to the end of the second lead wire 12 through a second via 133. Refer to Figure 6 , Figure 7 , Figure 8 . As shown, at the position of the resistor connection structure 13, it is equivalent to realizing the cross-wire connection between the first lead wire 11 and the second lead wire 12. By using the relatively large resistance of the first via 132 and the second via 133, a region with a relatively large resistance is formed, making the charge accumulation at both ends of the resistor connection structure 13 more obvious and increasing the possibility of electrostatic discharge. Both the first via 132 and the second via 133 have conductor columns.

[0056] In specific implementation, at least one of the first via 132 and the second via 133 can be designed with multiple vias, for example, it can be designed with double vias. That is, the first via 132 includes a first sub-via and a second sub-via, and / or the second via 133 includes a third sub-via and a fourth sub-via. This can improve the reliability of the via connection and increase the possibility of electrostatic discharge.

[0057] Among them, the double vias can be arranged as parallel vias, that is, the arrangement direction of the first sub-via and the second sub-via is parallel to the extension direction of the lead wire. Refer to Figure 9 . As shown, the extension direction of the lead wire is denoted as the first direction, and the first sub-via and the second sub-via are arranged along the first direction; and / or the arrangement direction of the third sub-via and the fourth sub-via is parallel to the extension direction of the lead wire. Refer to Figure 9 . As shown, the third sub-via and the fourth sub-via are arranged along the first direction. This is beneficial to using a longer wire routing to achieve a greater resistance increase and improve the possibility of electrostatic discharge.

[0058] Among them, the double vias can be arranged as vertical vias, that is, the arrangement direction of the first sub-via and the second sub-via intersects with the extension direction of the lead wire. Refer to Figure 10 . As shown, the extension direction of the lead wire is denoted as the first direction, the first sub-via and the second sub-via are arranged along the second direction, and the second direction intersects with the first direction. For example, the second direction is perpendicular to the first direction; and / or the arrangement direction of the third sub-via and the fourth sub-via is perpendicular to the extension direction of the lead wire. Refer to Figure 10 . As shown, the third sub-via and the fourth sub-via are arranged along the second direction. This can achieve a more compact structure design, reduce the requirement for the design space, and save the wiring area.

[0059] In the double vias of the first via 132 and the second via 133, they can both be set as parallel vias, or both be set as perpendicular vias, or one can be set as a parallel via and the other as a perpendicular via. The specific setting can be determined according to the actual design requirements.

[0060] In an embodiment of the present application, the resistor connection structure 13 can be located on the side of the first lead 11 away from the substrate 30.

[0061] In an embodiment of the present application, the conductive pad 20 can be located on the side of the first lead 11 or the second lead 12 close to the substrate 30. Then, when manufacturing the display panel 01, the lead wire 10 is manufactured after the conductive pad 20 is manufactured. In this way, before the resistor connection structure 13 is formed, electrostatic discharge can be achieved through the conductive pad 20. There is an insulating layer 3B between the conductive pad 20 and the first lead 11, and between the conductive pad 20 and the second lead 12. Refer to Figure 4 and Figure 7 As shown, when manufacturing the display panel 01, the insulating layer 3B is manufactured after the conductive pad 20 is manufactured and before the lead wire 10 is manufactured.

[0062] Among them, a first dielectric layer 3A can be provided between the conductive pad 20 and the substrate 30; an insulating layer 3B is provided between the conductive pad 20 and the film layer where the first lead 11 is located; the first lead 11 and the second lead 12 can be covered by a second dielectric layer 3C, and the first via 132 and the second via 133 can penetrate through the second dielectric layer 3C; the connection line 131 can be covered by a third dielectric layer 3D. Isolation between each conductive film layer is achieved.

[0063] In order to realize the regulation of pixel light emission in the display device, the display panel 01 includes a pixel circuit or a pixel control transistor. The pixel circuit or the pixel control transistor is electrically connected to the first electrode and outputs a signal for controlling light emission to the corresponding pixel through the first electrode. For example, when the display panel 01 includes an organic light-emitting diode (OLED), the first electrode can be the anode of the OLED. In addition, the display panel 01 further includes a second electrode, and the second electrode can be the cathode of the OLED; when the display panel 01 is combined with Mini-LED or Micro-LED, the first electrode can be an electrode electrically connected to the anode of the Mini-LED / MicroLED; when the display panel 01 is applied to display devices such as LCD or EPD, the first electrode can be a pixel electrode. The first electrode is an electrode for controlling light emission.

[0064] In an embodiment of the present application, the display panel 01 includes a transistor, and the transistor is electrically connected to a first electrode. Then, whether the first electrode can receive a signal for controlling pixel light emission may depend on the state of the transistor. When the first electrode is electrically connected to a pixel circuit, the transistor may be a transistor directly electrically connected to the first electrode in the pixel circuit; when the first electrode is electrically connected to a pixel control transistor, the first electrode may be the pixel control transistor. It should be noted that the transistor being electrically connected to the first electrode may mean that the transistor is directly connected to the first electrode through a conductive structure, rather than the transistor needing to be electrically connected to the first electrode through a control structure.

[0065] The transistor includes an active layer 31 and a gate 33. The first lead 11 and the second lead 12 are on the same layer as the gate 33, and the conductive pad 20 is on the same layer as the active layer 31. Then, the conductive pad 20 and the gate 33 of the transistor are prepared simultaneously, and the first lead 11 and the second lead 12 and the active layer 31 of the transistor are prepared simultaneously. Among them, the active layer 31 of the transistor includes a channel and source and drain regions. The source and drain regions are heavily doped regions, and the conductive pad 20 may also be a heavily doped semiconductor structure, that is, the conductive pad 20 may also be prepared simultaneously with the source and drain regions of the active layer 31 included in the transistor by processes such as deposition, etching, and doping.

[0066] An insulating layer 3B is included between the active layer 31 and the gate 33, and this insulating layer 3B is on the same layer as the insulating layer 3B between the lead wire 10 and the conductive pad 20. In addition, the first dielectric layer 3A may extend between the active layer 31 and the substrate 30, and the second dielectric layer 3C may also extend and cover the gate 33.

[0067] The transistor further includes: a source-drain lead layer 34. Refer to Figure 4 and Figure 7 As shown, the source-drain lead layer 34 is connected to the active layer 31 through a third via 32 and is connected to other film layers through a fourth via 35. Conductor posts are provided in both the third via 32 and the fourth via 35; a part of the source-drain lead layer 34 and the resistance connection structure are on the same layer, for example, on the same layer as the connection wire 131. The third via 32 penetrates through the second dielectric layer 3C and the insulating layer 3B to connect to the active layer 131 for leading out source-drain signals outward. Therefore, the third dielectric layer 3D may extend and cover the source-drain lead layer 34, and the fourth via 35 penetrates through the third dielectric layer 3D.

[0068] In an embodiment of the present application, the conductive pad 20 may overlap with the first lead 11 or may overlap with the second lead 12. Of course, the conductive pad 20 may also overlap with both the first lead 11 and the second lead 12 at the same time. At this time, the conductive pad 20 may include a first conductive portion 21 and a second conductive portion 22. Refer to Figure 3 、Figure 6 , Figure 9 , Figure 10 As shown in Figure 10 , in the direction perpendicular to the plane where the substrate 30 is located, the first conductive portion 21 overlaps with the first lead-out wire 11, and the second conductive portion 22 overlaps with the second lead-out wire 12, that is, both ends of the conductive pad 20 are respectively located on both sides of the resistance connection structure 13, so that the charges accumulated on both sides of the resistance connection structure 13 can be respectively released to the conductive pad 20. Among them, in the direction parallel to the plane where the substrate 30 is located, the first conductive portion 21 and the second conductive portion 22 can be presented in a square shape. In this way, the overlapping area of the conductive pad 20 and the lead-out wire 10 is enlarged, and the conductive pads 20 are arranged on both sides, increasing the possibility of electrostatic discharge, improving the electrostatic charge discharge efficiency, and improving the electrostatic protection effect.

[0069] In the embodiment of the present application, the first conductive portion 21 and the second conductive portion 22 can be independently arranged, or the conductive pad 20 can further include a conductive connection portion 23 connected between the first conductive portion 21 and the second conductive portion 22. The conductive connection portion 23 connects the first conductive portion 21 and the second conductive portion 22 together to jointly form a U-shaped conductive pad 20. Refer to Figure 11 and Figure 12 As shown in Figure 12 , the area of the conductive pad 20 is increased, the possibility of electrostatic discharge is increased, and the electrostatic protection effect is improved. Among them,

[0070] the conductive connection portion 23 can be a straight line or a curve. The conductive connection portion 23 can connect the ends on the same side of the first conductive portion 21 and the second conductive portion 22, or can connect the ends on different sides of the first conductive portion 21 and the second conductive portion 22.

[0071] In the direction perpendicular to the plane where the substrate 30 is located, the conductive connection portion 23 does not overlap with the first lead-out wire 11 and the second lead-out wire 12.

[0072] Of course, the conductive connection portion 23 can also overlap with the lead-out portion of at least one of the first lead-out wire 11 and the second lead-out wire 12. Refer to Figure 13As shown, specifically, the display panel 01 may include at least one of a first lead-out portion 111 and a second lead-out portion 121 that are on the same layer as the first lead-out wire 11. In a direction perpendicular to the plane of the substrate, the first lead-out portion 111 overlaps with the conductive connection portion 23. For example, one end of the first lead-out portion 111 is connected to the first lead-out wire 11, and the other end overlaps with the conductive connection portion 23 in a direction perpendicular to the plane of the substrate 30. It is equivalent to the first lead-out wire 11 having the first lead-out portion 111, and the first lead-out portion 111 can serve as a point discharge position; in a direction perpendicular to the plane of the substrate, the second lead-out portion 121 overlaps with the conductive connection portion 23. For example, one end of the second lead-out portion 121 is connected to the second lead-out wire 12, and the other end overlaps with the conductive connection portion 23 in a direction perpendicular to the plane of the substrate 30. It is equivalent to the second lead-out wire 12 having the second lead-out portion 121, and the second lead-out portion 121 can serve as a point discharge position.

[0073] Among them, the first lead-out portion 111 extends in a third direction. In the third direction, the first lead-out portion 111 includes a first connection portion facing the first lead-out wire 11 and a first end portion facing away from the first lead-out wire 11. The size of the first end portion in a fourth direction is smaller than the size of the first connection portion in the fourth direction, and the third direction and the fourth direction intersect. That is, one end of the first lead-out portion 111 that overlaps with the conductive connection portion 23 can be set as a tip, referring to Figure 13 As shown, this can increase the point discharge efficiency. The first end portion can be trapezoidal, triangular, or other polygons.

[0074] The second lead-out portion 121 extends in a third direction. In the third direction, the second lead-out portion 121 includes a second connection portion facing the second lead-out wire 12 and a second end portion facing away from the second lead-out wire 12. The size of the second end portion in a fourth direction is smaller than the size of the second connection portion in the fourth direction, and the third direction and the fourth direction intersect. That is, one end of the second lead-out portion 121 that overlaps with the conductive connection portion 23 can be set as a tip, referring to Figure 13 As shown, this can increase the point discharge efficiency. The second end portion can be trapezoidal, triangular, or other polygons.

[0075] In this way, even during the manufacturing process of the display panel 01 when the resistive connection structure 13 has not been formed yet, when there is electrostatic accumulation in the lead-out wire 10, the first lead-out portion 111 and the second lead-out portion 121, as point discharge positions, can make the electrostatic charge accumulation region be in the tip regions of the first lead-out portion 111 and the second lead-out portion 121, and still can release static electricity to the conductive pad at the tip position. The static electricity release position is in a non-critical part of the display panel 01, which can prevent internal damage to the screen caused by static electricity release.

[0076] An embodiment of the present application provides a display panel, which includes a first region and a second region. The first region is located on one side of the second region close to the edge of the display panel. The display panel includes a substrate, a lead-out wire, and a conductive pad. The lead-out wire is located on one side of the substrate and in the first region. The lead-out wire includes a first lead-out wire, a second lead-out wire, and a resistance connection structure located between the first lead-out wire and the second lead-out wire. The conductive pad is located on one side of the substrate and is in a different layer from the resistance connection structure. In the direction perpendicular to the plane where the substrate is located, the conductive pad overlaps with the first lead-out wire and / or the second lead-out wire. Static electricity is likely to accumulate on both sides of the resistance connection structure for static electricity release. In this way, when there is static electricity at the edge of the display panel, during the process of the static electricity forming a path in the lead-out wire, it is easy to release the static electricity to the conductive pad on both sides of the resistance connection structure, isolate the static electricity on the conductive pad, achieve the directional release of static electricity, prevent the static electricity from affecting the inside of the display panel, and realize the static electricity protection of the display panel while ensuring the electrical signal connection.

[0077] Based on the same inventive concept, an embodiment of the present application further provides a display device, which includes the display panel 01 described in the above embodiment.

[0078] Reference Figure 14 , is a schematic plan view of a display device provided by an embodiment of the present application. As can be seen from the figure, the display device 1000 includes a display panel 01, and the display panel 01 is the display panel 01 described in any of the above embodiments. The display device 1000 provided by an embodiment of the present application can be a display device with a display function such as a mobile phone, a computer, a television, a vehicle-mounted display device, etc., and the embodiment of the present application does not make specific limitations. The display device 1000 provided by an embodiment of the present application has the beneficial effects of the display panel 01 provided by an embodiment of the present application. For specific descriptions of the display panel 01, reference can be made to the above embodiments, and the embodiments of the present application will not be elaborated herein.

[0079] Based on the same inventive concept, an embodiment of the present invention further provides a tiled display device, as Figure 15 shown. The display device is a tiled display device including the above display panel 01. At least part of the first region R1 of the display panel 01 can be its splicing side, and the splicing side is the side of the display panel 01 that is spliced with an adjacent display panel 01. Such a tiled display device can be a tiled large screen and can be applied to public information display (PID) scenarios such as stations and airports. When the tiled display device includes the above display panel 01, the anti-static ability of the device can be effectively improved, thereby improving the display effect of the tiled display device.

[0080] The above are only the preferred embodiments of the present application. Although the present application has been disclosed above with preferred embodiments, it is not intended to limit the present application. Any person skilled in the art can make many possible changes and modifications to the technical solution of the present application, or modify it into equivalent embodiments with equivalent changes, without departing from the scope of the technical solution of the present application. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present application without departing from the content of the technical solution of the present application still fall within the scope of protection of the technical solution of the present application.

Claims

1. A display panel, characterized in that: The display panel includes a first area and a second area, wherein the first area is located on a side of the second area close to an edge of the display panel, and the display panel includes: substrate substrate; Leading wires located at one side of the base substrate and in the first region, the leading wires comprising a first leading wire, a second leading wire, and a resistor connection structure located between the first leading wire and the second leading wire; The conductive pad on one side of the base substrate and on a different layer from the resistor connection structure overlaps the first lead wire and / or the second lead wire in a direction perpendicular to the plane where the base substrate is located.

2. The display panel according to claim 1, characterized in that: The resistance per unit length of the resistance connection structure is greater than the resistance per unit length of the first lead wire or the second lead wire.

3. The display panel according to claim 2, characterized in that: The lead wire extends along a first direction, the length of the resistor connection structure in a second direction is smaller than that of the first lead wire or the second lead wire, and the first direction and the second direction intersect.

4. The display panel according to claim 3, characterized in that: The resistor connection structure is in the same layer as the first lead wire and / or the second lead wire.

5. The display panel according to claim 2, characterized in that: The first lead wire and the second lead wire are in the same layer, and the resistor connection structure and the first lead wire are in a different layer.

6. The display panel according to claim 5, characterized in that: The resistor connection structure includes a connection line located at a different layer from the first lead line; one end of the connection line is connected to the end of the first lead line through a first via hole, and the other end of the connection line is connected to the end of the second lead line through a second via hole.

7. The display panel according to claim 6, characterized in that: The lead wire extends along a first direction; The first via hole includes a first sub-via hole and a second sub-via hole arranged in the first direction, and / or the second via hole includes a third sub-via hole and a fourth sub-via hole arranged in the first direction.

8. The display panel according to claim 6, characterized in that: The lead wire extends along a first direction; The first via hole includes a first sub-via hole and a second sub-via hole arranged in the second direction, and / or the second via hole includes a third sub-via hole and a fourth sub-via hole arranged in the second direction; the first direction and the second direction intersect.

9. The display panel according to claim 5, characterized in that: The resistor connection structure is located at a side of the first lead wire away from the base substrate.

10. The display panel according to claim 1, characterized in that: The conducting pad is located on a side of the first lead or the second lead close to the base substrate.

11. The display panel according to claim 10, characterized in that: The display panel includes a transistor, the transistor includes an active layer and a gate, the first lead wire and the second lead wire are in the same layer as the gate, and the conductive pad is in the same layer as the active layer.

12. The display panel according to claim 1, characterized in that: The conducting pad includes a first conducting portion and a second conducting portion; in a direction perpendicular to a plane where the base substrate is located, the first conducting portion overlaps with the first lead wire, and the second conducting portion overlaps with the second lead wire.

13. The display panel according to claim 12, characterized in that: The conductive pad further includes a conductive connecting portion connected between the first conductive portion and the second conductive portion; In a direction perpendicular to the plane where the substrate is located, the conductive connection portion and the resistance connection structure do not overlap.

14. The display panel according to claim 13, characterized in that: It also includes a first lead-out portion connected to the first lead-out line, the first lead-out portion and the first lead-out line being in the same layer; In a direction perpendicular to a plane where the base substrate is located, the first lead portion overlaps with the conductive connection portion.

15. The display panel according to claim 14, characterized in that: The first lead-out portion extends along a third direction. In the third direction, the first lead-out portion includes a first connecting portion facing the first lead-out line and a first end facing away from the first lead-out line. The size of the first end in a fourth direction is smaller than the size of the first connecting portion in the fourth direction. The third direction intersects with the fourth direction.

16. The display panel according to claim 1, characterized in that: Also includes: An insulating layer is located between the conductive pad and the first lead wire, and between the conductive pad and the second lead wire.

17. The display panel according to claim 1, characterized in that: The display panel includes a signal line to be tested, the signal line to be tested includes at least one of a first signal line, a second signal line and a third signal line, the first signal line is used to transmit a pulse signal, the second signal line is used to transmit a data voltage, and the third signal line is used to transmit a fixed voltage signal; The first lead-out line is connected to the signal line to be tested, and the second lead-out line extends to the edge of the display panel.

18. The display panel according to claim 1, characterized in that: The first region includes a first sub-region and a second sub-region; the first sub-region and the second region are arranged along a first pixel arrangement direction, the second sub-region and the second region are arranged along a second pixel arrangement direction, and the first pixel arrangement direction and the second pixel arrangement direction intersect; At least one of the first sub-region and the second sub-region includes the lead wire.

19. A display device, characterized in that: A display panel comprising any one of claims 1-18.

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