Display panel, manufacturing method thereof and display device

Abstract

The invention relates to a display panel, a manufacturing method thereof and a display device. The display panel comprises an array substrate, a pixel definition layer, a hole layer, a light-emitting layer and a cathode layer. The pixel definition layer is arranged on the array substrate, a plurality of pixel openings are formed in the pixel definition layer, and the pixel definition layer comprises retaining walls arranged between the adjacent pixel openings; the hole layer comprises a hole part arranged in the pixel opening; the light-emitting layer comprises a light-emitting part arranged in the pixel opening and located on the side, away from the array substrate, of the hole part; the cathode layer comprises a first cathode part which is arranged in the pixel opening and is positioned on one side, far away from the hole part, of the light-emitting part; wherein an undercut opening is formed in the side face, close to the pixel opening, of the retaining wall, the hole part and the light-emitting part extend into the undercut opening, and the first cathode part and the hole part are arranged in a spaced mode; according to the display panel, the contact between the hole part and the first cathode part can be avoided, the probability of short circuit between the hole layer and the cathode layer can be reduced, and the performance and the display effect of the display panel are improved.

Description

Technical Field

[0001] This application relates to the field of display technologies, and in particular, to a display panel, a manufacturing method thereof, and a display device. Background Art

[0002] Organic Light-Emitting Diode (OLED) display panels have the advantages of low cost, wide viewing angle, high contrast, and bendability, and have achieved remarkable results in applications such as small and large sizes.

[0003] In the preparation of the organic functional layer of the OLED display panel, in the inkjet printing technology, the ink dissolved with the OLED material is directly drop-coated into the pre-fabricated pixel definition layer, and the required pattern is formed after the solvent volatilizes. For example, the hole injection layer, the hole transport layer, and the light-emitting layer can all be prepared by the inkjet printing process.

[0004] Generally, a hydrophobic surface is formed on the upper side of the dam in the pixel definition layer to make it easier for the ink to flow into the pixel opening; among them, the film layer climbing cut-off points of the hole injection layer, the hole transport layer, and the light-emitting layer on the side wall of the dam are all below the hydrophobic surface, and the climbing heights are not very different. Therefore, at the side wall of the dam, the hole injection layer is easily exposed and not wrapped, and thus the hole injection layer is easily short-circuited with the cathode layer above the light-emitting layer, resulting in leakage and affecting the device performance and display effect. Summary of the Invention

[0005] Embodiments of this application provide a display panel, a manufacturing method thereof, and a display device, which can reduce the probability of short circuit between the hole layer and the cathode layer, and improve the performance and display effect of the display panel.

[0006] Embodiments of this application provide a display panel, which includes:

[0007] An array substrate;

[0008] A pixel definition layer, disposed on the array substrate, wherein a plurality of pixel openings are formed in the pixel definition layer, and the pixel definition layer includes dams disposed between adjacent pixel openings;

[0009] A hole layer, including a hole portion disposed in the pixel opening;

[0010] A light-emitting layer, including a light-emitting portion disposed in the pixel opening and on a side of the hole portion away from the array substrate;

[0011] A cathode layer, including a first cathode portion disposed in the pixel opening and on a side of the light-emitting portion away from the hole portion;

[0012] Wherein, a side surface of the retaining wall close to the pixel opening is provided with an undercut opening, the cavity portion and the light-emitting portion extend into the undercut opening, and the first cathode portion is spaced apart from the cavity portion.

[0013] In an embodiment of the present application, within the pixel opening, a positive projection of the first cathode portion on the array substrate is located within a positive projection of the light-emitting portion on the array substrate.

[0014] In an embodiment of the present application, the retaining wall includes a first sub-portion and a second sub-portion arranged in a stacked manner, and the first sub-portion is located between the second sub-portion and the array substrate;

[0015] The undercut opening is formed in the second sub-portion, and the undercut opening is located on a side of the second sub-portion close to the first sub-portion.

[0016] In an embodiment of the present application, the cavity portion extends into the undercut opening and is located on a side of the first sub-portion away from the array substrate;

[0017] The light-emitting portion extends into the undercut opening and is located on a side of the cavity portion away from the first sub-portion.

[0018] In an embodiment of the present application, the second sub-portion includes a top surface on a side away from the first sub-portion and a side surface connected to the top surface. The side surface includes a bottom side surface on a side close to the first sub-portion and a top side surface on a side away from the first sub-portion. The bottom side surface is recessed toward a side away from the center of the pixel opening relative to the top side surface to form the undercut opening.

[0019] In an embodiment of the present application, the display panel further includes an anode layer provided between the array substrate and the pixel definition layer. The anode layer plate includes a plurality of anodes corresponding to a plurality of the pixel openings, and the cavity portion is located on a side of the anode away from the array substrate;

[0020] Wherein, a positive projection of the bottom side surface on the array substrate is located within a positive projection of the anode on the array substrate, or a positive projection of the bottom side surface on the array substrate is located outside a positive projection of the anode on the array substrate.

[0021] In an embodiment of the present application, a contact angle of the top surface is greater than a contact angle of the bottom side surface, and at least a contact angle of a side of the top side surface away from the bottom side surface is greater than the contact angle of the bottom side surface.

[0022] In an embodiment of the present application, the light-emitting part extends to the bottom side, and there is a first distance between the side of the light-emitting part extending to the bottom side away from the array substrate and the array substrate, and a second distance between the side of the first cathode part away from the array substrate and the array substrate, and the first distance is greater than the second distance.

[0023] In an embodiment of the present application, the display panel further includes a residual part disposed in the undercut opening, and the residual part is located on the side of the first sub-part away from the array substrate;

[0024] Wherein, the material of the residual part includes an inorganic insulating material or a metal material.

[0025] In an embodiment of the present application, a plurality of the pixel openings are arranged in a first direction and a second direction, and the first direction and the second direction intersect;

[0026] The first sub-part extends along the first direction and the second direction and is disposed around each of the pixel openings;

[0027] The second sub-part extends along the second direction, and a plurality of the pixel openings arranged along the second direction are disposed between two adjacent second sub-parts. The undercut opening extends along the second direction, and the undercut openings are formed on both opposite sides of the second sub-part along the first direction.

[0028] In an embodiment of the present application, a plurality of the undercut openings arranged along the second direction are formed on the same side of the second sub-part, and the plurality of undercut openings are correspondingly communicated with the plurality of pixel openings arranged along the second direction, and two adjacent undercut openings are spaced apart in the region between two adjacent pixel openings along the second direction.

[0029] In an embodiment of the present application, the cathode layer further includes a second cathode part located on the side of the pixel defining layer away from the array substrate. The first cathode part and the second cathode part are separated at the undercut opening, and the first cathode part and the second cathode part are connected between two adjacent pixel openings along the second direction.

[0030] In an embodiment of the present application, one undercut opening extending along the second direction is formed on the same side of the second sub-part, and the undercut opening is communicated with the plurality of pixel openings arranged along the second direction.

[0031] In an embodiment of the present application, the cathode layer further includes a third cathode portion and a fourth cathode portion. The third cathode portion is located between two adjacent pixel openings along the second direction and is connected to the first cathode portion in the adjacent pixel opening. The fourth cathode portion is located on the side of the second sub-portion away from the array substrate. The first cathode portion and the fourth cathode portion are separated at the undercut opening, and the third cathode portion and the fourth cathode portion are separated at the undercut opening.

[0032] In an embodiment of the present application, the display panel includes a display area and a non-display area adjacent to the display area. A plurality of pixel openings are provided in the display area, and the third cathode portion and the fourth cathode portion extend from the display area to the non-display area;

[0033] The display panel further includes a cathode connection line provided in the non-display area, and the cathode connection line is connected between the third cathode portion and the fourth cathode portion.

[0034] In an embodiment of the present application, the display panel further includes:

[0035] An electron layer, including a first electron portion provided in the pixel opening and located between the light-emitting portion and the first cathode portion. The first electron portion is spaced apart from the hole portion, and the orthographic projection of the first electron portion on the array substrate is located within the orthographic projection of the light-emitting portion on the array substrate.

[0036] In an embodiment of the present application, the hole layer includes a hole injection layer, and the electron layer includes an electron transport layer.

[0037] According to the above object of the present application, an embodiment of the present application further provides a method for manufacturing a display panel, which includes:

[0038] Forming a pixel definition layer on the array substrate, wherein a plurality of pixel openings and barrier walls located between adjacent pixel openings are formed in the pixel definition layer, and an undercut opening is formed on the side of the barrier wall close to the pixel opening;

[0039] Forming a hole layer, wherein a hole portion located in the pixel opening is formed in the hole layer, and the hole portion extends into the undercut opening;

[0040] Forming a light-emitting layer, wherein a light-emitting portion located in the pixel opening and on the side of the hole portion away from the array substrate is formed in the light-emitting layer, and the light-emitting portion extends into the undercut opening;

[0041] A cathode layer is formed, and a first cathode portion is formed in the cathode layer, which is located within the pixel opening and on the side of the light-emitting portion away from the hole portion. The first cathode portion is disposed at an interval from the hole portion.

[0042] According to the above object of the present application, an embodiment of the present application further provides a display device, and the display device includes the display panel.

[0043] An embodiment of the present application provides a display panel, a manufacturing method thereof, and a display device. By forming an undercut opening on a side of the barrier rib close to the pixel opening, and the hole portion and the light-emitting portion extend into the undercut opening, and the first cathode portion is disposed at an interval from the hole portion, it is possible to avoid contact between the hole portion and the first cathode portion, reduce the probability of short circuit between the hole layer and the cathode layer, and improve the performance and display effect of the display panel.

[0044] Other features and advantages of the present application will be described in detail in the subsequent specific implementation section. Description of the Drawings

[0045] To more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present application. For those skilled in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0046] To more fully understand the present application and its beneficial effects, the following description will be made in conjunction with the drawings, where the same reference numerals represent the same parts in the following description.

[0047] Figure 1 It is a schematic structural diagram of a display panel provided for an embodiment;

[0048] Figure 2 It is a schematic structural diagram of a display panel provided for an embodiment of the present application;

[0049] Figure 3 It is a schematic plan view of a pixel definition layer of a display panel provided for an embodiment of the present application;

[0050] Figure 4 It is a schematic plan view of an electron layer and a cathode layer provided for an embodiment of the present application;

[0051] Figure 5 It is another schematic plan view of an electron layer and a cathode layer provided for an embodiment of the present application;

[0052] Figure 6 It is a flowchart of a manufacturing method of a display panel provided for an embodiment of the present application;

[0053] Figure 7 Schematic structural diagram of the first manufacturing process of the display panel provided by the embodiment of the present application;

[0054] Figure 8 Provided by the embodiment of the present application Figure 7 Cross-sectional structural diagram taken along line aa in;

[0055] Figure 9 Schematic structural diagram of the second manufacturing process of the display panel provided by the embodiment of the present application;

[0056] Figure 10 Provided by the embodiment of the present application Figure 9 Cross-sectional structural diagram taken along line bb in;

[0057] Figure 11 Schematic structural diagram of the third manufacturing process of the display panel provided by the embodiment of the present application;

[0058] Figure 12 Provided by the embodiment of the present application Figure 11 Cross-sectional structural diagram taken along line cc in;

[0059] Figure 13 Schematic structural diagram of the fourth manufacturing process of the display panel provided by the embodiment of the present application;

[0060] Figure 14 Provided by the embodiment of the present application Figure 13 A cross-sectional structural diagram taken along line dd in;

[0061] Figure 15 Provided by the embodiment of the present application Figure 13 Another cross-sectional structural diagram taken along line dd in.

[0062] Explanation of reference numerals:

[0063] 1. Anode; 2. Pixel definition layer; 3. Hole injection layer; 4. Hole transport layer; 5. Light-emitting layer; 6. Cathode layer; 7. Leakage current location;

[0064] 10. Array substrate; 101. Display area; 102. Non-display area;

[0065] 20. Pixel definition layer; 21. Barrier wall; 211. First sub-part; 212. Second sub-part; 201. Pixel opening; 202. Undercut opening; 203. Top surface; 204. Side surface; 2041. Bottom side surface; 2042. Top side surface;

[0066] 30. Hole layer; 31. Hole part;

[0067] 40. Light-emitting layer; 41. Light-emitting part;

[0068] 50. Electron layer; 51. First electron part; 52. Second electron part; 53. Third electron part; 54. Fourth electron part;

[0069] 60. Cathode layer; 61. First cathode part; 62. Second cathode part; 63. Third cathode part; 64. Fourth cathode part; 65. Cathode connection line;

[0070] 70. Anode layer; 71. Anode;

[0071] 81. Spacer structure; 82. Residual part. Detailed implementation manners

[0072] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative efforts belong to the protection scope of the present application.

[0073] Please refer to Figure 1 , the display panel includes an anode 1, a pixel definition layer 2 disposed on the anode 1, a hole injection layer 3, a hole transport layer 4, a light-emitting layer 5, and a cathode layer 6 disposed on the pixel definition layer 2 and the light-emitting layer 5; wherein, a pixel opening is formed in the pixel definition layer 2, and the hole injection layer 3, the hole transport layer 4, and the light-emitting layer 5 can all be located within the pixel opening. Usually, an inkjet printing process can be used to prepare the hole injection layer 3, the hole transport layer 4, and the light-emitting layer 5; in the inkjet printing process, a hydrophobic surface is often formed on the upper side of the dam in the pixel definition layer 2, so that the inks of the hole injection layer 3, the hole transport layer 4, and the light-emitting layer 5 can more easily flow into the pixel opening; wherein, the film layer climbing cut-off points of the hole injection layer 3, the hole transport layer 4, and the light-emitting layer 5 on the side wall of the dam are all located below the hydrophobic surface, and the climbing heights are not very different. Therefore, at the side wall of the dam, the hole injection layer 3 is easily exposed and not wrapped, and thus the hole injection layer 3 is easily in contact with the cathode layer 6 above the light-emitting layer. For example Figure 1 as shown by the leakage current point 7 in

[0074] Please refer to Figure 2 , an embodiment of the present application provides a display panel, and the display panel includes an array substrate 10, a pixel definition layer 20, a hole layer 30, a light-emitting layer 40, and a cathode layer 60.

[0075] The pixel definition layer 20 is disposed on the array substrate 10. A plurality of pixel openings 201 are formed in the pixel definition layer 20. The pixel definition layer 20 includes barrier walls 21 disposed between adjacent pixel openings 201. The hole layer 30 includes hole portions 31 disposed in the pixel openings 201. The light-emitting layer 40 includes light-emitting portions 41 disposed in the pixel openings 201 and on a side of the hole portions 31 away from the array substrate 10. The cathode layer 60 includes first cathode portions 61 disposed in the pixel openings 201 and on a side of the light-emitting portions 41 away from the hole portions 31.

[0076] Wherein, a bottom-cut opening 202 is formed on a side of the barrier wall 21 close to the pixel opening 201. The hole portions 31 and the light-emitting portions 41 extend into the bottom-cut opening 202. The first cathode portions 61 and the hole portions 31 are spaced apart.

[0077] In the implementation and application process, in the embodiment of the present application, the bottom-cut opening 202 is formed on the side of the barrier wall 21 close to the pixel opening 201, and the hole portions 31 and the light-emitting portions 41 extend into the bottom-cut opening 202, while the first cathode portions 61 and the hole portions 31 are spaced apart. Thereby, contact between the hole portions 31 and the first cathode portions 61 can be avoided, the probability of short circuit between the hole layer 30 and the cathode layer 60 can be reduced, and the performance and display effect of the display panel are improved.

[0078] Specifically, please continue to refer to Figure 2 , the display panel further includes an anode layer 70 disposed between the array substrate 10 and the pixel definition layer 20, and the anode layer 70 includes a plurality of anodes 71 disposed at intervals.

[0079] In some embodiments, the array substrate 10 includes a substrate and a thin-film transistor layer disposed on the substrate.

[0080] In some embodiments, the substrate may be a rigid substrate, such as a glass substrate; or, the substrate may be a flexible substrate, such as a substrate formed of polyimide. When the substrate is a flexible substrate, the substrate may be formed of multiple sub-substrates with the same material such as polyimide, and adjacent sub-substrates are bonded by a bonding sub-layer.

[0081] In some embodiments, the thin film transistor layer includes thin film transistors, and each thin film transistor includes a semiconductor located on the substrate. The semiconductor can be formed of polysilicon or a metal oxide (such as indium gallium zinc oxide). The semiconductor is divided into a channel region, a source region formed on both sides of the channel region, and a drain region. The thin film transistor layer further includes a first gate insulating layer covering the semiconductor. The thin film transistor further includes a first gate formed on the first gate insulating layer, and the first gate overlaps with the channel region. The first gate can be formed as a single layer or multiple layers including a low-resistance material such as Al, Ti, Mo, Cu, Ni, or an alloy thereof, or a material with high anti-corrosion performance. The thin film transistor layer further includes a second gate insulating layer covering the first gate. The thin film transistor further includes a second gate located on the second gate insulating layer, and the second gate overlaps with the first gate. The second gate can be formed as a single layer or multiple layers including a low-resistance material such as Al, Ti, Mo, Cu, Ni, or an alloy thereof, or a material with high anti-corrosion performance. The thin film transistor layer further includes a first interlayer insulating layer formed on the second gate. The first interlayer insulating layer, the first gate insulating layer, and the second gate insulating layer include source contact holes and drain contact holes, and the source region and the drain region are respectively exposed through the source contact holes and the drain contact holes.

[0082] The thin film transistor further includes a source and a drain arranged on the same layer, and both the source and the drain are formed on the first interlayer insulating layer. The source passes through the source contact hole and is connected to the source region, and the drain passes through the drain contact hole and is connected to the drain region. The source and the drain can be formed as a single layer or multiple layers including a low-resistance material such as Al, Ti, Mo, Cu, Ni, or an alloy thereof, or a material with high anti-corrosion performance. For example, the source and the drain can be a triple layer such as Ti / Cu / Ti, Ti / Ag / Ti, Ti / Al / Ti, or Mo / Al / Mo, or other single-layer or multi-layer structures.

[0083] In some embodiments, the thin film transistor layer further includes a planarization layer on a side of the first interlayer insulating layer away from the substrate, and the planarization layer covers the source and the drain.

[0084] In some embodiments, the pixel defining layer 20 is disposed on the planarization layer, and a plurality of pixel openings 201 are formed in the pixel defining layer 20.

[0085] In some embodiments, the anode layer 70 is disposed between the flat layer and the pixel defining layer 20, and the anode layer 70 includes a plurality of anodes 71. The plurality of anodes 71 may be arranged in one-to-one correspondence with a plurality of pixel openings 201; the pixel openings 201 expose the surface of the corresponding anode 71 on the side away from the array substrate 10.

[0086] In an embodiment of the present application, the hole portion 31 is located within the pixel opening 201 and on the side of the anode 71 away from the array substrate 10, and the light emitting portion 41 is located within the pixel opening 201 and on the side of the hole portion 31 away from the anode 71.

[0087] In some embodiments, the display panel further includes an electron layer 50. The electron layer 50 is disposed on the pixel defining layer 20. The electron layer 50 includes a first electron portion 51 disposed within the pixel opening 201 and between the light emitting portion 41 and the first cathode portion 61; the cathode layer 60 is disposed on the electron layer 50, and the first cathode portion 61 is disposed within the pixel opening 201 and on the side of the first electron portion 51 away from the light emitting portion 41.

[0088] To prevent the hole portion 31 from being short-circuited with the cathode layer 60 at the sidewall of the pixel opening 201, in an embodiment of the present application, an undercut opening 202 is formed at the sidewall of the pixel opening 201, so that the cathode layer 60 can be disconnected at the undercut opening 202, thereby reducing the probability of short-circuit between the hole layer 30 and the cathode layer 60.

[0089] Furthermore, similarly, to prevent the hole portion 31 from being short-circuited with the electron layer 50 at the sidewall of the pixel opening 201, in an embodiment of the present application, an undercut opening 202 is formed at the sidewall of the pixel opening 201, so that the electron layer 50 can be disconnected at the undercut opening 202, thereby reducing the probability of short-circuit between the hole layer 30 and the electron layer 50.

[0090] In some embodiments, the hole layer 30 includes a hole injection layer, and the electron layer 50 includes an electron transport layer; in addition, the display panel may further include a hole transport layer disposed between the hole layer 30 and the light emitting layer 40 and an electron injection layer disposed between the electron layer 50 and the cathode layer 60.

[0091] Specifically, the pixel definition layer 20 includes a barrier wall 21 disposed between adjacent pixel openings 201, and the barrier wall 21 surrounds each pixel opening 201; a bottom cut opening 202 is formed on a side of the barrier wall 21 close to the pixel opening 201, and the bottom cut opening 202 communicates with the pixel opening 201.

[0092] Wherein, the hole portion 31 is disposed in the pixel opening 201 and extends into the bottom cut opening 202, and the light emitting portion 41 is disposed in the pixel opening 201 and extends into the bottom cut opening 202; while the electron layer 50 and the cathode layer 60 are blocked at the bottom cut opening 202, and the first electron portion 51 and the first cathode portion 61 do not extend into the bottom cut opening 202, or the distance that the first electron portion 51 and the first cathode portion 61 extend into the bottom cut opening 202 is less than the distance that the light emitting portion 41 and the hole portion 31 extend into the bottom cut opening 202.

[0093] It can be understood that in the embodiments of the present application, the hole layer 30 and the light emitting layer 40 can be prepared by an inkjet printing process, which is a liquid process. Furthermore, the ink materials of the hole layer 30 and the light emitting layer 40 can flow into the bottom cut opening 202, so that the hole portion 31 and the light emitting portion 41 can extend into the bottom cut opening 202. The electron layer 50 and the cathode layer 60 can be prepared by an evaporation process. Furthermore, the electron layer 50 and the cathode layer 60 can be blocked at the bottom cut opening 202, and by controlling the evaporation angle, the first electron portion 51 and the first cathode portion 61 do not extend into the bottom cut opening 202, or the portion extending into the bottom cut opening 202 is less, so that the hole portion 31 is spaced apart from the first electron portion 51 and the first cathode portion 61.

[0094] It should be noted that within the pixel opening 201, the orthographic projection of the first electron portion 51 on the array substrate 10 is located within the orthographic projection of the light emitting portion 41 on the array substrate 10, and the orthographic projection of the first cathode portion 61 on the array substrate 10 is located within the orthographic projection of the light emitting portion 41 on the array substrate 10; furthermore, the light emitting portion 41 is spaced between the first electron portion 51 and the hole portion 31, the light emitting portion 41 is spaced between the first cathode portion 61 and the hole portion 31, or the light emitting portion 41 and the first electron portion 51 are spaced therebetween; therefore, in the embodiments of the present application, by providing the bottom cut opening 202 on the side surface of the barrier wall 21, the probability of short circuit between the hole portion 31 and the first electron portion 51 and the first cathode portion 61 can be effectively reduced, and the performance and display effect of the display panel are improved.

[0095] Further, please combine Figure 2 and Figure 3 , a plurality of the pixel openings 201 may be arranged in an array along a first direction X and a second direction Y, and the first direction X and the second direction Y intersect each other.

[0096] In some embodiments, the first direction X and the second direction Y are perpendicular to each other.

[0097] Wherein, the barrier wall 21 in the pixel definition layer 20 includes a first sub - portion 211 and a second sub - portion 212 which are stacked, and the first sub - portion 211 is located between the second sub - portion 212 and the array substrate 10.

[0098] In some embodiments, the first sub - portion 211 extends along the first direction X and the second direction Y and surrounds each of the pixel openings 201; the second sub - portion 212 extends along the second direction Y and is located on a side of the first sub - portion 211 extending along the second direction Y away from the array substrate 10.

[0099] In some embodiments, a plurality of the second sub - portions 212 are arranged along the first direction X, and a plurality of the pixel openings 201 arranged along the second direction Y are provided between two adjacent second sub - portions 212.

[0100] It should be noted that the thickness of the first sub - portion 211 is less than the thickness of the second sub - portion 212, and the hole layer 30 and the light - emitting layer 40 may be continuously provided along the second direction Y, and the hole layer 30 and the light - emitting layer 40 are spaced along the first direction X.

[0101] Wherein, the hole layer 30 further includes an auxiliary hole portion disposed between two adjacent pixel openings 201 along the second direction Y, and the hole portions 31 in two adjacent pixel openings 201 are connected through the auxiliary hole portion, and the auxiliary hole portion is located on a side of the first sub - portion 211 away from the array substrate 10; the light - emitting layer 40 further includes an auxiliary light - emitting portion disposed between two adjacent pixel openings 201 along the second direction Y, and the light - emitting portions 41 in two adjacent pixel openings 201 are connected through the auxiliary light - emitting portion, and the auxiliary light - emitting portion is located on a side of the auxiliary hole portion away from the first sub - portion 211.

[0102] The hole portions 31 in two adjacent pixel openings 201 along the first direction X are separated and spaced apart by the second sub-portion 212, and the light-emitting portions 41 in two adjacent pixel openings 201 along the first direction X are separated and spaced apart by the second sub-portion 212.

[0103] In some embodiments, since the second sub-portion 212 needs to separate the hole layer 30 and the light-emitting layer 40 along the first direction X, the thickness of the second sub-portion 212 is relatively large. Therefore, a bottom-cut opening 202 is formed in the second sub-portion 212, and the bottom-cut opening 202 is located on the side of the second sub-portion 212 close to the first sub-portion 211.

[0104] The second sub-portion 212 includes a top surface 203 on a side away from the first sub-portion 211 and a side surface 204 connected to the top surface 203. The side surface 204 includes a bottom side surface 2041 on a side close to the first sub-portion 211 and a top side surface 2042 on a side away from the first sub-portion 211. The bottom side surface 2041 is recessed towards a side away from the center of the pixel opening 201 relative to the top side surface 2042 to form the bottom-cut opening 202.

[0105] In some embodiments, the orthographic projection of the bottom side surface 2041 on the array substrate 10 is within the orthographic projection of the anode 71 on the array substrate 10, or the orthographic projection of the bottom side surface 2041 on the array substrate 10 is outside the orthographic projection of the anode 71 on the array substrate 10.

[0106] In some embodiments, the width of the second sub-portion 212 along the first direction X is less than the width of the first sub-portion 211 along the first direction X.

[0107] In some embodiments, the hole portion 31 extends into the bottom-cut opening 202 and is located on the side of the first sub-portion 211 away from the array substrate 10; the light-emitting portion 41 extends into the bottom-cut opening 202 and is located on the side of the hole portion 31 away from the first sub-portion 211.

[0108] In some embodiments, the contact angle of the top surface 203 is greater than that of the bottom side surface 2041, and at least the contact angle of the side surface 2042 away from the first sub - portion 211 is greater than that of the bottom side surface 2041; further, the top surface 203 and at least the side surface 2042 away from the first sub - portion 211 can be hydrophobic surfaces, and the contact angles of the top surface 203 and at least the side surface 2042 away from the first sub - portion 211 can both be greater than 90°, while the bottom side surface 2041 can be a hydrophilic surface, and the contact angle of the bottom side surface 2041 can be less than 90°; thus, during the ink - jet printing process, it is more conducive to the ink of the hole layer 30 and the light - emitting layer 40 flowing into the pixel opening 201.

[0109] It can be understood that the bottom side surface 2041 being a hydrophilic surface is more conducive to the ink of the hole layer 30 and the light - emitting layer 40 flowing into the undercut opening 202, so that the hole portion 31 and the light - emitting portion 41 can extend into the undercut opening 202.

[0110] In some embodiments, the light - emitting portion 41 extends to the bottom side surface 2041, and there is a first distance H1 between the side of the light - emitting portion 41 extending to the bottom side surface 2041 and away from the array substrate 10 and the array substrate 10, and there is a second distance H2 between the side of the first cathode portion 61 away from the array substrate 10 and the array substrate 10, and the first distance H1 is greater than the second distance H2; it can be understood that because the bottom side surface 2041 is hydrophilic, the ink of the light - emitting portion 41 will form a slope at the bottom side surface 2041. Furthermore, the film surface of the light - emitting portion 41 formed at the bottom side surface 2041 will be higher than the film surface of the first cathode portion 61, thereby improving the coating effect of the light - emitting portion 41 on the hole portion 31 and further reducing the probability of short - circuit between the hole portion 31 and the first cathode portion 61.

[0111] In the embodiments of the present application, the undercut opening 202 is provided on the side surface of the second sub - portion 212. Therefore, the undercut opening 202 also extends along the second direction Y, and the undercut openings 202 are provided on both opposite sides of the second sub - portion 212 along the first direction X.

[0112] In one embodiment of the present application, please refer to Figure 2 、 Figure 3 and Figure 4, a plurality of the undercut openings 202 arranged along the second direction Y are formed on the same side of the second sub - portion 212, and the plurality of the undercut openings 202 communicate with the plurality of the pixel openings 201 arranged along the second direction Y correspondingly, that is, the undercut openings 202 extending along the second direction Y are arranged on the opposite two sides of each pixel opening 201 along the first direction X; two adjacent undercut openings 202 corresponding to two adjacent pixel openings 201 along the second direction Y are arranged at intervals in the region between the two adjacent pixel openings 201 along the second direction Y.

[0113] Wherein, the electronic layer 50 further includes a second electronic portion 52 located on the side of the pixel definition layer 20 away from the array substrate 10. The second electronic portion 52 extending along the second direction Y is located on the side of the second sub - portion 212 away from the array substrate 10, and the second electronic portion 52 extending along the first direction X is located on the side of the first sub - portion 211 away from the array substrate 10.

[0114] The first electronic portion 51 and the second electronic portion 52 are separated at the undercut opening 202, and the first electronic portion 51 and the second electronic portion 52 are connected between two adjacent pixel openings 201 along the second direction Y.

[0115] Further, the cathode layer 60 further includes a second cathode portion 62 located on the side of the pixel definition layer 20 away from the array substrate 10. The second cathode portion 62 extending along the second direction Y is located on the side of the second sub - portion 212 away from the array substrate 10, and the second cathode portion 62 extending along the first direction X is located on the side of the first sub - portion 211 away from the array substrate 10.

[0116] The first cathode portion 61 and the second cathode portion 62 are separated at the undercut opening 202, and the first cathode portion 61 and the second cathode portion 62 are connected between two adjacent pixel openings 201 along the second direction Y.

[0117] It can be understood that the hole layer 30 and the light-emitting layer 40 are continuously arranged along the second direction Y between the adjacent second sub-parts 212. Further, along the second direction Y, the light-emitting layer 40 can cover the hole layer 30 without causing a short circuit between the hole layer 30 and the electron layer 50 and the cathode layer 60. Along the first direction X, the hole layer 30 and the light-emitting layer 40 are blocked by the second sub-part 212 and slope at the side wall of the second sub-part 212. Therefore, in the embodiment of the present application, the undercut opening 202 extends along the second direction Y, and thus can block the electron layer 50 and the cathode layer 60 between two adjacent pixel openings 201 along the first direction X, so as to prevent the hole layer 30 from connecting with the electron layer 50 and the cathode layer 60 during the sloping process, avoid the occurrence of leakage current phenomenon, and improve the performance and display effect of the display panel.

[0118] In another embodiment of the present application, please refer to Figure 2 , Figure 3 and Figure 5 , one undercut opening 202 extending along the second direction Y is formed on the same side of the second sub-part 212, and the undercut opening 202 is communicated with a plurality of pixel openings 201 arranged along the second direction Y; that is, Figure 4 the plurality of undercut openings 202 arranged along the second direction Y in the illustrated embodiment are communicated with each other.

[0119] The electron layer 50 further includes a third electron part 53 and a fourth electron part 54. The third electron part 53 is located between two adjacent pixel openings 201 along the second direction Y and is connected to the first electron part 51 in the adjacent pixel opening 201. The fourth electron part 54 is located on the side of the second sub-part 212 away from the array substrate 10. The first electron part 51 and the fourth electron part 54 are blocked at the undercut opening 202, and the third electron part 53 and the fourth electron part 54 are blocked at the undercut opening 202. Among them, the third electron part 53 connects the plurality of first electron parts 51 in the plurality of pixel openings 201 arranged along the second direction Y to form a whole strip along the second direction Y. The whole strip of the first electron part 51 and the third electron part 53 are arranged at intervals with a whole strip of the fourth electron part 54 extending along the second direction Y.

[0120] In this embodiment, the cathode layer 60 further includes a third cathode portion 63 and a fourth cathode portion 64. The third cathode portion 63 is located between two adjacent pixel openings 201 along the second direction Y and is connected to the first cathode portion 61 within the adjacent pixel openings 201. The fourth cathode portion 64 is located on the side of the second sub-portion 212 away from the array substrate 10. The first cathode portion 61 and the fourth cathode portion 64 are separated at the undercut opening 202, and the third cathode portion 63 and the fourth cathode portion 64 are separated at the undercut opening 202. Among them, the third cathode portion 63 connects multiple first cathode portions 61 among the multiple pixel openings 201 arranged along the second direction Y to form a whole strip arranged along the second direction Y. The whole strip of the first cathode portion 61 and the third cathode portion 63 are spaced apart from a whole strip of the fourth cathode portion 64 extending along the second direction Y.

[0121] It should be noted that the display panel includes a display area 101 and a non-display area 102 adjacent to the display area 101. Multiple pixel openings 201 are provided in the display area 101. The third cathode portion 63 and the fourth cathode portion 64 extend from the display area 101 to the non-display area 102. The display panel further includes a cathode connection line 65 provided in the non-display area 102, and the cathode connection line 65 is connected between the third cathode portion 63 and the fourth cathode portion 64 to connect the first cathode portion 61, the third cathode portion 63, and the fourth cathode portion 64 in the display area 101, facilitating signal input.

[0122] Continuing from the above, in the embodiment of the present application, by providing the undercut opening 202 on the side of the barrier rib 21, and the undercut opening 202 extends along the second direction Y, the electron layer 50 and the cathode layer 60 between two adjacent pixel openings 201 along the first direction Y can be separated, and the hole portion 31 and the light-emitting portion 41 can be extended into the undercut opening 202 to prevent the hole layer 30 from connecting with the electron layer 50 and the cathode layer 60 during the climbing process, avoiding the occurrence of leakage current, and improving the performance and display effect of the display panel.

[0123] In addition, the embodiment of the present application also provides a manufacturing method of the display panel described in the above embodiment. Please refer to Figure 2 、 Figure 3 、 Figure 6 、 Figures 7 to 15 as shown.

[0124] The manufacturing method of the display panel includes the following steps:

[0125] S10. Form a pixel definition layer 20 on the array substrate 10. A plurality of pixel openings 201 and barriers 21 located between adjacent pixel openings 201 are formed in the pixel definition layer 20. An undercut opening 202 is formed on a side surface of the barrier 21 close to the pixel opening 201.

[0126] S20. Form a hole layer 30. A hole portion 31 located within the pixel opening 201 is formed in the hole layer 30, and the hole portion 31 extends into the undercut opening 202.

[0127] S30. Form a light-emitting layer 40. A light-emitting portion 41 located within the pixel opening 201 and on a side of the hole portion 31 away from the array substrate 10 is formed in the light-emitting layer 40, and the light-emitting portion 41 extends into the undercut opening 202.

[0128] S40. Form a cathode layer 60. A first cathode portion 61 located within the pixel opening 201 and on a side of the light-emitting portion 41 away from the hole portion 31 is formed in the cathode layer 60, and the first cathode portion 61 is disposed at an interval from the hole portion 31.

[0129] Specifically, in step S10, an anode layer 70 is formed on the array substrate 10, and a plurality of anodes 71 arranged along a first direction X and a second direction Y are formed in the anode layer 70.

[0130] A first sub-portion 211 is formed on the array substrate 10. The first sub-portion 211 extends along the first direction X and along the second direction Y, and surrounds each anode 71. The first sub-portion 211 covers a partial surface of the anode 71 near the edge. A surrounded area of the first sub-portion 211 is the pixel opening 201, as Figure 7 and Figure 8 shown.

[0131] Then, a spacer structure 81 is formed on a side of the first sub-portion 211 close to the center of the anode 71. A part of the spacer structure 81 is located on a side of the first sub-portion 211 away from the array substrate 10, and another part of the spacer structure 81 may extend to a surface of the anode 71 on a side away from the array substrate 10, as Figure 9 and Figure 10 shown.

[0132] In some embodiments, the spacer structure 81 is located on opposite sides of the anode 71 along the first direction X, and the spacer structure 81 extends along the second direction Y.

[0133] In some embodiments, the material of the spacer structure 81 may include an inorganic insulating material or a metal material; for example, when the spacer structure 81 is an inorganic insulating material, it may include silicon oxide or silicon nitride; when the spacer structure 81 is a metal material, it may be a metal element, a metal alloy or a metal oxide, and may be aluminum, copper, molybdenum or indium zinc oxide.

[0134] Next, a second sub - portion 212 is formed on the first sub - portion 211, and the second sub - portion 212 extends along the second direction Y and is located on the side of the first sub - portion 211 extending along the second direction Y away from the array substrate 10; between two adjacent second sub - portions 212 along the first direction X, a plurality of pixel openings 201 arranged along the second direction Y are provided.

[0135] Wherein, one side of the second sub - portion 212 close to the pixel opening 201 covers one side of the spacer structure 81 away from the first sub - portion 211, as Figure 11 and Figure 12 shown.

[0136] Then, the spacer structure 81 is removed, and then a bottom - cut opening 202 can be formed on the side of the second sub - portion 212 close to the pixel opening 201, and the pixel opening 201 is located on the side of the second sub - portion 212 close to the first sub - portion 211, as Figure 13 and Figure 14 shown.

[0137] In some embodiments, there may be residues during the removal of the spacer structure 81, and then a residue portion 82 will be formed in the bottom - cut opening 202, and the residue portion 82 is located on the side of the first sub - portion 211 away from the array substrate 10, as Figure 15 shown.

[0138] In some embodiments, the material of the residue portion 82 may include an inorganic insulating material or a metal material; for example, when the residue portion 82 is an inorganic insulating material, it may include silicon oxide or silicon nitride; when the residue portion 82 is a metal material, it may be a metal element, a metal alloy or a metal oxide, and may be aluminum, copper, molybdenum or indium zinc oxide.

[0139] In step S20, an ink - jet printing process is used to form a hole layer 30 on the pixel definition layer 20, and the hole layer 30 includes the hole portions 31 disposed in each of the pixel openings 201, and the hole portions 31 extend into the bottom - cut opening 202.

[0140] In step S30, an inkjet printing process is used to form a light-emitting layer 40 on the hole layer 30. The light-emitting layer 40 includes a light-emitting portion 41 disposed in each pixel opening 201, and the light-emitting portion 41 is located on a side of the hole portion 31 away from the array substrate 10 and extends into the undercut opening 202.

[0141] In step S40, an evaporation process is used to form an electron layer 50 on the light-emitting layer 40. A first electron portion 51 is formed in the electron layer 50 within the pixel opening 201 and on a side of the light-emitting portion 41 away from the hole portion 31, and the first electron portion 51 is spaced apart from the hole portion 31.

[0142] Next, an evaporation process is used to form a cathode layer 60 on the electron layer 50. A first cathode portion 61 is formed in the cathode layer 60 within the pixel opening 201 and on a side of the first electron portion 51 away from the light-emitting portion 41, and the first cathode portion 61 is spaced apart from the hole portion 31.

[0143] In summary, in the embodiment of the present application, an undercut opening 202 is formed on a side of the barrier rib 21 close to the pixel opening 201, and the hole portion 31 and the light-emitting portion 41 extend into the undercut opening 202, while the first cathode portion 61 and the first electron portion 51 are spaced apart from the hole portion 31. Therefore, contact between the hole portion 31 and the first cathode portion 61 and the first electron portion 51 can be avoided, the probability of short circuit between the hole layer 30 and the cathode layer 60 and the electron layer 50 can be reduced, and the performance and display effect of the display panel can be improved.

[0144] In addition, an embodiment of the present application further provides a display device, which includes the display panel described in the above embodiment, or a display panel manufactured by using the manufacturing method of the display panel described in the above embodiment.

[0145] In the description of the present application, the terms "first" and "second" are only used for descriptive purposes and cannot be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more features. In the description of the present application, "a plurality of" means two or more unless otherwise specifically defined.

[0146] In the above embodiments, the descriptions of the respective embodiments have their own emphases. For parts not detailed in a certain embodiment, reference may be made to the relevant descriptions of other embodiments.

[0147] The embodiments, implementation manners and related technical features of the present application can be combined and replaced with each other without conflict.

[0148] The above are only the preferred embodiments of the present application, and do not impose any formal restrictions on the present application. However, any simple modifications, equivalent changes and decorations made to the above embodiments based on the technical essence of the present application without departing from the content of the technical solution of the present application still fall within the scope of the technical solution of the present application.

Claims

1. A display panel, characterized in that: include: An array substrate; A pixel definition layer is disposed on the array substrate, a plurality of pixel openings are formed in the pixel definition layer, and the pixel definition layer includes retaining walls disposed between adjacent pixel openings; a cavity layer, comprising a cavity portion disposed in the pixel opening; a light-emitting layer, comprising a light-emitting portion disposed in the pixel opening and located on a side of the cavity portion away from the array substrate; A cathode layer, comprising a first cathode portion disposed in the pixel opening and located on a side of the light emitting portion away from the cavity portion; The side of the retaining wall close to the pixel opening is provided with an undercut opening, the cavity portion and the light emitting portion extend into the undercut opening, and the first cathode portion is spaced apart from the cavity portion.

2. The display panel according to claim 1, characterized in that: In the pixel opening, an orthographic projection of the first cathode portion on the array substrate is located within an orthographic projection of the light emitting portion on the array substrate.

3. The display panel according to claim 1, characterized in that: The retaining wall comprises a first sub-portion and a second sub-portion which are stacked, and the first sub-portion is located between the second sub-portion and the array substrate; The undercut opening is formed in the second sub-portion, and the undercut opening is located at a side of the second sub-portion close to the first sub-portion.

4. The display panel according to claim 3, characterized in that: The cavity portion extends into the undercut opening and is located at a side of the first sub-portion away from the array substrate; The light emitting portion extends into the undercut opening and is located at a side of the cavity portion away from the first sub-portion.

5. The display panel according to claim 3, characterized in that: The second sub-section includes a top surface away from the first sub-section and a side surface connected to the top surface, the side surface includes a bottom side close to the first sub-section and a top side away from the first sub-section, the bottom side is retracted relative to the top side toward a side away from the center of the pixel opening to form the undercut opening.

6. The display panel according to claim 5, characterized in that: The display panel further comprises an anode layer disposed between the array substrate and the pixel definition layer, the anode layer comprises a plurality of anodes disposed corresponding to the plurality of pixel openings, and the cavity portion is located on a side of the anode away from the array substrate; The orthographic projection of the bottom side surface on the array substrate is located within the orthographic projection of the anode on the array substrate, or the orthographic projection of the bottom side surface on the array substrate is located outside the orthographic projection of the anode on the array substrate.

7. The display panel according to claim 5, characterized in that: The contact angle of the top surface is greater than the contact angle of the bottom side surface, and at least the contact angle of the top side surface away from the bottom side surface is greater than the contact angle of the bottom side surface.

8. The display panel according to claim 5, characterized in that: The light-emitting portion extends to the bottom side, and the light-emitting portion extending to the bottom side has a first distance from the side away from the array substrate to the array substrate, and the first cathode portion has a second distance from the side away from the array substrate to the array substrate, and the first distance is greater than the second distance.

9. The display panel according to claim 3, characterized in that: The display panel further comprises a residual portion disposed in the undercut opening, wherein the residual portion is located on a side of the first sub-portion away from the array substrate; Wherein, the material of the residual part includes inorganic insulating material or metal material.

10. The display panel according to any one of claims 3 to 9, characterized in that: The plurality of pixel openings are arranged along a first direction and a second direction, and the first direction and the second direction intersect; The first sub-portion extends along the first direction and the second direction and is arranged around each of the pixel openings; The second sub-portion extends along the second direction, a plurality of the pixel openings arranged along the second direction are arranged between two adjacent second sub-portions, the bottom cut opening extends along the second direction, and the bottom cut openings are arranged on opposite sides of the second sub-portion along the first direction.

11. The display panel according to claim 10, characterized in that: A plurality of bottom cut openings arranged along the second direction are provided on the same side of the second sub-portion, and the plurality of bottom cut openings are correspondingly connected to the plurality of pixel openings arranged along the second direction, and two adjacent bottom cut openings are spaced apart in the area between two adjacent pixel openings along the second direction.

12. The display panel according to claim 10, characterized in that: The cathode layer also includes a second cathode portion located on a side of the pixel definition layer away from the array substrate, the first cathode portion and the second cathode portion are separated at the bottom cut opening, and the first cathode portion and the second cathode portion are connected between two adjacent pixel openings along the second direction.

13. The display panel according to claim 10, characterized in that: An undercut opening extending along the second direction is formed on the same side of the second sub-portion, and the undercut opening is connected to a plurality of pixel openings arranged along the second direction.

14. The display panel according to claim 13, characterized in that: The cathode layer also includes a third cathode portion and a fourth cathode portion, the third cathode portion is located between two adjacent pixel openings along the second direction and is connected to the first cathode portion in the adjacent pixel opening, the fourth cathode portion is located on the side of the second sub-portion away from the array substrate, the first cathode portion and the fourth cathode portion are separated at the bottom cut opening, and the third cathode portion and the fourth cathode portion are separated at the bottom cut opening.

15. The display panel according to claim 14, characterized in that: The display panel comprises a display area and a non-display area adjacent to the display area, a plurality of pixel openings are arranged in the display area, and the third cathode portion and the fourth cathode portion extend from the display area to the non-display area; The display panel further includes a cathode connection line disposed in the non-display area, and the cathode connection line is connected between the third cathode portion and the fourth cathode portion.

16. The display panel according to any one of claims 1 to 9, characterized in that: The display panel further includes: The electron layer includes a first electron portion arranged in the pixel opening and located between the light-emitting portion and the first cathode portion, the first electron portion is spaced apart from the hole portion, and the orthographic projection of the first electron portion on the array substrate is located within the orthographic projection of the light-emitting portion on the array substrate.

17. The display panel according to claim 16, characterized in that: The hole layer includes a hole injection layer, and the electron layer includes an electron transport layer.

18. A method for manufacturing a display panel, characterized in that: include: A pixel definition layer is formed on the array substrate, wherein a plurality of pixel openings and a retaining wall located between adjacent pixel openings are formed in the pixel definition layer, and an undercut opening is formed on a side of the retaining wall close to the pixel opening; forming a cavity layer, wherein a cavity portion located in the pixel opening is formed in the cavity layer, and the cavity portion extends into the undercut opening; forming a light-emitting layer, wherein the light-emitting layer includes a light-emitting portion located in the pixel opening and on a side of the cavity portion away from the array substrate, and the light-emitting portion extends into the undercut opening; A cathode layer is formed, wherein a first cathode portion is formed in the cathode layer and is located in the pixel opening and on a side of the light emitting portion away from the cavity portion, and the first cathode portion is spaced apart from the cavity portion.

19. A display device, characterized in that: The display device comprises the display panel according to any one of claims 1 to 17.

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