Negative transient voltage suppression in wireless communication device

Abstract

Circuits and methods for suppressing negative transient voltages may be implemented in systems that combine high speed data, audio, and charging at plugs. Circuits and methods for suppressing negative transient voltages may include a first diode (322) and a transistor (324) coupled in series between a pin (DNL) and ground, wherein the transistor (324) is controlled by an output of a voltage comparator (310) also coupled to the first pin (DNL). The negative transient voltage event may cause the comparator (310) to activate the transistor (324) to absorb current through the diode (322).

Description

[0001] Cross - Reference to Related Applications

[0002] This application claims the benefit and priority of U.S. Patent Application No. 18 / 055,306, filed on November 14, 2022, the disclosure of which is incorporated herein by reference in its entirety as if fully set forth below and for all applicable purposes. Field of the Invention

[0003] This application relates to transient voltage suppression and, more particularly, to negative transient voltage protection in wireless communication devices. Background Art

[0004] Some wireless communication devices (e.g., smartphones) are evolving towards having a single input for high - speed data, direct current (DC) charging, and analog audio signals. However, sharing the responsibility for data, audio, and DC charging at a single input can create the possibility of voltage surges, which can potentially damage internal circuits. For example, IEC - 61000 - 4 - 5 imposes constraints on the reliability of connector pins and, thus, on the response time of detection circuits in response to high - voltage events that may affect those connector pins. However, another constraint for some wireless communication devices is low distortion, and thus, in some applications where large transistors would be affected by the capacitance of those large transistors, using large transistors to dissipate voltage surges may be prohibited.

[0005] There is a need in the art for voltage suppression circuits with improved performance and reduced capacitance. Summary of the Invention

[0006] In one embodiment, a wireless communication device includes: an application processor; an audio signal amplifier; a charging integrated circuit, wherein the application processor, the audio signal amplifier, and the charging integrated circuit are coupled to a set of wires through a multiplexing circuitry; a first pin on a first wire of the set of wires; a data and charging plug, the data and charging plug being coupled to the set of wires through the first pin; a first voltage comparator having an inverting input coupled to the first pin, wherein a non - inverting input of the first voltage comparator is coupled to a reference voltage; and a first diode and a transistor serially coupled between the first pin and ground, wherein a gate of the transistor is coupled to an output of the first voltage comparator.

[0007] In another embodiment, a method of operating a transient voltage suppression circuit includes: receiving a negative current surge at a data and audio combined pin; applying a level-shifted voltage at a first input of a voltage comparator, wherein the level-shifted voltage is reduced due to the negative current surge, and further wherein the first input of the voltage comparator is coupled to the data and audio combined pin; changing an output state of the voltage comparator in response to the level-shifted voltage dropping below a reference voltage level at a second input of the voltage comparator; turning on a voltage clamp through the output state of the voltage comparator; and absorbing a current associated with the negative current surge through a diode serially coupled between the data and audio combined pin and the voltage clamp.

[0008] In another embodiment, a wireless communication device includes: an application processor; an audio signal amplifier; a charging integrated circuit; components for multiplexing the application processor, the audio signal amplifier, and the charging integrated circuit over a set of wires; a first pin on a first wire of the set of wires; a data and charging plug coupled to the set of wires through the first pin; and components for canceling a negative surge at the first pin, wherein the components for canceling include a first diode and a shunt transistor serially coupled between ground and the first pin.

[0009] In yet another embodiment, a wireless communication device includes a first chip and an audio signal amplifier coupled to a set of wires through a multiplexing circuitry; a first pin on the set of wires, wherein the first pin is coupled to a combined data and audio plug; a codec chip including a set of wires and a multiplexing circuitry; an electrostatic discharge (ESD) protection feedback loop, wherein the ESD protection feedback loop couples the first pin to a first input of a first comparator and couples an output of the first comparator to a gate of a shunt transistor, wherein the shunt transistor is serially coupled between a first diode and ground.

[0010] These and additional advantages can be better understood from the following detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 FIG. illustrates a block diagram of an example wireless device including a circuit for negative voltage transient suppression, in accordance with one embodiment.

[0012] Figure 2 FIG. illustrates an example architecture for multiplexing an audio signal, a high-speed data signal, and charging while providing negative voltage transient suppression in a device (e.g., Figure 1 of a device), in accordance with one embodiment.

[0013] Figure 3 FIG. illustrates, in accordance with one embodiment, that can be in Figure 2An example circuit for negative voltage transient suppression used in the architecture of

[0014] Figure 4 Illustrates an example circuit for negative voltage transient suppression that can be used in the architecture of Figure 2 An example circuit for negative voltage transient suppression used in the architecture of

[0015] Figure 5 Shows a flowchart of an example method that can be performed by the Figures 2 to 4 circuit of

[0016] The embodiments of the present disclosure and their advantages can be best understood by referring to the following detailed description. It should be understood that the same reference numerals are used to identify the same elements shown in one or more of the drawings. Detailed Description

[0017] In one example, a wireless device includes a Universal Serial Bus (USB) Type-C (USB-C) socket for charging, for high-speed data, and for analog audio signals. For example, the device can omit a 3.5 mm audio jack, facilitating the use of the USB-C socket to physically attach a headset or earbuds. An advantage of such devices is that they can use a single chip for both USB-C and audio, thus saving area within the device's enclosure.

[0018] A disadvantage of using a USB-C socket for analog audio is that the physical pins on a set of wires coupled to the charging hardware, data hardware, and audio amplifier can be subject to overvoltage phenomena, such as negative surges due to negative transient voltages. Specifically, relatively long cables, such as those that can be associated with a USB or audio cable, can build up static charge. When the cable is inserted into the device, this static charge can then discharge into the device.

[0019] One solution to handle negative surges is to employ a shunt clamp device; however, the shunt clamp device can be relatively large to handle the magnitude of current that may be expected. For example, one solution includes sizing the shunt device as a transistor with a width of 4 mm per ampere of surge. For a device expected to handle up to 6 A, the transistor would have a width of approximately 24 mm. The capacitance attributable to the 24 mm transistor would be expected to be quite large enough to substantially reduce the bandwidth of a high-speed data connection. The various embodiments herein provide effective negative surge protection while reducing capacitance.

[0020] In one example, a wireless communication device includes an application processor, an audio signal amplifier, and a charging integrated circuit (IC) coupled to a set of wires through multiplexing circuitry. The first set of wires may include pins, and a data and charging plug are coupled to the set of wires through the pins. This implementation provides negative surge protection at the pins to reduce harmful voltages and currents that may be seen at the application processor, audio signal amplifier, charging integrated circuit, or codec chip coupled to the wires.

[0021] Continuing with the example, the voltage protection circuit includes a first voltage comparator. The inverting input of the comparator is coupled to a first pin, and the non-inverting input is coupled to a reference voltage. The reference voltage is selected such that when the voltage level at the inverting input drops below the reference voltage, the comparator output signals to turn on a shunt transistor.

[0022] The voltage protection circuit may include the shunt transistor (mentioned above) and a diode. The shunt transistor and the diode may be placed in series with ground. The gate of the shunt transistor is coupled to the output of the comparator.

[0023] In one example use case, a negative surge may cause the voltage at the pin to drop, causing the voltage level at the inverting input of the comparator to drop and causing the output of the comparator to change state. When the output of the comparator changes state, the output voltage level of the comparator turns on the shunt transistor, which allows current to flow from ground to the pin and counteracts the negative surge.

[0024] The diode may be implemented with low capacitance. For example, the diode may be implemented as a positive-negative (p-n) junction device rather than a metal-oxide-semiconductor field-effect transistor (MOSFET) transistor connected in a diode arrangement. The physical characteristics of the p-n junction device allow a smaller device with lower capacitance to absorb a given amount of current, while a MOSFET transistor is typically expected to be much larger to absorb the same amount of current. The combined series capacitance of the low-capacitance diode and the high-capacitance shunt transistor is lower than the capacitance of the high-capacitance shunt transistor. In some examples, the capacitance of the diode may be designed to be much lower (e.g., greater than an order of magnitude) than the capacitance of the shunt transistor, such that the combined capacitance is closer to the capacitance of the diode than to the capacitance of the shunt transistor.

[0025] In other words, various implementations can be designed to provide effective protection against negative surges while also reducing the capacitance seen at the pins from the voltage protection device. The lower capacitance can result in less distortion and thus a higher bandwidth on the wires.

[0026] Figure 1FIG. 100 illustrates an example device 100 in which aspects of the present disclosure may be implemented. Device 100 may be a battery-operated device such as a cellular phone, a handheld device, a wireless device, a laptop computer, a tablet computer, a smart phone, a wearable device, and the like.

[0027] Device 100 may include a processor 104 that controls the operation of device 100. Processor 104 may also be referred to as a central processing unit (CPU). A memory 106 that may include both read only memory (ROM) and random access memory (RAM) provides instructions and data to processor 104. A portion of memory 106 may also include non-volatile random access memory (NVRAM). Processor 104 generally performs logical and arithmetic operations based on program instructions stored within memory 106.

[0028] In some aspects, device 100 may also include a housing 108 that may include a transmitter 110 and a receiver 112 to allow transmission and reception of data between device 100 and a remote location. For some aspects, transmitter 110 and receiver 112 may be combined into a transceiver 114. One or more antennas 116 may be attached to or otherwise coupled to housing 108 and electrically connected to transceiver 114. Device 100 may also include (not shown) multiple transmitters, multiple receivers, and / or multiple transceivers.

[0029] Device 100 may also include a signal detector 118 that may be used to attempt to detect and quantify the level of signals received by transceiver 114. Signal detector 118 may detect signal parameters such as total energy, per-subcarrier per-symbol energy, and power spectral density. Device 100 may also include a digital signal processor (DSP) 120 for processing signals.

[0030] Device 100 may also include a battery 122 for powering the various components of device 100. Device 100 may also include a power management integrated circuit (power management IC or PMIC) 124 for managing power from the battery to the various components of device 100. PMIC 124 may perform various functions of the device such as direct current (DC) to DC conversion, battery charging, power selection, voltage scaling, power sequencing, and the like. In some aspects, PMIC 124 may include a battery charging circuit (e.g., a master-slave battery charging circuit) or other switched-mode power supply. The various components of device 100 may be coupled together by a bus system 126 that may include a power bus, a control signal bus, and / or a status signal bus in addition to a data bus.

[0031] For some aspects, device 100 may have an input / output (I / O) module 128 for receiving and / or outputting data and / or power. In some aspects, I / O module 128 may include a connector 130, such as a Universal Serial Bus Type-A (USB-A) receptacle or a USB-C receptacle. The pins of connector 130 may be routed to processor 104 and / or PMIC 124 via bus system 126 and / or signal lines of I / O module 128, and at least some of bus system 126 and / or I / O module 128 may include overvoltage protection circuitry, as further described herein. Additionally, as described herein, I / O module 128 may include a codec chip, which includes an audio signal path and drivers and other hardware components to facilitate audio over connector 130.

[0032] Figure 2 FIG. 4 is a diagram of an example hardware architecture 200 that provides more details regarding how some portions of device 100 may be implemented. For example, architecture 200 includes an application processor 210, which may include some or all of the functionality of processor 104 and DSP 120. In some examples, application processor 210 may be a system-on-a-chip (SOC) that includes multiple processor cores, a digital signal processor (DSP), memory, and the like. For example, one or more of the processor cores may run an operating system with a kernel that provides functionality for, e.g., controlling multiplexing circuitry 235. Architecture 200 also includes a charger integrated circuit 220, which may include some or all of the functionality of PMIC 124.

[0033] Codec chip 230 may provide some or all of the functionality of I / O module 128 and may also include a connector 130 to physically interface with a plug 250. In this example, plug 250 is a USB-C plug, but the scope of the implementation may include any suitable plug, whether standard-compliant or otherwise. Codec chip 230 interfaces with an audio signal path and a USB data path. For example, codec chip 230 receives high-speed data on the DN and DP data lines from USB-C plug 250. Then, codec chip 230 may route the high-speed data to application processor 210.

[0034] Additionally, codec chip 230 includes audio signal amplifiers 231, 232 for the left and right channels, respectively. Analog audio signals may be output to USB-C plug 250 for use, e.g., with wired headphones. It is also noteworthy that USB-C plug 250 may be used for charging such that DC power may be provided from USB-C plug 250 to charger IC 220.

[0035] To facilitate shared connections, codec chip 230 includes multiplexing circuitry 235, which is shown in Figure 2 as a plurality of switches. For example, when an audio signal is sent from audio signal amplifiers 231, 232 to USB-C plug 250, switches can be turned on to create a circuit path from audio signal amplifiers 231, 232 to USB-C plug 250, while other switches can be turned off to isolate application processor 210 from the audio signal path and also isolate charger IC 220 from the audio signal path. Similarly, when application processor 210 sends and receives digital data through DP and DN pins using USB-C plug 250, charger IC 220 and audio signal amplifiers 231, 232 can be isolated from USB-C plug through multiplexing circuitry 235. Additionally, when charger IC 220 receives DC power through DN and DP pins of USB-C plug 250, multiplexing circuitry 235 can create an electrical connection from charger IC 220 to USB-C plug 250 while isolating application processor 210 and audio signal amplifiers 231, 232 from the DC charging power. Multiplexing circuitry 235 can be controlled, for example, by application processor 210 or some other suitable hardware or software logic within architecture 200.

[0036] Codec chip 230 also includes overvoltage protection and electrostatic discharge circuitry 236 (hereinafter referred to as electrostatic discharge or ESD circuitry 236), which monitors the signal levels on lines DPR and DNL and can activate transient voltage suppression, as described in more detail below.

[0037] Electrostatic discharge (ESD) conditions can occur at one or more pins of a connector (such as a USB-A or USB-C receptacle) of a device (e.g., device 100). An ESD scheme, as shown in architecture 200, can be employed to prevent electro - overstress (EOS) damage to a chipset integrated circuit (IC) having various signal nodes for coupling to connector pins (such as DN and DP pins). In this example, the ESD scheme is shown by ESD circuitry 236. Specifically, the ESD scheme can be implemented at DPR and DNL pins of codec chip 230, which are configured to make electrical contact with the paired DP and DN pins of USB-C plug 250. In an example ESD scenario, a USB-C cable (not shown) interfacing with USB-C plug 250 has an accumulation of static charge. When the connector of the cable physically creates an electrical connection with the DN and DP pins of USB-C plug 250, the static charge can be released. In the absence of ESD protection, current may surge through codec chip 230 and application processor 210 and potentially cause damage.

[0038] Figure 2The ESD solution seeks to minimize the likelihood of damage to the codec chip 230 and the application processor 210 by using the ESD protection circuit 236 to detect a negative surge and then absorb the current associated with the surge.

[0039] Various embodiments herein include a feedback loop within the ESD circuit 236, where the feedback loop includes a comparator that controls a shunt transistor, and the shunt transistor is serially disposed between a diode and ground.

[0040] Figure 3 is an illustration of a voltage suppression system 300 that can be implemented within the Figure 2 ESD circuit 236 according to one embodiment. Figure 3 Illustrates voltage suppression at the DNL pin 316, and Figure 4 (described in more detail below) illustrates that the voltage suppression concept can be scaled to protect more pins.

[0041] The DNL pin 316 is coupled to a diode 322 and a shunt transistor 324. Specifically, the diode 322 and the shunt transistor 324 are placed in series between ground and the DNL pin 316. The gate of the shunt transistor 324 is coupled to the output of the comparator 310, where the output is shown as the voltage NCOMP. The DNL pin 316 is coupled to the comparator 310's inverting input via a level shifter circuit 312. The non-inverting input of the comparator 310 is coupled to a reference voltage Vref. The DNL pin 316 is coupled to Figure 2 the DNL trace of

[0042] to provide an electrical coupling between the USB-C plug 250 and the multiplexing circuitry system 235. The comparator 310 is powered by a positive voltage source Vdd. In this example, the level shifter circuit 312 is used to add a positive direct current (DC) offset to the voltage level at the inverting input of the comparator 310 such that the voltage level experienced at the inverting input is expected to be positive and higher than the level of the reference voltage Vref during normal operation. When the voltage level at the inverting input drops below the voltage level of Vref, the output of the comparator 310 changes state to turn on the shunt transistor 324. However, the scope of the embodiments is not limited to a positive-powered comparator with a level shifter circuit. In another example, the comparator 310 can be powered using a negative voltage source, a negative reference voltage, and a normal negative voltage level at the inverting input.

[0043] In addition, in this example, the shunt transistor is an n-channel metal oxide semiconductor (NMOS) transistor sized to conduct the amount of current expected during the negative surge of an event. For example, if the amount of current during a negative surge event is expected to be a maximum of 6 A at about a 20 μs pulse, the shunt transistor 324 can be sized to have a width of about 24 mm. However, the scope of the embodiments is not limited to any particular surge current amount or size of the shunt transistor 324. Instead, the scope of the embodiments can scale the shunt transistor 324 appropriately to accommodate any expected surge event.

[0044] The diode 322 in this example is a p-n junction diode sized appropriately to conduct the amount of current expected during a negative surge event at the DNL pin 316. The diode 322 is designed to have a capacitance less than the capacitance associated with the shunt transistor 324. In one example, even though the diode 322 and the shunt transistor 324 may be able to conduct the same amount of current, the diode 322 can have a capacitance that is approximately 90 times less than the capacitance associated with the shunt transistor 324. Thus, the combined series capacitance of the diode 322 and the shunt transistor 324 is much less than the capacitance associated with the shunt transistor 324 itself. For example, if the capacitance associated with the diode 322 is 1.0x and the capacitance associated with the shunt transistor 324 is 90x, the combined series resistance is approximately 0.99x.

[0045] Of course, the scope of the embodiments is not limited to any capacitance values of the diode 322 and the shunt transistor 324. Instead, the relative capacitance values, current-carrying ratings, and distortion limits of the high-speed data on the wires DNL and DPR are some of the factors available for selecting the diode 322 and the shunt transistor 324.

[0046] Surge event 314 produces a current that is negative in this example. For example, if surge event 314 is associated with a voltage level of -100V and an Rs of 2 ohms, the current associated with surge event 314 can be -50A. Although not shown herein, the scope of the embodiments can include an external (e.g., external to codec chip 230) surge protection circuit that absorbs most of the -50A. In some examples, the remainder of the surge current can be up to, for example, -6A. The remainder of the surge current is blocked by the level shift circuit 312 and the shunt transistor 324 that is turned off. The remainder of the surge current causes the voltage level at the DNL pin 316 to drop. The voltage level at the DNL pin 316 plus the DC offset attributable to the level shift circuit 312 is shown as NSURGE. Once NSURGE drops to a voltage level equal to or lower than Vref, the output of the comparator 310 changes to a positive value large enough to turn on the shunt transistor 324. In the case where the shunt transistor 324 is turned on, the current from the ground cancels the remainder of the surge current through the shunt transistor 324 and the diode 322. In the case where the remainder of the surge current is neutralized, the voltage level at the DNL pin 316 rises, thereby changing the output state of the comparator 310 such that the shunt transistor 324 is turned off.

[0047] The scope of the embodiments is not limited to the examples given above for the voltage or current associated with the surge. Instead, the scope of the embodiments includes the settings of the DC voltage offset, Vref, and NCOMP of the level shift circuit 312 suitable for a given application.

[0048] In this example, Figure 3 the feedback loop of Figure 3 is not timed. In other words, the feedback loop can react as the voltage level of the DNL pin 316 changes. As described above, during normal operation, the shunt transistor 324 is turned off because its gate-source voltage is zero or less than zero. Therefore, during normal operation, the power consumption of the Figure 3 feedback loop is limited to any leakage current attributable to the comparator 310 and the shunt transistor 324. As the leakage current is minimized, the power consumption during normal operation of the Figure 3 feedback loop is expected to be close to zero. Therefore, the

[0049] Figure 4 embodiments of Figure 2 can provide effective negative transient voltage suppression with minimal or negligible added power usage and minimal added capacitance. Figure 4 Illustrated is voltage suppression in a stereo system that has a left channel and a right channel. For example, the left channel can be associated with Figure 2is associated with the DNL wire and Figure 3 is associated with the DNL pin 316. The right channel can be associated with Figure 2 is associated with the DPR wire and Figure 4 is associated with the DPR pin 416.

[0050] A logic gate OR gate 450 is provided between the outputs of the comparators 310, 410 and the gate of the shunt transistor 324. The logic gate 450 outputs a low voltage (digital zero) unless one or both of its inputs go high. Thus, when the comparator 310 changes its output state to a high voltage (digital one) or the comparator 410 changes its output state to a high voltage, the logic gate 450 outputs a high voltage at NCOMP (digital one) to turn on the shunt transistor 324.

[0051] The feedback loop including the comparator 310 operates in the same manner as described above with respect to Figure 3 That is, when the voltage level at the DNL pin 316 drops such that the voltage level seen at the inverting input of the comparator 310 is equal to or lower than Vref, the output state of the comparator 310 goes high.

[0052] The feedback loop including the comparator 410 operates similarly. When the voltage level at the DPR pin 416 drops such that the voltage level seen at the inverting input of the comparator 410 is equal to or lower than Vref, the output state of the comparator 410 goes high. A surge event on the right channel is shown by surge 414.

[0053] Figure 4 The embodiment of achieves a certain amount of space savings by sharing the shunt transistor 324 between the left and right channels. The diode 422 is coupled to the drain of the shunt transistor 324 at its anode. In a scenario where there is a negative surge on the right channel but no negative surge on the left channel, the voltage level at the DPR pin 416 drops, and the voltage level at the DNL pin 316 can be approximately 0V DC. Once the voltage level (NSURGE_R) at the inverting input of the comparator 410 drops to a voltage level equal to or lower than Vref, the output state of the comparator 410 goes high, which causes the output state of the logic gate 450 to go high, which turns on the shunt transistor 324. Current then flows from ground through the diode 422 to the DPR pin 416 to neutralize the negative surge.

[0054] In a scenario where there is a negative surge on the left channel but no negative surge on the right channel, the voltage level at the DNL pin 316 drops, and the voltage level at the DPR pin 416 can be approximately 0V DC. Once the voltage level (NSURGE_L) at the inverting input of the comparator 310 drops to a voltage level equal to or lower than Vref, the output state of the comparator 310 goes high, which causes the output state of the logic gate 450 to go high, turning on the shunt transistor 324. Then, current flows from ground through the diode 322 to the DNL pin 316 to neutralize the negative surge.

[0055] In a situation where there are negative surges on both the right and left channels simultaneously, the output state of the logic gate 450 will go high, and the shunt transistor 324 will absorb the current associated with both the DNL pin 316 and the DPR pin 416.

[0056] Now, a sample method for operating a negative transient voltage suppression system will be discussed with reference to the flowchart shown in Figure 5 The method 500 can be executed by an ESD protection circuit (such as the ESD protection circuit 236 illustrated in Figure 2 ) during its operation to monitor and detect negative surge events.

[0057] At operation 510, the method includes receiving a negative current surge at a data and audio combined pin. Figure 3 Examples are shown in Figure 4 where the data and audio combined pin is shown as the DNL pin 316 and the DPR pin 416. Either or both of the pins 316, 416 can receive a negative current surge during a negative surge event. As described above, a negative surge event can include electrostatic discharge due to inserting a USB cable with a static charge accumulation into the Figure 2 USB-C plug 250.

[0058] At operation 520, the method includes applying a level-shifted voltage at a first input of a voltage comparator. In this example, the level-shifted voltage is reduced by the negative current surge, and the first input of the voltage comparator is coupled to the data and audio combined pin. In the examples of Figure 3 and Figure 4 , the comparators are illustrated as comparators 310 and 410, and each of the comparators 310, 410 includes an inverting input coupled to a level-shifting circuit 312, 412.

[0059] The level-shifted voltage associated with comparator 310 is applied to its inverting input, and the level-shifted voltage associated with comparator 410 is applied to its inverting input. The reference voltage Vref is applied to the non-inverting inputs of comparators 310 and 410. When the voltage level at the inverting inputs of comparators 310 and 410 drops below the voltage level of Vref, either or both of comparators 310 and 410 may change their output state to high (digital one). Otherwise, the output state of comparators 310 and 410 is low (digital zero).

[0060] At operation 530, the method includes changing the output state of a voltage comparator in response to the level-shifted voltage dropping below the reference voltage level at a second input of the voltage comparator. In other words, as explained above, when the voltage level at the inverting inputs of voltage comparators 310 and 410 drops below the voltage level of Vref, the output states of voltage comparators 310 and 410 may change to high.

[0061] Continuing with operation 530, the change in the output state of the comparator may or may not be associated with a change in the output state of a logic gate (as shown in Figure 4 ). In other words, voltage suppression may be applied on a single channel, or a logic gate (e.g., an OR gate) may be used to expand the number of channels on which voltage suppression is applied. Figure 3 ).

[0062] At operation 540, the method includes turning on a voltage clamp through the output state of the voltage comparator. For example, as shown in Figure 3 , the voltage clamp may be implemented by a shunt transistor (e.g., shunt transistor 324) that couples the data and audio combined pin to ground through a diode. Similarly, as shown in Figure 4 , a voltage clamp implemented as a shunt transistor may be shared among multiple channels.

[0063] At operation 550, the method includes absorbing the current associated with a negative current surge through a diode. In an embodiment of Figure 3 , the diode is serially coupled between the data and audio combined pin and the voltage clamp and ground. The current conducts from ground through the shunt transistor and the diode to the data and audio combined pin and to the source of the negative current surge. The current through the diode cancels the current associated with the negative current surge.

[0064] The scope of the embodiments is not limited to that regarding Figure 5A series of described actions. In contrast, an ESD condition such as a negative surge event is expected to exist for only a fraction of a second, and once that fraction of a second ends, the voltage level of the data and audio combined pin returns to the normal operating range. Thus, the state of the voltage comparator can change from digital one to digital zero, thereby turning off the voltage clamp.

[0065] In addition, a scope of embodiments is described with respect to NMOS transistors used as shunt transistors or voltage clamps. However, a shunt transistor can be implemented as a PMOS transistor by applying a low voltage to the gate of a p-channel metal oxide semiconductor (PMOS) transistor during a negative surge event and a high voltage to the gate of the PMOS transistor during normal operation.

[0066] Some embodiments can be part of a normally-on ESD protection scheme. For example, as long as a reference voltage Vref is provided and as long as the Vdd power supply remains on, the voltage comparators 310, 410 can be powered on. In addition, the exemplary embodiments operate continuously rather than discretely and thus do not consume clock resources.

[0067] As those skilled in the art will appreciate by now and depending on the particular application at hand, many modifications, substitutions, and variations can be made to the materials, devices, configurations, and methods of use of the devices of the present disclosure without departing from the scope of the present disclosure. In view of this, the scope of the present disclosure should not be limited to the scope of the specific embodiments shown and described herein, as they are merely by way of some examples, but should be fully commensurate with the scope of the appended claims and their functional equivalents.

[0068] Examples of embodiments are described in the following numbered clauses:

[0069] 1. A wireless communication device, comprising:

[0070] An application processor;

[0071] An audio signal amplifier;

[0072] A charging integrated circuit, wherein the application processor, the audio signal amplifier, and the charging integrated circuit are coupled to a set of wires through a multiplexing circuit system;

[0073] A first pin on a first wire of the set of wires;

[0074] A data and charging plug, the data and charging plug being coupled to the set of wires through the first pin;

[0075] A first voltage comparator having an inverting input coupled to the first pin, wherein a non-inverting input of the first voltage comparator is coupled to a reference voltage; and

[0076] A first diode and a transistor, the first diode and the transistor being serially coupled between the first pin and ground, wherein a gate of the transistor is coupled to an output of the first voltage comparator.

[0077] 2. The wireless communication device according to clause 1, further comprising:

[0078] A second diode, the second diode being coupled to a second pin on a second wire of the group of wires, wherein the second diode is coupled to a drain of the transistor, and wherein the first diode is coupled to the drain of the transistor.

[0079] 3. The wireless communication device according to clause 2, further comprising:

[0080] A second voltage comparator having an inverting input coupled to the second pin and a non-inverting input coupled to the reference voltage; and

[0081] A logic gate coupled to the output of the first voltage comparator and to the output of the second voltage comparator, wherein an output of the logic gate is coupled to the gate of the transistor.

[0082] 4. The wireless communication device according to clause 3, wherein the logic gate includes an OR gate.

[0083] 5. The wireless communication device according to any one of clauses 1-4, wherein the first diode includes a positive-negative (p-n) junction diode.

[0084] 6. The wireless communication device according to any one of clauses 1-5, wherein the transistor includes an n-type metal oxide semiconductor (NMOS) transistor.

[0085] 7. The wireless communication device according to any one of clauses 1-6, wherein the data and charging plug includes a universal serial bus (USB) plug.

[0086] 8. The wireless communication device according to clause 7, further comprising:

[0087] A codec chip including the group of wires, the audio signal amplifier, the first pin, and the multiplexing circuitry.

[0088] 9. The wireless communication device according to any one of clauses 1-8, further comprising:

[0089] A level-shifting circuit coupled between the first pin and the inverting input, wherein the level-shifting circuit is configured to add a positive direct current (DC) offset to the voltage level of the first pin.

[0090] 10. The wireless communication device according to any one of clauses 1-9, wherein the cathode of the first diode is coupled to the first pin, and wherein the anode of the first diode is coupled to the drain of the transistor, and further wherein the source of the transistor is coupled to ground.

[0091] 11. A method of operating a transient voltage suppression circuit, the method comprising:

[0092] Receiving a negative current surge at a data and audio combined pin;

[0093] Applying a level-shifted voltage at a first input of a voltage comparator, wherein the level-shifted voltage is reduced due to the negative current surge, and further wherein the first input of the voltage comparator is coupled to the data and audio combined pin;

[0094] Changing an output state of the voltage comparator in response to the level-shifted voltage dropping below a reference voltage level at a second input of the voltage comparator;

[0095] Turning on a voltage clamp through the output state of the voltage comparator; and

[0096] Absorbing a current associated with the negative current surge through a diode serially coupled between the data and audio combined pin and the voltage clamp.

[0097] 12. The method according to clause 11, further comprising:

[0098] Turning off the voltage clamp after absorbing the current.

[0099] 13. The method according to any one of clauses 11-12, wherein turning on the voltage clamp includes applying a positive voltage to the gate of an n-channel metal oxide semiconductor (NMOS) transistor.

[0100] 14. The method according to any one of clauses 11-13, wherein absorbing the current includes causing another current to conduct from ground, through the diode, and through the data and audio combined pin.

[0101] 15. The method according to any one of clauses 11-14, wherein the first input of the voltage comparator is an inverting input, and wherein the second input of the voltage comparator is a non-inverting input.

[0102] 16. The method according to any one of clauses 11 - 15 further comprises:

[0103] Adding a positive direct current (DC) offset to the voltage level associated with the data and audio combination pin.

[0104] 17. The method according to any one of clauses 11 - 16, wherein receiving the negative current surge is associated with inserting a cable into a wireless device including the data and audio combination pin.

[0105] 18. The method according to any one of clauses 11 - 17, wherein turning on the voltage clamp includes changing the state of a logic gate based on the output state of the voltage comparator, wherein the output of the logic gate is coupled to a terminal of the voltage clamp.

[0106] 19. The method according to clause 18, wherein the logic gate includes an OR gate.

[0107] 20. A wireless communication device comprising:

[0108] An application processor;

[0109] An audio signal amplifier;

[0110] A charging integrated circuit;

[0111] Components for multiplexing the application processor, the audio signal amplifier, and the charging integrated circuit on a set of wires;

[0112] A first pin on a first wire of the set of wires;

[0113] A data and charging plug, the data and charging plug being coupled to the set of wires through the first pin; and

[0114] Components for canceling a negative surge at the first pin, wherein the components for canceling include a first diode and a shunt transistor serially coupled between ground and the first pin.

[0115] 21. The wireless communication device according to clause 20, wherein the components for canceling further comprise:

[0116] A feedback loop that couples the first pin to an input of a first comparator and couples the output of the first comparator to the gate of the shunt transistor.

[0117] 22. The wireless communication device according to clause 21, wherein the components for canceling further comprise:

[0118] A second diode, the second diode being coupled to a second pin on the set of wires, wherein the second diode is coupled to the drain of the shunt transistor, and wherein the first diode is coupled to the drain of the shunt transistor.

[0119] 23. The wireless communication device according to clause 22, wherein the components for cancellation further include:

[0120] A second comparator, the second comparator being coupled to the second pin; and

[0121] A logic gate, the logic gate being coupled to the output of the first comparator and the output of the second comparator, wherein the output of the logic gate is coupled to the gate of the shunt transistor.

[0122] 24. The wireless communication device according to clause 23, wherein the logic gate includes an OR gate.

[0123] 25. The wireless communication device according to any one of clauses 20 - 24, wherein the shunt transistor includes a metal-oxide-semiconductor field-effect transistor (MOSFET), and wherein the first diode includes a positive-negative (p-n) junction device.

[0124] 26. A wireless communication device, comprising:

[0125] A first chip and an audio signal amplifier, the first chip and the audio signal amplifier being coupled to a set of wires through a multiplexing circuit system;

[0126] A first pin on the set of wires, wherein the first pin is coupled to a combined data and audio plug;

[0127] A codec chip, the codec chip including the set of wires and the multiplexing circuit system;

[0128] An electrostatic discharge (ESD) protection feedback loop, wherein the ESD protection feedback loop couples the first pin to a first input of a first comparator and couples the output of the first comparator to the gate of a shunt transistor, wherein the shunt transistor is serially coupled between a first diode and ground.

[0129] 27. The wireless communication device according to clause 26, further comprising:

[0130] A second diode, the second diode being coupled to a second pin on the set of wires, wherein the second diode is coupled to the drain of the shunt transistor, and wherein the first diode is coupled to the drain of the shunt transistor.

[0131] 28. The wireless communication device according to clause 27 further comprises:

[0132] a second voltage comparator coupled to the second pin; and

[0133] a logic gate coupled to the output of the first comparator and the output of the second voltage comparator, wherein the output of the logic gate is coupled to the gate of the shunt transistor.

[0134] 29. The wireless communication device according to clause 28, wherein the logic gate comprises an OR gate.

[0135] 30. The wireless communication device according to any one of clauses 26-29, wherein the first chip comprises an application processor configured to receive high-speed data on the set of wires and through the multiplexing circuitry.

Claims

1. A wireless communication device, comprising: an application processor; an audio signal amplifier; a charging integrated circuit, wherein the application processor, the audio signal amplifier, and the charging integrated circuit are coupled to a set of wires through a multiplexing circuit system; a first pin on a first wire of the set of wires; a data and charging plug, the data and charging plug being coupled to the set of wires through the first pin; a first voltage comparator having an inverting input coupled to the first pin, wherein a non-inverting input of the first voltage comparator is coupled to a reference voltage; and a first diode and transistor, the first diode and transistor being serially coupled between the first pin and ground, wherein a gate of the transistor is coupled to an output of the first voltage comparator.

2. The wireless communication device according to claim 1, further comprising: a second diode, the second diode being coupled to a second pin on a second wire of the set of wires, wherein the second diode is coupled to a drain of the transistor, and wherein the first diode is coupled to the drain of the transistor.

3. The wireless communication device according to claim 2, further comprising: a second voltage comparator having an inverting input coupled to the second pin and a non-inverting input coupled to the reference voltage; and a logic gate coupled to the output of the first voltage comparator and coupled to the output of the second voltage comparator, wherein an output of the logic gate is coupled to the gate of the transistor.

4. The wireless communication device according to claim 3, wherein, the logic gate comprises an OR gate.

5. The wireless communication device according to claim 1, wherein, the first diode comprises a positive-negative (p-n) junction diode.

6. The wireless communication device according to claim 1, wherein, the transistor comprises an n-type metal oxide semiconductor (NMOS) transistor.

7. The wireless communication device according to claim 1, wherein, the data and charging plug comprises a universal serial bus (USB) plug.

8. The wireless communication device according to claim 7, further comprising: a codec chip, the codec chip comprising the set of wires, the audio signal amplifier, the first pin, and the multiplexing circuit system.

9. The wireless communication device according to claim 1, further comprising: a level shifting circuit coupled between the first pin and the inverting input, wherein the level shifting circuit is configured to add a positive direct current (DC) offset to a voltage level of the first pin.

10. The wireless communication device according to claim 1, wherein, a cathode of the first diode is coupled to the first pin, and wherein an anode of the first diode is coupled to the drain of the transistor, and further wherein a source of the transistor is coupled to ground.

11. A method of operating a transient voltage suppression circuit, the method comprising: receiving a negative current surge at a data and audio combined pin; Apply a level - shifted voltage at a first input of a voltage comparator, wherein the level - shifted voltage is reduced due to the negative current surge, and further wherein the first input of the voltage comparator is coupled to the data and audio combined pin; Change the output state of the voltage comparator in response to the level - shifted voltage dropping below a reference voltage level at a second input of the voltage comparator; Turn on a voltage clamp through the output state of the voltage comparator; and Absorb the current associated with the negative current surge through a diode serially coupled between the data and audio combined pin and the voltage clamp.

12. The method according to claim 11, further comprising: Turn off the voltage clamp after absorbing the current.

13. The method according to claim 11, wherein, Turning on the voltage clamp includes applying a positive voltage to the gate of an n - channel metal - oxide - semiconductor (NMOS) transistor.

14. The method according to claim 11, wherein, Absorbing the current includes causing another current to conduct from ground, through the diode, and through the data and audio combined pin.

15. The method according to claim 11, wherein, The first input of the voltage comparator is an inverting input, and wherein the second input of the voltage comparator is a non - inverting input.

16. The method according to claim 11, further comprising: Adding a positive direct - current (DC) offset to the voltage level associated with the data and audio combined pin.

17. The method according to claim 11, wherein, Receiving the negative current surge is associated with inserting a cable into a wireless device including the data and audio combined pin.

18. The method according to claim 11, wherein, Turning on the voltage clamp includes changing the state of a logic gate based on the output state of the voltage comparator, wherein the output of the logic gate is coupled to a terminal of the voltage clamp.

19. The method according to claim 18, wherein, The logic gate includes an OR gate.

20. A wireless communication device, comprising: An application processor; An audio signal amplifier; A charging integrated circuit; Components for multiplexing the application processor, the audio signal amplifier, and the charging integrated circuit on a set of wires; A first pin on a first wire of the set of wires; A data and charging plug, the data and charging plug being coupled to the set of wires through the first pin; and Components for canceling a negative surge at the first pin, wherein the components for canceling include a first diode and a shunt transistor serially coupled between ground and the first pin.

21. The wireless communication device according to claim 20, wherein, The components for canceling further include: A feedback loop that couples the first pin to an input of a first comparator and couples the output of the first comparator to the gate of the shunt transistor.

22. The wireless communication device according to claim 21, wherein, The components for canceling further include: A second diode, the second diode being coupled to a second pin on the set of wires, wherein the second diode is coupled to the drain of the shunt transistor, and wherein the first diode is coupled to the drain of the shunt transistor.

23. The wireless communication device according to claim 22, wherein, the components for cancellation further include: a second comparator, the second comparator being coupled to the second pin; and a logic gate, the logic gate being coupled to the output of the first comparator and the output of the second comparator, wherein the output of the logic gate is coupled to the gate of the shunt transistor.

24. The wireless communication device according to claim 23, wherein, the logic gate includes an OR gate.

25. The wireless communication device according to claim 20, wherein, the shunt transistor includes a metal oxide semiconductor field effect transistor (MOSFET), and wherein the first diode includes a positive-negative (p-n) junction device.

26. A wireless communication device, comprising: a first chip and an audio signal amplifier, the first chip and the audio signal amplifier being coupled to a set of wires through a multiplexing circuit system; a first pin on the set of wires, wherein the first pin is coupled to a combined data and audio plug; a codec chip, the codec chip including the set of wires and the multiplexing circuit system; an electrostatic discharge (ESD) protection feedback loop, wherein the ESD protection feedback loop couples the first pin to a first input of a first comparator and couples the output of the first comparator to the gate of a shunt transistor, wherein the shunt transistor is serially coupled between a first diode and ground.

27. The wireless communication device according to claim 26, further comprising: a second diode, the second diode being coupled to a second pin on the set of wires, wherein the second diode is coupled to the drain of the shunt transistor, and wherein the first diode is coupled to the drain of the shunt transistor.

28. The wireless communication device according to claim 27, further comprising: a second voltage comparator, the second voltage comparator being coupled to the second pin; and a logic gate, the logic gate being coupled to the output of the first comparator and the output of the second voltage comparator, wherein the output of the logic gate is coupled to the gate of the shunt transistor.

29. The wireless communication device according to claim 28, wherein, the logic gate includes an OR gate.

30. The wireless communication device according to claim 26, wherein, the first chip includes an application processor, the application processor being configured to receive high-speed data on the set of wires and through the multiplexing circuit system.

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