An error suppression compilation optimization method for quantum computers

Abstract

The present invention relates to the field of quantum compilation technology and discloses an error suppression compilation optimization method for quantum computers. The method captures the physical quantum gate operation error rate and hardware topology of a quantum processor that performs a mapping task to construct a hardware feature matrix; captures the gate interaction properties of a quantum logic circuit to be compiled to construct a circuit feature matrix; establishes a mapping scheme representation model and a corresponding cost function based on the constructed hardware feature matrix and circuit feature matrix; solves the cost function using a genetic algorithm to find a mapping scheme that minimizes the cost function value while satisfying the resource constraints of the quantum processor; applies the optimized mapping scheme to the quantum logic circuit to be compiled to perform compilation optimization on the quantum logic circuit to be compiled. The present invention solves the problems of poor adaptability of quantum bit allocation schemes and insufficient error rate optimization in the prior art, and realizes low-error and reliable quantum circuit mapping processing.

Description

Technical Field

[0001] The present invention relates to the field of quantum compilation technology, and in particular to an error suppression compilation optimization method for quantum computers. Background Art

[0002] Modern quantum systems are often categorized as noisy intermediate-scale quantum (NISQ) devices due to their susceptibility to quantum decoherence and noise. Unlike stable classical computing systems, quantum computers are extremely sensitive to various forms of error interference, a problem that becomes more pronounced as the runtime of quantum programs increases and the number of operations increases. This poses a significant challenge to maintaining the accuracy and reliability of quantum computations. Consequently, executing quantum programs on existing quantum processors is a challenging task, as existing quantum computers were not designed with adequate consideration of noise and physical hardware limitations.

[0003] To address this issue, quantum compilers play a key role, adapting quantum circuits to real-world quantum devices to improve fault tolerance. Quantum mapping is a crucial step in the quantum compilation process, its core goal being to map the logical qubits in the quantum circuit to the physical qubits in the quantum hardware. Because quantum hardware typically has a fixed topology, the connectivity between physical qubits is limited, and the position and error rates of different physical qubits vary significantly. Therefore, a sound quantum mapping strategy is crucial for the efficiency and reliability of quantum computation. Quantum mapping not only directly impacts the success rate of quantum programs but also determines the overhead of subsequent compilation. For example, effectively reducing the number of extra gates required to match the logical gates with the hardware topology during the initial qubit mapping can reduce the accumulated error and latency of the program. Furthermore, by prioritizing physical qubits with low error rates, the accuracy and robustness of quantum circuit operations can be further improved. Therefore, quantum mapping is a crucial step in improving quantum computing performance and fully utilizing existing hardware resources, laying the foundation for efficient and low-error quantum computing.

[0004] With the development of technology, an increasing number of quantum bit mapping methods have been proposed. These methods generally focus only on basic mapping problems under hardware topology constraints and fail to fully consider hardware errors, dynamic interactions between quantum bits, and diverse hardware characteristics during the mapping process. Traditional mapping methods mostly use fixed rules or simple heuristic algorithms. Although these methods can solve some hardware constraint problems, they lack sufficient adaptability to complex quantum circuits and diverse hardware environments. In addition, existing mapping algorithms often rely too much on manually designed rules during the optimization process and lack autonomous optimization capabilities. This makes it difficult for the algorithms to achieve comprehensive performance improvements when faced with new hardware architectures or complex circuits, ultimately affecting the running accuracy of quantum programs and the efficient utilization of hardware resources.

[0005] Therefore, a qubit mapping method that can efficiently adapt to different quantum hardware topologies and error characteristics is needed to improve mapping reliability and flexibility. This new mapping method should be able to dynamically analyze the qubit error rate and connectivity in the hardware environment and optimize the initial mapping scheme in real time, reducing the insertion overhead of additional gates and the accumulated error. Furthermore, the mapping method must possess stronger adaptability, allowing for flexible adjustments to different quantum circuit and hardware environments, thereby achieving a more efficient and accurate quantum program compilation process. Summary of the Invention

[0006] The purpose of this invention is to solve the above problems and design an error suppression compilation optimization method for quantum computers to achieve a more efficient and reliable quantum program compilation process.

[0007] The present invention provides an error suppression compilation optimization method for a quantum computer, the error suppression compilation optimization method for a quantum computer comprising:

[0008] Capture the physical quantum gate operation error rate and hardware topology of the quantum processor that performs the mapping task, and construct a hardware feature matrix;

[0009] Capture the gate interaction properties of the quantum logic circuit to be compiled and construct the circuit feature matrix;

[0010] According to the constructed hardware feature matrix and circuit feature matrix, a mapping scheme representation model and a corresponding cost function are established;

[0011] The cost function is solved using a genetic algorithm, and a mapping scheme that minimizes the cost function value is found while satisfying the resource constraints of the quantum processor.

[0012] The optimized mapping scheme is applied to the quantum logic circuit to be compiled, and the compilation optimization of the quantum logic circuit to be compiled is performed.

[0013] Optionally, in the first implementation of the present invention, capturing the physical quantum gate operation error rate and hardware topology of the quantum processor that performs the mapping task and constructing the hardware feature matrix includes:

[0014] Identify the physical quantum bits in the quantum processor and construct a Hardware feature matrix , for the physical quantum bit And when physical quantum bits The expected error rate of constructing CNOT gates between can be estimated as:

[0015] ;

[0016] in, Is connecting and Each connectivity path on the path between Is the path Error rate on hardware feature matrix and The value of is equal to , It is physical quantum bits, It is physical quantum bits.

[0017] Optionally, in a second implementation of the present invention, capturing gate interaction properties of the quantum logic circuit to be compiled and constructing a circuit feature matrix includes:

[0018] Analyze the quantum logic circuit to be compiled, traverse the analyzed quantum logic circuit, and determine the logical quantum bits corresponding to each CNOT gate control bit and target bit and ;

[0019] Construct a size of The circuit characteristic matrix , for each element of the circuit characteristic matrix , obtain logical qubits and logical qubits The number of CNOT gates executed between .

[0020] Optionally, in a third implementation of the present invention, establishing a mapping scheme representation model and a corresponding cost function based on the constructed hardware feature matrix and circuit feature matrix includes:

[0021] Defining Boolean variables , if and only if the logical qubit Mapped to physical qubits Upper time variable , otherwise there is ;

[0022] For all logical bits and all physical bits, the overhead function of the mapping is completed for:

[0023] ;

[0024] Among them, the hardware feature matrix Represented in physical quantum bits and Construct the expected error rate of the CNOT gate between Represented in logical qubits and The number of CNOT gates that need to be executed between Represents a set of logical qubits, including all logical qubits in the quantum logic circuit to be compiled; Represents a set of physical quantum bits, including the physical quantum bits that actually exist in the quantum processor.

[0025] Optionally, in a fourth implementation of the present invention, the Boolean variable and Used to judge logical quantum bits Whether it is mapped to a physical quantum bit , and logical qubits Whether it is mapped to a physical quantum bit ,The product of hardware error rate and the number of circuit gates is included in the overhead cost calculation only when the logical qubit pair is mapped to the corresponding physical qubit pair.

[0026] Optionally, in a fifth implementation of the present invention, when calculating the overhead cost, double summation is performed. Traversing all possible logical qubit pairs and physical qubit pairs combination.

[0027] Optionally, in a sixth implementation of the present invention, solving the cost function using a genetic algorithm to find a mapping solution that minimizes the cost function value while satisfying quantum processor resource constraints includes:

[0028] S1. Represent the solution structure of the mapping scheme representation model as individuals of the genetic algorithm, and calculate the fitness of each individual using the cost function of the mapping scheme representation model;

[0029] S2. Generate an initial population and use the 2-opt operator of local nearest neighbor search to try to improve each individual in the population. The specific details are as follows: starting from the first gene of the individual, it cyclically exchanges with adjacent genes. If the individual's fitness improves, the exchange is retained;

[0030] S3, executing the following steps S4 to S8 in a loop until the specified iteration round is reached;

[0031] S4, looping through steps S5 to S6 until the number of offspring individuals is no less than the set value;

[0032] S5. Execute the tournament strategy on the existing population to obtain the parent generation;

[0033] S6. Execute the elite crossover strategy on the parent generation to obtain new offspring individuals and add them to the offspring population;

[0034] S7. Update individuals in the existing population based on the existing population and the new population;

[0035] S8. When the optimal individual of the population has not been updated for a long time, disturb the existing population;

[0036] S9. Return the optimal individual, whose chromosome arrangement is the optimal solution to the mapping optimization problem.

[0037] Optionally, in a seventh implementation of the present invention, executing the elite crossover strategy on the parent generation to obtain new offspring individuals and adding them to the offspring population includes:

[0038] When two parents have identical genes at the same position, all identical genes are copied to the corresponding positions of the offspring;

[0039] For the unassigned position in the offspring, one is randomly and uniformly selected from the position genes of the two parents for replication if there is no gene conflict with the offspring;

[0040] For the still vacant positions, randomly select unused genes for allocation to obtain chromosomes for generating offspring. Repeat the above operation to generate several offspring, and execute the bidding strategy among the offspring to select the best elite offspring.

[0041] Optionally, in an eighth implementation of the present invention, updating individuals in the existing population based on the existing population and the new population includes:

[0042] Sort in descending order according to fitness, and select the first few individuals with the highest fitness as the new existing population.

[0043] Optionally, in a ninth implementation of the present invention, when the optimal individual in the population has not been updated for a long time, perturbing the existing population includes:

[0044] A mutation operation is performed on the chromosome of each individual in the population, cutting the gene from the specified cutting position, exchanging the positions of the two gene fragments and splicing them into a new gene.

[0045] Minimizing the cumulative error in quantum circuit operations is the core goal of the quantum bit mapping problem. Since the solution process of this problem is NP-hard, and the error characteristics, topological structure of quantum hardware and the dynamic characteristics of quantum circuits may change at any time; compared with the existing technology, the advantages of the present invention are: by capturing the physical quantum gate operation error rate and hardware topological structure of the quantum processor and other factors to construct a hardware feature matrix, by capturing the gate interaction properties of the quantum logic circuit to be compiled to construct a circuit feature matrix, according to the hardware feature matrix and the circuit feature matrix, the mapping task is remodeled into a mathematical optimization model based on the quadratic allocation problem to find a more reliable mapping strategy; in order to improve the optimization performance, the error rate of the physical quantum bit is modeled using an error model, and it is embedded in the mapping optimization process to dynamically adapt to different hardware topologies and error distributions. The proposed method is verified by experiments. The method can significantly reduce the impact of hardware errors on quantum circuits; it combines the global exploration ability of genetic algorithms and the individual development ability of local search strategies, and introduces an elite crossover strategy to effectively balance the inheritance of excellent characteristics and the maintenance of offspring diversity, and ultimately obtains the optimal mapping layout with minimum error expectation. According to the obtained optimal mapping layout, quantum compilation decisions are optimized to reduce operational errors caused by hardware errors; the present invention solves the problems of poor adaptability and insufficient error rate optimization of quantum bit allocation schemes in the prior art, realizes low-error and reliable quantum circuit mapping processing, can fully adapt to the characteristic limitations of quantum hardware, effectively meet the operation requirements of complex quantum circuits, and at the same time achieves efficient mapping of quantum bits with lower overhead, thereby improving the overall performance and reliability of the quantum compilation process. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] Various other advantages and benefits will become apparent to those skilled in the art by reading the following detailed description of the preferred embodiment.The accompanying drawings are only for the purpose of illustrating the preferred embodiment and are not to be considered as limiting the present invention.

[0047] Figure 1 This is a flowchart of an error suppression compilation optimization method for quantum computers provided by an embodiment of the present invention;

[0048] Figure 2 Schematic diagram of the topological structure of a quantum processor that needs to be compiled according to an embodiment of the present invention;

[0049] Figure 3 Schematic diagram of the overhead of the mapping solution under different numbers of CNOT gates provided by the embodiment of the present invention;

[0050] Figure 4 1 is a schematic diagram of the overall overhead of a mapping solution for eight random circuits provided by an embodiment of the present invention;

[0051] Figure 5 Schematic diagram of the overall overhead of the mapping solution under nine real circuit conditions provided by an embodiment of the present invention;

[0052] Figure 6 Schematic diagram of the average gate overhead of the mapping solution in nine real circuit cases provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0053] The terms "first," "second," "third," "fourth," and so forth (if any) in the description and claims of the present invention and in the accompanying drawings are used to distinguish similar items and are not necessarily used to describe a particular order or precedence. It should be understood that the terms used in this manner are interchangeable where appropriate, so that the embodiments described herein can be implemented in an order other than that shown or described herein. In addition, the terms "including" or "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, apparatus, product, or device that includes a series of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, product, or device.

[0054] For ease of understanding, the specific process of the embodiment of the present invention is described below. Figure 1 A flowchart of an error suppression compilation optimization method for quantum computers provided by an embodiment of the present invention, the method specifically comprising the following steps:

[0055] Step 101: Capture the physical quantum gate operation error rate and hardware topology of the quantum processor that performs the mapping task, and construct a hardware feature matrix;

[0056] In this embodiment, the physical quantum bits in the quantum processor are identified and a quantum computer with a size of Hardware feature matrix , for the physical quantum bit And when physical quantum bits The expected error rate of constructing CNOT gates between can be estimated as:

[0057] ;

[0058] in, Is connecting and Each connectivity path on the path between Is the path Error rate on hardware feature matrix and The value of is equal to , It is physical quantum bits, It is physical quantum bits.

[0059] Step 102: Capture the gate interaction properties of the quantum logic circuit to be compiled and construct a circuit feature matrix;

[0060] In this embodiment, the quantum logic circuit to be compiled is parsed, and the parsed quantum logic circuit is traversed to determine the logical quantum bits corresponding to each CNOT gate control bit and target bit. and ;

[0061] Construct a size of The circuit characteristic matrix , for each element of the circuit characteristic matrix , obtain logical qubits and logical qubits The number of CNOT gates executed between .

[0062] Step 103: Establish a mapping scheme representation model and a corresponding cost function based on the constructed hardware feature matrix and circuit feature matrix;

[0063] In this embodiment, define a Boolean variable , if and only if the logical qubit Mapped to physical qubits Upper time variable , otherwise there is ;

[0064] For all logical bits and all physical bits, the overhead function of the mapping is completed for:

[0065] ;

[0066] Among them, the hardware feature matrix Represented in physical quantum bits and Construct the expected error rate of the CNOT gate between Represented in logical qubits and The number of CNOT gates that need to be executed between Represents a set of logical qubits, including all logical qubits in the quantum logic circuit to be compiled; Represents a set of physical quantum bits, including the physical quantum bits that actually exist in the quantum processor; Boolean variable and Used to judge logical quantum bits Whether it is mapped to a physical quantum bit , and logical qubits Whether it is mapped to a physical quantum bit , only when the logical qubit pair is mapped to the corresponding physical qubit pair, the product of the hardware error rate and the number of circuit gates is included in the overhead cost calculation; when calculating the overhead cost, the double summation Traversing all possible logical qubit pairs and physical qubit pairs combination.

[0067] Step 104: Solve the cost function using a genetic algorithm to find a mapping solution that minimizes the cost function value while satisfying the resource constraints of the quantum processor.

[0068] In this embodiment, the resource constraints of the quantum processor include qubit-related constraints, connection relationship constraints, and operation resource constraints; quantity constraints: the number of physical qubits in a quantum processor is limited. For example, the number of qubits in many current quantum processors ranges from dozens to hundreds. The mapping scheme must ensure that logical qubits are reasonably mapped to these limited physical qubits and cannot exceed their quantity range; quality differences: the performance of different physical qubits varies, such as coherence time (the time it takes to maintain a quantum state), decoherence rate (the rate at which quantum coherence is lost), error rate, and other indicators. Qubits with short coherence times cannot undertake long-term computing tasks, and qubits with high error rates should be used with caution in key computing steps. These characteristics must be comprehensively considered during mapping; hardware topology constraints: qubits in a quantum processor have specific connection methods and topological structures, such as two-dimensional grids and linear structures. Two-bit gate operations (such as CNOT gates) can usually only be performed between qubits with direct connections. The mapping scheme must follow this connection relationship to ensure that gate operations between logical qubits are feasible on physical hardware, and avoid mapping logical qubits that require frequent interaction to physical qubits without direct connections. ; Coupling strength difference: Even if there is a connection between quantum bits, the coupling strength between them may be different, affecting the fidelity and execution efficiency of gate operations; this factor must be taken into account during mapping, so that logic gate operations with high coupling strength requirements are mapped to physical quantum bit pairs with appropriate coupling strength; Gate operation error rate limit: Each physical quantum bit has a certain error rate when performing single-bit gate operations, two-bit gate operations, etc.; To ensure the accuracy of the calculation results, the mapping scheme should try to assign logic gate operations to physical quantum bits with low error rates, or make the error accumulation of the overall operation within an acceptable range; Operation time limit: It takes a certain amount of time for quantum bits to perform gate operations, and different types of gate operations take different amounts of time; If the quantum logic circuit has strict requirements on operation time (such as real-time computing scenarios), the mapping scheme must consider the operation time characteristics of the physical quantum bits and reasonably arrange the logic gate operation sequence and mapping location to avoid calculation timeouts or task failures due to excessive operation time; In some quantum processor architectures, there are resource sharing mechanisms such as classical instrument sharing, and multiple quantum bits are connected to the same instrument and need to be time-shared; The mapping scheme must consider this resource sharing method to avoid the inability to execute operations due to resource conflicts.

[0069] In this embodiment, a hybrid genetic algorithm suitable for solving a mapping solution with a minimum cost function value includes the following steps:

[0070] S1. Represent the solution structure of the mapping scheme representation model as individuals of the genetic algorithm, and calculate the fitness of each individual using the cost function of the mapping scheme representation model;

[0071] S2. Generate an initial population and use the 2-opt operator of local nearest neighbor search to try to improve each individual in the population. The specific details are as follows: starting from the first gene of the individual, it cyclically exchanges with adjacent genes. If the individual's fitness improves, the exchange is retained;

[0072] S3, executing the following steps S4 to S8 in a loop until the specified iteration round is reached;

[0073] S4, looping through steps S5 to S6 until the number of offspring individuals is no less than the set value;

[0074] S5. Execute the tournament strategy on the existing population to obtain the parent generation;

[0075] S6. Execute the elite crossover strategy on the parent generation to obtain new offspring individuals and add them to the offspring population;

[0076] S7. Update individuals in the existing population based on the existing population and the new population;

[0077] S8. When the optimal individual of the population has not been updated for a long time, disturb the existing population;

[0078] S9. Return the optimal individual, whose chromosome arrangement is the optimal solution to the mapping optimization problem.

[0079] The specific process of step S6 is as follows: when two parents have consistent genes at the same position, all consistent genes are copied to the corresponding positions of the offspring; for positions in the offspring that have not been assigned, if there is no gene conflict with the offspring, one is randomly and uniformly selected from the positional genes of the two parents for copying; for positions that are still vacant, an unused gene is randomly selected for assignment to obtain the chromosomes for generating offspring, the above operations are repeated to generate several offspring, and a bidding competition strategy is executed among the offspring to select the best elite offspring.

[0080] The specific process of step S7 is: sorting in descending order according to fitness, and selecting the first several individuals with the highest fitness as the new existing population;

[0081] The specific process of step S8 is: performing a mutation operation on the chromosome of each individual in the population, cutting the gene from the specified cutting position, exchanging the positions of the two gene fragments and splicing them into a new gene.

[0082] Step 105: Apply the optimized mapping scheme to the quantum logic circuit to be compiled, and perform compilation optimization on the quantum logic circuit to be compiled.

[0083] The performance of the experimental platform used in the embodiment of the present invention is as follows: AMD Ryzen 7 5800H CPU, 16GB memory, Windows 10 software environment, Python 3.7.

[0084] In order to verify the mapping capability of the compilation optimization algorithm proposed in this invention for different circuits, mapping tests were carried out on randomly generated circuit datasets and real quantum circuit datasets. The 7-qubit processor IBM_Nairobi was selected as the quantum processor to be compiled. Its architecture topology is shown in the figure below. Figure 2 As shown in the figure, the expected error overhead generated by the mapping layout is used as the key indicator for the performance evaluation of this experiment. Through experimental tests, we compared the expected error overhead of the compilation optimization method of the present invention with that of algorithms such as trivial, dense, and sabre under different environment settings.

[0085] Figure 3 The mapping performance of all mapping algorithms on circuits with different numbers of CNOT gates is compared. Figure 3 "Different Gates" refers to the number of CNOT gates, "Overhead" refers to the overhead, "trivial," "dense," and "sabre" are the three benchmark algorithms used for comparison, and "QHGA" is the method used in this embodiment. We randomly generated quantum circuits with 15 to 150 CNOT gates for testing. To minimize the potential for randomness caused by the random distribution of CNOT gates in the circuit, the test was repeated three times at each quantum gate scale. The final result is the average of these repetitions. It can be observed that the overall prediction trends of the four layouts are basically consistent with different quantum gate counts, namely, the circuit error overhead increases linearly with the number of CNOT gates. The three benchmark mapping methods have similar overhead, but the compilation optimization method proposed in this invention consistently demonstrates the best performance among the compared methods. On average, it reduces overhead by 13.3% compared to other mapping algorithms. Furthermore, as we increase the number of CNOT gates in the test circuit, we still achieve good prediction results.

[0086] Figure 4 Eight random circuit sets were generated, each containing five circuits with the same number of two-qubit gates. Figure 4"Different Random Circuits" refers to different random circuits, and "Overhead" refers to overhead. The subgraph caption indicates the number of CNOT gates in the circuit. For example, "(a) 112 gates" indicates that the circuit in the random circuit set has 112 CNOT gates. The figure compares the performance of the proposed compilation optimization method with three benchmark mapping methods at eight different two-qubit gate counts. Each subgraph represents the total overhead generated by all random circuits in the corresponding dataset. The experimental results show that the other three benchmark mapping methods all exhibit significant fluctuations in predicted performance at the same scale of two-qubit gate counts, indicating that they are difficult to adapt to changes in circuit design. In contrast, the proposed compilation optimization method achieves the best performance in all subgraphs and maintains good stability at every scale. Regardless of the number and arrangement of two-qubit gates in the quantum circuit, the mapping layout generated by the proposed compilation optimization method consistently maintains significantly lower error overhead than the benchmark methods.

[0087] Figure 5 The present invention selects 9 7-qubit circuits with different numbers of two-qubit gates for testing, and compares the overall error overhead of each circuit using different mapping methods. Figure 5 "DifferentCircuits" means different circuits, and "Overhead" means overhead; due to the large differences in circuit characteristics in the data set, the average performance of the mapping method fluctuates greatly. In circuits with more CNOT gates, the overhead differences caused by different mapping methods are more significant. It can be seen that the compilation optimization method proposed in the present invention still shows significant superiority, and its average overhead is far lower than the other three mapping methods. At the same time, the compilation optimization method proposed in the present invention significantly reduces the error overhead caused by the mapping method in most real circuits, and even in the worst case, it achieves performance comparable to the suboptimal compilation optimization method. In the entire data set, the compilation optimization method proposed in the present invention relatively reduces the overhead by 23.6%.

[0088] Figure 6 The present invention selects 9 7-qubit circuits with different numbers of two-qubit gates for testing, and compares the average gate error overhead of each circuit using different compilation optimization methods. Figure 6"Different Circuits" refers to different circuits, and "Overhead" refers to overhead. By dividing the total overhead by the number of CNOT gates in the circuit, we can focus on the mapping performance of different compilation optimization methods for circuits with different gate arrangement characteristics. The comparison results show that no baseline method can well adapt to the differences in circuit characteristics, which is reflected in the fact that no baseline method consistently outperforms other baseline methods. In contrast, the compilation optimization method proposed in this paper demonstrated excellent performance in every circuit test case, while maintaining a consistently low average gate overhead.

[0089] The above shows and describes the basic principles, main features, and advantages of the present invention. Those skilled in the art should understand that the present invention is not limited to the above embodiments. The above embodiments and descriptions are merely preferred examples of the present invention and are not intended to limit the present invention. Various changes and improvements may be made to the present invention without departing from the spirit and scope of the present invention. Such changes and improvements fall within the scope of the present invention. The scope of protection claimed in the present invention is defined by the appended claims and their equivalents.

Claims

1. An error suppression compilation optimization method for quantum computers, characterized in that: The error suppression compilation optimization method for quantum computers includes: Capture the physical quantum gate operation error rate and hardware topology of the quantum processor that performs the mapping task, and construct a hardware feature matrix; Capture the gate interaction properties of the quantum logic circuit to be compiled and construct the circuit feature matrix; According to the constructed hardware feature matrix and circuit feature matrix, a mapping scheme representation model and a corresponding cost function are established; The cost function is solved using a genetic algorithm, and a mapping scheme that minimizes the cost function value is found while satisfying the resource constraints of the quantum processor. Applying the optimized mapping scheme to the quantum logic circuit to be compiled to perform compilation optimization on the quantum logic circuit to be compiled; The capturing of the physical quantum gate operation error rate and hardware topology of the quantum processor performing the mapping task and the construction of the hardware feature matrix include: Identify the physical quantum bits in the quantum processor and construct a Hardware feature matrix , for the physical quantum bit And when physical quantum bits The expected error rate of constructing CNOT gates between can be estimated as: ； in, Is connecting and Each connectivity path on the path between Is the path Error rate on hardware feature matrix and The value of is equal to , It is physical quantum bits, It is physical quantum bits.

2. The error suppression compilation optimization method for quantum computers according to claim 1, characterized in that: The capturing of gate interaction properties of the quantum logic circuit to be compiled and the construction of a circuit feature matrix include: Analyze the quantum logic circuit to be compiled, traverse the analyzed quantum logic circuit, and determine the logical quantum bits corresponding to each CNOT gate control bit and target bit and ; Construct a size of The circuit characteristic matrix , for each element of the circuit characteristic matrix , obtain logical qubits and logical qubits The number of CNOT gates executed between .

3. The error suppression compilation optimization method for quantum computers according to claim 1, characterized in that: The step of establishing a mapping scheme representation model and a corresponding cost function based on the constructed hardware feature matrix and circuit feature matrix includes: Defining Boolean variables , if and only if the logical qubit Mapped to physical qubits Upper time variable , otherwise there is ; For all logical bits and all physical bits, the overhead function of the mapping is completed for: ； Among them, the hardware feature matrix Represented in physical quantum bits and Construct the expected error rate of the CNOT gate between Represented in logical qubits and The number of CNOT gates that need to be executed between Represents a set of logical qubits, including all logical qubits in the quantum logic circuit to be compiled; Represents a set of physical quantum bits, including the physical quantum bits that actually exist in the quantum processor; Boolean variable and Used to judge logical quantum bits Whether it is mapped to a physical quantum bit , and logical qubits Whether it is mapped to a physical quantum bit .

4. The error suppression compilation optimization method for quantum computers according to claim 3, characterized in that: Boolean variables and Used to judge logical quantum bits Whether it is mapped to a physical quantum bit , and logical qubits Whether it is mapped to a physical quantum bit ,The product of hardware error rate and the number of circuit gates is included in the overhead cost calculation only when the logical qubit pair is mapped to the corresponding physical qubit pair.

5. The error suppression compilation optimization method for quantum computers according to claim 1, characterized in that: When calculating overhead costs, double sum Traversing all possible logical qubit pairs and physical qubit pairs combination; Represents a set of logical qubits, including all logical qubits in the quantum logic circuit to be compiled; Represents a set of physical quantum bits, including the physical quantum bits that actually exist in the quantum processor.

6. The error suppression compilation optimization method for quantum computers according to claim 1, characterized in that: The method of solving the cost function by using a genetic algorithm and finding a mapping scheme that minimizes the cost function value under the condition that the quantum processor resource constraints are satisfied includes: S1. Represent the solution structure of the mapping scheme representation model as individuals of the genetic algorithm, and calculate the fitness of each individual using the cost function of the mapping scheme representation model; S2. Generate an initial population and use the 2-opt operator of local nearest neighbor search to try to improve each individual in the population. The specific details are as follows: starting from the first gene of the individual, it exchanges with adjacent genes cyclically. If the individual's fitness improves, the exchange is retained; S3, executing the following steps S4 to S8 in a loop until the specified iteration round is reached; S4, looping through steps S5 to S6 until the number of offspring individuals is no less than the set value; S5. Execute the tournament strategy on the existing population to obtain the parent generation; S6. Execute the elite crossover strategy on the parent generation to obtain new offspring individuals and add them to the offspring population; S7. Update individuals in the existing population based on the existing population and the new population; S8. When the optimal individual of the population has not been updated for a long time, disturb the existing population; S9. Return the optimal individual, whose chromosome arrangement is the optimal solution to the mapping optimization problem.

7. The error suppression compilation optimization method for quantum computers according to claim 6, characterized in that: The method of executing the elite crossover strategy on the parent generation to obtain new offspring individuals and adding them to the offspring population includes: When two parents have identical genes at the same position, all identical genes are copied to the corresponding positions of the offspring; For the unassigned position in the offspring, one is randomly and uniformly selected from the position genes of the two parents for replication if there is no gene conflict with the offspring; For the still vacant positions, randomly select unused genes for allocation to obtain chromosomes for generating offspring. Repeat the above operation to generate several offspring, and execute the bidding strategy among the offspring to select the best elite offspring.

8. The error suppression compilation optimization method for quantum computers according to claim 6, characterized in that: The updating of individuals in the existing population according to the existing population and the new population includes: Sort in descending order according to fitness, and select the first few individuals with the highest fitness as the new existing population.

9. The error suppression compilation optimization method for quantum computers according to claim 6, characterized in that: When the optimal individual of the population has not been updated for a long time, the existing population is disturbed, including: A mutation operation is performed on the chromosome of each individual in the population, cutting the gene from the specified cutting position, exchanging the positions of the two gene fragments and splicing them into a new gene.

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