Test circuit, display chip and display

Abstract

The invention discloses a test circuit, a display chip and a display, and belongs to the technical field of electronics. A first test sub-circuit in the test circuit receives a first input signal transmitted by an input interface circuit and generates and outputs a first output signal based on the first input signal, and the first output signal and the input signal of the input interface circuit are used for determining whether the logic of the input interface circuit is correct or not. The first input signal is determined based on an input signal of the input interface circuit; a second test sub-circuit in the test circuit obtains and transmits a second input signal to the output interface circuit, the second input signal and an output signal of the output interface circuit are used for determining whether the logic of the output interface circuit is correct, and the output signal of the output interface circuit is determined based on the second input signal. The first output signal and the second input signal respectively enable signals output by the input interface circuit and signals input to the output interface circuit to be observable, so that the input interface circuit and the output interface circuit are testable.

Description

Technical Field

[0001] The present application relates to the field of electronic technology, and in particular to a test circuit, a display chip and a display. Background Art

[0002] The test circuit is a circuit used to test whether other circuits in the chip are accurate. The test circuit can be implemented through DFT (Design for Test). DFT refers to inserting devices or structures for testing into the circuit during the circuit design stage, so that the test signal can be applied to the designed circuit, thereby achieving the accuracy test of the logical function of the tested circuit through the test signal and the device or structure for testing. Therefore, DFT technology is usually used to build test circuits for IP (Intelligence Property) modules that encapsulate circuits in chips. Summary of the invention

[0003] The present application provides a test circuit, a display chip and a display, which can be used to implement the test of the interface circuit. The technical solution is as follows:

[0004] On the one hand, the present application provides a test circuit, which includes a first test sub-circuit and a second test sub-circuit; the first test sub-circuit is used to receive a first input signal output by an input interface circuit, generate a first output signal based on the first input signal, and output the first output signal, the first output signal and the input signal of the input interface circuit are used to determine whether the logic of the input interface circuit is correct, and the first input signal is determined based on the input signal of the input interface circuit; the second test sub-circuit is used to obtain a second input signal, transmit the second input signal to the output interface circuit, the second input signal and the output signal of the output interface circuit are used to determine whether the logic of the output interface circuit is correct, and the output signal of the output interface circuit is determined based on the second input signal.

[0005] In one possible implementation, the input interface circuit includes N input interface modules, the first input signal includes N first input sub-signals output by the N input interface modules, and the first output signal includes N first output sub-signals, where N is a positive integer; the first test sub-circuit includes N first triggers; the i-th first trigger is used to receive the i-th first input sub-signal and the first clock signal output by the i-th input interface module, and when the value of the first clock signal changes from a first value to a second value, the value of the i-th first input sub-signal is stored; when the value of the first clock signal changes from the first value to the second value again, the i-th first output sub-signal that is the same as the value of the i-th first input sub-signal is generated and output, where i is a positive integer less than or equal to N.

[0006] In a possible implementation, the input interface circuit includes N input interface modules, N is a positive integer greater than 1, the first input signal includes N second input sub-signals output by the N input interface modules, and the first output signal includes M second output sub-signals, M is a positive integer less than N; the first test sub-circuit includes M second triggers and M first logic modules, i is a positive integer less than or equal to M; the i-th first logic module is used to receive X second input sub-signals among the N second input sub-signals, and generate an i-th third input sub-signal according to the X second input sub-signals, X is less than or equal to N; the i-th second trigger is used to receive the i-th third input sub-signal and the second clock signal, and when the value of the second clock signal changes from the first value to the second value, the value of the i-th third input sub-signal is stored; when the value of the second clock signal changes from the first value to the second value again, the i-th second output sub-signal that is the same as the value of the i-th third input sub-signal is generated and output.

[0007] In one possible implementation, the input interface circuit includes N input interface modules, N is a positive integer greater than 1, and the first input signal includes N fourth input sub-signals output by the N input interface modules; the first test sub-circuit includes L third triggers and a second logic module, the L third triggers are connected in sequence, and L is a positive integer greater than 1 and less than or equal to N; the second logic module is used to receive the N fourth input sub-signals and generate a third input signal based on the N fourth input sub-signals; the L third triggers are used to receive the third input signal and a third clock signal, and based on the third clock signal, store and serially transmit the value of the third input signal until a first output signal with the same value as the third input signal is generated.

[0008] In one possible implementation, the output interface circuit includes A output interface modules, the second input signal includes A fifth input sub-signals, where A is a positive integer; the second test sub-circuit includes A fourth triggers; the i-th fourth trigger is used to receive the test signal and the fourth clock signal, and when the value of the fourth clock signal changes from the first value to the second value, the value of the test signal is stored; when the value of the fourth clock signal changes from the first value to the second value again, the i-th fifth input sub-signal having the same value as the test signal is generated and output to the i-th output interface module, where i is a positive integer less than or equal to A.

[0009] In one possible implementation, the output interface circuit includes A output interface modules, the second input signal includes A sixth input sub-signals, and A is a positive integer; the second test sub-circuit includes a third logic module and B fifth triggers; the B fifth triggers are used to receive the test signal and the fifth clock signal, generate a fourth input signal based on the fifth clock signal and the test signal, and transmit the fourth input signal to the third logic module; the third logic module is used to receive the fourth input signal and generate A sixth input sub-signals according to the fourth input signal.

[0010] In one possible implementation, the third logic module includes a logic unit and A selection units; the logic unit is used to receive a fourth input signal and generate an i-th sixth input sub-signal based on the fourth input signal; the i-th selection unit is used to receive the i-th sixth input sub-signal and a mode selection signal, and when the mode indicated by the mode selection signal is a test mode, output the i-th sixth input sub-signal to the i-th output interface module.

[0011] In one possible implementation, the output interface circuit and the second test sub-circuit are both connected to the analog IP core, and the i-th selection unit is also used to receive the output signal of the analog IP core, and when the mode indicated by the mode selection signal is the working mode, the output signal of the analog IP core is output to the i-th output interface module.

[0012] On the other hand, a display chip is provided, which includes an analog intellectual property IP core, an input interface circuit for transmitting signals to the analog IP core, an output interface circuit for receiving signals output by the analog IP core, and a test circuit as in any possible implementation method described above.

[0013] On the other hand, a display is provided, comprising the above-mentioned display chip.

[0014] The technical solution provided by this application brings at least the following beneficial effects:

[0015] The present application deploys a first test subcircuit for the input interface circuit, and a second test subcircuit for the output interface circuit. The first test subcircuit generates a first output signal based on the first input signal output by the input interface circuit, which can be observed. Since the logic of the first test subcircuit generating the first output signal based on the first input signal is known, the value of the first input signal can be determined by observing the first output signal, so that the first input signal can be observed, and the conversion relationship between the input signal of the input interface circuit and the output first input signal can be tested, that is, the logic of the input interface circuit can be tested. The second input signal transmitted by the second test subcircuit to the output interface circuit can be observed, and the conversion relationship between the input signal and the output signal of the output interface circuit can be tested, that is, the logic of the output interface circuit can be tested. Thus, the input interface circuit and the output interface circuit are tested through the first test subcircuit and the second test subcircuit, and the test coverage of the circuit is improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0017] Figure 1 is a structural schematic diagram of a test circuit provided in an embodiment of the present application;

[0018] Figure 2 is a structural schematic diagram of a first test sub-circuit provided in an embodiment of the present application;

[0019] Figure 3 is a structural schematic diagram of another first test sub-circuit provided in an embodiment of the present application;

[0020] Figure 4 is a structural schematic diagram of another first test sub-circuit provided in an embodiment of the present application;

[0021] Figure 5 is a structural schematic diagram of a second test sub-circuit provided in an embodiment of the present application;

[0022] Figure 6 is a structural schematic diagram of another second test sub-circuit provided in an embodiment of the present application;

[0023] Figure 7 is a structural diagram of a third logic module provided in an embodiment of the present application;

[0024] Figure 8It is a partial structural schematic diagram of a test circuit provided in an embodiment of the present application;

[0025] Fig. 9 It is a structural schematic diagram of a test circuit provided in an embodiment of the present application. DETAILED DESCRIPTION

[0026] In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation methods of the present application will be further described in detail below with reference to the accompanying drawings.

[0027] The test circuit is a circuit used to test whether other circuits in the chip are accurate. The test circuit can be implemented through DFT (Design for Test). DFT is usually used to insert test devices or structures into the digital circuits in the chip, so as to test the accuracy of the digital circuits in the chip after the chip is produced, packaged or used, so as to timely discover and improve the problems of the digital circuits in the chip. The digital IP module encapsulated with digital circuits in the chip has been packaged before being mounted on the chip. It is difficult to determine the performance and accuracy of the digital IP module by observing the state of the routing or devices in the digital IP module. Therefore, it is more necessary to test the digital IP module to determine the accuracy of the digital IP module.

[0028] For example, a test circuit is inserted around the digital IP module to be tested in the chip, and a test signal is input into the digital IP module through the test circuit, so as to obtain a signal obtained by the digital IP module based on the test signal processing. Then, through a comparison device externally connected to the chip, the test signal input into the digital IP module and the signal generated by the digital IP module based on the test signal are compared to determine whether the signal processed by the digital IP module is correct, thereby determining whether the logical function of the digital circuit inside the digital IP module is accurate. If the processing logic between the signal processed by the digital IP module based on the test signal and the test signal conforms to the preset logic of the digital IP module, it means that the logic of the digital circuit inside the digital IP module is correct, and the digital IP module is not abnormal. If the conversion logic between the signal processed by the digital IP module based on the test signal and the test signal does not conform to the preset logic of the digital IP module, it means that the logic of the digital circuit inside the digital IP module is wrong, and the digital IP module is abnormal.

[0029] Some chips may integrate not only digital IP modules but also analog IP modules to be compatible with multiple protocols. The circuits inside the analog IP modules are mostly analog circuits. For example, the circuits of the analog IP core in the analog IP module are analog circuits. However, the interface parts of the analog IP module other than the analog IP core may integrate digital interface circuits to connect the analog IP module with other digital IP modules or digital circuits in the chip. If DFT is not performed on the analog IP module, it is difficult to determine the accuracy of the digital interface circuits in the analog IP module and to ensure the quality of the chip.

[0030] Take the display chip, such as a scaler chip, as an example. The scaler chip is widely used in consumer electronics products such as notebooks and computer monitors. The main function of the scaler chip is to receive image information from the front-end graphics card, and process image information such as image capture and zooming. In combination with the display driver chip and the TCON (timing control) chip, high-quality images are presented on the display screen. Among them, the scaler chip needs to be compatible with various audio and video protocols, so a large number of analog IP modules with specific analog signal processing functions are required, such as HDMIPHY (High-Definition Multimedia Interface Physical Layer) module, EDP PHY (Embedded DisplayPort Physical Layer) module, DP PHY (DisplayPort Physical Layer) module and DDR PHY (Double Data Rate Physical Layer) module, which are all analog IP modules. Moreover, many high-specification display screens may be deployed with multiple DP interfaces or HDMI interfaces, which increases the number of analog IP modules used in the scaler chip.

[0031] Since most of the circuits in HDMI PHY modules, DP PHY modules, and other modules are analog circuits, the chip generally does not have a built-in scan chain for detecting these modules. Among them, the scan chain refers to the structure used to test digital circuits by linking multiple registers generated based on flip-flops through ATPG (Automatic Test Pattern Generation) technology. Therefore, HDMI PHY modules, DP PHY modules, and other modules usually do not have built-in scan chains.

[0032] However, there are many digital interfaces in the interface part of the HDMI PHY module, DP PHY module, etc., such as the data receiving interface (RX DATA) circuit, etc. The digital interface part of a DP PHY module has a data receiving interface circuit that can transmit digital signals of about 150 bits in serial or parallel. If a high-performance scaling chip is deployed with dual DP PHY modules or dual HDMI PHY modules, then the data receiving interface circuit connected to the dual DP PHY modules or dual HDMI PHY modules can transmit digital signals of about 600 bits in serial or parallel.

[0033] It can be seen that the digital interface circuits in the analog IP modules account for a certain proportion of the chip circuits. If the digital interface circuits in these analog IP modules are not tested, the test coverage rate of the digital circuits in the chip will be low, and the accuracy of the digital interface circuits in the analog IP modules will be difficult to guarantee, thereby making it difficult to guarantee the performance of the chip. In addition, in vehicle-mounted or high-stability scenarios, there are certain requirements for the test coverage rate of the digital circuits in the chip, so a circuit structure is needed to generate test coverage for the digital interface circuits in the analog IP modules to improve the test coverage rate of the digital circuits in the chip, thereby ensuring the quality and performance of the chip.

[0034] Based on the above description, it can be known that in the process of testing a digital circuit, by comparing whether the input signal and output signal of the digital input interface circuit conform to the preset logic of the digital input interface circuit, it is determined whether the logic of the digital input interface circuit is accurate; by comparing whether the input signal and output signal of the digital output interface circuit conform to the preset logic of the digital output interface circuit, it is determined whether the logic of the digital output interface circuit is accurate. However, since the output signal of the digital input interface circuit is transmitted to the connected analog IP core, it is difficult to obtain the output signal of the digital input interface circuit, resulting in difficulty in determining whether the logic of the digital input interface circuit is accurate. Correspondingly, the input signal of the digital output interface circuit is the output signal of the connected analog IP core. Since the signal of the analog IP core and the processing logic of the analog IP core for the input signal are unknown, it is also difficult to obtain the input signal of the digital output interface circuit, resulting in difficulty in determining whether the logic of the digital output interface circuit is accurate.

[0035] The embodiment of the present application provides a test circuit, which can make the output signal of the input interface circuit connected to the analog IP core or the unknown IP core and the input signal of the output interface circuit controllable, so as to test the accuracy of the input interface circuit and the output interface circuit according to the output signal of the input interface circuit and the input signal of the output interface circuit. Optionally, the input interface circuit and the output interface circuit can both be digital circuits or analog circuits. Figure 1, shows a schematic diagram of the structure of a test circuit provided in an embodiment of the present application, the test circuit includes a first test subcircuit 11 and a second test subcircuit 12. In a possible implementation, the first test subcircuit 11 and the second test subcircuit 12 are located in the display chip, the first test subcircuit 11 is connected to the input interface circuit in the display chip, the input interface circuit is used to transmit signals to the analog IP core or the unknown IP core, and the second test subcircuit 12 is connected to the output interface circuit, and the output interface circuit is used to receive the signal output by the analog IP core or the unknown IP core. Optionally, the display chip can be a display driver chip, an image processing chip, a power management chip, etc., which includes both digital IP modules and analog IP modules, such as the scaling chip mentioned above.

[0036] In an exemplary embodiment, the first test subcircuit 11 and the second test subcircuit 12 are both connected to a comparison device. The comparison device is a device for determining whether the logic of the input interface circuit and the output interface circuit is accurate according to the input or output signals of the first test subcircuit 11 and the second test subcircuit 12. For example, the comparison device can be ATE (Automatic Test Equipment), a boundary scan test unit (Boundary-Scan Test Unit) or a response analyzer.

[0037] The first test subcircuit 11 in the test circuit is used to receive a first input signal output by the input interface circuit, generate a first output signal based on the first input signal, and output the first output signal. The first output signal and the input signal of the input interface circuit are used to determine whether the logic of the input interface circuit is correct, and the first input signal is determined based on the input signal of the input interface circuit. The second test subcircuit 12 is used to obtain a second input signal, transmit the second input signal to the output interface circuit, and the second input signal and the output signal of the output interface circuit are used to determine whether the logic of the output interface circuit is correct, and the output signal of the output interface circuit is determined based on the second input signal.

[0038] During the process of testing the input interface circuit, the input interface circuit processes the current input signal to the input interface circuit to generate a first input signal. The input signal of the input interface circuit can be a test signal or a signal that needs to be input to the input interface circuit during the operation of the display chip. The first input signal is transmitted to the first test sub-circuit 11.

[0039] After receiving the first input signal, the first test subcircuit 11 generates a first output signal based on the first input signal. In the embodiment of the present application, the manner in which the first test subcircuit 11 generates the first output signal based on the first input signal is related to the structure of the first test subcircuit 11, and the structure of the first test subcircuit 11 is related to the structure of the input interface circuit. The embodiment of the present application does not limit the structure of the first test subcircuit 11, and correspondingly does not limit the manner in which the first test subcircuit 11 generates the first output signal based on the first input signal. Below, taking Examples 1 to 3 as examples, various possible structures of the first test subcircuit 11 and the corresponding manner in which the first output signal is generated based on the first input signal are described.

[0040] Example 1, see Figure 2 , showing a schematic diagram of the structure of a first test subcircuit 11 provided in an embodiment of the present application. The input interface circuit includes N input interface modules, and the first test subcircuit 11 includes N first triggers 111. Among them, the first input signal includes N first input sub-signals output by the N input interface modules, and the first output signal includes N first output sub-signals, and N is a positive integer. That is, the number of input interface modules can be one or more, and the number of first triggers 111 in the first test subcircuit 11 is the same as the number of input interface modules, or it can be one or more, one first trigger 111 is connected to one input interface module, and one input interface module is connected to one first trigger 111, and different input interface modules are connected to different first triggers 111. Optionally, the first trigger 111 can be a D (data) trigger or a composite trigger with a D trigger function.

[0041] The i-th (i is a positive integer less than or equal to N) first flip-flop 111 is used to receive the i-th first input sub-signal and the first clock signal output by the i-th input interface module. That is, each first flip-flop 111 receives the first input sub-signal output by the corresponding input interface module as the input of each first flip-flop 111. The first clock signal is a signal used to control the frequency of the output signal of the first flip-flop 111, and the first clock signals received by different first flip-flops 111 may be the same or different.

[0042] Still taking the i-th first trigger 111 as an example, when the value of the first clock signal changes from the first value to the second value, the i-th first trigger 111 stores the value of the i-th first input sub-signal; when the value of the first clock signal changes from the first value to the second value again, the i-th first output sub-signal that is the same as the value of the i-th first input sub-signal is generated and output. Among them, the first value is different from the second value, and the specific values ​​of the first value and the second value are not limited in this application. If the first value is a signal value indicating a high level, the second value is a signal value indicating a low level; if the first value is a signal value indicating a low level, the second value is a signal value indicating a high level.

[0043] For example, the first value is a signal value indicating a high level, and the second value is a signal value indicating a low level. After the i-th first trigger 111 receives the i-th first input sub-signal, when the first falling edge of the first clock signal arrives, that is, the value of the first clock signal changes from the first value to the second value for the first time, the i-th first trigger 111 reads the value of the i-th first input sub-signal and stores it. When the second falling edge of the first clock signal arrives, that is, the value of the first clock signal changes from the first value to the second value for the second time, the i-th first trigger 111 reads the stored value of the i-th first input sub-signal, generates the i-th first output sub-signal, and outputs it.

[0044] The N first flip-flops 111 generate and output the first output sub-signals based on their respective first input sub-signals, that is, to realize the generation and output of the first output signal. In Example 1, the first flip-flops 111 realize the output of the value of the first input signal according to the first clock signal, so that the value of the first input signal is easy to obtain and observe by the comparison device.

[0045] Example 2, see Figure 3 , shows a schematic diagram of the structure of another possible first test subcircuit 11 provided in an embodiment of the present application. The input interface circuit includes N input interface modules, N is a positive integer greater than 1, the first test subcircuit 11 includes M second triggers 112 and M first logic modules 113, the i-th second trigger 112 is connected to the i-th first logic module 113, i is a positive integer less than or equal to M. Among them, the first input signal includes N second input sub-signals output by the N input interface modules, the first output signal includes M second output sub-signals, M is a positive integer less than N. One input interface module can be connected to one or more first logic modules 113, the first logic module 113 can be connected to one or more input interface modules, one first logic module 113 is connected to one second trigger 112, and different first logic modules 113 are connected to different second triggers 112.

[0046] Optionally, the second trigger 112 may be a D trigger or a composite trigger having the function of a D trigger. The structure and processing logic of the first logic module 113 are not limited in the embodiment of the present application. The first logic module 113 may include one or more logic gates, and the types of the different logic gates included may be the same or different. The structures and processing logics of different first logic modules 113 may be the same or different.

[0047] The i-th first logic module 113 is used to receive X second input sub-signals among the N second input sub-signals, where X is greater than or equal to 1 and X is less than or equal to N. The X second input sub-signals received by the i-th first logic module 113 are second input sub-signals transmitted to the i-th first logic module 113 by each (a total of X) input interface module connected to the i-th first logic module 113.

[0048] After receiving the X second input sub-signals, the i-th first logic module 113 generates the i-th third input sub-signal according to the X second input sub-signals. Exemplarily, the i-th first logic module 113 generates the i-th third input sub-signal corresponding to the X second input sub-signals according to the processing logic of the i-th logic module 113.

[0049] The i-th second flip-flop 112 is used to receive the i-th third input sub-signal and the second clock signal, and when the value of the second clock signal changes from the first value to the second value, the value of the i-th third input sub-signal is stored; when the value of the second clock signal changes from the first value to the second value again, the i-th second output sub-signal having the same value as the i-th third input sub-signal is generated and output. The process of the i-th second flip-flop 112 generating and outputting the i-th second output sub-signal based on the i-th third input sub-signal and the second clock signal can refer to the process of the i-th first flip-flop 111 generating and outputting the i-th first output sub-signal based on the i-th first input sub-signal and the first clock signal in Example 1, which will not be repeated here.

[0050] The M second flip-flops 112 generate and output the second output sub-signals based on their respective third input sub-signals, that is, to realize the generation and output of the first output signal. In Example 2, the N second input sub-signals are processed by the M first logic modules 113, reducing the number of required second flip-flops 112, thereby reducing the area occupied by the test circuit and the required cost. In addition, the second flip-flop 112 realizes the output of the value of the first input signal according to the second clock signal, so that the value of the first input signal is easy to obtain and observe by the comparison device.

[0051] Example 3, see Figure 4, shows a schematic diagram of the structure of another first test subcircuit 11 provided in an embodiment of the present application. The input interface circuit includes N input interface modules, N is a positive integer greater than 1, the first test subcircuit 11 includes L third triggers 114 and a second logic module 115, the second logic module 115 is connected to the first third trigger 114, and the second logic module 115 is connected to the N input interface modules, the L third triggers 114 are connected in sequence, and L is a positive integer greater than 1 and less than or equal to N. Among them, the first input signal includes N fourth input sub-signals output by the N input interface modules, and the first output signal is the signal output by the Lth third trigger 114.

[0052] The second logic module 115 is used to receive the N fourth input sub-signals and generate the third input signals corresponding to the N fourth input sub-signals according to the N fourth input sub-signals. Exemplarily, the second logic module 115 generates and outputs the third input signals corresponding to the N fourth input sub-signals according to the processing logic of the second logic module 115. The structure and processing logic of the second logic module 115 are not limited in the embodiment of the present application. For example, the second logic module 115 may include one or more logic gates.

[0053] L third flip-flops 114 are used to receive a third input signal and a third clock signal, and store and serially transmit the value of the third input signal based on the third clock signal until a first output signal having the same value as the third input signal is generated. The frequencies and phases of the third clock signals input to different third flip-flops 114 are consistent.

[0054] For example, the first third flip-flop 114 is connected to the output port of the second logic module 115. After the first third flip-flop 114 receives the third input signal output by the second logic module 115, when the third clock signal input to the first third flip-flop 114 changes from the first value to the second value for the first time, the first third flip-flop 114 reads and stores the value of the third input signal. When the third clock signal input to the first third flip-flop 114 changes from the first value to the second value for the second time, the first third flip-flop 114 outputs a signal identical to the value of the third input signal. After the second third flip-flop 114 receives the signal output by the first third flip-flop 114, when the value of the third clock signal input to the second third flip-flop 114 changes from the first value to the second value for the first time, the second third flip-flop 114 reads and stores the value of the signal output by the first third flip-flop 114. When the value of the third clock signal input to the second third flip-flop 114 changes from the first value to the second value for the second time, the second third flip-flop 114 outputs a signal identical to the value of the third input signal. And so on, until the Lth third flip-flop 114 outputs a signal having the same value as the third input signal, and this signal is the first output signal.

[0055] In Example 3, L third flip-flops 114 are connected to form a scan chain, and the second logic module 115 generates a third input signal based on N fourth input sub-signals, and the third input signal is transmitted serially through the scan chain to finally output a first output signal. The scan chain composed of L third flip-flops 114 can synchronously read and output signals in a scan cycle, thereby reducing the time and number of tests required and improving test efficiency.

[0056] The above introduces a variety of different structures of the first test subcircuit 11 and the way in which the first test subcircuit 11 generates and outputs the first output signal. Regardless of the structure of the first test subcircuit 11 used to generate and output the first output signal, the first output signal can be transmitted to the comparison device. Exemplarily, the output end of the first test subcircuit 11 can be an output pin of a display chip, that is, the signal output by an output pin of the display chip is the signal output by the output end of the first test subcircuit 11. The comparison device is connected to the output pin of the display chip so that the first output signal can be transmitted to the comparison device.

[0057] After the comparison device obtains the first output signal, it can compare the value of the first output signal and the value of the first reference output signal to obtain a comparison result. The value of the first reference output signal is the value of the signal obtained by the first test subcircuit 11 after the input interface circuit processes the input signal according to accurate logic. When the comparison result obtained is that the value of the first output signal is the same as the value of the first reference output signal, the logic of the input interface circuit is correct, that is, the input interface circuit has no abnormality; when the comparison result obtained is that the value of the first output signal is different from the value of the first reference output signal, the logic of the input interface circuit is incorrect, that is, the input interface circuit has an abnormality.

[0058] In addition to the first test subcircuit 11, the test circuit provided in the embodiment of the present application also includes a second test subcircuit 12. In the process of testing the output interface circuit, the second test subcircuit 12 obtains the second input signal that needs to be transmitted to the output interface circuit. In the embodiment of the present application, the way in which the second test subcircuit 12 obtains the second input signal is related to the structure of the second test subcircuit 12, and the structure of the second test subcircuit 12 is related to the structure of the output interface circuit. The embodiment of the present application does not limit the structure of the second test subcircuit 12, and correspondingly does not limit the way in which the second test subcircuit 12 obtains the second input signal. Below, taking Example 4 and Example 5 as examples, various possible structures of the second test subcircuit 12 and the corresponding ways of obtaining the second input signal are explained.

[0059] Example 4, see Figure 5, showing a schematic diagram of the structure of a second test sub-circuit 12 provided in an embodiment of the present application. The output interface circuit includes A output interface modules, A is a positive integer; the second test sub-circuit 12 includes A fourth triggers 121. Among them, the second input signal includes A fifth input sub-signals. That is, the number of output interface modules can be one or more, the number of fourth triggers 121 in the second test sub-circuit 12 is the same as the number of output interface modules, and can also be one or more, one fourth trigger 121 is connected to one output interface module, and one output interface module is connected to one fourth trigger 121, and different output interface modules are connected to different fourth triggers 121. Optionally, the first trigger 111 can be a D trigger or a composite trigger with a D trigger function.

[0060] The i-th (i is a positive integer less than or equal to A) fourth trigger 121 is used to receive a test signal and a fourth clock signal. Optionally, the test signals received by different fourth triggers 121 may be the same or different. The test signal may be a signal dedicated to testing output by a front-end circuit connected to the fourth trigger 121. In a possible implementation, the second test subcircuit 12 is connected to the first test subcircuit 11. In this implementation, the test signal may be the first output signal output by the first test subcircuit 11. The fourth clock signal is a signal used to control the frequency of the output signal of the fourth trigger 121. The fourth clock signals received by different fourth triggers 121 may be the same or different.

[0061] Still taking the i-th fourth trigger 121 as an example, when the value of the fourth clock signal changes from the first value to the second value, the value of the test signal is stored; when the value of the fourth clock signal changes from the first value to the second value again, the i-th fifth input sub-signal with the same value as the test signal is generated and output to the i-th output interface module.

[0062] The N fourth flip-flops 121 generate and output the fifth input sub-signal based on the test signals received by each of them, that is, to realize the generation and output of the second input signal. In Example 4, the output of the second input signal of the value of the test signal is realized by the fourth flip-flop 121 according to the fourth clock signal, so that the value of the second input signal is easy to obtain and observe by the comparison device.

[0063] Example 5, see Figure 6, shows a schematic diagram of the structure of another possible second test subcircuit 12 provided in an embodiment of the present application. The output interface circuit includes A output interface modules, A is a positive integer; the second test subcircuit 12 includes a third logic module 123 and B fifth triggers 122. Among them, the third logic module 123 is connected to the A output interface modules, and the third logic module 123 is connected to one or more fifth triggers 122 in the B fifth triggers 122. The B fifth triggers 122 can be connected in series in sequence or not connected to each other. In Example 5, the second input signal includes A sixth input sub-signals.

[0064] B fifth flip-flops 122 are used to receive a test signal and a fifth clock signal, generate a fourth input signal based on the fifth clock signal and the test signal, and transmit the fourth input signal to the third logic module 123. If the B fifth flip-flops 122 are not connected to each other and are all connected to the third logic module 123, the B fifth flip-flops generate their respective corresponding fourth input sub-signals based on the received test signal and the fifth clock signal. For example, the i-th fifth flip-flop 122 receives a test signal and a fifth clock signal and generates an i-th fourth input signal. The process of the i-th fifth flip-flop 122 generating the i-th fourth input signal based on the test signal and the fifth clock signal can refer to the process of the i-th first flip-flop 111 generating the i-th first output sub-signal based on the first input sub-signal and the first clock signal in Example 1, which will not be repeated here.

[0065] Alternatively, if B fifth flip-flops 122 are connected in series in sequence, and the Bth fifth flip-flop 122 is connected to the third logic module 123, the B fifth flip-flops 122 are used to receive the test signal and the fifth clock signal, and store and serially transmit the value of the test signal based on the fifth clock signal until a fourth input signal having the same value as the test signal is generated. The frequency phase and frequency of the fifth clock signals input to different fifth flip-flops 122 are consistent.

[0066] For example, after the first fifth flip-flop 122 receives the test signal, when the fifth clock signal input to the first fifth flip-flop 122 changes from the first value to the second value for the first time, the first fifth flip-flop 122 reads and stores the value of the test signal, and when the fifth clock signal input to the first fifth flip-flop 122 changes from the first value to the second value for the second time, the first fifth flip-flop 122 outputs a signal that is the same as the value of the test signal. After the second fifth flip-flop 122 receives the signal output by the first fifth flip-flop 122, when the value of the fifth clock signal input to the second fifth flip-flop 122 changes from the first value to the second value for the first time, the second fifth flip-flop 122 reads and stores the value of the signal output by the first fifth flip-flop 122, and when the value of the fifth clock signal input to the second fifth flip-flop 122 changes from the first value to the second value for the second time, the second fifth flip-flop 122 outputs a signal that is the same as the value of the test signal. This is done by analogy until the Bth fifth flip-flop 122 outputs a signal that is the same as the value of the test signal, which is the fourth input signal.

[0067] Regardless of how the B fifth flip-flops 122 generate the fourth input signal, the third logic module 123 can receive the fourth input signal, and generate and output A sixth input sub-signals according to the processing logic of the third logic module 123. The processing logic of the third logic module 123 is not limited in the embodiment of the present application. The processing logic of the third logic module 123 is related to the structure of the third logic module 123. For example, if the third logic module 123 includes an AND gate, the processing logic of the third logic module 123 is an AND processing logic. The embodiment of the present application also does not limit the structure of the third logic module 123.

[0068] For example, see Figure 7 , shows a schematic diagram of the structure of a third logic 123 provided in an embodiment of the present application. The third logic module 123 includes a logic unit 1231 and A selection units 1232. The logic unit 1231 is connected to one or more fifth triggers 122 of the B fifth triggers 122. The logic unit 1231 is used to receive the fourth input signal, and according to the processing logic of the logic unit 1231, generates and outputs the i-th sixth input sub-signal to the i-th selection unit 1232. The processing logic of the logic unit 1231 is also the processing logic of the third logic module 123. The embodiment of the present application does not limit the processing logic of the logic unit 1231, and the logic unit 1231 may include one or more logic gates.

[0069] The i-th selection unit 1232 is used to receive the i-th sixth input sub-signal and a mode selection signal, where the modes include: working mode and test mode. When the mode indicated by the mode selection signal is the test mode, the i-th sixth input sub-signal is output to the i-th output interface module. The mode selection signals received by different selection units 1232 may be the same or different. The mode selection signal may be input through the input pin of the display chip and transmitted to each selection unit 1232.

[0070] Since the output interface circuit not only needs to be tested for accuracy, but also needs to work normally based on the signal output by the analog IP core or the unknown IP core when the accuracy test is not performed, the embodiment of the present application adds a selection unit 1232 in the third logic module 123 and controls the mode of the selection unit 1232. Taking the connection between the output interface circuit and the analog IP core as an example, in the test mode, the selection unit 1232 outputs the sixth input sub-signal required for the test. In addition, the i-th selection unit 1232 is also used to receive the output signal of the analog IP core, and when the mode indicated by the mode selection signal is the working mode, the output signal of the analog IP core is output to the i-th output interface module.

[0071] The A sixth input sub-signals output by the third logic module 123 are transmitted to the A output interface modules respectively, and one sixth input sub-signal is transmitted to one output interface module. The values ​​of different sixth input sub-signals can be the same or different.

[0072] The above describes a variety of different structures of the second test subcircuit 12 and the manner in which the second test subcircuit 12 obtains the second input signal. Regardless of the structure of the second test subcircuit 12 used to obtain the second input signal, the second input signal can be transmitted to the output interface circuit. Optionally, the second input signal can also be transmitted to the comparison device, and the output end of the second test subcircuit 12 can not only be connected to the output interface circuit, but also serve as an output pin of the display chip. The comparison device is connected to the output pin of the display chip, so that the comparison device can obtain the second input signal.

[0073] The output interface circuit processes based on the second input signal and outputs the processed signal. The signal output by the output interface circuit is transmitted to the comparison device. After the comparison device obtains the output signal of the output interface circuit, it can compare the value of the output signal of the output interface circuit and the value of the second reference output signal to obtain a comparison result. The value of the second reference output signal is the value of the output signal obtained after the output interface circuit processes the second input signal output by the second test subcircuit 12 according to accurate logic. When the value of the signal output by the output interface circuit based on the second input signal is the same as the value of the second reference output signal, the logic of the output interface circuit is correct, that is, the output interface circuit has no abnormality; when the value of the signal output by the output interface circuit based on the second input signal is different from the value of the second reference output signal, the logic of the output interface circuit is incorrect, that is, the output interface circuit has an abnormality.

[0074] The following is an example of the test circuit provided in the embodiment of the present application. Figure 8 , showing a partial structural diagram of a test circuit provided by an embodiment of the present application. The first test sub-circuit 11 and the second test sub-circuit 12 in the test circuit share the same trigger, that is, Figure 8 The obs_analog_output1_reg, obs_analog_output2_reg and obs_analog_input_reg belong to both the first test sub-circuit 11 and the second test sub-circuit 12 .

[0075] Figure 8The types and functions of the triggers in the trigger are the same. Taking obs_analog_output1_reg as an example, the D port is the data input port, which is the port for the trigger to receive external data. When the effective edge of the clock signal (rising edge or falling edge, depending on the trigger type) arrives, the trigger will store the current level state of the D port and reflect it at the output end (Q end). The RDN port is a low-level active reset port, which is used to force the output of the trigger to a specific state. When the RDN port is low (usually logic 0), regardless of the state of other input signals, the trigger will be reset, and the Q port output will usually be set to logic 0, that is, reset. When the RDN port is high (logic 1), the trigger works normally and performs state transitions according to the clock and data input. The SE port is a shift enable port, which is used to control whether the trigger performs a shift operation. When SE is valid (usually high), the trigger allows data to be shifted; when SE is invalid (usually low), the trigger does not perform a shift operation and maintains the current storage state. SI port is a serial input port, which is used to input data in serial mode. Data is input bit by bit through SI port, and under the action of clock signal, data is shifted into the trigger in sequence to realize serial transmission and storage of data. CKN port is a clock active-low port, which is used to provide clock signal for the operation of trigger.

[0076] Figure 8 It is the structure of the test circuit that simulates the input interface circuit and output interface circuit of the IP core before passing through the scan chain. Figure 8 The intersection of the two lines with a connection point indicates that the two lines are connected, and the intersection of the two lines without a connection point indicates that the two lines are not connected. Wherein, AnalogIP is an analog IP core, n101 port, n102 port, n188 port and n206 port are ports for connecting the input interface circuit with the first test subcircuit 11, and 7_p port and 8_p port are ports for connecting the output interface circuit with the second test subcircuit 12. Figure 8 The first test subcircuit 11 included in the circuit shown is the above Figure 4 The first test subcircuit 11 of the structure shown, Figure 8 The logic gates C951, C95, C951C and C654 in Figure 4 The second logic module 115 in the first test sub-circuit 11 of this structure, that is, the second logic module 115 includes these logic gates, and the connection relationship between the various logic gates is as follows: Figure 8 As shown. Figure 8In the circuit shown, obs_analog_input_reg corresponds to Figure 4 The first test subcircuit 11 of this structure includes the first third flip-flop 114, obs_analog_output1_reg corresponds to Figure 4 The first test subcircuit 11 of this structure includes a second third flip-flop 114, obs_analog_output2_reg corresponds to Figure 4 The first test sub-circuit 11 of this structure includes a third flip-flop 114 .

[0077] The N fourth input sub-signals included in the first input signal are four fourth input sub-signals outputted from the n101 port, the n102 port, the n188 port and the n206 port. The signal inputted to the A1 terminal of the logic gate C951 is the fourth input sub-signal outputted from the n101 port, the signal inputted to the A2 terminal of the logic gate C951 is the fourth input sub-signal outputted from the n102 port, the type of the logic gate C951 is an exclusive OR gate, the logic gate C951 performs an exclusive OR (Exclusive OR, XOR) process on the two received fourth input sub-signals, and the signal obtained by the exclusive OR process of the logic gate C951 is inputted to the A2 terminal of the logic gate C951C. The signal input to the A1 end of the logic gate C95 is the fourth input sub-signal output by the n206 port, and the signal input to the A2 end of the logic gate C95 is the fourth input sub-signal output by the n188 port. The type of the logic gate C95 is an XOR gate, and the logic gate C95 performs XOR processing on the two received signals, and the signal obtained by the XOR processing of the logic gate C95 is input to the A1 end of the logic gate C951C. The type of the logic gate C951C is an XOR gate, and the logic gate C951C performs XOR processing on the two received signals, and the signal obtained by the XOR processing is input to the A1 end of the logic gate C654. The signal input to the A2 end of the logic gate C654 is the signal output by the obs_en_tdr port. The type of the logic gate C654 is an AND gate, and the logic gate C654 performs AND processing on the two received signals, and the signal obtained by the AND processing is the third input signal. Among them, the advantage of using an XOR gate in the second logic module 115 is that the output of the XOR gate is related to both inputs of the XOR gate. This can improve the coverage of the test. The signal output by the obs_en_tdr port is an enable signal, which sets the signal output by the obs_en_tdr port to a high level, so that the signal output by the logic gate C654 is determined based on the input signal at the A1 terminal, thereby making the signal output by the logic gate C654 determined based on each fourth input sub-signal.

[0078] The signal output by the logic gate C654 is the third input signal. The third input signal is input into the first third trigger 114 included in the first test sub-circuit 11. The first third trigger 114 is also Figure 8 obs_analog_input_reg in. Figure 8 In the circuit shown, the triggers are not yet connected, so the description of the process of each trigger generating the first output signal based on the third input signal is described below. Fig. 9 The relevant instructions are not elaborated here.

[0079] Figure 8 The third clock signals received by the multiple triggers in are all signals output by the clk port, thereby realizing clock synchronization of the multiple triggers. The signals output by the rst port are transmitted to the RDN terminals of the multiple triggers, thereby controlling whether the multiple triggers are reset. When the signals output by the rst port control the multiple triggers not to be reset, the signals output by the Q terminals of the multiple triggers are determined based on the signals input by the D terminal or the SI terminal, thereby realizing the storage of the signals input by the D terminal or the SI terminal to realize the test.

[0080] Figure 8 In the circuit shown, the three flip-flops obs_analog_input_reg, obs_analog_output1_reg and obs_analog_output2_reg belong not only to the first test sub-circuit 11 , but also to the second test sub-circuit 12 . Figure 8 The structure of the second test subcircuit 12 included in the circuit shown corresponds to the above Figure 6 and Figure 7 The structure shown. Figure 8 obs_analog_input_reg, obs_analog_output1_reg, and obs_analog_output2_reg in all correspond to Figure 6 The fifth flip-flop 122, logic gate C65411 and logic gate C65422 in the second test subcircuit 12 of this structure correspond to Figure 6 The third logic module 123 in the second test subcircuit 12 of this structure specifically corresponds to Figure 7 The logic unit 1231 in the third logic module 123 of this structure. Figure 8 Selectors U409 and U4092 in correspond to Figure 7 The selection unit 1232 in the third logic module 123 of this structure.

[0081] During the test, the D terminal or SI terminal of each trigger receives the test signal, and the CKN terminal receives the fifth clock signal output by the clk port. A fourth input signal is generated based on the fifth clock signal and the test signal. The fourth input signal includes the signal output by the Q terminal of obs_analog_output1_reg and the signal output by the Q terminal of obs_analog_output2_reg. The signal output by the Q terminal of obs_analog_output1_reg is input to the A1 terminal of the logic gate C65411, and the signal output by the Q terminal of obs_analog_output2_reg is input to the A1 terminal of the logic gate C65422 as the fourth input signal input to the third logic module 123. In addition, the signal output by the obs_en_tdr port is input to the A2 end of the logic gate C65411 and the A2 end of the logic gate C65422. The signal output by the obs_en_tdr port is an enable signal, which sets the signal output by the obs_en_tdr port to a high level. Since the types of the logic gates C65411 and C65422 are AND gates, when the input signals at the A2 end of the logic gate C65411 and the A2 end of the logic gate C65422 are high-level signals, the signal output by the logic gate C65411 is determined based on the input signal at the A1 end, and the signal output by the logic gate C65422 is determined based on the input signal at the A1 end, so that the signals output by the logic gates C65411 and C65422 are determined based on the fourth input signal, and the signals output by the logic gates C65411 and C65422 are the sixth input sub-signals.

[0082] The signal output by the dft_mode port corresponds to the above-mentioned mode selection signal, and is used to control the ports of each selection unit 1232 outputting the signal, thereby realizing the control of the circuit mode. In the Dft mode, that is, the test mode, the selector U409 and the selector U4092 corresponding to the selection unit 1232 select the signal input from the I1 port for output, that is, the selector U409 selects the signal transmitted by the logic gate C65411 to the selector U409 for output, and the selector U4092 selects the signal transmitted by the logic gate C65422 to the selector U4092 for output, so that the signal output by the 7_p port and the 8_p port is the signal generated by the second test sub-circuit 12, which is the second input signal including two sixth input sub-signals. In this way, the signals output by the 7_p port and the 8_p port can be observed, because the signals output by the 7_p port and the 8_p port are the signals input to the output interface circuit, and thus through Figure 8 The circuit shown can make the signal input to the output interface circuit observable, so as to facilitate the subsequent determination of whether the logic of the output interface circuit is correct based on the signal input to the output interface circuit and the signal output from the output interface circuit.

[0083] In the functional mode, that is, the working mode, selectors U409 and U4092 select the signal input by the I0 port for output, so that the signal input to the output interface power supply is the signal output by the tx o[7:0] terminal of the Analog IP for normal operation, which facilitates the output interface circuit to perform subsequent processing based on the signal output by the Analog IP for normal operation, thereby ensuring the normal operation of the chip.

[0084] See also Fig. 9 , is Figure 8 Based on the circuit structure after passing through the scan chain, Fig. 9 For details, see the corresponding relationship between the components of the first test sub-circuit 11 and the second test sub-circuit 12 described in the above embodiment. Figure 8 The description is not repeated here. Fig. 9 If there is a connection point at the intersection of two lines, it means that the two lines are connected. If there is no connection point at the intersection of two lines, it means that the two lines are not connected. Fig. 9 Compared to Figure 8 The difference is Fig. 9 All triggers in are strung together, i.e. Fig. 9 The signal output from the Q end of obs_analog_input_reg is input to the SI end of obs_analog_output1_reg, and the signal output from the Q end of obs_analog_output1_reg is input to the SI end of obs_analog_output2_reg. The signal output from the scan enable port is used to control the opening and closing of the scan chain, that is, to control whether each trigger is registered and output based on the signal received from the SI port.

[0085] When testing the input interface circuit, each trigger serves as the third trigger 114 in the first test subcircuit 11. The fourth input sub-signal outputted from the n101 port, the n102 port, the n188 port and the n206 port is inputted into the second logic module 115 composed of the logic gates C951, C95, C951C and C654. Under the action of the enable signal outputted from the obs_en_tdr port, the logic gate C654 in the second logic module 115 transmits the generated third input signal to obs_analog_input_reg. Then, under the action of the third clock signal outputted from the clk port, the signal outputted from the Q end of obs_analog_input_reg is inputted into the SI end of obs_analog_output1_reg, and the signal outputted from the Q end of obs_analog_output1_reg is inputted into the SI end of obs_analog_output2_reg. The signal output by scan_enable is used to enable each trigger to store and serially transmit the value of the third input signal output by the logic gate C654 until the first output signal is output through the scan_channel_out port connected to the Q end of obs_analog_output2_reg.

[0086] When testing the output interface circuit, Fig. 9 Each trigger in the second test subcircuit 12 is used as the fifth trigger 122 in the second test subcircuit 12. The signal output by the scan_channel_in port is a test signal, and the test signal is transmitted to the SI terminal of obs_analog_input_reg as the input of obs_analog_input_reg. Under the action of the fifth clock signal output by the clk port, obs_analog_input_reg transmits the value of the received test signal to obs_analog_output1_reg, and obs_analog_output1_reg then transmits the value of the received test signal to obs_analog_output2_reg. obs_analog_output1_reg generates a fourth input signal based on the value of the received test signal, and inputs the fourth input signal to the A1 terminal of the logic gate C65422. obs_analog_output2_reg generates a fourth input signal based on the value of the received test signal, and inputs the fourth input signal to the A1 terminal of the logic gate C65411.

[0087] When the mode selection signal output by the dft_mode port indicates that the mode is the test mode, the selector U409 selects the signal transmitted by the logic gate C65411 to the selector U409 for output, and the selector U4092 selects the signal transmitted by the logic gate C65422 to the selector U4092 for output, so that the signal output by the 7_p port and the 8_p port is the signal generated by the second test sub-circuit 12, which is the second input signal including the two sixth input sub-signals. In this way, the signals output by the 7_p port and the 8_p port can be observed, because the signals output by the 7_p port and the 8_p port are the signals input to the output interface circuit, and thus through Figure 8 The circuit shown can make the signal input to the output interface circuit observable and controllable, so as to facilitate the subsequent determination of whether the logic of the output interface circuit is correct based on the signal input to the output interface circuit and the signal output from the output interface circuit.

[0088] Among them, the scan chain can be automatically completed by the DFT tool. Therefore, in the embodiment of the present application, a customized test circuit structure can be developed in advance, and then the DFT tool can automatically complete the scan chain and test tasks, thereby achieving the return of ensuring the testability of the peripheral interface logic of the analog circuit at the cost of a relatively small area and improving the test efficiency.

[0089] In summary, the first output signal generated by the first test subcircuit based on the first input signal output by the input interface circuit can be observed. Since the logic of the first test subcircuit generating the first output signal based on the first input signal is known, the value of the first input signal can be determined by observing the first output signal, so that the first input signal can be observed, and the conversion relationship between the input signal of the input interface circuit and the output first input signal can be tested, that is, the logic of the input interface circuit can be tested. The second input signal transmitted by the second test subcircuit to the output interface circuit can be observed, and the conversion relationship between the input signal and the output signal of the output interface circuit can be tested, that is, the logic of the output interface circuit can be tested. Therefore, the input interface circuit and the output interface circuit are tested through the first test subcircuit and the second test subcircuit, thereby improving the test coverage of the circuit.

[0090] In an exemplary embodiment, a display chip is provided, which includes an analog IP core, an input interface circuit for transmitting signals to the analog IP core, an output interface circuit for receiving signals output by the analog IP core, and a test circuit in any possible implementation method of the above-mentioned test circuit embodiment.

[0091] In an exemplary embodiment, a display is provided. The display includes the above-mentioned display chip, and the number of the display chip is one or more.

[0092] It should be noted that the information (including but not limited to user device information, user personal information, etc.), data (including but not limited to data used for analysis, stored data, displayed data, etc.) and signals involved in this application are all authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data must comply with the relevant laws, regulations and standards of relevant countries and regions. For example, the signals involved in this application are all obtained with full authorization.

[0093] It should be understood that the "plurality" mentioned in this article refers to two or more. "And / or" describes the association relationship of the associated objects, indicating that there can be three relationships. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the associated objects are in an "or" relationship.

[0094] The above description is only an exemplary embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the principles of the present application shall be included in the protection scope of the present application.

Claims

1. A test circuit, characterized in that: The test circuit comprises a first test subcircuit and a second test subcircuit; The first test subcircuit is used to receive a first input signal output by the input interface circuit, generate a first output signal based on the first input signal, and output the first output signal, wherein the first output signal and the input signal of the input interface circuit are used to determine whether the logic of the input interface circuit is correct, and the first input signal is determined based on the input signal of the input interface circuit; The second test subcircuit is used to obtain a second input signal and transmit the second input signal to the output interface circuit. The second input signal and the output signal of the output interface circuit are used to determine whether the logic of the output interface circuit is correct. The output signal of the output interface circuit is determined based on the second input signal.

2. The test circuit according to claim 1, characterized in that: The input interface circuit includes N input interface modules, the first input signal includes N first input sub-signals output by the N input interface modules, the first output signal includes N first output sub-signals, and N is a positive integer; the first test sub-circuit includes N first triggers; The i-th first trigger is used to receive the i-th first input sub-signal and the first clock signal output by the i-th input interface module, and when the value of the first clock signal changes from a first value to a second value, store the value of the i-th first input sub-signal; when the value of the first clock signal changes from the first value to the second value again, generate and output the i-th first output sub-signal that is the same as the value of the i-th first input sub-signal, where i is a positive integer less than or equal to N.

3. The test circuit according to claim 1, characterized in that: The input interface circuit includes N input interface modules, where N is a positive integer greater than 1, the first input signal includes N second input sub-signals output by the N input interface modules, the first output signal includes M second output sub-signals, where M is a positive integer less than N; the first test sub-circuit includes M second triggers and M first logic modules, and i is a positive integer less than or equal to M; The i-th first logic module is used to receive X second input sub-signals among the N second input sub-signals, and generate an i-th third input sub-signal according to the X second input sub-signals, where X is less than or equal to N; The i-th second trigger is used to receive the i-th third input sub-signal and the second clock signal, and when the value of the second clock signal changes from a first value to a second value, store the value of the i-th third input sub-signal; when the value of the second clock signal changes from the first value to the second value again, generate and output the i-th second output sub-signal that is the same as the value of the i-th third input sub-signal.

4. The test circuit according to claim 1, characterized in that: The input interface circuit includes N input interface modules, where N is a positive integer greater than 1, and the first input signal includes N fourth input sub-signals output by the N input interface modules; the first test sub-circuit includes L third triggers and a second logic module, where the L third triggers are connected in sequence, and L is a positive integer greater than 1 and less than or equal to N; The second logic module is used to receive the N fourth input sub-signals, and generate a third input signal corresponding to the N fourth input sub-signals according to the N fourth input sub-signals; The L third flip-flops are used to receive the third input signal and a third clock signal, and based on the third clock signal, store and serially transmit the value of the third input signal until the first output signal having the same value as the third input signal is generated.

5. The test circuit according to any one of claims 1 to 4, characterized in that: The output interface circuit includes A output interface modules, the second input signal includes A fifth input sub-signals, and A is a positive integer; the second test sub-circuit includes A fourth triggers; The i-th fourth trigger is used to receive a test signal and a fourth clock signal, and when the value of the fourth clock signal changes from a first value to a second value, the value of the test signal is stored; when the value of the fourth clock signal changes from the first value to the second value again, the i-th fifth input sub-signal with the same value as the test signal is generated and output to the i-th output interface module, where i is a positive integer less than or equal to A.

6. The test circuit according to any one of claims 1 to 4, characterized in that: The output interface circuit includes A output interface modules, the second input signal includes A sixth input sub-signals, and A is a positive integer; the second test sub-circuit includes a third logic module and B fifth triggers; The B fifth flip-flops are configured to receive a test signal and a fifth clock signal, generate a fourth input signal based on the fifth clock signal and the test signal, and transmit the fourth input signal to the third logic module; The third logic module is used to receive the fourth input signal and generate the A sixth input sub-signals according to the fourth input signal.

7. The test circuit according to claim 6, characterized in that: The third logic module includes a logic unit and A selection units; The logic unit is configured to receive the fourth input signal and generate an i-th sixth input sub-signal according to the fourth input signal; The i-th selection unit is used to receive the i-th sixth input sub-signal and a mode selection signal, and when the mode indicated by the mode selection signal is a test mode, output the i-th sixth input sub-signal to the i-th output interface module.

8. The test circuit according to claim 7, characterized in that: The output interface circuit and the second test sub-circuit are both connected to the analog intellectual property IP core. The i-th selection unit is also used to receive the output signal of the analog IP core, and when the mode indicated by the mode selection signal is the working mode, output the output signal of the analog IP core to the i-th output interface module.

9. A display chip, characterized in that: The display chip comprises an analog intellectual property IP core, an input interface circuit for transmitting signals to the analog IP core, an output interface circuit for receiving signals output by the analog IP core, and a test circuit as described in any one of claims 1-8.

10. A display, characterized in that: The display comprises the display chip as claimed in claim 9.

Images