Display device and method of driving same

Abstract

The present disclosure relates to a display device and a method of driving the display device. The display device includes: a display panel including a sub-pixel having a switching transistor and a sensing transistor; a driving circuit; a sensing circuit; and a timing controller, in which the sensing circuit is configured to: in a first sensing period in which a first reference voltage is applied through the reference line, acquire, as a first sampling value, a first sensing voltage charged in the reference line during a period in which the switching transistor and the sensing transistor are turned on; and acquiring, as a second sampling value, a first sensing voltage charged in the reference line during a period in which the switching transistor and the sensing transistor are turned off, and a timing controller preliminarily determining whether the display module has a defect based on a first difference between the first sampling value and the second sampling value.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Korean Patent Application No. 10-2023-0175489, filed on December 6, 2023, which is hereby incorporated by reference as if fully set forth herein. Technical Field

[0003] The present disclosure relates to a display device and a method of driving the display device. Background Art

[0004] With the development of information technology, the market for display devices as a communication medium between users and information is growing. Therefore, display devices such as light emitting display (LED) devices, quantum dot display (QDD) devices and liquid crystal display (LCD) devices are increasingly used.

[0005] The above-mentioned display device includes: a display panel including sub-pixels, a driver outputting a driving signal for driving the display panel, and a power supply for generating power to be supplied to the display panel or the driver.

[0006] In such a display device, when driving signals such as a scan signal and a data signal are supplied to sub-pixels formed in a display panel, selected sub-pixels transmit light or directly emit light, thereby displaying an image.

[0007] However, sub-pixels in a display device may have different or inconsistent characteristics and may degrade over time. Therefore, there is a need for a display device that can accurately determine defective sub-pixels and provide compensation as well as improve driving stability and reliability and extend the life of the display device. Summary of the invention

[0008] Accordingly, the present disclosure is directed to a display device and a method of driving the same that substantially obviate one or more problems due to limitations and disadvantages of the related art.

[0009] An object of the present disclosure is to improve driving stability and driving reliability of a display device, and to improve the lifespan of the display device.

[0010] Additional advantages, purposes and features of the present disclosure will be set forth in part in the following description, and in part will become apparent to those of ordinary skill in the art after examining the following, or may be learned from the practice of the present disclosure. The purposes and other advantages of the present disclosure may be realized and obtained through the structures particularly pointed out in the written description and claims and the drawings.

[0011] To achieve these objectives and other advantages and in accordance with the purposes of the present disclosure, as embodied and broadly described herein, a display device includes: a display panel including a sub-pixel having a switching transistor connected to a data line and a sensing transistor connected to a reference line; a driving circuit connected to the data line; a sensing circuit connected to the reference line; and a timing controller configured to control at least one of the driving circuit and the sensing circuit, wherein the sensing circuit is configured to: in a first sensing period in which a first reference voltage is applied through the reference line, obtain a first sensing voltage charged in the reference line during a period in which the switching transistor and the sensing transistor are turned on as a first sampling value, and obtain a first sensing voltage charged in the reference line during a period in which the switching transistor and the sensing transistor are turned off as a second sampling value, and the timing controller is configured to: preliminarily determine whether a display module including the display panel has a defect based on a first difference between the first sampling value and the second sampling value.

[0012] The sensing circuit can be configured to: in a second sensing period in which a second reference voltage different from the first reference voltage is applied through the reference line when the switching transistor and the sensing transistor are turned off, obtain the second sensing voltage charged in the reference line during the period in which the second reference voltage is applied as a third sampling value, and obtain the second sensing voltage charged in the reference line during the period in which the second reference voltage is not applied as a fourth sampling value.

[0013] The display device may further include a data driver including a driving circuit and a sensing circuit, and a timing controller for controlling the data driver may be configured to secondarily determine whether a display module including the display panel has a defect based on a second difference between the third sampling value and the fourth sampling value.

[0014] When there is a first difference between the first sampling value and the second sampling value, the second sensing period may be set; and when there is no first difference, the second sensing period may be skipped.

[0015] The first sensing period and the second sensing period may be included in a driving start period in which power is applied to the display panel.

[0016] The first sensing period and the second sensing period may be included in a driving termination period in which power applied to the display panel is cut off.

[0017] The first sensing period may be included in a driving start period in which power is applied to the display panel, and the second sensing period may be included in a driving end period in which power applied to the display panel is cut off.

[0018] In another aspect of the present disclosure, a method for driving a display device includes: applying a first reference voltage through a reference line, obtaining a first sensing voltage charged in the reference line during a period in which a switching transistor and a sensing transistor are turned on as a first sampling value, and obtaining a first sensing voltage charged in the reference line during a period in which the switching transistor and the sensing transistor are turned off as a second sampling value, and preliminarily determining whether a display module including a display panel has a defect based on a first difference between the first sampling value and the second sampling value.

[0019] The method may further include: applying a second reference voltage different from the first reference voltage through the reference line when the switching transistor and the sensing transistor are turned off, and obtaining a second sensing voltage charged in the reference line during a period in which the second reference voltage is applied as a third sampling value, and obtaining a second sensing voltage charged in the reference line during a period in which the second reference voltage is not applied as a fourth sampling value.

[0020] The method may further include secondarily determining whether a display module including the display panel has a defect based on a second difference between the third sampling value and the fourth sampling value.

[0021] It is to be understood that both the foregoing general description and the following detailed description of the present disclosure are exemplary and explanatory and are intended to provide further explanation of the disclosure as claimed. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The accompanying drawings are included to provide a further understanding of the present disclosure and are incorporated in and constitute a part of this application. These drawings illustrate embodiments of the present disclosure and together with the description serve to explain the principles of the present disclosure. In the drawings:

[0023] Figure 1 is a block diagram schematically showing a light emitting display device, Figure 2 It is schematically shown Figure 1 The sub-pixel configuration diagram shown in FIG. Figure 3 is a diagram schematically showing a pixel composed of sub-pixels;

[0024] Figure 4 and Figure 5 is a diagram showing a configuration of a gate-in-panel type gate driver, and Figure 6 is a diagram showing an example of arrangement of a gate-in-panel type gate driver;

[0025] Figure 7 is a diagram schematically showing a sub-pixel and a data driver according to a first example of an embodiment, Figure 8 is a diagram schematically showing a sub-pixel and a data driver according to a second example of an embodiment, and Fig. 9is a waveform diagram showing a sensing period and a display period according to an embodiment;

[0026] Fig.10 is a diagram showing some of the components included in the data driver according to an embodiment in more detail, and Fig.11 and Fig.12 A diagram showing a method of sensing a display panel according to an embodiment;

[0027] Fig.13 is a driving waveform diagram showing a first sensing step for determining whether there is a defect in a light emitting display device according to an embodiment, Fig.14 is a graph showing the difference between the sensed voltages sensed in the first sensing step, Fig.15 is a driving waveform diagram showing a second sensing step for determining whether there is a defect in a light emitting display device according to an embodiment, and Fig.16 and Fig.17 is a diagram showing the operation of the device performed in the second sensing step;

[0028] Fig.18 are diagrams showing defects that may occur in elements, signal lines, and power lines of a light emitting display device according to an embodiment, and Fig.19 is a diagram illustrating a defect that may occur in a signal line of a light emitting display device according to an embodiment; and

[0029] Fig. 20 is a block diagram showing an internal configuration of a data driver according to an embodiment, and Figure 21 to Figure 23 It is shown based on Fig. 20 Flow chart of a process in which a data driver processes a sensing voltage into a digital form that can be transmitted to a timing controller. DETAILED DESCRIPTION

[0030] The display device according to the present disclosure may be implemented as a television system, an image player, a personal computer (PC), a home theater, an automotive electrical device, a smart phone, etc., but is not limited thereto. The display device according to the present disclosure may be implemented as a light emitting display (LED) device, a quantum dot display (QDD) device, a liquid crystal display (LCD) device, etc. However, for ease of description, as an example, a light emitting display device based on direct light emission of an inorganic light emitting diode or an organic light emitting diode will be described below.

[0031] Figure 1 is a block diagram schematically showing a light emitting display device, Figure 2 It is schematically shown Figure 1 The sub-pixel configuration diagram shown in FIG. Figure 3 is a diagram schematically showing a pixel composed of sub-pixels.

[0032] like Figure 1 , Figure 2 and Figure 3 As shown, the light emitting display device may include an image provider 110, a timing controller 120, a gate driver 130, a data driver 140, a display panel 150, a power supply 180, and the like.

[0033] The image provider 110 (device (set) or host system) may output various driving signals, as well as an image data signal provided externally or an image data signal stored in an internal memory. The image provider 110 may supply the data signal and various driving signals to the timing controller 120 .

[0034] The timing controller 120 may output a gate timing control signal GDC for controlling the operation timing of the gate driver 130, a data timing control signal DDC for controlling the operation timing of the data driver 140, and various synchronization signals. The timing controller 120 may supply the data signal DATA supplied from the image provider 110 together with the data timing control signal DDC to the data driver 140. The timing controller 120 may be implemented in the form of an integrated circuit (IC) and mounted on a printed circuit board, but is not limited thereto.

[0035] The gate driver 130 may output a gate signal (or a gate voltage) in response to a gate timing control signal GDC supplied from the timing controller 120. The gate driver 130 may supply the gate signal to the sub-pixels included in the display panel 150 through the gate lines GL1 to GLm. The gate driver 130 may be implemented in the form of an IC or directly formed on the display panel 150 in a gate-in-panel structure, but is not limited thereto.

[0036] The data driver 140 may sample and latch the data signal DATA in response to the data timing control signal DDC supplied from the timing controller 120, convert the digital data signal into an analog data voltage based on the gamma reference voltage, and output the analog data voltage. The data driver 140 may supply data voltages to sub-pixels included in the display panel 150 through the data lines DL1 to DLn. The data driver 140 may be implemented in the form of an integrated circuit (IC) and mounted on the display panel 150 or on a printed circuit board, but is not limited thereto. In addition, one or more of the data driver 140, the gate driver 130, and the timing controller 120 may be collectively referred to as a controller (e.g., a controller connected to the display panel).

[0037] The power supply 180 may generate a first power at a high level and a second power at a low level based on an external input voltage supplied from the outside. The power supply 180 may output the first power through the first power line EVDD and output the second power through the second power line EVSS. The power supply 180 may generate and output voltages (e.g., a scan high voltage and a scan low voltage) required to drive the gate driver 130 and voltages (e.g., a drain voltage and a half-drain voltage) required to drive the data driver 140, as well as the first power and the second power.

[0038] The display panel 150 may display an image in response to a drive signal including a scan signal and a data voltage, a first power, and a second power. The sub-pixels of the display panel 150 may emit light directly (e.g., without a backlight unit). The display panel 150 may be manufactured based on a rigid or flexible substrate such as glass, silicon, polyimide, etc. For example, one sub-pixel SP may be connected to a first data line DL1, a first gate line GL1, a first power line EVDD, and a second power line EVSS and may include a pixel circuit including a switching transistor, a driving transistor, a capacitor, an organic light emitting diode, etc.

[0039] The sub-pixel SP used for the light-emitting display device directly emits light, and therefore its circuit configuration is complicated. In addition, there are various compensation circuits that compensate not only for the degradation of the organic light-emitting diode that emits light, but also for the degradation of the driving transistor that supplies the driving current required to drive the organic light-emitting diode. Therefore, the sub-pixel SP is simply shown in the form of a block.

[0040] The luminous sub-pixels may be composed of red pixels, green pixels, and blue pixels, or of red pixels, green pixels, blue pixels, and white pixels. For example, one pixel P may include a red sub-pixel SPR connected to a first data line DL1, a white sub-pixel SPW connected to a second data line DL2, a green sub-pixel SPG connected to a third data line DL3, and a blue sub-pixel SPB connected to a fourth data line DL4. Additionally, the red sub-pixel SPR, the white sub-pixel SPW, the green sub-pixel SPG, and the blue sub-pixel SPB may be connected to a first reference line VREF1 in common. The first reference line VREF1 may be used to sense degradation of an element included in one of the red sub-pixel SPR, the white sub-pixel SPW, the green sub-pixel SPG, and the blue sub-pixel SPB, which will be described below.

[0041] Meanwhile, the timing controller 120, the gate driver 130, and the data driver 140 have been described as separate components. However, depending on the implementation method of the light-emitting display device, one or more of the timing controller 120, the gate driver 130, and the data driver 140 may be integrated into a single IC. In addition, the timing controller 120, the gate driver 130, the data driver 140, the power supply 180, and the display panel 150 are components for displaying an image and may be defined as a display module.

[0042] In addition, as an example, a pixel P in which red subpixel SPR, white subpixel SPW, green subpixel SPG, and blue subpixel SPB are sequentially arranged has been illustrated. However, the arrangement order and direction of the subpixels may vary according to the implementation of the light emitting display device.

[0043] Figure 4 and Figure 5 is a diagram showing a configuration of a gate-in-panel type gate driver, and Figure 6 is a diagram showing an example of arrangement of a gate-in-panel type gate driver.

[0044] like Figure 4 As shown, the gate-in-panel type gate driver may include a shift register 131 and a level shifter 135. The level shifter 135 may generate a driving clock signal Clks and a start signal Vst based on signals and voltages output from the timing controller 120 and the power supply 180.

[0045] The shift register 131 operates based on the signals Clks and Vst output from the level shifter 135 and can output scanning signals Gate[1] to Gate[m] for turning on or off transistors formed in the display panel. The shift register 131 can be in the form of a thin film having an in-panel gate structure on the display panel.

[0046] like Figure 4 and Figure 5 As shown, unlike the shift register 131, the level shifter 135 may be independently formed in the form of an IC, or may be included in the power supply 180. However, this is only an example and is not limited thereto.

[0047] like Figure 6As shown, the shift registers 131a and 131b that output gate signals in the gate-in-panel type gate driver may be disposed in the non-display area NA of the display panel 150. For example, the shift registers 131a and 131b are disposed in the left non-display area and the right non-display area NA of the display panel 150, but the shift registers 131a and 131b may also be disposed in the upper non-display area and the lower non-display area NA of the display panel 150, or may be disposed in the display area AA of the display panel 150.

[0048] Figure 7 is a diagram schematically showing a sub-pixel and a data driver according to a first example of an embodiment, Figure 8 is a diagram schematically showing a sub-pixel and a data driver according to a second example of an embodiment, and Fig. 9 is a waveform diagram showing a sensing period and a display period.

[0049] like Figure 7 As shown, according to the first example, one sub-pixel SP may include a switching transistor SW, a driving transistor DT, a sensing transistor ST, a capacitor CST, and an organic light emitting diode OLED.

[0050] The driving transistor DT may include a gate electrode connected to a first electrode of the capacitor CST, a first electrode connected to a first power line EVDD, and a second electrode connected to an anode electrode of the organic light emitting diode OLED. The capacitor CST may have a first electrode connected to the gate electrode of the driving transistor DT and a second electrode connected to an anode electrode of the organic light emitting diode OLED. The organic light emitting diode OLED may have an anode connected to a second electrode of the driving transistor DT and a cathode connected to a second power line EVSS.

[0051] The switching transistor SW may include a gate electrode connected to a first scan line Gate1 included in the first gate line GL1, a first electrode connected to a first data line DL1, and a second electrode connected to a gate electrode of the driving transistor DT. The sensing transistor ST may include a gate electrode connected to a second scan line Gate2 included in the first gate line GL1, a first electrode connected to a first reference line VREF1, and a second electrode connected to an anode of the organic light emitting diode OLED.

[0052] The sensing transistor ST is a type of compensation circuit added to compensate for degradation (of threshold voltage, mobility, etc.) of the driving transistor DT or the organic light emitting diode OLED. The sensing transistor ST can implement physical threshold voltage sensing based on the source follower operation of the driving transistor DT. The sensing transistor ST can operate to obtain a sensing voltage through a sensing node defined between the driving transistor DT and the organic light emitting diode OLED.

[0053] According to an embodiment, the data driver 140 may include a driving circuit 141 for driving the sub-pixel SP and a sensing circuit 145 for sensing the sub-pixel SP. The driving circuit 141 may be connected to the first data line DL1 through the first data channel DCH1. The driving circuit 141 may output a data voltage Vdata for driving the sub-pixel SP through the first data channel DCH1.

[0054] The sensing circuit 145 may be connected to the first reference line VREF1 through the first sensing channel SCH1. The sensing circuit 145 may acquire the sensing voltage Vsen sensed from the sub-pixel SP through the first sensing channel SCH1. The sensing circuit 145 may acquire the sensing voltage Vsen based on a current sensing method or a voltage sensing method.

[0055] like Figure 8 As shown, according to the second example, the first gate line GL1 can be integrated into one. That is, unlike the first example, the first gate line GL1 may not be divided into the first scan line and the second scan line. In this case, the switching transistor SW and the sensing transistor ST are commonly connected to the first gate line GL1, and thus can be turned on or off at the same time.

[0056] like Fig. 9 As shown, according to the embodiment, when the light-emitting display device operates to drive the display panel, it can adopt driving modes corresponding to the first operating period PWR_ON (for example, when the display device is powered on), the second operating period DISPLAY and the third operating period PWR_OFF (for example, when the display device is powered off).

[0057] The first operation period PWR_ON may correspond to a driving start period in which power is applied to the display panel; the second operation period DISPLAY may correspond to a panel driving period in which operations such as displaying an image are performed after power is applied to the display panel; and the third operation period PWR_OFF may correspond to a driving end period in which the power applied to the display panel is cut off. At the same time, the third operation period PWR_OFF is the following period: the display panel is driven for a certain period of time while displaying black, so that the sensing operation of the display panel can be performed. That is, note that during the third operation period PWR_OFF, the power applied to the display panel, etc. is not completely cut off. In this way, for the user, the light-emitting display device is immediately turned off in response to the shutdown instruction, but when the sensing operation is performed before the final shutdown, the light-emitting display device displays black (nothing is displayed) but remains turned on.

[0058] The light-emitting display device according to the embodiment can sense the display panel in at least one of the first operation period PWR_ON, the second operation period DISPLAY and the third operation period PWR_OFF. For example, in the second operation period DISPLAY (for example, during the BLK period), the blank period BLK included in the vertical synchronization signal Vsync can be defined as the sensing period PSP, and the active period ACT included in the vertical synchronization signal Vsync can be defined as the display period DSP.

[0059] Fig.10 is a diagram showing some of the components included in the data driver according to an embodiment in more detail, and Fig.11 and Fig.12 A diagram showing a method of sensing a display panel according to an embodiment. Figure 7 The structure of the sub-pixel SP is shown.

[0060] like Fig.10 In the illustrated embodiment, the driving circuit 141 may include a digital-to-analog converter DAC to output a sensing data voltage, a black data voltage, or a display data voltage through the first data line DL1. The sensing circuit 145 may include a first voltage circuit SPRE, a second voltage circuit RPRE, a sampling circuit SAM, and an analog-to-digital converter ADC to output and sense a voltage through the first reference line VREF1.

[0061] The first voltage circuit SPRE and the second voltage circuit RPRE may perform a voltage output operation to initialize a node or circuit included in the subpixel SP, or charge the node or circuit to a specific voltage level. The first voltage circuit SPRE and the second voltage circuit RPRE may include a first reference voltage source VPRES and a second reference voltage source VPRER, respectively. The first voltage circuit SPRE may output a first reference voltage based on the first reference voltage source VPRES, and the second voltage circuit RPRE may output a second reference voltage based on the second reference voltage source VPRER. The first reference voltage may be set to a voltage lower than the second reference voltage.

[0062] The sampling circuit SAM may perform a sampling operation to acquire a sensing voltage through the first reference line VREF1. For example, the sampling circuit SAM may acquire a sensing voltage from a sensing capacitor PCAP formed on the first reference line VREF1 based on the sensing capacitor PCAP.

[0063] The analog-to-digital converter ADC can convert the analog sensing voltage obtained by the sampling circuit SAM into a digital sensing voltage and output the digital sensing voltage. For example, the analog-to-digital converter ADC can convert the analog sensing voltage charged in the sensing capacitor PCAP into a digital sensing voltage and output the digital sensing voltage. At the same time, the sensing voltage can be temporarily stored in the sampling capacitor (SCAP).

[0064] The timing controller 120 may receive a sensing voltage (sensing data value) from the sensing circuit 145. The timing controller 120 may determine whether the driving transistor DT or the organic light emitting diode OLED included in the sub-pixel SP is degraded based on the sensing voltage, and perform an operation to compensate for the degradation. In addition, the timing controller 120 may determine whether the light emitting display device has a defect based on the sensing voltage, and perform an operation to notify or remove the defect.

[0065] like Fig.11 As shown, according to the first example, the light emitting display device may perform a sequential sensing method in which sensing is performed from the first gate line GL1 to the Mth gate line GLm of the display panel 150. Fig.11 An example is shown in which sensing is sequentially performed starting from the first gate line GL1 which is the top of the display panel 150 , but sensing may start from the Mth gate line GLm which is the bottom of the display panel 150 .

[0066] like Fig.12 As shown, according to the second example, the light emitting display device may perform a random sensing method in which only the first gate line GLi of the display panel 150 is sensed. Fig.12 An example in which only the I-th gate line GLi, which is one of the specific gate lines, is sensed is shown, but the sensing target may be two or more gate lines.

[0067] Fig.13 is a driving waveform diagram showing a first sensing step for determining whether there is a defect in a light emitting display device according to an embodiment, Fig.14 is a graph showing the difference between the sensed voltages sensed in the first sensing step, Fig.15 is a driving waveform diagram showing a second sensing step for determining whether there is a defect in a light emitting display device according to an embodiment, and Fig.16 and Fig.17 is a diagram showing the device operation performed in the second sensing step.

[0068] like Fig. 9 , Fig.10 , Fig.13 and Fig.14As shown, the light emitting display device according to the embodiment may sense the display panel during at least one of the first operation period PWR_ON, the second operation period DISPLAY, and the third operation period PWR_OFF to determine whether there is a defect.

[0069] The operation of determining whether the light emitting display device is defective may be performed during the first operation period PWR_ON or the third operation period PWR_OFF excluding the second operation period DISPLAY so that the display panel is operable in a suitable period of time. Fig.13 The first sensing step shown and Fig.15 The second sensing step shown is used to perform the determination of whether there is a defect in the light emitting display device. However, the first sensing step may be performed in the first operation period PWR_ON, and the second sensing step may be performed in the third operation period PWR_OFF.

[0070] like Fig.10 and Fig.13 As shown, the first sensing step is the following step: based on a method of randomly sensing a specific gate line of the display panel or a method of sequentially sensing all gate lines of the display panel, it is preliminarily determined whether there is a defect between the display panel and the data driver driving the display panel. The first sensing step may include a (1-1)th sensing period P1, a (1-2)th sensing period P2, and a (1-3)th sensing period P3. In the following, the first sub-pixel is defined as a sensing target sub-pixel, and the operation performed in the first sensing step is described. Fig.13 The first sampling control signal Sam1 shown in FIG. 5 may include a (1-1)th sampling control signal Sam1 - 1 and a (1-2)th sampling control signal Sam1 - 2 .

[0071] During the (1-1)th sensing period P1, a first reference voltage may be applied to a first reference line VREF1 of a first sub-pixel included in the display panel. During the (1-1)th sensing period P1, a first voltage circuit SPRE including a first reference voltage source VPRES may be turned on in response to a first voltage circuit control signal VpreS at a high voltage. The first voltage circuit control signal VpreS may be applied as a high voltage during the (1-1)th sensing period P1 and then changed to a low voltage. During the (1-1)th sensing period P1, a sensing node of a driving transistor DT included in the first sub-pixel may be initialized by the first reference voltage.

[0072] During the (1-2)th sensing period P2, a sensing data voltage Sdata may be applied to the first data line DL1 of the first sub-pixel included in the display panel. During the (1-2)th sensing period P2, a first scanning signal and a first sensing signal Scan&Sense at a high voltage may be applied to the first scan line Gate1 and the second scan line Gate2. The switching transistor SW and the sensing transistor ST included in the first sub-pixel may be turned on by the first scanning signal and the first sensing signal Scan&Sense at a high voltage. The first scanning signal and the first sensing signal Scan&Sense may be applied as a high voltage during the (1-2)th sensing period P2 and then changed to a low voltage.

[0073] During the (1-2)th sensing period P2, the driving transistor DT of the first sub-pixel may perform a source follower operation by sensing the data voltage Sdata. Due to the source follower operation of the driving transistor DT, the first sensing voltage Vsen1 applied to the sensing node of the first sub-pixel drops to a first reference voltage level, then gradually increases, and saturates to a voltage level close to a threshold voltage.

[0074] During the (1-2)th sensing period P2, the sampling circuit SAM may be turned on in response to the temporarily generated (1-1)th sampling control signal Sam1-1. During the (1-2)th sensing period P2, the sampling circuit SAM may acquire the first sensing voltage Vsen1 applied to the sensing node of the first sub-pixel as the first sampling value a. The (1-1)th sampling control signal Sam1-1 may be applied as a high voltage in the latter stage of the (1-2)th sensing period P2, and then changed to a low voltage. The (1-1)th sampling control signal Sam1-1 may be temporarily generated between the moment when the first sensing voltage Vsen1 is saturated to be close to the threshold voltage of the driving transistor DT and the moment when the first scan signal and the first sensing signal Scan&Sense are changed to a low voltage.

[0075] During the (1-3)th sensing period P3, the sampling circuit SAM may be turned on in response to the temporarily generated (1-2)th sampling control signal Sam1-2. During the (1-3)th sensing period P3, the sampling circuit SAM may acquire the first sensing voltage Vsen1 applied to the sensing node of the first sub-pixel as the second sampling value b. The (1-2)th sampling control signal Sam1-2 may be applied as a high voltage during the (1-3)th sensing period P3 and then changed to a low voltage. The (1-2)th sampling control signal Sam1-2 may be temporarily generated after a certain delay time from the moment when the first scan signal and the first sensing signal Scan&Sense are changed to a low voltage.

[0076] The light-emitting display device according to the present embodiment can preliminarily determine whether there is a defect between the display panel and the data driver driving the display panel by comparing the first sampling value a with the second sampling value b. At this time, the determination can be made by the timing controller 120, which receives the first sampling value a and the second sampling value b of the first sensing voltage Vsen1 in digital form; or the determination can be made by the image provider, which is a device more advanced than the timing controller.

[0077] like Fig.14 As shown, if there is a first voltage difference ΔV between the first sampling value a and the second sampling value b obtained by the two sensing processes, the timing controller 120 can store the number of the gate line where the voltage difference ΔV occurs or the position of the sub-pixel where the voltage difference occurs in the memory. On the other hand, if there is no first voltage difference ΔV between the first sampling value a and the second sampling value b, the timing controller 120 can control the device so that the second sensing step to be performed subsequently is omitted (skipped).

[0078] According to an embodiment, if the first voltage difference ΔV between the first sampling value a and the second sampling value b is greater than a predetermined value, the timing controller 120 may store the number of the corresponding gate line or sub-pixel, which may indicate a defective threshold voltage of the driving transistor DT of the sub-pixel.

[0079] Therefore, the first sensing step can sense whether there is an inappropriate change in the threshold voltage of the driving transistor DT of a given sub-pixel. In addition, the first sensing step for sensing the threshold voltage of the driving transistor DT of a given sub-pixel can be performed during the first operating period PWR_ON (e.g., when the display device is powered on) or the third operating period PWR_OFF (e.g., when the display device is turned off).

[0080] like Fig.10 as well as Figures 15 to 17 As shown, the second sensing step is the step of re-sensing the gate line or sub-pixel where the voltage difference occurs in the first sensing step to secondarily determine whether there is a defect between the display panel and the data driver driving the display panel. The second sensing step may include a (2-1)th sensing period P1', a (2-2)th sensing period P2', and a (2-3)th sensing period P3'. Fig.15 The second sampling control signal Sam2 shown in FIG. 4 may include a (2-1)th sampling control signal Sam2-1 and a (2-2)th sampling control signal Sam2-2.

[0081] During the (2-1)th sensing period P1', the first scan line Gate1 and the second scan line Gate2 may be applied with a first scan signal and a first sensing signal Scan&Sense at a low voltage. The switching transistor SW and the sensing transistor ST included in the first subpixel may be turned off by the first scan signal and the first sensing signal Scan&Sense at a low voltage.

[0082] During the (2-2)th sensing period P2', a second reference voltage Vprer may be applied to a first reference line VREF1 of a first sub-pixel included in the display panel. During the (2-2)th sensing period P2', a second voltage circuit RPRE including a second reference voltage source VPRER may be turned on in response to a second voltage circuit control signal VpreR at a high voltage. The second voltage circuit control signal VpreR may be applied as a high voltage during the (2-2)th sensing period P2', and then changed to a low voltage. Since the switching transistor SW and the sensing transistor ST included in the first sub-pixel are turned off during the (2-2)th sensing period P2', the second reference voltage Vprer may be charged as a second sensing voltage Vsen2 in the sensing capacitor PCAP of the first reference line VREF1. At the same time, the second reference voltage Vprer may be changed to a higher level and output in order to improve the determination as to whether a defect exists. In other words, a first sensing operation can identify which subpixel or gate line may have a defect (e.g., during a power-on operation), and a second sensing operation can then be performed at a later time to retest that gate line or subpixel to more accurately measure whether it is indeed defective (e.g., during a power-off operation).

[0083] During the (2-2)th sensing period P2', the sampling circuit SAM may be turned on in response to the temporarily generated (2-1)th sampling control signal Sam2-1. During the (2-2)th sensing period P2', the sampling circuit SAM may acquire the second sensing voltage Vsen2 charged in the sensing capacitor PCAP of the first reference line VREF1 of the first sub-pixel as the third sampling value c. The (2-1)th sampling control signal Sam2-1 may be applied as a high voltage in the middle and late stages of the (2-2)th sensing period P2', and then changed to a low voltage.

[0084] During the (2-3)th sensing period P3', the sampling circuit SAM may be turned on in response to the temporarily generated (2-2)th sampling control signal Sam2-2. During the (2-3)th sensing period P3', the sampling circuit SAM may acquire the second sensing voltage Vsen2 charged in the sensing capacitor PCAP of the first reference line VREF1 of the first sub-pixel as the fourth sampling value d. The (2-2)th sampling control signal Sam2-2 may be applied as a high voltage in the (2-3)th sensing period P3' and then changed to a low voltage. The (2-2)th sampling control signal Sam2-2 may temporarily occur after a certain delay time from the moment when the second voltage circuit control signal VpreR changes to a low voltage.

[0085] The light-emitting display device according to the embodiment can secondarily determine whether there is a defect between the display panel and the data driver driving the display panel based on the second voltage difference between the third sampling value c and the fourth sampling value d. At this time, the determination can be made by the timing controller 120, which receives the third sampling value c and the fourth sampling value d as the second sensing voltage Vsen2 in digital form; or the determination can be made by the image provider, which is a device more advanced than the timing controller.

[0086] According to an embodiment, if the second voltage difference ΔV′ between the third sampling value c and the fourth sampling value d is greater than the second predetermined value, the timing controller 120 may accurately confirm that the corresponding gate line or sub-pixel is actually defective.

[0087] At the same time, the timing controller 120 can secondarily determine whether there is a defect between the display panel and the data driver driving the display panel by comparing the sampling value (or reference sampling value) obtained from the normal sub-pixel under the same driving condition with the third sampling value c or the fourth sampling value d without obtaining the second voltage difference. For example, any one of the third sampling value c or the fourth sampling value d can be compared with the sampling value of the normal sub-pixel (for example, the sub-pixel tested by the first sensing operation), and if the difference is greater than a predetermined value, the timing controller 120 can accurately confirm that the corresponding gate line or sub-pixel is actually defective.

[0088] According to an embodiment, if a sub-pixel is determined to be defective during one or both of the first sensing operation and the second sensing operation, a compensation voltage may be applied to the sub-pixel during the display period.

[0089] Fig.18 are diagrams showing defects that may occur in elements, signal lines, and power lines of a light emitting display device according to an embodiment, and Fig.19 is a diagram illustrating a defect that may occur in a signal line of a light emitting display device according to an embodiment.

[0090] Hereinafter, an example in which the timing controller determines whether there is a defect in the light emitting display device will be described.

[0091] like Fig.18 and Fig.19 As shown, the display panel and the data driver 140 may be electrically connected to each other through the pads PD1 and PD2 present in the pad area PDA (or the bonding area). In addition, there may be a power line in the pad area PDA as well as signal lines DL1 and VREF1 that electrically connect the display panel and the data driver 140. Therefore, if there is an open circuit defect (or bonding defect) caused by non-contact (non-contact due to cracks) between the same type of signal lines in the pad area PDA (or the bonding area), or there is a short circuit caused by foreign matter (PTC) contact (or moisture permeable contact) between different types of signal lines, the sensing range may be exceeded or an incorrect sensing value may be obtained due to current leakage, etc.

[0092] An example will be described below in which the timing controller according to the embodiment comprehensively determines whether there is a defect in the light-emitting display device based on the first voltage difference obtained in the first sensing step and the second voltage difference obtained in the second sensing step.

[0093] The timing controller 120 can determine whether there are defects in the elements included in the sub-pixel SP of the display panel (at least one of the switching transistor SW, the capacitor CST, the driving transistor DT, the organic light emitting diode OLED and the sensing transistor ST), the power line EVDD or EVSS of the display panel, and the signal lines DL1 and VREF1 located between the display panel and the data driver 140 based on the first voltage difference obtained in the first sensing step.

[0094] When the first voltage difference occurs, the elements included in the sensing target sub-pixel, and the data line and the reference line disposed between the sensing target sub-pixel and the data driver may be selected as a defect candidate group (e.g., possible defects that may be identified for later retesting). In addition, when the second voltage difference occurs, only the reference line disposed between the sensing target sub-pixel and the data driver may be selected as a defect candidate group.

[0095] As a first example, when only the first voltage difference occurs, the timing controller may determine at least one of the elements included in the sensing target sub-pixel and the data line and the reference line connected thereto as a defective factor. As a second example, when only the second voltage difference occurs, the timing controller may determine that only the reference line is a defective factor. As a third example, when the first voltage difference and the second voltage difference occur, the timing controller may determine all of the elements included in the sensing target sub-pixel and the data line and the reference line connected thereto as defective factors. Therefore, by using the first sensing operation and the second operation, the timing controller can determine which parts of the sub-pixel are defective with finer granularity.

[0096] In addition, the timing controller may include a lookup table in which defect determination data is stored, and the defect determination data can be used to determine whether a component included in the light-emitting display device is defective based on the first voltage difference and the second voltage difference. In this case, the timing controller can more easily determine which component has a defect based on an increase or decrease in the first voltage difference or the second voltage difference. Here, the defect determination data can be prepared by testing.

[0097] Fig. 20 is a block diagram showing an internal configuration of a data driver according to an embodiment, and Figure 21 to Figure 23 It is shown based on Fig. 20 Flow chart of a process in which a data driver processes a sensing voltage into a digital form that can be transmitted to a timing controller.

[0098] like Fig. 20 As shown, the data driver 140 according to the embodiment may include a driving circuit 141 and a sensing circuit 145. The driving circuit 141 may include a data receiving and recovery unit RX&CDR, a first data processing and logic unit S2P&PLOG, a shift register SRES, a first latch LAT1, a second latch LAT2, a digital-to-analog converter DAC, and an output circuit COC.

[0099] The data receiving and recovery unit RX&CDR may be used to receive and process packet data transmitted from the timing controller, and to recover an error in receiving a data signal or a clock signal included in the packet data if an error occurs.

[0100] The first data processing and logic unit S2P&PLOG may be used to convert a serial signal output from the data receiving and recovering unit RX&CDR into a parallel signal, and to output a control signal to be applied to the controller TCL and a data signal to be applied to the first latch LAT1, respectively.

[0101] The shift register SRES may be used to generate a signal so that a data signal applied to the first latch LAT1 or the second latch LAT2 is sampled and latched for one line.

[0102] The first latch LAT1 and the second latch LAT2 can be used to sample, latch and output the data signal output from the first data processing and logic unit S2P & PLOG for one line. Here, the second latch LAT2 can output the data signal based on the source output enable signal output from the first data processing and logic unit S2P & PLOG.

[0103] The digital-to-analog converter DAC may be used to convert the digital data signal output from the second latch LAT2 into an analog data voltage based on the gamma reference voltage and output the analog data voltage.

[0104] The output circuit COC may be used to perform additional modulation, for example, to amplify the data voltage output from the digital-to-analog converter DAC, and then output it through the data channel.

[0105] The sensing circuit 145 may include a controller TCL, a sensing processor CIA, a multiplexer MUX, a sampling and downscaling unit SAM&DS, a gain amplifier GA, an analog-to-digital converter ADC, a second data processor P2S, and a data transmitter TX.

[0106] The controller TCL may be used to control operation timings of elements included in the sensing circuit 145 based on control signals output from the first data processing and logic unit S2P&PLOG.

[0107] The sensing processor CIA can be used to obtain a sensing voltage through a sensing channel connected to a reference line, process the sensing voltage, and output the processed sensing voltage. The sensing processor CIA can be configured according to the sensing method of the sensing circuit 145. For example, the sensing processor CIA can be configured as a current integration circuit or a voltage sensing circuit.

[0108] The multiplexer MUX may be used to selectively output a first reference voltage and a second reference voltage applied from the outside. The multiplexer MUX may include a first voltage circuit that outputs the first reference voltage and a second voltage circuit that outputs the second reference voltage.

[0109] The sampling and shrinking unit SAM&DS can be used to sample the sensing voltage obtained by the sensing processor CIA and to shrink the sensing voltage. Fig. 20 and Fig.21As shown, the sampling and shrinking unit SAM&DS may sample the sensing voltage output from the sensing processor CIA in the form of an analog signal into a sampled analog signal, and shrink the sampled analog signal to output it as a sampled and shrunken analog signal.

[0110] The gain amplifier GA may be used to control the gain of the sensing voltage output from the sampling and shrinking unit SAM&DS.

[0111] The analog-to-digital converter ADC may be used to convert the analog sensing voltage output from the gain amplifier GA into a digital sensing voltage (sensing data value) and output the digital sensing voltage. Fig. 20 and Fig. 22 As shown, the analog-to-digital converter ADC can output the analog sensing voltage output from the sampling and shrinking unit SAM&DS as a digital sensing voltage. Fig. 22 The circuit blocks (SHA, MDAC, FLASH, digital correction logic), analog voltage and digital data in the analog-to-digital converter ADC are described to help understand the detailed circuit configuration and the conversion method based thereon, and therefore the detailed description will be omitted.

[0112] The second data processor P2S may be used to process the parallel digital sensing voltage output from the analog-to-digital converter ADC into a serial digital sensing voltage. Fig. 20 and Fig.23 As shown, the second data processor P2S may process the parallel digital sensing voltage Vsen (parallel data) output from the analog-to-digital converter ADC into a serial digital sensing voltage Vsen (serial data).

[0113] exist Fig. 22 In the example, "DOUT" is the output terminal of the digital correction logic. In addition, "C1023", "C0", "C511" and 0.4V, 0.9V, 1.4V are examples of digital data and analog voltage, respectively. In addition, SHA is a sample-and-hold circuit, and MDAC is a digital-to-analog converter.

[0114] The data transmitter TX may be used to send the serial digital sensing voltage output from the second data processor P2S to the timing controller. Fig. 20 and Fig.23 As shown, the data transmitter TX can configure the digital sensing voltage Vsen (parallel data) output from the second data processor P2S in a bus low voltage differential signaling transmission format and send it to the timing controller. Fig.23 The transmission format in is used to facilitate the understanding of data packets, so its detailed description will be omitted.

[0115] exist Fig.23, "SEN 0", "SEN 1", "SEN 2", "SEN N-3", "SEN N-2", "SEN N-1" are examples of sensing data. In addition, "B-LVDS TX format" is an example of a data transmission format. In addition, "CH1.D0-D9", "CH2.D0-D9", "CH240.D0-D9" are examples of data for each channel.

[0116] As described above, the present disclosure has the effect of improving the life of a display device by compensating for elements included in the sub-pixels that constitute a display panel, and improving the driving stability and driving reliability of the display device by detecting whether there are defects in the overall display device including a display panel and a driver that drives the display panel.

[0117] It will be apparent to those skilled in the art that various modifications and variations may be made in the present disclosure without departing from the spirit or scope of the present disclosure. Therefore, the present disclosure is intended to cover modifications and variations of the present disclosure as long as they are within the scope of the appended claims and their equivalents.

Claims

1. A display device, comprising: a display panel including a sub-pixel having a switching transistor connected to a data line and a sensing transistor connected to a reference line; a driving circuit connected to the data line; a sensing circuit connected to the reference line; as well as a timing controller configured to control at least one of the driving circuit and the sensing circuit, The sensing circuit is configured to: in a first sensing period in which a first reference voltage is applied through the reference line, obtain a first sensing voltage charged in the reference line during a period in which the switch transistor and the sensing transistor are turned on as a first sampling value, and obtain a first sensing voltage charged in the reference line during a period in which the switch transistor and the sensing transistor are turned off as a second sampling value, and The timing controller is configured to preliminarily determine whether a display module including the display panel has a defect based on a first difference between the first sampling value and the second sampling value.

2. The display device according to claim 1, wherein: The sensing circuit is configured to: in a second sensing period in which a second reference voltage different from the first reference voltage is applied through the reference line when the switching transistor and the sensing transistor are turned off, obtain a second sensing voltage charged in the reference line during the period in which the second reference voltage is applied as a third sampling value, and obtain a second sensing voltage charged in the reference line during the period in which the second reference voltage is not applied as a fourth sampling value.

3. The display device according to claim 2, further comprising a data driver, the data driver comprising the driving circuit and the sensing circuit, in, The timing controller for controlling the data driver is configured to secondarily determine whether the display module including the display panel has a defect based on a second difference between the third sampling value and the fourth sampling value.

4. The display device according to claim 2, wherein: When the first difference exists between the first sampling value and the second sampling value, the second sensing period is set; and when the first difference does not exist, the second sensing period is skipped.

5. The display device according to claim 2, wherein: The first sensing period and the second sensing period are included in a driving start period in which power is applied to the display panel.

6. The display device according to claim 2, wherein: The first sensing period and the second sensing period are included in a driving termination period in which power applied to the display panel is cut off.

7. The display device according to claim 2, wherein: The first sensing period is included in a driving start period in which power is applied to the display panel, and the second sensing period is included in a driving end period in which power applied to the display panel is cut off.

8. A method for driving a display device, the display device comprising: a display panel including a sub-pixel having a switching transistor connected to a data line and a sensing transistor connected to a reference line; a driving circuit connected to the data line; a sensing circuit connected to the reference line; and a timing controller configured to control at least one of the driving circuit and the sensing circuit, the method comprising: applying a first reference voltage through the reference line; Acquire a first sensing voltage charged in the reference line during a period in which the switch transistor and the sensing transistor are turned on as a first sampling value, and acquire a first sensing voltage charged in the reference line during a period in which the switch transistor and the sensing transistor are turned off as a second sampling value; and Based on a first difference between the first sampling value and the second sampling value, it is preliminarily determined whether a display module including the display panel has a defect.

9. The method according to claim 8, further comprising: applying a second reference voltage different from the first reference voltage through the reference line when the switch transistor and the sensing transistor are turned off; as well as A second sensing voltage charged in the reference line during a period in which the second reference voltage is applied is acquired as a third sampling value, and a second sensing voltage charged in the reference line during a period in which the second reference voltage is not applied is acquired as a fourth sampling value.

10. The method according to claim 9, further comprising: Based on a second difference between the third sampling value and the fourth sampling value, it is secondarily determined whether the display module including the display panel has a defect.

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