Display driving device, display device including the same, and display driving method

Abstract

The invention relates to a display driving device, a display device including the same and a display driving method. The invention discloses a display driving device, a display device and a display driving method. The display driving apparatus may include: a control circuit configured to control a driving circuit configured to drive a display panel pixel; a power supply circuit configured to supply power to the drive circuit and the control circuit in response to an input voltage; a sensing circuit configured to sense a peak current on a power supply path through which the input voltage is applied; and a power supply control circuit configured to increase a time interval between the power supply activation signals input to the power supply circuit. Accordingly, it is possible to reduce electromagnetic interference (EMI) and minimize an increase in noise caused by overlapping noise.

Description

Technical Field

[0001] The present disclosure relates to a display driving device, a display device including the display driving device, and a display driving method, such as but not limited to a display driving device including a high-efficiency and low-reflection electrode structure and a display device including the display driving device. Background Art

[0002] A display device is a device for displaying one or more images on one screen. The display device may include a plurality of display panels and perform a multi-display function capable of displaying images on a plurality of screens. Examples of such a multi-display system include a tiled display device or a video wall system in which a plurality of display panels are connected to form a large screen.

[0003] The multi-display system may include an external power supply device for supplying power to multiple display modules and a display driving device for driving the multiple display modules. When a signal generated by the external power supply device is transmitted to the multiple display driving devices, a peak value of a specific physical characteristic is generated, thereby causing electromagnetic interference (EMI).

[0004] Recently, EMI regulations for home appliances and communication devices are being tightened. As for display devices, various EMI reduction technologies are being applied to meet EMI standards.

[0005] The description provided in this discussion of the related art section should not be assumed to be prior art simply because it is mentioned in or associated with the description of the related art section. The discussion of the related art section may include information that describes one or more aspects of the subject technology, and the description of this section does not limit the present disclosure. Summary of the invention

[0006] Therefore, the inventors of the present disclosure recognized the above-mentioned limitations or problems and other limitations associated with the prior art, and conducted various experiments to realize a display device including a high-efficiency and low-reflection electrode structure.

[0007] The present disclosure is intended to achieve the above-mentioned needs and / or solve the problems of the related art.

[0008] The objects of the present disclosure are not limited to the above objects, and other objects not mentioned will be clearly understood by those skilled in the art from the following description.

[0009] According to the present disclosure, a display driving device includes: a first power supply circuit, which is configured to supply power to a first driving circuit and a first control circuit upon receiving a first power activation signal, the first driving circuit is configured to drive pixels of a first display panel, and the first control circuit is configured to control the first driving circuit; a second power supply circuit, which is configured to supply power to a second driving circuit and a second control circuit upon receiving a second power activation signal, the second driving circuit is configured to drive pixels of a second display panel, and the second control circuit is configured to control the second driving circuit; a first sensing circuit, which is configured to sense a first current input to the first power supply circuit; a second sensing circuit, which is configured to sense a second current input to the second power supply circuit; and a power control circuit, which is configured to increase the time interval between the first power activation signal and the second power activation signal when at least one of the first current and the second current is greater than or equal to a preset threshold value.

[0010] According to the present disclosure, a display device includes: a main power supply circuit; a plurality of display panels; a plurality of power supply circuits configured to supply power to a plurality of drive circuits and a plurality of control circuits, wherein the plurality of drive circuits are configured to respectively drive pixels of the plurality of display panels, and the plurality of control circuits are configured to respectively control the plurality of drive circuits; a plurality of sensing circuits, each sensing circuit being configured to sense a current input to one of the plurality of power supply circuits; and a power supply control circuit configured to increase at least one time interval among a plurality of power supply activation signals input to the plurality of power supply circuits when at least one of the plurality of currents is greater than or equal to a preset threshold value.

[0011] The display device according to the present disclosure includes: an external power supply device, which includes a main power supply circuit configured to output a voltage; and a display driving device, which is operated by receiving a voltage from the external power supply device, wherein the display driving device includes: a first power supply circuit, which is configured to supply power to a first driving circuit and a first control circuit upon receiving a first power activation signal, the first driving circuit being configured to drive pixels of a first display panel, and the first control circuit being configured to control the first driving circuit; and a second power supply circuit, which is configured to supply power to a second driving circuit and a second control circuit upon receiving a second power activation signal, the second driving circuit The circuit is configured to drive pixels of a second display panel, the second control circuit is configured to control the second driving circuit, and the external power supply device includes: a first sensing circuit, which is arranged between the main power supply circuit and the first power supply circuit and is configured to sense a first current input to the first power supply circuit; a second sensing circuit, which is arranged between the main power supply circuit and the second power supply circuit and is configured to sense a second current input to the second power supply circuit; and a power control circuit, which is configured to increase the time interval between the first power activation signal and the second power activation signal when at least one of the first current and the second current is greater than or equal to a preset threshold.

[0012] According to the present disclosure, a display device includes: an external power supply device, which includes a main power supply circuit configured to output a voltage; and a display driving device, which operates by receiving a voltage from the external power supply device, wherein the display driving device includes: a first power supply circuit, which is configured to supply power to a first driving circuit and a first control circuit upon receiving a first power activation signal, the first driving circuit being configured to drive pixels of a first display panel, and the first control circuit being configured to control the first driving circuit; and a second power supply circuit, which is configured to supply power to a second driving circuit and a second control circuit upon receiving a second power activation signal, the second driving circuit being configured to drive pixels of a second display panel, and the second control circuit being configured to control the second driving circuit; a first sensing circuit, which is configured to sense a first current input to the first power supply circuit; a second sensing circuit, which is configured to sense a second current input to the second power supply circuit; and a power control circuit, which is configured to increase the time interval between the first power activation signal and the second power activation signal when at least one of the first current and the second current is greater than or equal to a preset threshold.

[0013] The display driving method according to the present disclosure includes the following steps: a power control circuit receives a timing signal synchronized with an image signal and generates a sensing signal; a first sensing circuit senses a first current in response to the sensing signal; a second sensing circuit senses a second current in response to the sensing signal; a first control circuit controls a first driving circuit upon receiving a first power activation signal; a second control circuit controls a second driving circuit upon receiving a second power activation signal; and when at least one of the first current and the second current is greater than or equal to a preset threshold, increases the time interval between the first power activation signal and the second power activation signal.

[0014] The effects according to the present disclosure are not limited to the contents exemplified above, and more various effects are included in the present disclosure.

[0015] It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the inventive concepts as claimed. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The above and other aspects, features and other advantages of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0017] Figure 1 is a schematic perspective view of a display device according to an embodiment of the present disclosure.

[0018] Figure 2 FIG. 1 is a schematic diagram showing a display module according to an embodiment of the present disclosure.

[0019] Figure 3 is a detailed view showing a display module according to one embodiment of the present disclosure.

[0020] Figure 4 is a view showing a configuration and a connection relationship of a display device according to a first exemplary embodiment of the present disclosure.

[0021] Figure 5 2 is a view showing a configuration and a connection relationship of a display device according to a second exemplary embodiment of the present disclosure.

[0022] Figure 6 is a view showing a configuration and connection relationship of a display device according to a third exemplary embodiment of the present disclosure.

[0023] Figure 7 is a view showing a configuration and a connection relationship of a display device according to a fourth exemplary embodiment of the present disclosure.

[0024] Figure 8is a view showing a configuration and connection relationship of a display device according to a fifth exemplary embodiment of the present disclosure.

[0025] Fig. 9 : is a schematic plan view showing the configuration and connection relationship of a display device according to a fifth exemplary embodiment of the present disclosure.

[0026] Fig.10 is a schematic diagram illustrating a configuration and a connection relationship between two display driving devices according to a sixth exemplary embodiment of the present disclosure.

[0027] Fig.11 is a schematic diagram illustrating a configuration and a connection relationship between an external power supply device and a display driving device according to a seventh exemplary embodiment of the present disclosure.

[0028] Fig.12 is a view showing a driving period of a display device.

[0029] Fig.13 is a diagram showing the timing of power activation signals sent to each power circuit.

[0030] Fig.14 is a diagram showing the peak current of the main power supply circuit and the effect of reducing the peak current.

[0031] Fig.15 2 is a diagram showing noise superposition of a display driving device and an effect of reducing the noise superposition.

[0032] Fig.16 is a diagram illustrating generation and transmission of a sensing signal.

[0033] Fig.17 is a waveform diagram showing a timing signal synchronized with an image signal.

[0034] Fig.18 is a waveform diagram showing a process of determining a sensing frequency using an input / output signal of a level shifter and a gate timing control signal.

[0035] Fig.19 is a waveform diagram showing a process of determining a sensing frequency using a vertical synchronization signal.

[0036] Fig. 20 is a waveform diagram showing a process of determining a sensing frequency using a horizontal synchronization signal.

[0037] Fig.21 is a waveform diagram illustrating a process of determining a sensing frequency using a data enable signal.

[0038] Fig. 22 is a waveform diagram showing a process of determining a sensing frequency using a dot clock signal.

[0039] Fig.23 is a diagram illustrating functions and operations of components of a display driving device.

[0040] Fig.24 and Fig.25 is a diagram showing various examples of time intervals between power activation signals.

[0041] Fig.26 is a table of simulation results used to determine the optimal time interval value range for the power supply activation signal.

[0042] Fig. 27 2 is a diagram showing the connection relationship between the power supply control circuit and the display driving device.

[0043] Figure 28 to Figure 31 are views showing various examples of waveforms of pulse width modulation signals generated by reflecting an increased time interval.

[0044] Fig.32 is a flowchart illustrating a display driving method according to an exemplary embodiment of the present disclosure.

[0045] Throughout the drawings and detailed description, unless otherwise described, the same drawing reference numerals should be understood to refer to the same elements, features, and structures.The size, length, thickness, and depiction of layers, regions, and elements may be exaggerated for clarity, illustration, and convenience. DETAILED DESCRIPTION

[0046] Reference will now be made in detail to embodiments of the present disclosure, examples of which may be illustrated in the accompanying drawings. The progression of processing steps and / or operations described are examples; however, the order of steps and / or operations is not limited to the order set forth herein and may be varied as is known in the art, except that the steps and / or operations must occur in a particular order. The names of the various elements used in the following description are selected solely for ease of writing the specification and therefore may differ from those used in actual products.

[0047] The advantages and features of the present disclosure and methods for achieving them will become clear with reference to the exemplary embodiments described in detail below in conjunction with the accompanying drawings. The present disclosure is not limited to the exemplary embodiments disclosed below, but can be implemented in various different forms, which are provided only to make the disclosure of the present disclosure complete and to fully convey the scope of the present disclosure to those skilled in the art, and the present disclosure is limited only by the scope of the appended claims.

[0048] The shapes, sizes, ratios, angles, quantities, etc. shown in the accompanying drawings for describing the exemplary embodiments of the present disclosure are merely examples, and the present disclosure is not limited thereto. Throughout the specification, the same reference numerals generally represent the same elements. In addition, in the following description of the present disclosure, the detailed description of the related known technologies may be omitted to avoid unnecessarily obscuring the subject matter of the present disclosure. Terms such as "including", "having", "constituting", etc. used herein are generally intended to allow the addition of other components unless these terms are used together with the term "only". Unless otherwise expressly stated, any reference to the singular may include the plural. Any implementation described herein as an "example" is not necessarily to be interpreted as being preferred or advantageous relative to other implementations.

[0049] In describing the present invention, when it is determined that a detailed description of related known technologies may unnecessarily obscure the gist of the present invention, the detailed description thereof will be omitted or given in brief.

[0050] When the terms "including," "comprising," "having," and "consisting of" described in the present disclosure are used, other components may be added unless "only" is used. When a component is expressed in the singular, it may be construed as plural components unless explicitly stated otherwise.

[0051] When describing the positional relationship and interconnection relationship between two components (such as "on", "over", "under", "below", "beside", "connected or coupled", "crossed or intersected", etc.), unless the term "immediately next to" or "directly" is described, one or more other components may be interposed between the components. For example, when one element or layer is disposed "on" another element or layer, a third layer or element may be interposed between them.

[0052] When the terms "after," "subsequently," "then," "before," etc. are used to describe a temporal relationship, non-sequential cases may be included unless the terms "immediately after" or "directly" are used.

[0053] Although terms such as "first," "second," "A," "B," "(a)," "(b)," etc. may be used to distinguish components, the function or structure of the components is not limited by the ordinal number added to the front of the components or the component names.

[0054] The following exemplary embodiments may be partially or completely connected or combined, and may be interconnected and driven by various technologies. These embodiments may be implemented independently of each other or together in an associated relationship.

[0055] The term "at least one" should be understood to include any and all combinations of one or more associated listed items. For example, the meaning of "at least one of the first item, the second item, and the third item" covers the combination of all three listed items, the combination of any two of the three elements, and each individual element (the first element, the second element, or the third element).

[0056] In the description of the embodiments, when a structure is described as being located "on or above" or "below or below" another structure, the description should be understood to include a case where the structures are in contact with each other and a case where a third structure is disposed therebetween. The size and thickness of each element shown in the drawings may be given only for the convenience of description, and the embodiments of the present disclosure may not be limited thereto.

[0057] The features of the various embodiments of the present disclosure may be partially or entirely interconnected or combined, and as those skilled in the art can fully understand, may interoperate and technically drive in various ways. The embodiments of the present disclosure may be implemented independently of each other, or may be implemented together in a mutually dependent relationship.

[0058] In addition, the terms (including technical terms and scientific terms) used in the embodiments of the present disclosure may be interpreted as meanings that can be generally understood by technicians in the field to which the present disclosure belongs, unless explicitly defined and described specifically, and the meanings of general terms (for example, terms defined in dictionaries) may be interpreted in consideration of the contextual meaning of the relevant technology.

[0059] In addition, when any dimension, relative size, etc. is mentioned, it should be considered that even if no relevant description is specified, the numerical value or corresponding information (e.g., level, range, etc.) of the element or feature also includes the tolerance or error range that may be caused by various factors (e.g., process factors, internal or external influences, noise, etc.). In addition, the term "may" fully encompasses all meanings of the term "can".

[0060] Hereinafter, exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. For ease of description, the proportion of each element shown in the accompanying drawings is different from the actual proportion, and therefore is not limited to the proportion shown in the accompanying drawings.

[0061] Embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0062] Figure 1 is a schematic perspective view of a display device according to an embodiment of the present disclosure.

[0063] Reference Figure 1, a display device DD according to an exemplary embodiment of the present disclosure may include a plurality of display panels PN arranged on an XY plane. Each display panel PN may reproduce an input image. The display device DD may be connected in units of display panels PN. In the accompanying drawings, for convenience of description, four display panels PN are connected, but similarly, additional display panels extending along the X-axis direction and / or the Y-axis direction may be connected to form a large-screen display device DD. The display device DD may have a honeycomb structure or a delta structure, but is not limited thereto.

[0064] One or more pixels P may be provided on the display panel PN. The pixels P may be provided along a plurality of row lines and a plurality of column lines. The pixel P may include a plurality of sub-pixels SP for emitting light of different colors. The sub-pixel SP may include a light-emitting element and a pixel circuit, and may emit light independently by a power supply provided from the outside. The sub-pixel SP may be any one selected from a group including a plurality of sub-pixels SP emitting light of different colors such as a red sub-pixel, a blue sub-pixel, and a green sub-pixel, but is not limited thereto. The light-emitting element may be an organic light-emitting diode (OLED), a quantum dot light-emitting diode, or an inorganic light-emitting diode (e.g., a micro light-emitting diode (LED) or a nano-LED), etc., but is not limited thereto.

[0065] Figure 2 is a schematic diagram illustrating a display module according to an exemplary embodiment of the present disclosure. Figure 3 is a detailed view showing a display module according to an exemplary embodiment of the present disclosure.

[0066] Reference Figure 2 and Figure 3 , the display module DM may include a display panel PN on which pixels are arranged, a driving circuit DRC for driving the pixels P of the display panel PN, a control circuit CC for controlling the driving circuit DRC, and a power supply circuit PC for supplying power to the pixels P, the driving circuit DRC, the control circuit CC, etc. arranged on the display panel. The driving circuit DRC may include a data driver DDR, a gate driver GDR, and a pixel circuit embedded in each pixel P, but is not limited thereto. The control circuit CC may include a level shifter (not shown) and a timing controller TC, but is not limited thereto. The power supply circuit PC may include a power supply PS, but is not limited thereto.

[0067] Each pixel P of the display panel PN can receive a data voltage supplied by a data driver DDR, a gate signal supplied by a gate driver GDR, a high potential voltage Vddel and a low potential voltage Vssel supplied by a power supply PS, etc., and display an input image. In addition to receiving a high potential voltage Vddel and a low potential voltage Vssel, the display panel PN can also receive an initialization voltage Vini. The initialization voltage Vini can be supplied by a power supply PS or a data driver DDR. Each pixel P may include a plurality of sub-pixels for emitting light of different colors to achieve color. Each sub-pixel may include a light-emitting element and a pixel circuit, the light-emitting element being used to emit light corresponding to the pixel data of the input image with a brightness, and the pixel circuit being used to drive the light-emitting element. The pixel circuit may include a pixel driver.

[0068] The level shifter (not shown) may generate and output a plurality of clock signals based on the signal output from the timing controller TC. The plurality of clock signals may be generated and output in the form of N phases with different phases, such as 2 phases, 4 phases, or 8 phases (N is an integer of 2 or more).

[0069] The timing controller TC may receive pixel data DATA of an input image and timing signals such as signals Hsync, Vsync, MCLK, and DE synchronized with the pixel data DATA from an external host system, but is not limited thereto. As an example, the timing signal may include a data enable signal DE, a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a dot clock signal MCLK, etc., but is not limited thereto. The timing controller TC may output a gate timing control signal GTCS for controlling the operation timing of the gate driver GDR, a data timing control signal DTCS for controlling the operation timing of the data driver DDR, etc. based on the timing signal, but is not limited thereto. The timing controller TC may be mounted on a board of a display driving device in the form of an integrated circuit (IC), but is not limited thereto.

[0070] The data driver DDR can sample and latch the pixel data DATA received from the timing controller TC in the form of a digital signal using the clock of the data timing control signal DTCS, and convert the serial signal system of the input signal including the pixel data into a parallel signal system. Subsequently, the data driver DDR can convert the latched data into a gamma compensation voltage for each grayscale and output the data voltage of the pixel data. The data driver DDR can be implemented in the form of an IC and electrically connected to the data line of the display module.

[0071] The gate driver GDR may output a gate signal, etc. in response to a gate timing control signal GTCS from a timing controller TC. The gate driver GDR may output a gate signal, etc. through a gate line. The gate driver GDR may be formed in the form of an IC or formed on a display panel (PN) using an in-panel gate method (a method of forming a transistor on a substrate using a thin film process). The gate driver GDR may include a plurality of transistors, capacitors, etc. The gate driver GDR may be disposed in a non-display area of ​​the display panel PN. Alternatively, at least some of the gate drivers GDR may be disposed in a display area of ​​the display panel PN.

[0072] The power supply PS may be electrically connected to the display panel PN through a first power line DPPLDD and a second power line DPPLSS. The power supply PS may output a high potential voltage Vddel, a low potential voltage Vssel, etc. Each of the high potential voltage Vddel and the low potential voltage Vssel output from the power supply PS may be supplied to the display panel PN through a first power line DPPLDD and a second power line DPPLSS. The power supply PS may be formed in the form of an IC, but is not limited thereto.

[0073] The power supply PS may be electrically connected to the above-mentioned pixel circuit through the first power line DPPLDD and the second power line DPPLSS. The power supply PS may be electrically connected to the data driver DDR through the third power line DDRPL. The power supply PS may be electrically connected to the gate driver GDR through the fourth power line GDRPL. The power supply PS may be electrically connected to the timing controller TC through the fifth power line TCPL, but is not limited thereto.

[0074] The display driving device according to the present disclosure may include a driving circuit, a control circuit, a power supply circuit, etc. for driving the display device, and these circuits may be mounted on a board in the display driving device in the form of an IC. However, this is exemplary, and at least some components of the display driving device may be integrated into the display panel PN.

[0075] Figure 4 : is a view showing the configuration and connection relationship of the display device according to the first embodiment of the present disclosure. Figure 5 2 is a view showing a configuration and connection relationship of a display device according to a second embodiment of the present disclosure. Figure 6 is a view showing a configuration and connection relationship of a display device according to a third embodiment of the present disclosure. Figure 7 Components performing substantially the same functions between the embodiments are denoted by the same reference numerals, and repeated descriptions thereof will be omitted or briefly given.

[0076] Reference Figure 4 In one embodiment, the display device may include a first display driving device DRD1 and a second display driving device DRD2, but is not limited thereto. In addition, the display device may further include an external power supply device EPSD. The first display driving device DRD1 and the second display driving device DRD2 may drive the first display module and the second display module, respectively.

[0077] The external power supply device EPSD may include a main power supply circuit MPSC.

[0078] The first display driving device DRD1 may include a first driving circuit DRC1 for driving pixels of a first display panel provided in a first display module, a first control circuit CC1 for controlling the first driving circuit DRC1, a first power supply circuit PC1 for supplying power to the first driving circuit DRC1 and the first control circuit CC1, a first sensing circuit SC1 for sensing voltage and / or current, etc., but is not limited thereto. As an example, more or fewer elements may be included in the first display driving device DRD1. Alternatively, the first display driving device DRD1 may further include a power control circuit PCC for generating a first power activation signal. The first power activation signal may be supplied from the power control circuit PCC to the first power circuit PC1 to activate the generation of a first pulse width modulation (PWM) signal in the first power circuit PC1. A sensing signal may be supplied from the power control circuit PCC to the first sensing circuit SC1. The first PWM signal may suppress fluctuations in a constant voltage level output from the first power circuit PC1.

[0079] The first driving circuit DRC1 may include the above-mentioned data driver and gate driver, but is not limited thereto. The first control circuit may include the above-mentioned timing controller, but is not limited thereto.

[0080] The first power circuit PC1 may be electrically connected to the main power supply circuit MPSC through the first power cables 1111 and 1112. Specifically, the first power circuit PC1 may be electrically connected to the first sensing circuit SC1 through the 1-2 power cable 1112, and the first sensing circuit SC1 may be electrically connected to the main power supply circuit MPSC through the 1-1 power cable 1111. The first power circuit PC1 may be electrically connected to the first drive circuit DRC1 through the 1-1 wiring 1211. The first power circuit PC1 may be electrically connected to the first control circuit CC1 through the 1-2 wiring 1212.

[0081] The first power cables 1111 and 1112 may serve as a first power path 1100 , which is a path through which a first input voltage may be applied from the main power supply circuit MPSC to the first power circuit PC1 .

[0082] The first sensing circuit SC1 may be disposed on the first power cables 1111 and 1112, but is not limited thereto. The first sensing circuit SC1 may be electrically connected to the main power supply circuit MPSC through the 1-1 power cable 1111. The first sensing circuit SC1 may be electrically connected to the first power circuit PC1 through the 1-2 power cable 1112.

[0083] The power control circuit PCC may be electrically connected to the main power supply circuit MPSC through a power cable 900. The power control circuit PCC may be electrically connected to the first sensing circuit SC1 through a first sensing cable 1400 and a first transmission cable 1300. The power control circuit PCC may be electrically connected to the first power circuit PC1 through a first activation cable 1500. The power control circuit PCC may be electrically connected to the first control circuit CC1 through a first timing cable 1600.

[0084] As an example, the first transmission cable 1300 may include an analog-to-digital converter (ADC) 1700 configured to convert a voltage or current value into a digital value. The digital value is transmitted to the power control circuit PCC.

[0085] The second display driving device DRD2 may include a second driving circuit DRC2 for driving pixels of a second display panel provided in a second display module, a second control circuit CC2 for controlling the second driving circuit DRC2, a second power supply circuit PC2 for supplying power to the second driving circuit DRC2 and the second control circuit CC2, a second sensing circuit SC2 for sensing voltage and / or current, and the like, but is not limited thereto. As an example, more or fewer elements may be included in the second display driving device DRD2. Alternatively, the second display driving device DRD2 may further include a power control circuit PCC for generating a second power activation signal. The second power activation signal may be supplied from the power control circuit PCC to the second power circuit PC2 to activate the generation of a second PWM signal in the second power circuit PC2. The sensing signal may be supplied from the power control circuit PCC to the second sensing circuit SC2. The second PWM signal may suppress fluctuations in a constant voltage level output from the second power circuit PC2.

[0086] The second driving circuit DRC2 may include the above-mentioned data driver and gate driver, but is not limited thereto. The second control circuit CC2 may include the above-mentioned timing controller, but is not limited thereto.

[0087] The second power circuit PC2 may be electrically connected to the main power supply circuit MPSC through the second power cables 2111, 2112. Specifically, the second power circuit PC2 may be electrically connected to the second sensing circuit SC2 through the 2-2 power cable 2112, and the second sensing circuit SC2 may be electrically connected to the main power supply circuit MPSC through the 2-1 power cable 2111. The second power circuit PC2 may be electrically connected to the second drive circuit DRC2 through the 2-1 wiring 2211. The second power circuit PC2 may be electrically connected to the second control circuit CC2 through the 2-2 wiring 2212.

[0088] The second power cables 2111 and 2112 may serve as a second power path 2100 , which is a path through which a second input voltage may be applied from the main power supply circuit MPSC to the second power circuit PC2 .

[0089] The second sensing circuit SC2 may be disposed on the second power cables 2111 and 2112, but is not limited thereto. The second sensing circuit SC2 may be electrically connected to the main power supply circuit MPSC via the 2-1 power cable 2111. The second sensing circuit SC2 may be electrically connected to the second power circuit PC2 via the 2-2 power cable 2112.

[0090] The power control circuit PCC may be electrically connected to the second sensing circuit SC2 through the second sensing cable 2400 and the second transmission cable 2300. The power control circuit PCC may be electrically connected to the second power circuit PC2 through the second activation cable 2500. The power control circuit PCC may be electrically connected to the first control circuit CC1 through the first timing cable 1600, or may be electrically connected to the second control circuit CC2 through the second timing cable 2600. As shown, the power control circuit PCC is electrically connected to the first control circuit CC1 through the first timing cable 1600 shown in solid line, but is not limited thereto. Although not shown in the drawings, the present disclosure is not limited thereto, and the power control circuit PCC is electrically connected to the second control circuit CC2 through the second timing cable 2600. The power control circuit PCC may be connected to the first control circuit CC1 through the first timing cable 1600 to receive a timing signal synchronized with the image signal. Since it is sufficient for the power control circuit PCC to receive a timing signal synchronized with the image signal, the power control circuit PCC may be connected to only at least one of the first control circuit CC1 and the second control circuit CC2. In this case, the power control circuit PCC is not electrically connected to the second control circuit CC2 , but is not limited thereto. Alternatively, the power control circuit PCC is electrically connected to the second control circuit CC2 through the second timing cable 2600 .

[0091] As an example, the second transmission cable 2300 may include a second analog-to-digital converter 2700 configured to convert a voltage or a current into a digital value. The digital value is sent to the power control circuit PCC.

[0092] Reference Figure 5 In one embodiment, the display device may include a first display driving device DRD1 and a second display driving device DRD2, but is not limited thereto. In addition, the display device may further include an external power supply device EPSD. The first display driving device DRD1 and the second display driving device DRD2 may drive the first display module and the second display module, respectively.

[0093] The external power supply device EPSD may include a main power supply circuit MPSC and a first sensing circuit SC1 and a second sensing circuit SC2 for sensing voltage and / or current, but is not limited thereto. As an example, the external power supply device EPSD may include more or fewer elements. Alternatively, the external power supply device EPSD may also include a power control circuit PCC for generating the above-mentioned first power activation signal and the second power activation signal. Figure 4 and Figure 5 Components performing substantially the same functions between the embodiments are denoted by the same reference numerals, and their repeated descriptions will be omitted or briefly given.

[0094] The first display driving device DRD1 may include a first driving circuit DRC1 for driving pixels of a first display panel arranged in a first display module, a first control circuit CC1 for controlling the first driving circuit DRC1, a first power supply circuit PC1 for supplying power to the first driving circuit DRC1 and the first control circuit CC1, etc., but is not limited thereto.

[0095] The second display driving device DRD2 may include a second driving circuit DRC2 for driving pixels of a second display panel arranged in a second display module, a second control circuit CC2 for controlling the second driving circuit DRC2, a second power supply circuit PC2 for supplying power to the second driving circuit DRC2 and the second control circuit CC2, etc., but is not limited thereto.

[0096] Reference Figure 6 In one embodiment, the display device may include a first display driving device DRD1 and a second display driving device DRD2, but is not limited thereto. In addition, the display device may further include an external power supply device EPSD. The first display driving device DRD1 and the second display driving device DRD2 drive the first display module and the second display module respectively.

[0097] Similar to Figure 4According to an exemplary embodiment, the external power supply device EPSD may include a main power supply circuit MPSC.

[0098] The first display driving device DRD1 may include a first driving circuit DRC1 for driving pixels of a first display panel provided in a first display module, a first control circuit CC1 for controlling the first driving circuit DRC1, a 1-1 power supply circuit PC1-1 for supplying power to the first driving circuit DRC1, a 1-2 power supply circuit PC1-2 for supplying power to the first control circuit CC1, a first sensing circuit SC1 for sensing voltage and / or current, etc., but is not limited thereto. As an example, more or fewer elements may be included in the first display driving device DRD1. Alternatively, the first display driving device DRD1 may further include a power control circuit PCC for generating a 1-1 power activation signal and a 1-2 power activation signal. The 1-1 power activation signal may be supplied from the power control circuit PCC to the 1-1 power circuit PC1-1 to activate the generation of a 1-1 PWM signal in the 1-1 power circuit PC1-1. The 1-1 PWM signal may suppress the fluctuation of a constant voltage level output from the 1-1 power circuit PC1-1. The 1-2 power activation signal may be supplied from the power control circuit PCC to the 1-2 power circuit PC1-2 to activate the generation of the 1-2 PWM signal in the 1-2 power circuit PC1-2. The 1-2 PWM signal may suppress the fluctuation of the constant voltage level output from the 1-2 power circuit PC1-2. The sensing signal may be supplied from the power control circuit PCC to the first sensing circuit SC1.

[0099] The 1-1 power circuit PC1-1 may be electrically connected to the main power supply circuit MPSC through the 1-1 power cable 1111 and the 1-2 power cable 1112. Specifically, the 1-1 power circuit PC1-1 may be electrically connected to the first sensing circuit SC1 through the 1-2 power cable 1112, and the first sensing circuit SC1 may be electrically connected to the main power supply circuit MPSC through the 1-1 power cable 1111. The 1-1 power circuit PC1-1 may be electrically connected to the first drive circuit DRC1 through the 1-1 wiring 1211.

[0100] The 1-2 power circuit PC1-2 may be electrically connected to the main power supply circuit MPSC through the 1-1 power cable 1111 and the 1-3 power cable 1113. Specifically, the 1-2 power circuit PC1-2 may be electrically connected to the first sensing circuit SC1 through the 1-3 power cable 1113, and the first sensing circuit SC1 may be electrically connected to the main power supply circuit MPSC through the 1-1 power cable 1111. The 1-2 power circuit PC1-2 may be electrically connected to the first control circuit CC1 through the 1-2 wiring 1212.

[0101] The 1-1 power cable 1111 and the 1-2 power cable 1112 may be used as a 1-1 power path 1101 which is a path through which a 1-1 input voltage may be applied from the main power supply circuit MPSC to the 1-1 power circuit PC1-1.

[0102] The 1-1 power cable 1111 and the 1-3 power cable 1113 may be used as a 1-2 power path 1102 which is a path through which a 1-2 input voltage may be applied from the main power supply circuit MPSC to the 1-2 power circuit PC1-2.

[0103] The first sensing circuit SC1 may be provided on the 1-1 power cable 1111, but is not limited thereto. The first sensing circuit SC1 may be electrically connected to the main power supply circuit MPSC through the 1-1 power cable 1111. The first sensing circuit SC1 may be electrically connected to the 1-1 power circuit PC1-1 through the 1-2 power cable 1112. The first sensing circuit SC1 may be electrically connected to the 1-2 power circuit PC1-2 through the 1-3 power cable 1113.

[0104] Although not shown in the figure, the present disclosure is not limited thereto, and the first sensing circuit may not be provided on the 1-1 power cable. Alternatively, the first sensing circuit SC1 may include a 1-1 sensing circuit provided on the 1-2 power cable 1112 and a 1-2 sensing circuit provided on the 1-3 power cable 1113.

[0105] The 1-1 sensing circuit may be electrically connected to the main power supply circuit MPSC through a 1-1 power cable 1111. The 1-1 sensing circuit may be electrically connected to the 1-1 power circuit PC1-1 through a 1-2 power cable 1112.

[0106] The 1-2 sensing circuit may be electrically connected to the main power supply circuit MPSC through a 1-1 power cable 1111. The 1-2 sensing circuit may be electrically connected to the 1-2 power supply circuit PC1-2 through a 1-3 power cable 1113.

[0107] The power control circuit PCC may be electrically connected to the 1-1 power circuit PC1-1 through the 1-1 activation cable 1511. The power control circuit PCC may be electrically connected to the 1-2 power circuit PC1-2 through the 1-2 activation cable 1512.

[0108] The power control circuit PCC may be electrically connected to the first sensing circuit SC1 through the first sensing cable 1400 and the first transmission cable 1300. As an example, the first transmission cable 1300 may include an analog-to-digital converter (ADC) 1700 configured to convert a voltage or current value into a digital value.

[0109] The second display driving device DRD2 may include a second driving circuit DRC2 for driving pixels of a second display panel disposed in a second display module, a second control circuit CC2 for controlling the second driving circuit DRC2, a 2-1 power supply circuit PC2-1 for powering the second driving circuit DRC2, a 2-2 power supply circuit PC2-2 for powering the second control circuit CC2, a second sensing circuit SC2 for sensing voltage and / or current, etc., but is not limited thereto. As an example, more or fewer elements may be included in the second display driving device DRD2. Alternatively, the second display driving device DRD2 may also include a power control circuit PCC for generating a 2-1 power activation signal and a 2-2 power activation signal (not shown). The power control circuit PCC may be included in any one of the first display driving device DRD1 and the second display driving device DRD2, but is not limited thereto. For example, in one embodiment, the second display driving device DRD2 may include a power control circuit PCC, which may be electrically connected to a first control circuit CC1 disposed in the first display driving device DRD1 to receive a timing signal synchronized with an image signal. The 2-1 power activation signal may be supplied from the power control circuit PCC to the 2-1 power circuit PC2-1 to activate generation of a 2-1 PWM signal in the 2-1 power circuit PC2-1. The 2-1 PWM signal may suppress fluctuations in a constant voltage level output from the 2-1 power circuit PC2-1. The 2-2 power activation signal may be supplied from the power control circuit PCC to the 2-2 power circuit PC2-2 to activate generation of a 2-2 PWM signal in the 2-2 power circuit PC2-2. The 2-2 PWM signal may suppress fluctuations in a constant voltage level output from the 2-2 power circuit PC2-2.

[0110] The 2-1 power circuit PC2-1 may be electrically connected to the main power supply circuit MPSC through the 2-1 power cable 2111 and the 2-2 power cable 2112. Specifically, the 2-1 power circuit PC2-1 may be electrically connected to the second sensing circuit SC2 through the 2-2 power cable 2112, and the second sensing circuit SC2 may be electrically connected to the main power supply circuit MPSC through the 2-1 power cable 2111. The 2-1 power circuit PC2-1 may be electrically connected to the second drive circuit DRC2 through the 2-1 wiring 2211.

[0111] The 2-2 power circuit PC2-2 may be electrically connected to the main power supply circuit MPSC through the 2-1 power cable 2111 and the 2-3 power cable 2113. Specifically, the 2-2 power circuit PC2-2 may be electrically connected to the second sensing circuit SC2 through the 2-3 power cable 2113, and the second sensing circuit SC2 may be electrically connected to the main power supply circuit MPSC through the 2-1 power cable 2111. The 2-2 power circuit PC2-2 may be electrically connected to the second control circuit CC2 through the 2-2 wiring 2212.

[0112] The 2-1 power cable 2111 and the 2-2 power cable 2112 may function as a 2-1 power path 2101 , which is a path through which a 2-1 input voltage may be applied from the main power supply circuit MPSC to the 2-1 power circuit PC2 - 1 .

[0113] The 2-1 power cable 2111 and the 2-3 power cable 2113 may be used as a 2-2 power path 2102 which is a path through which a 2-2 input voltage may be applied from the main power supply circuit MPSC to the 2-2 power circuit PC2-2.

[0114] The second sensing circuit SC2 may be disposed on the 2-1 power cable 2111. The second sensing circuit SC2 may be electrically connected to the main power supply circuit MPSC through the 2-1 power cable 2111. The second sensing circuit SC2 may be electrically connected to the 2-1 power circuit PC2-1 through the 2-2 power cable 2112. The second sensing circuit SC2 may be electrically connected to the 2-2 power circuit PC2-2 through the 2-3 power cable 2113.

[0115] Although not shown in the drawings, the present disclosure is not limited thereto, and the second sensing circuit SC2 may include a 2-1 sensing circuit provided on the 2-2 power cable 2112 and a 2-2 sensing circuit provided on the 2-3 power cable 2113 .

[0116] The 2-1 sensing circuit may be electrically connected to the main power supply circuit MPSC through a 2-1 power cable 2111. The 2-1 sensing circuit may be electrically connected to the 2-1 power circuit PC2-1 through a 2-2 power cable 2112.

[0117] The 2-2 sensing circuit may be electrically connected to the main power supply circuit MPSC via the 2-1 power cable 2111. The 2-2 sensing circuit may be electrically connected to the 2-2 power supply circuit PC2-2 via the 2-3 power cable 2113.

[0118] The power control circuit PCC may be electrically connected to the 2-1 power circuit PC2-1 through the 2-1 activation cable 2511. The power control circuit PCC may be electrically connected to the 2-2 power circuit PC2-2 through the 2-2 activation cable 2512.

[0119] The power control circuit PCC may be electrically connected to the 1-1 power circuit PC1-1 through the 1-1 activation cable 1511. The power control circuit PCC may be electrically connected to the 1-2 power circuit PC1-2 through the 1-2 activation cable 1512.

[0120] Reference Figure 7 In one embodiment, the display device may include a first display driving device DRD1 and a second display driving device DRD2, but is not limited thereto. In addition, the display device may further include an external power supply device EPSD. The first display driving device DRD1 and the second display driving device DRD2 may drive the first display module and the second display module, respectively.

[0121] Similar to Figure 5 In an exemplary embodiment, the external power supply device EPSD may include a main power supply circuit MPSC and a first sensing circuit SC1 and a second sensing circuit SC2 for sensing voltage and / or current, but is not limited thereto. As an example, the external power supply device EPSD may include more or fewer elements. Alternatively, the external power supply device EPSD may also include a power control circuit PCC for generating the above-mentioned first power activation signal and the second power activation signal. Figure 5 and Figure 7 Components performing substantially the same functions between the embodiments are denoted by the same reference numerals, and their repeated descriptions will be omitted or briefly given.

[0122] Figure 5 The display device and Figure 7 The display device of the present invention is different in that: a 1-1 power supply circuit PC1-1 for supplying power to the first drive circuit DRC1, a 1-2 power supply circuit PC1-2 for supplying power to the first control circuit CC1, a 2-1 power supply circuit PC2-1 for supplying power to the second drive circuit DRC2, a 2-2 power supply circuit PC2-2 for supplying power to the second control circuit CC2, etc. Specifically, the first display drive device DRD1 may include a first drive circuit DRC1 for driving pixels of a first display panel provided in a first display module, a first control circuit CC1 for controlling the first drive circuit DRC1, a 1-1 power supply circuit PC1-1 for supplying power to the first drive circuit DRC1, a 1-2 power supply circuit PC1-2 for supplying power to the first control circuit CC1, etc., but is not limited thereto.

[0123] Specifically, the second display driving device DRD2 may include a second driving circuit DRC2 for driving pixels of a second display panel arranged in a second display module, a second control circuit CC2 for controlling the second driving circuit DRC2, a 2-1 power supply circuit PC2-1 for supplying power to the second driving circuit DRC2, a 2-2 power supply circuit PC2-2 for supplying power to the second control circuit CC2, and the like, but is not limited thereto.

[0124] Figure 8 is a view showing a configuration and connection relationship of a display device according to a fifth embodiment of the present disclosure. Fig. 9 : is a schematic plan view showing the configuration and connection relationship of a display device according to a fifth embodiment of the present disclosure. Figure 8 and Fig. 9 The display device and Figures 4 to 7 The display device of the embodiment is different in the number of display driving devices and the number of display modules driven by one display driving device. Components performing substantially the same functions as those of the above-mentioned embodiment are denoted by the same reference numerals, and a repeated description thereof will be omitted or briefly given.

[0125] Reference Figure 8 and Fig. 9 , each display module (e.g., DM1-1, DM1-2, DM1-3, and DM1-4) may include a display panel (e.g., PN1-1, PN1-2, PN1-3, and PN1-4) and a display driving circuit DRC. Specifically, the display module DM1-1 may include a display panel PN1-1 and a display driving circuit DRC, and the display module DM1-2 may include a display panel PN1-2 and a display driving circuit DRC, and so on. Each display driving circuit DRC may be included in a display driving device (e.g., DRD1). The display driving device DRD1 may also include a power supply circuit (e.g., PC1), a sensing circuit (e.g., SC1), and / or a power supply control circuit PCC. The display driving device (e.g., DRD1) may also include a plurality of control circuits or a single control circuit (not shown) for controlling each or all of the driving circuits DRC. For example, the display driving device DRD1 may also include a first control circuit CC1 for controlling each or all of the driving circuits DRC.

[0126] The host system HS may be connected to the system board SB, and the system board SB may be connected to a control circuit (not shown) operating in the display drivers DRD1, DRD2, DRD3, and DRD4. Therefore, an image signal to be reproduced on a large screen of the display device DD in which all display panels are connected may be sent to each control circuit. The system board SB may synchronize the control circuits.

[0127] The system board SB may include a user interface port for receiving user input, an external interface port connected to an external device, a communication module for delaying various communication protocols, a processor for processing multimedia signals, a central processing unit (CPU), an external power supply device (not shown), etc. As an example, more or fewer elements may be included in the system board SB. The system board SB may send an input image signal and a timing signal synchronized with the image signal to a plurality of display driving devices such as the first to fourth display driving devices DRD1, DRD2, DRD3, and DRD4. The control circuit installed on the plurality of display driving devices such as the first to fourth display driving devices DRD1, DRD2, DRD3, and DRD4 may send the received image signal to the display modules (e.g., DM1-1, DM1-2, DM1-3, and DM1-4), respectively, and control the driving circuit DRC based on the timing signal synchronized with the image signal. The driving circuit DRC of the display modules (eg, DM1-1, DM1-2, DM1-3, and DM1-4) may write image data to corresponding display panels (eg, PN1-1, PN1-2, PN1-3, and PN1-4) under the control of the control circuit.

[0128] The external power supply device may include a main power supply circuit MPSC. The main power supply circuit MPSC may be connected to M display driving devices (M is a natural number of 2 or greater). For example, the main power supply circuit MPSC may be connected to a plurality of display driving devices such as the first to fourth display driving devices DRD1, DRD2, DRD3, DRD4 through a flexible film, a cable, or a wiring.

[0129] Each of the plurality of display driving devices such as the first to fourth display driving devices DRD1, DRD2, DRD3 and DRD4 may include a control circuit CC, a power circuit PC, and a sensing circuit SC, but is not limited thereto. As an example, at least one display driving device may further include a power control circuit PCC. A plurality of display modules (such as 1-1 display module to 1-4 display module DM1-1, DM1-2, DM1-3 and DM1-4) connected to one display driving device (e.g., DRD1) may share a control circuit, a power circuit PC1 and a sensing circuit SC1, but is not limited thereto.

[0130] Each of the display driving devices such as the first to fourth display driving devices DRD1, DRD2, DRD3 and DRD4 can be connected to N display modules DM (N is a natural number greater than or equal to 1). For example, the first display driving device DRD1 can be connected to the driving circuit DRC of multiple display modules (such as 1-1 display module to 1-4 display modules DM1-1, DM1-2, DM1-3 and DM1-4) through a signal transmission path. The second display driving device DRD2 can be connected to the driving circuit of multiple display modules (such as 2-1 display module to 2-4 display module) through a signal transmission path. The third display driving device DRD3 can be connected to the driving circuit of multiple display modules (such as 3-1 display module to 3-4 display module) through a signal transmission path. The fourth display driving device DRD4 can be connected to the driving circuit of multiple display modules (such as 4-1 display module to 4-4 display module) through a signal transmission path. The signal transmission path may include a flexible film, a cable or a wiring, but is not limited thereto.

[0131] The first power circuit PC1 may be electrically connected to the main power supply circuit MPSC through first power cables 1111 and 1112 .

[0132] The first power cables 1111 and 1112 may serve as a first power path, which is a path through which a first input voltage may be applied from the main power supply circuit MPSC to the first power circuit PC1 .

[0133] The first sensing circuit SC1 may be disposed on the first power cables 1111 and 1112, but is not limited thereto. The first sensing circuit SC1 may be electrically connected to the main power supply circuit MPSC through the 1-1 power cable 1111. The first sensing circuit SC1 may be electrically connected to the first power circuit PC1 through the 1-2 power cable 1112.

[0134] The power control circuit PCC may be electrically connected to the main power supply circuit MPSC through a power cable. The power control circuit PCC may be electrically connected to the first sensing circuit SC1 through a first sensing cable 1400 and a first transmission cable 1300. The power control circuit PCC may be electrically connected to the first power circuit PC1 through a first activation cable 1500. The power control circuit PCC may be electrically connected to the first control circuit (not shown) through a first timing cable (not shown). As an example, the first transmission cable 1300 may include an analog-to-digital converter configured to convert a voltage or current value into a digital value.

[0135] The second power circuit PC2 may be electrically connected to the main power supply circuit MPSC through the second power cables 2111 and 2112. Specifically, the second power circuit PC2 may be electrically connected to the second sensing circuit SC2 through the 2-2 power cable 2112, and the second sensing circuit SC2 may be electrically connected to the main power supply circuit MPSC through the 2-1 power cable 2111.

[0136] The second power cables 2111 and 2112 may function as a second power path, which is a path through which a second input voltage may be applied from the main power supply circuit MPSC to the second power circuit PC2 .

[0137] The second sensing circuit SC2 may be disposed on the second power cables 2111 and 2112, but is not limited thereto. The second sensing circuit SC2 may be electrically connected to the main power supply circuit MPSC via the 2-1 power cable 2111. The second sensing circuit SC2 may be electrically connected to the second power circuit PC2 via the 2-2 power cable 2112.

[0138] The power control circuit PCC may be electrically connected to the second sensing circuit SC2 through the second sensing cable 2400 and the second transmission cable 2300. The power control circuit PCC may be electrically connected to the second power circuit PC2 through the second activation cable 2500. The second transmission cable 2300 may include an analog-to-digital converter configured to convert a voltage or current value into a digital value.

[0139] The third power supply circuit PC3 may be electrically connected to the main power supply circuit MPSC through third power supply cables 3111 and 3112 .

[0140] The third power cables 3111 and 3112 may serve as a third power path, which is a path through which a third input voltage may be applied from the main power supply circuit MPSC to the third power circuit PC3 .

[0141] The third sensing circuit SC3 may be disposed on the third power cables 3111 and 3112. The third sensing circuit SC3 may be electrically connected to the main power supply circuit MPSC through the 3-1 power cable 3111. The third sensing circuit SC3 may be electrically connected to the third power circuit PC3 through the 3-2 power cable 3112.

[0142] The power control circuit PCC may be electrically connected to the third sensing circuit SC3 through the third sensing cable 3400 and the third transmission cable 3300. The power control circuit PCC may be electrically connected to the third power circuit PC3 through the third activation cable 3500. The third transmission cable 3300 may include an analog-to-digital converter configured to convert a voltage or current value into a digital value.

[0143] The fourth power supply circuit PC4 may be electrically connected to the main power supply circuit MPSC through fourth power supply cables 4111 and 4112 .

[0144] The fourth power cables 4111 and 4112 may function as a fourth power path, which is a path through which a fourth input voltage may be applied from the main power supply circuit MPSC to the fourth power circuit PC4.

[0145] The fourth sensing circuit SC4 may be disposed on the fourth power cables 4111 and 4112. The fourth sensing circuit SC4 may be electrically connected to the main power supply circuit MPSC through the 4-1 power cable 4111. The fourth sensing circuit SC4 may be electrically connected to the fourth power circuit PC4 through the 4-2 power cable 4112.

[0146] The power control circuit PCC may be electrically connected to the fourth sensing circuit SC4 through the fourth sensing cable 4400 and the fourth transmission cable 4300. The power control circuit PCC may be electrically connected to the fourth power circuit PC4 through the fourth activation cable 4500. The fourth transmission cable 4300 may include an analog-to-digital converter configured to convert a voltage or current value into a digital value.

[0147] For example, one power control circuit PCC may control the operation of a plurality of power circuits such as the first power circuit PC1 to the fourth power circuit PC4 based on the sensing results of a plurality of sensing circuits such as the first sensing circuit SC1 to the fourth sensing circuit SC4. For example, the power control circuit PCC may include one of the first to fourth display driving devices DRD1 to DRD4 (e.g., the first display driving device DRD1).

[0148] Fig.10 Components performing substantially the same functions as those of the above-described embodiments are denoted by the same reference numerals, and repeated descriptions thereof will be omitted or briefly given.

[0149] Reference Fig.10 As an example, the display device may include an external power supply device (not shown), a first display driving device DRD1, a second display driving device DRD2, a third display driving device (not shown), and a fourth display driving device (not shown). As an example, the display device may include more or fewer display driving devices. Multiple display driving devices may drive multiple display modules respectively. For example, the first display driving device to the fourth display driving device may drive the first display module to the fourth display module respectively, but is not limited thereto.

[0150] The first display driving device DRD1 may include a first driving circuit DRC1 for driving pixels of a first display panel provided in a first display module, and a first control circuit CC1 for controlling the first driving circuit DRC1, but is not limited thereto. The first driving circuit DRC1 may include a 1-1 driving circuit DRC1-1, a 1-2 driving circuit DRC1-2, and a 1-3 driving circuit DRC1-3. For example, the 1-1 driving circuit DRC1-1 may be the above-mentioned data driver. For example, the 1-2 driving circuit DRC1-2 may be the above-mentioned gate driver. For example, the 1-3 driving circuit DRC1-3 may be a circuit for driving the above-mentioned pixel circuit.

[0151] In addition, the first display driving device DRD1 may further include a first power supply circuit PC1. The first power supply circuit PC1 may include a plurality of power supply circuits (such as a 1-1 power supply circuit PC1-1 for supplying power to the first control circuit CC1, a 1-2 power supply circuit PC1-2 for supplying power to the 1-1 drive circuit DRC1-1, a 1-3 power supply circuit PC1-3 for supplying power to the 1-2 drive circuit DRC1-2, and a 1-4 power supply circuit PC1-4 for supplying power to the 1-3 drive circuit DRC1-3), a first sensing circuit SC1 for sensing voltage and / or current, and the like.

[0152] In addition, the first display driving device DRD1 may further include a power control circuit PCC for generating power activation signals such as 1-1 power activation signal to 1-4 power activation signal. The 1-1 power activation signal may activate the generation of a 1-1 PWM signal, which suppresses the fluctuation of the constant voltage level output from the 1-1 power circuit PC1-1 to the first control circuit CC1. The 1-2 power activation signal may activate the generation of a 1-2 PWM signal, which suppresses the fluctuation of the constant voltage level output from the 1-2 power circuit PC1-2 to the 1-1 drive circuit DRC1-1. The 1-3 power activation signal may activate the generation of a 1-3 PWM signal, which suppresses the fluctuation of the constant voltage level output from the 1-3 power circuit PC1-3 to the 1-2 drive circuit DRC1-2. The 1-4 power activation signal may activate the generation of a 1-4 PWM signal, which suppresses the fluctuation of the constant voltage level output from the 1-4 power circuit PC1-4 to the 1-3 drive circuit DRC1-3.

[0153] The 1-1 power circuit PC1-1 may be electrically connected to a main power supply circuit (not shown) through a 1-1 power cable 1111 and a 1-2 power cable 1112. The first sensing circuit SC1 may be provided on the 1-1 power cable 1111, but is not limited thereto. The 1-1 power circuit PC1-1 may be electrically connected to the first control circuit CC1 through a 1-1 wiring 1211.

[0154] The 1-2 power supply circuit PC1-2 may be electrically connected to the main power supply circuit through the 1-1 power cable 1111 and the 1-3 power cable 1113. The first sensing circuit SC1 may be provided on the 1-1 power cable 1111, but is not limited thereto. The 1-2 power supply circuit PC1-2 may be electrically connected to the 1-1 drive circuit DRC1-1 through the 1-2 wiring 1212.

[0155] The 1-3 power circuit PC1-3 may be electrically connected to the main power supply circuit through the 1-1 power cable 1111 and the 1-4 power cable 1114. The first sensing circuit SC1 may be provided on the 1-1 power cable 1111, but is not limited thereto. The 1-3 power circuit PC1-3 may be electrically connected to the 1-2 drive circuit DRC1-2 through the 1-3 wiring 1213.

[0156] The 1-4 power circuit PC1-4 may be electrically connected to the main power supply circuit through the 1-1 power cable 1111 and the 1-5 power cable 1115. The first sensing circuit SC1 may be provided on the 1-1 power cable 1111, but is not limited thereto. The 1-4 power circuit PC1-4 may be electrically connected to the 1-3 drive circuit DRC1-3 through the 1-4 wiring 1214.

[0157] The 1-1 power cable 1111 and the 1-2 power cable 1112 may function as a 1-1 power path, which is a path through which a 1-1 input voltage may be applied from the main power supply circuit to the 1-1 power circuit PC1-1.

[0158] The 1-1 power cable 1111 and the 1-3 power cable 1113 may be used as a 1-2 power path, which is a path through which a 1-2 input voltage may be applied from the main power supply circuit to the 1-2 power circuit PC1-2.

[0159] The 1-1 power cable 1111 and the 1-4 power cable 1114 may be used as a 1-3 power path, which is a path through which a 1-3 input voltage may be applied from the main power supply circuit to the 1-3 power circuit PC1-3.

[0160] The 1-1 power cable 1111 and the 1-5 power cable 1115 may be used as a 1-4 power path, which is a path through which a 1-4 input voltage may be applied from the main power supply circuit to the 1-4 power circuit PC1-4.

[0161] The first sensing circuit SC1 may be disposed on the 1-1 power cable 1111. The first sensing circuit SC1 may be electrically connected to a main power supply circuit (not shown) through the 1-1 power cable 1111. The first sensing circuit SC1 may be electrically connected to the 1-1 power circuit PC1-1 through the 1-2 power cable 1112. The first sensing circuit SC1 may be electrically connected to the 1-1 power circuit PC1-2 through the 1-3 power cable 1113. The first sensing circuit SC1 may be electrically connected to the 1-3 power circuit PC1-3 through the 1-4 power cable 1114. The first sensing circuit SC1 may be electrically connected to the 1-4 power circuit PC1-4 through the 1-5 power cable 1115.

[0162] The power control circuit PCC may be electrically connected to the first sensing circuit SC1 through the first sensing cable 1400 and the first transmission cable 1300. As an example, the first transmission cable 1300 may include an analog-to-digital converter (ADC) configured to convert a voltage or current value into a digital value.

[0163] Although not shown in the figure, the present disclosure is not limited thereto, and the first sensing circuit may not be provided on the 1-1 power line. The first sensing circuit SC1 may include a 1-1 sensing circuit provided on the 1-2 power cable 1112, a 1-2 sensing circuit provided on the 1-3 power cable 1113, a 1-3 sensing circuit provided on the 1-4 power cable 1114, and a 1-4 sensing circuit provided on the 1-5 power cable 1115, but is not limited thereto.

[0164] The power control circuit PCC may be electrically connected to the main power supply circuit via a power cable. The power control circuit PCC may be electrically connected to the first sensing circuit SC1 via a first sensing cable 1400 and a first transmission cable 1300. The power control circuit PCC may be electrically connected to the first control circuit CC1 via a first timing cable 1600, or may be electrically connected to the second control circuit CC2 via a second timing cable (not shown). As shown, the power control circuit PCC is electrically connected to the first control circuit CC1. The first transmission cable 1300 may include an analog-to-digital converter configured to convert a voltage or current value into a digital value.

[0165] The power control circuit PCC may be electrically connected to the 1-1 power circuit PC1-1 through the 1-1 activation cable 1511. The power control circuit PCC may be electrically connected to the 1-2 power circuit PC1-2 through the 1-2 activation cable 1512. The power control circuit PCC may be electrically connected to the 1-3 power circuit PC1-3 through the 1-3 activation cable 1513. The power control circuit PCC may be electrically connected to the 1-4 power circuit PC1-4 through the 1-4 activation cable 1514. However, the present disclosure is not limited thereto.

[0166] The second display driving device DRD2 may include a second driving circuit DRC2 for driving pixels of a second display panel provided in a second display module, and a second control circuit CC2 for controlling the second driving circuit DRC2, but is not limited thereto. The second driving circuit DRC2 may include a 2-1 driving circuit DRC2-1, a 2-2 driving circuit DRC2-2, and a 2-3 driving circuit DRC2-3. For example, the 2-1 driving circuit DRC2-1 may be the above-mentioned data driver. For example, the 2-2 driving circuit DRC2-2 may be the above-mentioned gate driver. For example, the 2-3 driving circuit DRC2-3 may be a circuit for driving the above-mentioned pixel circuit.

[0167] In addition, the second display driving device DRD2 may further include a second power supply circuit PC2. The second power supply circuit PC2 may include a plurality of power supply circuits (such as a 2-1 power supply circuit PC2-1 for supplying power to the second control circuit CC2, a 2-2 power supply circuit PC2-2 for supplying power to the 2-1 drive circuit DRC2-1, a 2-3 power supply circuit PC2-3 for supplying power to the 2-2 drive circuit DRC2-2, and a 2-4 power supply circuit PC2-4 for supplying power to the 2-3 drive circuit DRC2-3), a second sensing circuit SC2 for sensing voltage and / or current, and the like.

[0168] In addition, the second display driving device DRD2 may further include a power control circuit PCC for generating power activation signals such as a 2-1 power activation signal, a 2-2 power activation signal, a 2-3 power activation signal, and a 2-4 power activation signal. The 2-1 power activation signal may activate the generation of a 2-1PWM signal that suppresses the fluctuation of the constant voltage level output from the 2-1 power circuit PC2-1 to the second control circuit CC2. The 2-2 power activation signal may activate the generation of a 2-2PWM signal that suppresses the fluctuation of the constant voltage level output from the 2-2 power circuit PC2-2 to the 2-1 drive circuit DRC2-1. The 2-3 power activation signal may activate the generation of a 2-3PWM signal that suppresses the fluctuation of the constant voltage level output from the 2-3 power circuit PC2-3 to the 2-2 drive circuit DRC2-2. The 2-4 power activation signal may activate the generation of a 2-4PWM signal that suppresses the fluctuation of the constant voltage level output from the 2-4 power circuit PC2-4 to the 2-3 drive circuit DRC2-3.

[0169] The 2-1 power circuit PC2-1 may be electrically connected to a main power supply circuit (not shown) through a 2-1 power cable 2111 and a 2-2 power cable 2112. The second sensing circuit SC2 may be provided on the 2-1 power cable 2111, but is not limited thereto. The 2-1 power circuit PC2-1 may be electrically connected to the second control circuit CC2 through a 2-1 wiring 2211.

[0170] The 2-2 power supply circuit PC2-2 can be electrically connected to the main power supply circuit through the 2-1 power cable 2111 and the 2-3 power cable 2113. The second sensing circuit SC2 can be provided on the 2-1 power cable 2111, but is not limited thereto. The 2-2 power supply circuit PC2-2 can be electrically connected to the 2-1 drive circuit DRC2-1 through the 2-2 wiring 2212.

[0171] The 2-3 power supply circuit PC2-3 can be electrically connected to the main power supply circuit through the 2-1 power cable 2111 and the 2-4 power cable 2114. The second sensing circuit SC2 can be provided on the 2-1 power cable 2111, but is not limited thereto. The 2-3 power supply circuit PC2-3 can be electrically connected to the 2-2 drive circuit DRC2-2 through the 2-3 wiring 2213.

[0172] The 2-4 power circuit PC2-4 can be electrically connected to the main power supply circuit through the 2-1 power cable 2111 and the 2-5 power cable 2115. The second sensing circuit SC2 can be provided on the 2-1 power cable 2111, but is not limited thereto. The 2-4 power circuit PC2-4 can be electrically connected to the 2-3 drive circuit DRC2-3 through the 2-4 wiring 2214.

[0173] The 2-1 power cable 2111 and the 2-2 power cable 2112 may function as a 2-1 power path, which is a path through which a 2-1 input voltage may be applied from the main power supply circuit to the 2-1 power circuit PC2-1.

[0174] The 2-1 power cable 2111 and the 2-3 power cable 2113 may be used as a 2-2 power path, which is a path through which a 2-2 input voltage may be applied from the main power supply circuit to the 2-2 power circuit PC2-2.

[0175] The 2-1 power cable 2111 and the 2-4 power cable 2114 may be used as a 2-3 power path, which is a path through which a 2-3 input voltage may be applied from the main power supply circuit to the 2-3 power circuit PC2-3.

[0176] The 2-1 power cable 2111 and the 2-5 power cable 2115 may be used as a 2-4 power path, which is a path through which a 2-4 input voltage may be applied from the main power supply circuit to the 2-4 power circuit PC2-4.

[0177] The second sensing circuit SC2 can be arranged on the 2-1 power cable 2111. The second sensing circuit SC2 can be electrically connected to the main power supply circuit (not shown) through the 2-1 power cable 2111. The second sensing circuit SC2 can be electrically connected to the 2-1 power circuit PC2-1 through the 2-2 power cable 2112. The second sensing circuit SC2 can be electrically connected to the 2-2 power circuit PC2-2 through the 2-3 power cable 2113. The second sensing circuit SC2 can be electrically connected to the 2-3 power circuit PC2-3 through the 2-4 power cable 2114. The second sensing circuit SC2 can be electrically connected to the 2-4 power circuit PC2-4 through the 2-5 power cable 2115.

[0178] Although not shown in the figure, the present disclosure is not limited thereto, and the second sensing circuit may not be arranged on the 2-1 power cable. The second sensing circuit SC2 may include a 2-1 sensing circuit arranged on the 2-2 power cable 2112, a 2-2 sensing circuit arranged on the 2-3 power cable 2113, a 2-3 sensing circuit arranged on the 2-4 power cable 2114, and a 2-4 sensing circuit arranged on the 2-5 power cable 2115, but is not limited thereto.

[0179] The power control circuit PCC may be electrically connected to the main power supply circuit via a power cable. The power control circuit PCC may be electrically connected to the second sensing circuit SC2 via a second sensing cable 2400 and a second transmission cable 2300. The power control circuit PCC may be electrically connected to the first control circuit CC1 via a first timing cable 1600, or may be electrically connected to the second control circuit CC2 via a second timing cable (not shown). As shown, the power control circuit PCC is electrically connected to the first control circuit CC1. The second transmission cable 2300 may include an analog-to-digital converter configured to convert a voltage or current value into a digital value.

[0180] The power control circuit PCC may be electrically connected to the 2-1 power circuit PC2-1 through the 2-1 activation cable 2511. The power control circuit PCC may be electrically connected to the 2-2 power circuit PC2-2 through the 2-2 activation cable 2512. The power control circuit PCC may be electrically connected to the 2-3 power circuit PC2-3 through the 2-3 activation cable 2513. The power control circuit PCC may be electrically connected to the 2-4 power circuit PC2-4 through the 2-4 activation cable 2514. However, the present disclosure is not limited thereto.

[0181] The third transmission cable 3300 and the third sensing cable 3400 extending from the power control circuit PCC can electrically connect the power control circuit PCC with a third sensing circuit (not shown). The fourth transmission cable 4300 and the fourth sensing cable 4400 extending from the power control circuit PCC can electrically connect the power control circuit PCC with a fourth sensing circuit (not shown).

[0182] The third activation cable 3500 extending from the power control circuit PCC can electrically connect the power control circuit PCC with a third power circuit (not shown). The fourth activation cable 4500 extending from the power control circuit PCC can electrically connect the power control circuit PCC with a fourth power circuit (not shown).

[0183] Fig.11 Components performing substantially the same functions between the embodiments are denoted by the same reference numerals, and repeated descriptions thereof will be omitted or briefly given.

[0184] Reference Fig.11 The display device may include an external power supply device EPSD, a plurality of display driving devices, such as a first display driving device DRD1, a second display driving device (not shown), a third display driving device (not shown), and a fourth display driving device (not shown), but is not limited thereto. The plurality of display driving devices, such as the first to fourth display driving devices, may respectively drive a plurality of display modules, such as the first to fourth display modules.

[0185] The external power supply device EPSD may include a main power supply circuit (not shown), and a plurality of sensing circuits for sensing voltage and / or current, such as a first sensing circuit SC1 to a fourth sensing circuit SC4, but not limited thereto. In addition, the external power supply device EPSD may also include a power control circuit PCC for generating a plurality of power activation signals such as a 1-1 power activation signal to a 1-4 power activation signal. The 1-1 power activation signal may activate the generation of a 1-1 PWM signal that suppresses the fluctuation of the constant voltage level output from the 1-1 power circuit PC1-1 to the first control circuit CC1. The 1-2 power activation signal may activate the generation of a 1-2 PWM signal that suppresses the fluctuation of the constant voltage level output from the 1-2 power circuit PC1-2 to the 1-1 drive circuit DRC1-1. The 1-3 power activation signal may activate the generation of a 1-3 PWM signal that suppresses the fluctuation of the constant voltage level output from the 1-3 power circuit PC1-3 to the 1-2 drive circuit DRC1-2. The 1-4 power activation signal may activate generation of a 1-4 PWM signal that suppresses fluctuations in a constant voltage level output from the 1-4 power circuit PC1-4 to the 1-3 drive circuit DRC1-3.

[0186] The first display driving device DRD1 may include a first driving circuit DRC1 for driving pixels of a first display panel provided in a first display module, and a first control circuit CC1 for controlling the first driving circuit DRC1, but is not limited thereto. The first driving circuit DRC1 may include a 1-1 driving circuit DRC1-1, a 1-2 driving circuit DRC1-2, and a 1-3 driving circuit DRC1-3. For example, the 1-1 driving circuit DRC1-1 may be the above-mentioned data driver. For example, the 1-2 driving circuit DRC1-2 may be the above-mentioned gate driver. For example, the 1-3 driving circuit DRC1-3 may be a circuit for driving the above-mentioned pixel circuit.

[0187] The first transmission cable 1300 and the first sensing cable 1400 extending from the power control circuit PCC can electrically connect the power control circuit PCC with the first sensing circuit. The second transmission cable 2300 and the second sensing cable 2400 extending from the power control circuit PCC can electrically connect the power control circuit PCC with the second sensing circuit. The third transmission cable 3300 and the third sensing cable 3400 extending from the power control circuit PCC can electrically connect the power control circuit PCC with the third sensing circuit. The fourth transmission cable 4300 and the fourth sensing cable 4400 extending from the power control circuit PCC can electrically connect the power control circuit PCC with the fourth sensing circuit.

[0188] The first activation cable 1500 extending from the power control circuit PCC can electrically connect the power control circuit PCC with the first power circuit. The second activation cable 2500 extending from the power control circuit PCC can electrically connect the power control circuit PCC with the second power circuit. The third activation cable 3500 extending from the power control circuit PCC can electrically connect the power control circuit PCC with the third power circuit. The fourth activation cable 4500 extending from the power control circuit PCC can electrically connect the power control circuit PCC with the fourth power circuit.

[0189] Fig.12 is a view showing a driving period of a display device.

[0190] Reference Fig.12 , the driving period of the display device may include a first non-display period X1 and a second non-display period X2 and an image display period X0. The first non-display period X1 may be defined as a section from power-on to the start of the first frame. The second non-display period X2 may be defined as a section from power-off to power-on. The image display period X0 may be defined as a section between the first non-display period X1 and the second non-display period X2.

[0191] The image display period X0 may include an active segment AT and a vertical blank segment VB. In the active segment AT, a data voltage is written on a sub-pixel, and in the vertical blank segment VB, image data is not written. The compensation period may be outside the active segment AT. The compensation period may be included in the first non-display period X1 and the second non-display period X2 or the vertical blank segment VB. During the compensation period, the data driver may extract the threshold voltage of the driving transistor and calculate the change of the threshold voltage based on the threshold voltage to generate a compensated data voltage. The compensation period may include a programming period Tpg, a sensing period Tsen, a sampling period Tsam, and the like.

[0192] The active section AT may include an Nth frame FR(N) and an (N+1)th frame FR(N+1) (N is a natural number of 1 or more). The vertical blank section VB may be located between the Nth frame FR(N) and the (N+1)th frame FR(N+1).

[0193] In the display device according to the embodiment, the time interval between the power activation signals generated by the power control circuit may be adjusted based on the result sensed in the Nth frame FR(N).

[0194] Fig.13 is a diagram showing the timing of power activation signals sent to each power circuit. Fig.14 is a diagram showing the peak current of the main power supply circuit and the effect of reducing the peak current. Fig.152 is a diagram showing noise superposition of a display driving device and an effect of reducing the noise superposition.

[0195] Reference Figures 13 to 15 , the power supply circuit may include a DC-DC converter and output a constant voltage (or DC voltage). Specifically, the DC-DC converter may include a charge pump, a regulator, a buck converter, a boost converter, etc. However, the present disclosure is not limited thereto.

[0196] like Fig.13 As shown, during the vertical blank section VB, a low-level vertical synchronization signal Vsync is generated.

[0197] PWM signals such as PWMDRD1, PWMDRD2, PWMDRD3, and PWMDRD4 generated by the power supply circuit may be enabled by a power activation signal supplied from the power supply control circuit to the power supply circuit. The PWM signal may control the voltage input to the drive circuit and the control circuit.

[0198] The power circuit may start driving when a power activation signal is input from the power control circuit, and output a voltage having a preset voltage level. The power activation signal may be a voltage level of an input voltage, at which a target voltage of a preset level may be output from the power circuit. When the output voltage changes according to a change in a load connected to an output terminal, the power circuit may suppress a change in the output voltage level by generating PWM signals PWMDRD1, PWMDRD2, PWMDRD3, and PWMDRD4. For example, when the output voltage increases, the power circuit may reduce the output voltage level by reducing the duty cycle of the PWM signals PWMMDRD1, PWMDRD2, PWMDRD3, and PWMDRD4, and when the output voltage decreases, the power circuit may increase the output voltage level by increasing the duty cycle of the PWM signals PWMDRD1, PWMDRD2, PWMDRD3, and PWMDRD4, but the present disclosure is not limited thereto. The load may be a driving circuit and / or a control circuit. The load may depend on a pattern and / or brightness (e.g., an image data voltage according to a grayscale value) of image data input to each display panel in the display module.

[0199] The power activation signal may be generated in the vertical blank section VB. In a conventional display driving device, a plurality of PWM signals are generated and transmitted at substantially the same timing. Therefore, when a driving power or voltage is applied (input) from a main power supply circuit to a plurality of power supply circuits, the main power supply circuit generates a peak value of a specific physical characteristic (e.g., current or voltage), thereby causing a problem in which EMI exceeding established standards is measured.

[0200] When the power or voltage output by the main power supply circuit through multiple output terminals increases at the same time, the intensity of the peak current measured at the main power supply circuit increases, so that EMI exceeds the allowable limit, causing failure or damage to nearby devices. In addition, power supply noise such as ripple and impact current applied to the display drive device may be generated, making the operation of the display drive device unstable. Overlapping noise may occur. Therefore, it is necessary to reduce EMI phenomena and noise caused by peak values ​​of specific physical characteristics (such as current).

[0201] When the power activation signal has a time interval, the display driving device and the display device according to the present disclosure can reduce the peak current generated by the main power supply circuit (see Fig.14 ). In addition, the increase in noise caused by overlapping noise observed from each display driving device can be minimized (see Fig.15 ).

[0202] like Fig.14 As shown, the display driving device and the display device according to the present disclosure can reduce the peak current generated by the main power supply circuit compared with the peak value in the comparative example.

[0203] Fig.16 is a diagram illustrating generation and transmission of a sensing signal.

[0204] Reference Fig.16 , the power control circuit PCC can be connected to the first control circuit CC1 through a first timing cable 1600 (shown as a solid line) to receive a timing signal synchronized with the image signal. The first control circuit CC1 may include a level shifter. The timing signal may include a driving signal such as a data enable signal DE, a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a gate timing control signal GTCS, a data timing control signal DTCS, and a dot clock signal MCLK, but is not limited thereto.

[0205] The power control circuit PCC may receive the timing signal to determine the sensing number and generate and output the sensing signal. The sensing signal may be input to the sensing circuits SC1 and SC2.

[0206] The number of sensing times may be determined according to the frequency of a timing signal synchronized with an image signal.

[0207] Fig.17 is a waveform diagram showing a timing signal synchronized with an image signal. Fig.18 is a waveform diagram showing a process of determining a sensing frequency using an input / output signal of a level shifter and a gate timing control signal.

[0208] Reference Fig.17, the vertical synchronization signal Vsync can define a frame segment (1 frame). One frame segment (1 frame) can be the time of the sum of the active segment AT and the vertical blank segment VB. The vertical blank segment VB can be allocated as a predetermined time between the active segment AT of the Nth frame segment and the active segment AT of the (N+1)th frame segment. The control circuit can receive the data enable signal DE and the data of the input image during the active segment AT. The data enable signal DE and the data of the input image may not exist in the vertical blank segment VB. During the active segment AT, the control circuit can receive 1 frame of data to be written on the pixel.

[0209] The horizontal synchronization signal Hsync can define a horizontal period (1 horizontal time, 1H). The data enable signal DE can define a valid pixel data segment by synchronizing with the pixel data to be displayed on the display panel of the display module. One pulse cycle of the data enable signal DE is a horizontal period 1H, and the high logic segment of the data enable signal DE indicates the pixel data input segment of a pixel line. One horizontal period 1H is the time required to write data to the pixels of one pixel line in the display panel. The pixel line may include pixels arranged along the gate line direction and connected to the same gate line. The pixels of a pixel line may share a gate line to which a gate signal (or scan signal) is applied, and may be simultaneously addressed according to the scan signal to receive the data voltage of the pixel data.

[0210] As can be seen from the data enable signal DE, the display device may not be able to receive input data during the vertical blank section VB. The vertical blank section VB may include a vertical synchronization time VS, a vertical front porch FP, and a vertical back porch BP.

[0211] Reference Fig.18, the first input clock ICLK1 and the second input clock ICLK2 can be generated by the timing controller and input to the level shifter. The driver set in the level shifter can turn on the pull-up transistor in response to the first input clock ICLK1, and turn on the pull-down transistor in response to the second input clock ICLK2. Specifically, the driver can turn on the pull-up transistor at the rising edge of the first input clock ICLK1, and turn on the pull-down transistor at the falling edge of the second input clock ICLK2, but the present disclosure is not limited to this. Alternatively, the driver can turn on the pull-up transistor at the falling edge of the first input clock ICLK1, and turn on the pull-down transistor at the rising edge of the second input clock ICLK2, but the present disclosure is not limited to this. The level shifter can output the gate timing control signals GIP1, GIP2, GIP3... whose phases are sequentially shifted through multiple channels. The driver can send a carry signal to the driver of the next channel. The driver of the next channel can be enabled when the carry signal is received to generate an output. At least some of the gate timing control signals GIP1, GIP2, GIP3, ... output from the level shifter may overlap. In this case, a gate driver receiving the gate timing control signals GIP1, GIP2, GIP3, ... may sequentially provide gate pulses to the gate lines, at least some of which overlap with each other.

[0212] The on / off timing and frequency of the sensing signal SS may be determined based on the on (or off) section of the gate timing control signals GIP1 , GIP2 , GIP3 . . . output from the level shifter.

[0213] Fig.19 is a waveform diagram showing a process of determining a sensing frequency using a vertical synchronization signal. Fig. 20 is a waveform diagram showing a process of determining a sensing frequency using a horizontal synchronization signal. Fig.21 is a waveform diagram illustrating a process of determining a sensing frequency using a data enable signal.

[0214] Reference Fig.19 , the vertical synchronization signal Vsync can define a frame segment (1 frame). A frame segment (1 frame) can be the time of the sum of the active segment AT and the vertical blank segment VB. The on / off timing of the sensing signal SS can be determined based on the one frame segment (1 frame) of the vertical synchronization signal Vsync. The frequency of the sensing signal SS can be determined based on the on / off timing. For example, when the refresh rate of the display device is 60Hz, the time interval in a frame segment is 16.67ms. Assuming that the time interval in the active segment is 16ms, when 8 sensings are performed in the active segment, the frequency of the number of sensings in the active segment can be 500Hz. However, the present disclosure is not limited to this, and the on / off timing and frequency of the sensing signal SS can be determined based on the vertical blank segment VB and the active segment AT.

[0215] Reference Fig. 20 , the horizontal synchronization signal Hsync may define one horizontal period (1 horizontal time, 1H). The on / off timing and frequency of the sensing signal SS may be determined based on one horizontal period 1H. For example, when the refresh rate of the display device is 60Hz and the resolution is FHD (1920×1080), the 1H period may be 1 / (60×1080)s, and the frequency of the sensing signal SS in the active period may be 30×1080=32,400Hz.

[0216] Reference Fig.21 , and refer to the above Fig.19 and Fig. 20 Similar to those described, the on / off timing and frequency of the sensing signal SS may be determined based on a section in which data is input, and a detailed description thereof will be omitted or briefly given.

[0217] Fig. 22 is a waveform diagram showing a process of determining a sensing frequency using a dot clock signal.

[0218] Reference Fig. 22 The on / off timing and frequency of the sensing signal SS can be determined based on the number of dot clock signals MCLK. For example, when the refresh rate of the display device is 60 Hz (= 16.67 ms), the frequency of the clock signal is 74 MHz (= 1.35 ns), and the time interval in the active segment is 16 ms, the number of clock signals in the active segment is approximately 11×10 6 When 1×10 6 When sensing is performed in units of a clock signal, sensing is performed 11 times in the active section, and the frequency of the sensing signal in the active section is about 700 Hz.

[0219] Fig.23 is a diagram illustrating functions and operations of components of a display driving device.

[0220] Reference Fig.23, the main power supply circuit MPSC can supply power to the power circuit PC1 and the power circuit PC2 through the power cables 1111, 1112, 2111 and 2112. The first sensing circuit SC1 can be provided on the first power cable 1111, but is not limited thereto. The second sensing circuit SC2 can be provided on the second power cable 2111, but is not limited thereto. The first power cables 1111 and 1112 can be used as a first power path, which is a path through which a first input voltage can be applied from the main power supply circuit MPSC to the first power circuit PC1. The second power cables 2111 and 2112 can be used as a second power path, which is a path through which a second input voltage can be applied from the main power supply circuit MPSC to the second power circuit PC2.

[0221] The power control circuit PCC can determine the frequency, number of sensing times, etc. of the sensing signal based on the timing signal received from the first control circuit CC1 through the timing cable 1600 (or from the second control circuit CC2 through the timing cable 2600), and send a sensing signal indicating sensing to the sensing circuits SC1 and SC2. The sensing signal can be sent to the sensing circuits SC1 and SC2 through the sensing cables 1400 and 2400.

[0222] The first sensing circuit SC1 and the second sensing circuit SC2 receiving the sensing signal may be respectively arranged on the first power cable 1111 and the second power cable 2111 to sense the first voltage or current and the second voltage or current applied to the first power circuit PC1 and the second power circuit PC2, but are not limited thereto. The first current and the second current may be current values ​​consumed by the power circuits. The first voltage (or current) and the second voltage (or current) may be transmitted to the power control circuit PCC via the first transmission cable 1300 and the second transmission cable 2300, respectively.

[0223] Specifically, the first voltage or current value and the second voltage or current value can be converted into digital values ​​by an analog-to-digital converter (ADC) 1700 set in the first transmission cable 1300 and an analog-to-digital converter (ADC) 2700 set in the second transmission cable 2300, and sent to the power control circuit PCC.

[0224] The power control circuit PCC can calculate the current consumption value of each power circuit based on the first voltage or current value and the second voltage or current value. Based on the calculated current consumption value, the power control circuit PCC can determine the current value consumed by each display driver (and / or panel). In a display device, the image data input to each display panel constituting a display device may be different according to the position, arrangement, time or space of the panel. Even when only one frame is executed, it is necessary to input image data with different brightness and / or grayscale values ​​according to the position. Specifically, since the image data is expressed with relatively high brightness and / or relatively high grayscale, the current consumed by the display panel to which the image data is input can be larger. Alternatively, since the image data is expressed with relatively low brightness and / or relatively low grayscale, the current consumed by the display panel to which the image data is input can be smaller. Considering the same situation, the current value consumed by the display panel or the display driver can be changed.

[0225] The power control circuit PCC may determine the time interval between the power activation signals input to the power circuit PC1 and the power circuit PC2 based on the determined current consumption values. For example, when at least one of the determined current consumption values ​​is greater than a preset threshold, the power control circuit PCC may increase the time interval between the first power activation signal and the second power activation signal.

[0226] The preset threshold value may be an arithmetic mean of multiple currents input to each power circuit. However, the present disclosure is not limited thereto, and the preset threshold value may be set in consideration of the current value generally consumed by the display driving device. The power control circuit PCC may determine the order of the power activation signals input to the power circuits PC1 and PC2 based on the determined current consumption value.

[0227] The power circuit PC1 and the power circuit PC2 may receive a power activation signal through the activation cable 1500 and the activation cable 2500, and the power activation signal reflects the time interval between the power activation signals from the power control circuit PCC. Specifically, the first power circuit PC1 may input power to the first drive circuit DRC1 and the first control circuit CC1 in response to the first power activation signal received from the power control circuit PCC through the first activation cable 1500. The second power circuit PC2 may input power to the second drive circuit DRC2 and the second control circuit CC2 in response to the second power activation signal received from the power control circuit PCC through the second activation cable 2500. The first power activation signal transmitted to the first power circuit PC1 may activate the first PWM signal of the first power circuit PC1. The second power activation signal transmitted to the second power circuit PC2 may activate the second PWM signal of the second power circuit PC2. The first PWM signal and the second PWM signal may be transmitted to the first drive circuit DRC1 and the second drive circuit DRC2 and the first control circuit CC1 and the second control circuit CC2, and may serve as the basis for a command to allow the first drive circuit DRC1 and the second drive circuit DRC2 and the first control circuit CC1 and the second control circuit CC2 to receive power. Specifically, the first PWM signal may be transmitted to the first drive circuit DRC1 and the first control circuit CC1, and the second PWM signal may be transmitted to the second drive circuit DRC2 and the second control circuit CC2.

[0228] The first drive circuit DRC1 and the first control circuit CC1 receiving the first PWM signal and the second drive circuit DRC2 and the second control circuit CC2 receiving the second PWM signal can receive power. The first PWM signal can be transmitted to the first drive circuit DRC1 and the first control circuit CC1 through the 1-1 wiring 1211 and the 1-2 wiring 1212, respectively. The second PWM signal can be transmitted to the second drive circuit DRC2 and the second control circuit CC2 through the 2-1 wiring 2211 and the 2-2 wiring 2212, respectively.

[0229] Fig.24 and Fig.25 is a diagram showing various examples of time intervals between power activation signals.

[0230] Reference Fig.24, the time interval between the power activation signals can be determined based on the frequency and duty cycle of the PWM signal output from the power supply circuit for powering each display driving device. For example, when the duty cycle of one cycle of the PWM signals PWMMDRD1, PWMDRD2, PWMDRD3, and PWMDRD4 is K% (0≤K≤100), the time interval between the power activation signals is in the range of 0.2K% to 0.6K%, but is not limited thereto. Specifically, when the frequency of the PWM signal PWMMDRD1 is 200kHz and its duty cycle is 50%, the duration of one cycle of the PWM signal PWMMDRD1 is 5μs, and the duration of the on-time segment is 2.5μs. Assuming that the time intervals between the power activation signals are constant, the time intervals I1, I2, I3, I4, and I5 of the power activation signals can be 2.5μs / 5=0.5μs. Therefore, in this case, the time interval between the power activation signals is 0.5 μs / 5 μs×100(%)=0.2×50(%)=10% of one period of the PWM signal.

[0231] Reference Fig.25 For example, when the duty cycle of one cycle of the PWM signals PWMMDRD1, PWMDRD2, PWMDRD3, and PWMDRD4 is K% (0≤K≤100), the time interval between the power activation signals is in the range of 0.2K% to 0.6K%, but is not limited thereto. Specifically, when the frequency of the PWM signal PWMMDRD1 is 200kHz and its duty cycle is 50%, the duration of one cycle of the PWM signal PWMMDRD1 is 5μs, and the duration of the on-time segment is 2.5μs. Assuming that the time intervals between the power activation signals are constant, the time interval I6 of the power activation signals can be 2.5μs×0.6=1.5μs. Therefore, in this case, the time interval between the power activation signals is 1.5μs / 5μs×100(%)=0.6×50(%)=30% of one cycle of the PWM signal.

[0232] Fig.26 is a table of simulation results used to determine the optimal time interval value range for the power supply activation signal.

[0233] Reference Fig.26, the gain value indicates that there is a noise reduction compared to before the time interval between the power activation signals. When eight driving devices (such as driving devices 1 to driving devices 8) are used, it is confirmed that the gain values ​​in Examples 2, 3, and 5 are reduced compared to the gain of Control Example 1. It is confirmed that the optimal time interval between the power activation signals is between 0.5μs and 1.5μs. Therefore, when the duty cycle of one cycle of the PWM signal is K% (0≤K≤100), the time interval between the power activation signals according to an exemplary embodiment can be in the range of 0.2K% to 0.6K% of one cycle of the PWM signal, but is not limited thereto.

[0234] Fig. 27 2 is a diagram showing the connection relationship between the power supply control circuit and the display driving device. Figure 28 to Figure 31 are views showing various examples of waveforms of PWM signals generated by reflecting an increased time interval.

[0235] Reference Fig. 27 and Fig.28 , the power control circuit PCC may determine the order of power activation signals to be input to the power circuit based on the determined current consumption value.

[0236] As an example, the power control circuit PCC may send the power activation signal for driving the power circuit of the display driving device with the maximum current consumption value last, but is not limited thereto. For example, the current consumption value calculated based on the current value input to the power control circuit PCC may be 1.5A for the first display driving device DRD1, 1.7A for the second display driving device DRD2, 0.7A for the third display driving device DRD3, and 0.8A for the fourth display driving device DRD4. In an embodiment, based on the determined time interval I8 between the power activation signals, the power control circuit PCC may first send the first power activation signal for driving the first power circuit of the first display driving device DRD1 with a relatively low current consumption value, the third power activation signal for the third power circuit of the third display driving device DRD3, and the fourth power activation signal for the fourth power circuit of the fourth display driving device DRD4, and finally send the second power activation signal for driving the second power circuit of the second display driving device DRD2 with the maximum current consumption value.

[0237] As an example, the power control circuit PCC may first transmit a power activation signal for driving a power circuit of a display driving device having a maximum current consumption value, but is not limited thereto. Fig. 27 and Fig.29For example, the current consumption value calculated based on the current value input to the power control circuit PCC may be 1.5 A for the first display driving device DRD1, 1.7 A for the second display driving device DRD2, 0.7 A for the third display driving device DRD, and 0.8 A for the fourth display driving device DRD4. In an embodiment, based on the determined time interval I8 between the power activation signals, the power control circuit PCC may first send a second power activation signal for driving the second power circuit of the second display driving device DRD2 having the largest current consumption value.

[0238] Reference Fig. 27 and Fig.30 , for example, the current consumption value calculated based on the current value input to the power control circuit PCC may be 1.5A for the first display driving device DRD1, 1.7A for the second display driving device DRD2, 0.7A for the third display driving device DRD3, and 0.8A for the fourth display driving device DRD4. In an embodiment, based on the determined time intervals I8 and I9 between the power activation signals, the power control circuit PCC may later send a second power activation signal for driving the second power circuit of the second display driving device DRD2 having the largest current consumption value and a first power activation signal for driving the first power circuit of the first display driving device DRD1 having the second largest current consumption value. Specifically, the power control circuit PCC may send the second power activation signal for driving the second power circuit of the second display driving device DRD2 having the largest current consumption value last, but is not limited thereto.

[0239] In an embodiment, a third power activation signal for driving a third power circuit of a third display driving device DRD3 and a fourth power activation signal for driving a fourth power circuit of a fourth display driving device DRD4 may be sent first, and then a first power activation signal may be sent at a first time interval I9, and then a second power activation signal may be sent at a second time interval I8. However, the present disclosure is not limited thereto, and the third power activation signal and the fourth power activation signal may be sent first, and then a second power activation signal may be sent at a first time interval I9, and then a first power activation signal may be sent at a second time interval I8.

[0240] Reference Fig. 27 and Fig.31For example, the current consumption value calculated based on the current value input to the power control circuit PCC may be 1.5 A for the first display driving device DRD1, 1.7 A for the second display driving device DRD2, 0.7 A for the third display driving device DRD3, and 0.8 A for the fourth display driving device DRD4. In an embodiment, based on the determined time intervals I8, I9, and I10 between the power activation signals, the power control circuit PCC may later transmit a second power activation signal for driving the second power circuit of the second display driving device DRD2 having the largest current consumption value, a first power activation signal for driving the first power circuit of the first display driving device DRD1 having the second largest current consumption value, and a fourth power activation signal for driving the fourth power circuit of the fourth display driving device DRD4 having the third largest current consumption value.

[0241] In an embodiment, a third power activation signal for driving a third power circuit of a third display driving device DRD3 may be sent first, and then a fourth power activation signal for driving a fourth power circuit of a fourth display driving device DRD4 may be sent at a fourth time interval I10, and then a first power activation signal may be sent at a first time interval I9, and then a second power activation signal may be sent at a second time interval I8. As an example, the first time interval I9 may be greater than the fourth time interval I10 and less than the second time interval I8, but is not limited thereto. However, the present disclosure is not limited thereto, and the second power activation signal may be sent first, and then the first power activation signal may be sent at a fourth time interval I10, and then the fourth power activation signal may be sent at a first time interval I9, and then the third power activation signal may be sent at a second time interval I8.

[0242] In the display driving device according to the present embodiment, when there is a time interval between the power activation signals, the transmission order of the power activation signals can be appropriately changed according to the operator.

[0243] Fig.32 is a flowchart illustrating a display driving method according to an exemplary embodiment of the present disclosure.

[0244] Reference Fig.32 The display driving method may include: receiving, by a power control circuit, a timing signal synchronized with an image signal and generating a sensing signal (eg, operation S1 ).

[0245] The display driving method may further include sensing a first current by a first sensing circuit in response to a sensing signal and sensing a second current by a second sensing circuit in response to the sensing signal (eg, operation S2 ).

[0246] The display driving method may further include converting the sensed first current into a digital value and sending the converted first current to a power control circuit, and converting the sensed second current into a digital value and sending the converted second current to the power control circuit (eg, operation S3).

[0247] The display driving method may further include: determining, by the power control circuit, whether at least one of the first current and the second current converted into digital values ​​is greater than or equal to a preset threshold (eg, operation S4 ).

[0248] The display driving method may further include: when at least one of the first current and the second current is greater than or equal to a preset threshold, increasing, by the power control circuit, a time interval between the first power activation signal and the second power activation signal.

[0249] The display driving method may also include: a first power supply circuit receiving a first power activation signal and supplying power to a first drive circuit for driving pixels of a first display panel and a first control circuit for controlling the first drive circuit, and a second power supply circuit receiving a second power activation signal and supplying power to a second drive circuit for driving pixels of a second display panel and a second control circuit for controlling the second drive circuit (for example, operation S5).

[0250] According to the present disclosure, in a display device including a plurality of power supply circuits, when driving power is applied from a main power supply circuit to the plurality of power supply circuits, electromagnetic interference (EMI) measured at an external power supply device may be reduced.

[0251] According to the present disclosure, in a display device including a plurality of display driving devices, it is possible to reduce noise measured at each display driving device and minimize increase in noise due to overlap of noise.

[0252] Since the contents of the present disclosure described in the above technical problems, technical solutions and beneficial effects do not specify the essential features of the claims, the scope of the claims is not limited by the items described in the contents of the present disclosure.

[0253] Although the embodiments of the present disclosure have been described in more detail with reference to the accompanying drawings, the present disclosure is not necessarily limited to these embodiments, and various modifications may be made without departing from the technical spirit of the present disclosure. Therefore, the embodiments disclosed in the present disclosure are not intended to limit the technical spirit of the present disclosure, but are intended to describe the technical spirit of the present disclosure, and the scope of the technical spirit of the present disclosure is not limited to these embodiments. Therefore, it should be understood that the above-mentioned embodiments are illustrative and non-restrictive in all aspects. The scope of the present disclosure should be interpreted according to the attached claims, and all technical spirits within the equivalent scope should be interpreted as being included within the scope of the present disclosure.

[0254] CROSS-REFERENCE TO RELATED APPLICATIONS

[0255] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0173180, filed on Dec. 4, 2023, the disclosure of which is hereby incorporated by reference in its entirety as if fully set forth herein.

Claims

1. A display driving device, comprising: a first power circuit, the first power circuit being configured to supply power to a first drive circuit and a first control circuit upon receiving a first power activation signal, the first drive circuit being configured to drive pixels of a first display panel, and the first control circuit being configured to control the first drive circuit; a second power supply circuit, the second power supply circuit being configured to supply power to a second drive circuit and a second control circuit upon receiving a second power activation signal, the second drive circuit being configured to drive pixels of a second display panel, and the second control circuit being configured to control the second drive circuit; a first sensing circuit configured to sense a first current input to the first power circuit; a second sensing circuit configured to sense a second current input to the second power circuit; as well as A power control circuit is configured to increase a time interval between the first power activation signal and the second power activation signal when at least one of the first current and the second current is greater than or equal to a preset threshold.

2. The display driving device according to claim 1, wherein: The first sensing circuit is provided between a main power supply circuit and the first power supply circuit, and the second sensing circuit is provided between the main power supply circuit and the second power supply circuit.

3. The display driving device according to claim 1, wherein: The first power activation signal activates a first pulse width modulation signal generated by the first power circuit, and The second power supply activation signal activates a second pulse width modulation signal generated by the second power supply circuit.

4. The display driving device according to claim 3, wherein: The first pulse width modulation signal suppresses fluctuations in an output voltage of the first power supply circuit that is input to the first drive circuit and the first control circuit, and The second pulse width modulation signal suppresses fluctuations in an output voltage of the second power supply circuit that is input to the second drive circuit and the second control circuit.

5. The display driving device according to claim 3, wherein: A time interval between the first power activation signal and the second power activation signal is determined by a frequency of the first pulse width modulation signal and a duty cycle of the first pulse width modulation signal.

6. The display driving device according to claim 4, wherein: When the duty cycle of the first pulse width modulation signal is K%, the time interval is in the range of 0.2K% to 0.6K% of one cycle of the first pulse width modulation signal, and 0≤K≤100.

7. The display driving device according to claim 1, wherein: The first power supply circuit includes a 1-1 power supply circuit configured to supply power to the first drive circuit and a 1-2 power supply circuit configured to supply power to the first control circuit, and The second power supply circuit includes a 2-1 power supply circuit configured to supply power to the second drive circuit and a 2-2 power supply circuit configured to supply power to the second control circuit.

8. The display driving device according to claim 1, wherein: The first driving circuit includes a 1-1 driving circuit, a 1-2 driving circuit and a 1-3 driving circuit, and the second driving circuit includes a 2-1 driving circuit, a 2-2 driving circuit and a 2-3 driving circuit, The first power supply circuit includes a 1-1 power supply circuit configured to supply power to the first control circuit, a 1-2 power supply circuit configured to supply power to the 1-1 drive circuit, a 1-3 power supply circuit configured to supply power to the 1-2 drive circuit, and a 1-4 power supply circuit configured to supply power to the 1-3 drive circuit, and The second power supply circuit includes a 2-1 power supply circuit configured to supply power to the second control circuit, a 2-2 power supply circuit configured to supply power to the 2-1 drive circuit, a 2-3 power supply circuit configured to supply power to the 2-2 drive circuit, and a 2-4 power supply circuit configured to supply power to the 2-3 drive circuit.

9. The display driving device according to claim 1, further comprising: a first analog-to-digital converter configured to convert the sensed first current into a digital value and send the converted first current to the power control circuit; as well as a second analog-to-digital converter configured to convert the sensed second current into a digital value and send the converted second current to the power control circuit.

10. The display driving device according to claim 9, wherein: The first analog-to-digital converter is disposed between the power control circuit and the first sensing circuit, and the second analog-to-digital converter is disposed between the power control circuit and the second sensing circuit.

11. The display driving device according to claim 1, wherein: The power control circuit receives a timing signal synchronized with an image signal and generates a sensing signal. The first sensing circuit senses the first current in an active section with a frame section as a cycle in response to the sensing signal, and The second sensing circuit senses the second current in an active section with a frame section as a cycle in response to the sensing signal.

12. The display driving device according to claim 11, wherein: The timing signal includes at least one of a gate timing control signal, a data enable signal, a dot clock signal, a vertical synchronization signal, and a horizontal synchronization signal.

13. The display driving device according to claim 11, wherein: The timing signal includes a gate timing control signal, and The frequency of the sensing signal is determined according to the frequency of the gate timing control signal.

14. The display driving device according to claim 11, wherein: The timing signal includes a dot clock signal, and The frequency of the sensing signal is determined according to the frequency of the dot clock signal.

15. The display driving device according to claim 11, wherein: A time interval determined by sensing in an active section of an Nth frame section is reflected to a blank section of an N+1th frame section, N being a natural number of 1 or more, and In the blank section of the N+1th frame section, the first power activation signal and the second power activation signal with the time interval therebetween are input to the first power circuit and the second power circuit, respectively.

16. The display driving device according to claim 1, wherein: The preset threshold value is an arithmetic mean value of a plurality of currents input to each of the first power supply circuit and the second power supply circuit.

17. A display device, comprising: main power supply circuit; multiple display panels; a plurality of power supply circuits configured to supply power to a plurality of drive circuits and a plurality of control circuits, the plurality of drive circuits configured to drive pixels of the plurality of display panels respectively, and the plurality of control circuits configured to control the plurality of drive circuits respectively; a plurality of sensing circuits, each sensing circuit being configured to sense a current input to one of the plurality of power circuits; as well as A power control circuit is configured to increase at least one time interval among time intervals between a plurality of power activation signals input to the plurality of power circuits when at least one current among a plurality of currents is greater than or equal to a preset threshold.

18. The display device according to claim 17, wherein: The plurality of sensing circuits are disposed between the main power supply circuit and the plurality of power supply circuits.

19. The display device according to claim 17, wherein: The plurality of power supply circuits include a first power supply circuit, a second power supply circuit and a third power supply circuit, The plurality of power activation signals include a first power activation signal for activating a first pulse width modulation signal of the first power circuit, a second power activation signal for activating a second pulse width modulation signal of the second power circuit, and a third power activation signal for activating a third pulse width modulation signal of the third power circuit, and The power control circuit increases a time interval between the first power activation signal and the third power activation signal and a time interval between the second power activation signal and the third power activation signal.

20. The display device according to claim 19, wherein: The power control circuit increases a time interval between the first power activation signal and the second power activation signal.

21. The display device according to claim 17, wherein: The preset threshold value is an arithmetic mean value of a plurality of currents input to each of the plurality of power supply circuits.

22. A display device, comprising: an external power supply comprising a main power supply circuit configured to output a voltage; as well as a display driving device, the display driving device being operated by receiving the voltage from the external power supply device, Wherein, the display driving device comprises: a first power supply circuit configured to supply power to a first drive circuit and a first control circuit upon receiving a first power activation signal, the first drive circuit being configured to drive pixels of a first display panel, and the first control circuit being configured to control the first drive circuit; and a second power supply circuit, the second power supply circuit being configured to supply power to a second drive circuit and a second control circuit upon receiving a second power activation signal, the second drive circuit being configured to drive pixels of a second display panel, the second control circuit being configured to control the second drive circuit, and The external power supply device comprises: a first sensing circuit disposed between the main power supply circuit and the first power supply circuit and configured to sense a first current input to the first power supply circuit; a second sensing circuit provided between the main power supply circuit and the second power supply circuit and configured to sense a second current input to the second power supply circuit; and A power control circuit is configured to increase a time interval between the first power activation signal and the second power activation signal when at least one of the first current and the second current is greater than or equal to a preset threshold.

23. A display device, comprising: an external power supply comprising a main power supply circuit configured to output a voltage; as well as a display driving device, the display driving device being operated by receiving the voltage from the external power supply device, Wherein, the display driving device comprises the display driving device according to any one of claims 1 to 16.

24. A display driving method, the display driving method comprising the following steps: The power control circuit receives a timing signal synchronized with the image signal and generates a sensing signal; sensing a first current by a first sensing circuit in response to the sensing signal; sensing a second current by a second sensing circuit in response to the sensing signal; The first control circuit controls the first driving circuit when receiving the first power activation signal; The second control circuit controls the second driving circuit when receiving the second power activation signal; as well as When at least one of the first current and the second current is greater than or equal to a preset threshold, the time interval between the first power activation signal and the second power activation signal is increased.

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