Pixel and display device including same

Abstract

The invention relates to a pixel and a display device including the same. The pixel includes: a first transistor including a first electrode and a second electrode connected to a first node and a second node, respectively, and a gate electrode connected to a third node; a second transistor connected between the data line and the third node, and including a gate electrode; a third transistor connected between the first power line and the first node, and including a gate electrode connected to the emission control line; a fourth transistor including a first electrode connected to the second node, a second electrode connected to a third power line, and a gate electrode; and a light emitting element connected between the second node and the second power line. The second power voltage has a first voltage level during the transmission period. The second power voltage has a second voltage level during a degradation prevention period after the emission period. The second voltage level is higher than the first voltage level.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2023-0174682, filed on December 5, 2023, and all benefits obtained from the application, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0002] Various embodiments of the present disclosure relate to a pixel and a display device including the pixel. Background Art

[0003] As information technology develops, the importance of display devices, which are a connection medium between users and information, has been emphasized. Due to the importance of display devices, the use of various types of display devices, such as liquid crystal display devices and organic light emitting display devices, has increased.

[0004] A head-mounted display device (“HMD”) has been developed. The head-mounted display device (“HMD”) is a display device that allows a user to wear it in the form of glasses or a helmet, and is used to create a virtual reality (“VR”) or augmented reality (“AR”) experience in which a focus is formed at a close distance in front of the user's eyes. The head-mounted display device adopts a high-resolution panel, and therefore, it is desirable to prevent degradation of pixels that can be applied to the high-resolution panel. Summary of the invention

[0005] Various embodiments of the present disclosure relate to a pixel applicable to a high-resolution panel and a display device including the pixel.

[0006] An embodiment of the present disclosure provides a pixel, including: a first transistor, including a first electrode connected to a first node, a second electrode connected to a second node, and a gate electrode connected to a third node; a second transistor, connected between a data line and a third node, and including a gate electrode electrically connected to a first sub-gate line; a third transistor, connected between a first power line to which a first power voltage is supplied and a first node, and including a gate electrode electrically connected to an emission control line; a fourth transistor, including a first electrode connected to a second node, a second electrode electrically connected to a third power line to which an initialization voltage is supplied, and a gate electrode electrically connected to a second sub-gate line; and a light-emitting element, connected between a second node and a second power line to which a second power voltage is supplied. During an emission period in which the light-emitting element emits light at a brightness corresponding to a current supplied from the first transistor, the second power voltage has a first voltage level. During a degradation prevention period after the emission period, the second power voltage has a second voltage level. The second voltage level is higher than the first voltage level.

[0007] In an embodiment, one frame period may include a horizontal period, an emission period, and a degradation prevention period. During the degradation prevention period, the third transistor and the second transistor may be set to an off state, and the first transistor and the fourth transistor may be set to an on state.

[0008] In an embodiment, the start time point of the degradation prevention period may correspond to the end time point of the emission period. The end time point of the degradation prevention period may correspond to the end time point of the frame period.

[0009] In an embodiment, the horizontal period may include a first period and a second period. During the first period, the first to fourth transistors may be set to an on state. During a second period after the first period, the third transistor may be set to an off state, and the first, second, and fourth transistors may be set to an on state.

[0010] In an embodiment, during the emission period after the horizontal period, the second transistor and the fourth transistor may be set to a turn-off state, and the first transistor and the third transistor may be set to a turn-on state.

[0011] In an embodiment, the second voltage level may be higher than a sum of a voltage level of the initialization voltage and a voltage level of a threshold voltage of the light emitting element.

[0012] In an embodiment, the ratio of the emission period to the frame period may be a value ranging from 0.1 to 0.4.

[0013] In an embodiment, each of the first to fourth transistors may be a P-type transistor.

[0014] In an embodiment, the pixel may further include: a first capacitor connected between the first node and the third node; and a second capacitor connected between the second node and the third node.

[0015] An embodiment of the present disclosure provides a display device including pixels connected to gate lines, data lines, and emission control lines. Among the pixels, a pixel located on an i-th pixel row (where i is an integer of 1 or greater) and a j-th pixel column (where j is an integer of 1 or greater) includes: a first transistor including a first electrode connected to a first node, a second electrode connected to a second node, and a gate electrode connected to a third node; a second transistor connected between a j-th data line among the data lines and the third node, and configured to be turned on when a first sub-gate signal having a turn-on level is supplied to a first sub-gate line of an i-th gate line among the gate lines; a third transistor connected between the first node and a first power line to which a first power voltage is supplied, and configured to be turned on when an emission control signal having a turn-on level is supplied to an i-th emission control line among the emission control lines; a fourth transistor including a first electrode connected to a second node and a second electrode connected to a third power line to which an initialization voltage is supplied, and configured to be turned on when a second sub-gate signal having a turn-on level is supplied to a second sub-gate line of an i-th gate line among the gate lines; and a light-emitting element connected between the second node and a second power line to which a second power voltage is supplied. During an emission period in which the light emitting element emits light at a brightness corresponding to the current supplied from the first transistor, the second power voltage has a first voltage level. After the emission period, the second power voltage has a second voltage level.

[0016] The second voltage level is higher than the first voltage level.

[0017] In an embodiment, one frame period may include a horizontal period, an emission period, and a degradation prevention period. During the degradation prevention period, the third transistor and the second transistor may be set to an off state, and the first transistor and the fourth transistor may be set to an on state.

[0018] In an embodiment, the start time point of the degradation prevention period may correspond to the end time point of the emission period. The end time point of the degradation prevention period may correspond to the end time point of the frame period.

[0019] In an embodiment, the horizontal period may include a first period and a second period. During the first period, the first to fourth transistors may be set to an on state. During a second period after the first period, the third transistor may be set to an off state, and the first, second, and fourth transistors may be set to an on state.

[0020] In an embodiment, during the emission period after the horizontal period, the second transistor and the fourth transistor may be set to a turn-off state, and the first transistor and the third transistor may be set to a turn-on state.

[0021] In an embodiment, the second voltage level may be higher than a sum of a voltage level of the initialization voltage and a voltage level of a threshold voltage of the light emitting element.

[0022] In an embodiment, the ratio of the emission period to the frame period may be a value ranging from 0.1 to 0.4.

[0023] In an embodiment, each of the first to fourth transistors may be a P-type transistor.

[0024] In an embodiment, the pixel may further include: a first capacitor connected between the first node and the third node; and a second capacitor connected between the second node and the third node. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 is a diagram illustrating a transistor according to an embodiment of the present disclosure.

[0026] Figure 2 is a block diagram illustrating a display device according to an embodiment of the present disclosure.

[0027] Figure 3 It is a graphic Figure 2 A block diagram of an embodiment of any one of the sub-pixels.

[0028] Figure 4 It is a graphic Figure 3 A circuit diagram of an embodiment of a sub-pixel is shown in FIG.

[0029] Figure 5 It is a graphic driver Figure 4 2 is a waveform diagram of an embodiment of a sub-pixel method shown in FIG.

[0030] Figures 6 to 9 is a diagram in response to Figure 5 Circuit diagram of the sub-pixel operation process of the signal. DETAILED DESCRIPTION

[0031] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement the present invention. The present disclosure can be embodied in various forms and is not limited to the embodiments to be described herein.

[0032] In the drawings, parts unrelated to the present disclosure are omitted to clarify the description of the present disclosure, and the same reference numerals are used to designate the same or similar components throughout the different drawings.

[0033] It will be understood that when an element is referred to as "coupled" or "connected" to another element, the element may be directly coupled or connected to the other element, or an intermediate element may be present between the element and the other element. The terms used herein are only for the purpose of describing a specific embodiment and are not intended to be limited. In the specification, when an element is referred to as "comprising" or "including" a component, the element does not exclude another component, but may further include other components unless the context clearly indicates otherwise. "At least one of X, Y and Z" and "at least one selected from the group consisting of X, Y and Z" may be interpreted as any combination of only X, only Y, only Z or two or more of X, Y and Z (e.g., XYZ, XYY, YZ and ZZ). As used herein, the term "and / or" may include any combination and all combinations of one or more of the items listed in association.

[0034] Although the terms "first", "second", etc. can be used herein to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another element. Therefore, the first element discussed below can be referred to as the second element without departing from the teachings of the present disclosure.

[0035] Figure 1 is a diagram illustrating a transistor 10 according to an embodiment of the present disclosure.

[0036] refer to Figure 1 , the transistor 10 according to an embodiment of the present disclosure may include a first electrode 12, a second electrode 14, a gate electrode 16, and a body electrode 18. In an embodiment, for example, the transistor 10 may be a metal oxide semiconductor field effect transistor ("MOSFET"). The transistor 10 (e.g., MOSFET) including the body electrode 18 is suitable for realizing high-resolution pixels due to its reduced mounting area.

[0037] The transistor 10 may be disposed on a silicon wafer. For example, the panel may be implemented by stacking layers such as a transistor layer, an emission layer, and a cover layer on a silicon wafer. However, the above description is exemplary, and the transistor 10 may be disposed on various known substrates (e.g., a glass substrate).

[0038] The first electrode 12 of the transistor 10 may be set as a source electrode (or a drain electrode), and the second electrode 14 of the transistor 10 may be set as a drain electrode (or a source electrode). In the case where the transistor 10 includes a body electrode 18, the threshold voltage of the transistor 10 may be changed by the body effect. The body effect refers to a change in the threshold voltage of the transistor 10 due to a voltage difference between the body electrode 18 and the first electrode 12 of the transistor 10.

[0039] Figure 2is a block diagram illustrating an embodiment of a display device 100 .

[0040] refer to Figure 2 , the display device 100 may include a display panel 110 , a gate driver 120 , a data driver 130 , a voltage generator 140 , and a controller 150 .

[0041] The display panel 110 may include sub-pixels SP. The sub-pixels SP may be connected to the gate driver 120 through first to m-th gate lines GL1 to GLm. The sub-pixels SP may be connected to the data driver 130 through first to n-th data lines DL1 to DLn.

[0042] Each of the sub-pixels SP may include at least one light emitting element configured to generate light. Therefore, each of the sub-pixels SP may generate light of a specific color such as red, green, blue, cyan, magenta, or yellow. Two or more sub-pixels among the sub-pixels SP may form one pixel PXL. For example, Figure 2 As shown in the figure, three sub-pixels SP may form one pixel PXL.

[0043] The gate driver 120 may be connected to the sub-pixels SP arranged in the row direction through the first to m-th gate lines GL1 to GLm. The gate driver 120 may output a gate signal to the first to m-th gate lines GL1 to GLm in response to a gate control signal GCS. In an embodiment, the gate control signal GCS may include a start signal indicating the start of each frame and / or a horizontal synchronization signal for outputting a gate signal in synchronization with a timing of applying a data signal, etc.

[0044] In an embodiment, first to m-th emission control lines EL1 to ELm connected to the sub-pixels SP in the row direction may be further provided. In this case, the gate driver 120 may include an emission control driver configured to control the first to m-th emission control lines EL1 to ELm. The emission control driver may operate under the control of the controller 150.

[0045] The gate driver 120 may be disposed on one side of the display panel 110. However, the embodiment is not limited to the above example. For another example, the gate driver 120 may be divided into two or more drivers that are physically and / or logically distinguished from each other. The gate driver 120 may be disposed on a first side of the display panel 110 and on a second side of the display panel 110 opposite to the first side. Therefore, depending on the embodiment, the gate driver 120 may be disposed around the display panel 110 in various forms.

[0046] The data driver 130 may be connected to the sub-pixels SP arranged in the column direction through the first to nth data lines DL1 to DLn. The data driver 130 may receive image data DATA and a data control signal DCS from the controller 150. The data driver 130 may operate in response to the data control signal DCS. In an embodiment, the data control signal DCS may include a source start pulse, a source shift clock, and / or a source output enable signal, etc.

[0047] The data driver 130 may apply a data signal having a grayscale voltage corresponding to the image data DATA to the first to nth data lines DL1 to DLn using a voltage from the voltage generator 140. When a gate signal is applied to each of the first to mth gate lines GL1 to GLm, a data signal corresponding to the image data DATA may be applied to the data lines DL1 to DLm. Therefore, the corresponding sub-pixel SP may generate light corresponding to the data signal. As a result, an image may be displayed on the display panel 110.

[0048] In an embodiment, the gate driver 120 and the data driver 130 may include complementary metal oxide semiconductor (“CMOS”) circuit elements.

[0049] The voltage generator 140 may operate in response to a voltage control signal VCS provided from the controller 150. The voltage generator 140 is configured to generate a plurality of voltages and provide the generated voltages to components of the display device 100. For example, the voltage generator 140 may receive an input voltage from an external device provided outside the display device 100, adjust the received voltage, and adjust the adjusted voltage, thereby generating the plurality of voltages.

[0050] The voltage generator 140 may generate a first power voltage VDD and a second power voltage VSS. The generated first power voltage VDD and second power voltage VSS may be provided to the sub-pixel SP. The first power voltage VDD may have a relatively high voltage level. Compared to the first power voltage VDD, the second power voltage VSS may have a low voltage level. In other embodiments, the first power voltage VDD or the second power voltage VSS may be provided by an external device of the display device 100.

[0051] In an embodiment, the voltage generator 140 may generate a voltage having a first voltage level ( Figure 5 The second power voltage VSS having a second voltage level ( Figure 5 Each of the first voltage level V1 and the second voltage level V2 may be lower than the voltage level of the first power voltage VDD. The second voltage level V2 may be higher than the first voltage level V1.

[0052] In addition, the voltage generator 140 may generate various voltages. For example, the voltage generator 140 may generate an initialization voltage to be applied to the sub-pixel SP. For example, during a sensing operation for sensing electrical characteristics of a transistor and / or a light-emitting element of the sub-pixel SP, a specific reference voltage may be applied to each of the first to nth data lines DL1 to DLn. The voltage generator 140 may generate the reference voltage.

[0053] The controller 150 may control the overall operation of the display device 100. The controller 150 may receive input image data IMG and a control signal CTRL for controlling an operation of displaying the input image data IMG from an external device. The controller 150 may provide a gate control signal GCS, a data control signal DCS, and a voltage control signal VCS in response to the control signal CTRL.

[0054] The controller 150 may convert the input image data IMG to fit the display device 100 or the display panel 110 and then output the image data DATA. In an embodiment, the controller 150 may align the input image data IMG by row to fit the sub-pixels SP and then output the image data DATA.

[0055] Two or more components of the data driver 130, the voltage generator 140, and the controller 150 may be mounted on a single integrated circuit. Figure 2 As shown in FIG. 1 , the data driver 130, the voltage generator 140, and the controller 150 may be included in the driver integrated circuit DIC. In this case, the data driver 130, the voltage generator 140, and the controller 150 may be components that are functionally separated from each other in a single driver integrated circuit DIC. In other embodiments, at least one of the data driver 130, the voltage generator 140, and the controller 150 may be provided as a component separate from the driver integrated circuit DIC.

[0056] Figure 3 It is a graphic Figure 2 A block diagram of an embodiment of any one of the sub-pixels SP. Figure 3 In the figure, Figure 2 Among the sub-pixels SP, the sub-pixel SPij is arranged on the i-th row (where i is an integer of 1 or greater, specifically, an integer equal to or greater than 1 and equal to or less than m) and the j-th column (where j is an integer equal to or greater than 1 and equal to or less than n).

[0057] refer to Figure 3 , the sub-pixel SPij may include a sub-pixel circuit SPC and a light emitting element LD.

[0058] The light emitting element LD is connected between the first power voltage node VDDN and the second power voltage node VSSN. Here, the first power voltage node VDDN may be provided to transmit Figure 2 The second power voltage node VSSN may be provided to transmit Figure 2 A node of a second power voltage VSS is connected to the node.

[0059] The anode electrode AE ​​of the light emitting element LD may be connected to the first power voltage node VDDN through the sub-pixel circuit SPC. The cathode electrode CE of the light emitting element LD may be connected to the second power voltage node VSSN. In an embodiment, for example, the anode electrode AE ​​of the light emitting element LD may be connected to the first power voltage node VDDN through one or more transistors included in the sub-pixel circuit SPC.

[0060] The sub-pixel circuit SPC can be connected to Figure 2 The i-th gate line GLi among the first to m-th gate lines GL1 to GLm, Figure 2 The i-th emission control line ELi among the first to m-th emission control lines EL1 to ELm and Figure 2 The sub-pixel circuit SPC is configured to control the light emitting element LD in response to a signal received through the above-mentioned signal line.

[0061] The sub-pixel circuit SPC may operate in response to a gate signal received through the i-th gate line GLi. The i-th gate line GLi may include one or more sub-gate lines. Figure 3 As shown in the figure, the i-th gate line GLi may include a first sub-gate line SGL1 and a second sub-gate line SGL2. The sub-pixel circuit SPC may operate in response to a gate signal received through the first sub-gate line SGL1 and the second sub-gate line SGL2. Therefore, in the case where the i-th gate line GLi includes two or more sub-gate lines, the sub-pixel circuit SPC may operate in response to a gate signal received through the corresponding sub-gate line.

[0062] The sub-pixel circuit SPC may operate in response to an emission control signal received through the i-th emission control line ELi. In an embodiment, the i-th emission control line ELi may include one or more sub-emission control lines. In the case where the i-th emission control line ELi includes two or more sub-emission control lines, the sub-pixel circuit SPC may operate in response to an emission control signal received through the corresponding sub-emission control line.

[0063] The sub-pixel circuit SPC may receive a data signal through the j-th data line DLj. The sub-pixel circuit SPC may store a voltage corresponding to the data signal in response to at least one of the gate signals received through the first sub-gate line SGL1 and the second sub-gate line SGL2. The sub-pixel circuit SPC may adjust a current flowing from the first power voltage node VDDN through the light-emitting element LD to the second power voltage node VSSN according to the stored voltage in response to the emission control signal received through the i-th emission control line ELi. Therefore, the light-emitting element LD may emit light at a brightness corresponding to the data signal.

[0064] Figure 4 It is a graphic Figure 3 Circuit diagram of an embodiment of a sub-pixel SPij.

[0065] refer to Figure 4 , the sub-pixel SPij may include a sub-pixel circuit SPC and a light emitting element LD.

[0066] The light emitting element LD may be connected between the first power line PL1 and the second power line PL2. In an embodiment, for example, the first electrode (or anode electrode) of the light emitting element LD may be electrically connected to the first power line PL1 via the second node N2, the first transistor M1, the first node N1, and the third transistor M3. The second electrode (or cathode electrode) of the light emitting element LD may be electrically connected to the second power line PL2. The light emitting element LD may generate light of a specific brightness corresponding to the amount of current supplied from the first power line PL1 to the second power line PL2 via the sub-pixel circuit SPC.

[0067] An organic light emitting diode may be selected as the light emitting element LD. In addition, an inorganic light emitting diode such as a micro light emitting diode ("LED") or a quantum dot light emitting diode may be selected as the light emitting element LD. The light emitting element LD may be an element formed of a combination of an organic material and an inorganic material. Although Figure 4 The sub-pixel SPij is illustrated as including a single light emitting element LD, but the sub-pixel SPij in the embodiment may include a plurality of light emitting elements LD. The plurality of light emitting elements LD may be connected to each other in series, in parallel, or in series and parallel.

[0068] The sub-pixel circuit SPC can be connected to the i-th gate line GLi, the i-th emission control line ELi and the j-th data line DLj. The sub-pixel circuit SPC can also be connected to the first power line PL1, the second power line PL2 and the third power line PL3. In an embodiment, the sub-pixel circuit SPC can be connected to the first power line PL1 through the first power line PL2. Figure 3 The sub-pixel circuit SPC can be connected to the first power voltage node VDDN through the second power line PL2. Figure 3The sub-pixel circuit SPC may be connected to a node configured to transmit an initialization voltage Vint through a third power line PL3.

[0069] The sub-pixel circuit SPC may include a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a first capacitor C1, and a second capacitor C2.

[0070] In an embodiment, each of the first to fourth transistors M1 to M4 may include a body electrode 18 (see Figure 1 ) transistor. For example, each of the first to fourth transistors M1 to M4 may be formed by a metal oxide semiconductor field effect transistor ("MOSFET"). In this case, the first to fourth transistors M1 to M4 may be mounted in a relatively small area, thereby enabling the sub-pixel SPij to be applied to a high-resolution panel. In an embodiment, the body electrode 18 of each of the first to fourth transistors M1 to M4 may be supplied with a first power voltage VDD. For example, the body electrode 18 of each of the first to fourth transistors M1 to M4 may be electrically connected to a first power line PL1.

[0071] In an embodiment, each of the first to fourth transistors M1 to M4 may be a P-type transistor. However, this is exemplary, and in another embodiment, at least one of the first to fourth transistors M1 to M4 may be replaced with an N-type transistor.

[0072] The first transistor M1 may include a first electrode connected to a first node N1 and a second electrode connected to a second node N2. Here, the term "connection" means electrically linked or joined. The gate electrode of the first transistor M1 may be connected to a third node N3. The first node N1 may refer to a node to which the second electrode of the third transistor M3 is connected. The second node N2 may refer to a node to which the first electrode (i.e., the anode electrode) of the light emitting element LD is connected. The first transistor M1 may control the amount of current supplied from the first power line PL1 for supplying the first power voltage VDD to the second power line PL2 for supplying the second power voltage VSS via the light emitting element LD in response to the voltage of the third node N3.

[0073] The second transistor M2 may be connected between the data line DLj and the third node N3. The gate electrode of the second transistor M2 may be electrically connected to the first sub-gate line SGL1. When the first sub-gate signal GW is supplied to the first sub-gate line SGL1, the second transistor M2 may be turned on to electrically connect the data line DLj with the third node N3.

[0074] A first electrode of the third transistor M3 may be electrically connected to the first power line PL1, and a second electrode of the third transistor M3 may be connected to the first node N1. A gate electrode of the third transistor M3 may be electrically connected to the emission control line ELi. The third transistor M3 may be turned on when the emission control signal EM is supplied to the emission control line ELi, and may be turned off when the emission control signal EM is not supplied to the emission control line ELi. If the third transistor M3 is turned off, the first power line PL1 and the first node N1 may be electrically disconnected.

[0075] The fourth transistor M4 may include a first electrode connected to the second node N2 and a second electrode electrically connected to the third power line PL3. The gate electrode of the fourth transistor M4 may be electrically connected to the second sub-gate line SGL2. When the second sub-gate signal EB is supplied to the second sub-gate line SGL2, the fourth transistor M4 may be turned on to electrically connect the second node N2 to the third power line PL3.

[0076] The first capacitor C1 may be connected between the first node N1 and the third node N3. The first capacitor C1 may be driven as a coupling capacitor, thereby transmitting a voltage change of the first node N1 to the third node N3. In addition, the first capacitor C1 may store a voltage of the third node N3.

[0077] The second capacitor C2 may be connected between the second node N2 and the third node N3. The second capacitor C2 may be driven as a coupling capacitor, thereby transmitting a voltage change of the second node N2 to the third node N3.

[0078] Figure 5 It is a graphic driver Figure 4 Waveform diagram of an embodiment of the method for sub-pixel SPij shown in FIG.

[0079] refer to Figure 2 , Figure 4 and Figure 5 , illustrates signals supplied to the subpixels SPij from the gate driver 120, the data driver 130, and the voltage generator 140 of the display device 100 during the frame period FR. The frame period FR may refer to a period in which an image of one screen is displayed on the display panel 110. The frame period FR may include first to fourth periods T1 to T4.

[0080] The first sub gate driver (not shown) of the gate driver 120 may supply a first sub gate signal GW for setting the second transistor M2 to a turn-on state to the first sub gate line SGL1 during the horizontal period 1H.

[0081] The second sub gate driver (not shown) of the gate driver 120 may supply a second sub gate signal EB for setting the fourth transistor M4 to a turn-on state to the second sub gate line SGL2 during the horizontal period 1H and the fourth period T4.

[0082] The emission control driver (not shown) of the gate driver 120 may supply the emission control signal EM for setting the third transistor M3 to a turn-on state to the emission control line ELi during the first period T1 and the third period T3.

[0083] The data driver 130 may supply a voltage of a data signal to the data line DLj during a horizontal period 1 H. The horizontal period 1 H may be divided into a first period T1 and a second period T2.

[0084] Under the control of the controller 150, the voltage generator 140 may supply the second power voltage VSS having the first voltage level V1 to the second power line PL2 during the first to third periods T1 to T3, and may supply the second power voltage VSS having the second voltage level V2 to the second power line PL2 during the fourth period T4.

[0085] The first period T1 may be a period in which the first power voltage VDD is applied to the first node N1, the initialization voltage Vint is supplied to the second node N2, and the voltage of the data signal is supplied to the third node N3. During the first period T1, the light emitting element LD may be initialized. During the first period T1, the first capacitor C1 and the second capacitor C2 may be initialized, and at the same time, the voltage level of the data signal supplied to the third node N3 may be stored. The first period T1 may be referred to as an "initialization period" and a "data signal writing period". The start time point of the first period T1 may correspond to the start time point of the frame period FR.

[0086] The second period T2 may be a period in which the initialization voltage Vint is supplied to the second node N2 and the voltage of the data signal is supplied to the third node N3. During the second period T2, a voltage corresponding to the threshold voltage of the first transistor M1 may be stored in the first capacitor C1. The second period T2 may be referred to as a "threshold voltage compensation period". The start time point of the second period T2 may correspond to the end time point of the first period T1.

[0087] During the third period T3, the first transistor M1 may control the amount of current flowing from the first power line PL1 for supplying the first power voltage VDD to the second power line PL2 for supplying the second power voltage VSS via the light emitting element LD in response to the voltage of the third node N3. During the third period T3, the light emitting element LD may emit light at a brightness corresponding to the amount of current supplied from the first transistor M1. The third period T3 may be referred to as an "emission period". The start time point of the third period T3 may correspond to the end time point of the second period T2.

[0088] The fourth period T4 may be a period in which the second power voltage VSS having a second voltage level V2 is supplied to the second electrode (ie, cathode electrode) of the light emitting element LD through the second power line PL2. The second voltage level V2 of the second power voltage VSS may be higher than the sum of the voltage level of the initialization voltage Vint and the threshold voltage of the light emitting element LD. When the second power voltage VSS having a second voltage level V2 is supplied to the second electrode (ie, cathode electrode) of the light emitting element LD through the second power line PL2, the charge captured in the light emitting element LD may be de-trapped. Therefore, the degradation of the light emitting element LD due to high current density may be effectively prevented. The second voltage level V2 of the second power voltage VSS may be referred to as a "reverse bias voltage". The fourth period T4 may be referred to as a "degradation prevention period" or a "blank period". The starting time point of the fourth period T4 may correspond to the ending time point of the third period T3. The ending time point of the fourth period T4 may correspond to the ending time point of the frame period FR.

[0089] In an embodiment, the duty cycle of the third period T3 may have a value ranging from 0.1 to 0.4. The duty cycle may be a ratio of the third period T3 to the frame period FR. In the case where the duty cycle of the third period T3 has a value ranging from 0.1 to 0.4, the effect of preventing degradation in the fourth period T4 may be enhanced. The duty cycle may be a rational number.

[0090] Figures 6 to 9 is a graphic response to Figure 5 Circuit diagram of the operation process of the sub-pixel SPij. Figures 6 to 9 The sub-pixel circuit SPC may correspond to Figure 4 Sub-pixel circuit SPC.

[0091] refer to Figure 6During the first period T1, the first sub-gate signal GW for setting the second transistor M2 to the on state is supplied to the first sub-gate line SGL1, and the second sub-gate signal EB for setting the fourth transistor M4 to the on state is supplied to the second sub-gate line SGL2. In addition, during the first period T1, the emission control signal EM for setting the third transistor M3 to the on state is supplied to the emission control line ELi. If the third transistor M3 is turned on, the first power voltage VDD is supplied to the first node N1.

[0092] If the second transistor M2 is turned on, the voltage of the data signal is supplied from the data line DLj to the third node N3. Here, the first capacitor C1 may be initialized by the voltage of the data signal and the first power voltage VDD. For example, during the first period T1, the first capacitor C1 may be charged with the voltage of the data signal and a voltage corresponding to the first power voltage VDD, regardless of the voltage charged in the previous period (or previous frame period).

[0093] If the fourth transistor M4 is turned on, the initialization voltage Vint is supplied to the second node N2. If the initialization voltage Vint is supplied to the second node N2, the light emitting element LD can be initialized. For example, if the initialization voltage Vint is supplied, the parasitic capacitance (not shown) of the light emitting element LD can be discharged. Here, the initialization voltage Vint can be set to a voltage at which the light emitting element LD is turned off (or does not emit light). As a result, the light emitting element LD can be set to a non-luminous state.

[0094] The second capacitor C2 may be initialized by the voltage of the data signal supplied to the third node N3 and the initialization voltage Vint supplied to the second node N2. For example, during the first period T1, the second capacitor C2 may be charged with the voltage of the data signal and a voltage corresponding to the initialization voltage Vint, regardless of the voltage charged in the previous period (or previous frame period).

[0095] During the first period T1, the current supplied from the first transistor M1 may be supplied to the third power line PL3 via the fourth transistor M4 in response to the voltage of the third node N3. Therefore, during the first period T1, the light emitting element LD may be maintained in a non-light emitting state.

[0096] refer to Figure 7 During the second period T2, the first transistor M1, the second transistor M2, and the fourth transistor M4 may be maintained in the on state. During the second period T2, the emission control signal EM for setting the third transistor M3 to the off state may be supplied to the emission control line ELi. If the third transistor M3 is turned off, the electrical connection between the first power line PL1 and the first node N1 may be interrupted.

[0097] Since the second transistor M2 is set to the on state during the second period T2, the voltage of the data signal is supplied from the data line DLj to the third node N3. In this case, the voltage of the first node N1 can be reduced from the first power voltage VDD to a voltage obtained by adding the absolute threshold voltage of the first transistor M1 to the voltage of the data signal.

[0098] In other words, during the second period T2, the third node N3 may be set to the voltage of the data signal, and the first node N1 may be set to a voltage obtained by adding the absolute threshold voltage of the first transistor M1 to the voltage of the data signal. Therefore, during the second period T2, the threshold voltage of the first transistor M1 may be stored in the first capacitor C1.

[0099] Since the fourth transistor M4 is set to the on state during the second period T2, the current supplied from the first node N1 to the second node N2 via the first transistor M1 can be supplied to the third power line PL3 via the fourth transistor M4. Therefore, during the second period T2, the light emitting element LD can be maintained in a non-light emitting state.

[0100] refer to Figure 8 During the third period T3, the first sub-gate signal GW for setting the second transistor M2 to the off state may be supplied to the first sub-gate line SGL1. During the third period T3, the second sub-gate signal EB for setting the fourth transistor M4 to the off state may be supplied to the second sub-gate line SGL2. During the third period T3, the emission control signal EM for setting the third transistor M3 to the on state may be supplied to the emission control line ELi.

[0101] Here, the first transistor M1 may control the amount of current supplied from the first power line PL1 for supplying the first power voltage VDD to the second power line PL2 for supplying the second power voltage VSS via the light emitting element LD in response to the voltage of the third node N3. During the third period T3, the light emitting element LD may generate light at a brightness corresponding to the amount of current supplied from the first transistor M1.

[0102] refer to Fig. 9, during the fourth period T4, the supply of the emission control signal EM for setting the third transistor M3 to the on state to the emission control line ELi is interrupted. Therefore, the third transistor M3 can be turned off. During the fourth period T4, the second sub-gate signal EB for setting the fourth transistor M4 to the on state can be supplied to the second sub-gate line SGL2. During the fourth period T4, the first sub-gate signal GW for setting the second transistor M2 to the on state is not supplied to the first sub-gate line SGL1. Therefore, the second transistor M2 can be maintained in the off state.

[0103] During the fourth period T4, the second power voltage VSS having the second voltage level V2 may be supplied to the second electrode (i.e., cathode electrode) of the light emitting element LD through the second power line PL2. When the second power voltage VSS having the second voltage level V2 is supplied to the second electrode (i.e., cathode electrode) of the light emitting element LD, the charges captured in the light emitting element LD may be de-trapped. Therefore, the degradation of the light emitting element LD may be effectively prevented.

[0104] Embodiments of the present disclosure may provide a pixel capable of preventing degradation due to light emission and a display device including the pixel.

[0105] However, the effects of the present disclosure are not limited to the above-described effects, and various modifications may be made without departing from the spirit and scope of the present disclosure.

[0106] Although the spirit and scope of the present disclosure are described by detailed exemplary embodiments, it should be noted that the embodiments described above are only illustrative and should not be considered as limiting. It should be understood by those skilled in the art that various changes, substitutions and modifications can be made herein without departing from the scope of the present disclosure defined by the claims.

[0107] The scope of the present disclosure is not limited by the detailed description of this specification, but should be defined by the claims. In addition, all changes or modifications of the present disclosure derived from the meaning and scope of the claims and their equivalents should be interpreted as being included in the scope of the present disclosure.

Claims

1. A pixel comprising: a first transistor including a first electrode connected to the first node, a second electrode connected to the second node, and a gate electrode connected to a third node; a second transistor connected between the data line and the third node and comprising a gate electrode electrically connected to the first sub-gate line; a third transistor connected between the first power line to which the first power voltage is supplied and the first node and including a gate electrode electrically connected to an emission control line; a fourth transistor including a first electrode connected to the second node, a second electrode electrically connected to a third power line to which an initialization voltage is supplied, and a gate electrode electrically connected to a second sub-gate line; as well as a light emitting element connected between the second node and a second power line to which a second power voltage is supplied, wherein, during an emission period in which the light emitting element emits light at a brightness corresponding to a current supplied from the first transistor, the second power voltage has a first voltage level, wherein, during a degradation prevention period after the transmission period, the second power voltage has a second voltage level, and The second voltage level is higher than the first voltage level.

2. The pixel according to claim 1, in, One frame period includes a horizontal period, the emission period, and the degradation prevention period, and During the degradation prevention period, the third transistor and the second transistor are set to an off state, and the first transistor and the fourth transistor are set to an on state.

3. The pixel according to claim 2, in, The start time point of the degradation prevention period corresponds to the end time point of the emission period, and Here, the end time point of the degradation prevention period corresponds to the end time point of the frame period.

4. The pixel according to claim 2, in, The horizontal period includes a first period and a second period. wherein, during the first period, the first to fourth transistors are set to the on state, and During the second period after the first period, the third transistor is set to the off state, and the first transistor, the second transistor and the fourth transistor are set to the on state.

5. The pixel according to claim 2, wherein: During the emission period after the horizontal period, the second transistor and the fourth transistor are set to the off state, and the first transistor and the third transistor are set to the on state.

6. The pixel according to claim 2, wherein: The second voltage level is higher than a sum of a voltage level of the initialization voltage and a voltage level of a threshold voltage of the light emitting element.

7. The pixel according to claim 2, wherein: The ratio of the emission period to the frame period is a value ranging from 0.1 to 0.

4.

8. The pixel according to claim 1, wherein: Each of the first to fourth transistors includes a P-type transistor.

9. The pixel according to any one of claims 1 to 8, further comprising: a first capacitor connected between the first node and the third node; as well as A second capacitor is connected between the second node and the third node.

10. A display device comprising pixels connected to a gate line, a data line and an emission control line, in, Among the pixels, the pixels located on the i-th pixel row and the j-th pixel column include: a first transistor including a first electrode connected to the first node, a second electrode connected to the second node, and a gate electrode connected to a third node; a second transistor connected between a j-th data line among the data lines and the third node, and configured to be turned on when a first sub-gate signal having a turn-on level is supplied to a first sub-gate line of an i-th gate line among the gate lines; a third transistor connected between the first node and a first power line to which a first power voltage is supplied and configured to be turned on when an emission control signal having the turn-on level is supplied to an i-th emission control line among the emission control lines; a fourth transistor including a first electrode connected to the second node and a second electrode connected to a third power line to which an initialization voltage is supplied, and configured to be turned on when a second sub-gate signal having the turn-on level is supplied to a second sub-gate line of the i-th gate line among the gate lines; and a light emitting element connected between the second node and a second power line to which a second power voltage is supplied, wherein i is an integer of 1 or greater, and j is an integer of 1 or greater, wherein, during an emission period in which the light emitting element emits light at a brightness corresponding to a current supplied from the first transistor, the second power voltage has a first voltage level, wherein, after the transmission period, the second power voltage has a second voltage level, and The second voltage level is higher than the first voltage level.

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