Manufacturing process and application of nanoscale multi-layer thin film resistor

Abstract

The invention relates to the technical field of microelectronic device manufacturing, discloses a manufacturing process of a nanoscale multilayer thin film resistor, and solves the problems of poor binding force, high residual stress, structural defects and the like in the traditional process through gradient buffer layer design, ion beam auxiliary sputtering and pulse laser annealing technologies. The resistor has an interface bonding force of 120-150 MPa and a residual stress sum lt of less than or equal to 50 MPa; and the density of pinholes is 10 / cm, so that the material is suitable for smart phones, tablet personal computers, high-performance computers, automotive electronic systems and aerospace electronic equipment.

Description

Technical Field

[0001] The present invention relates to the technical field of microelectronic device manufacturing, and in particular to a manufacturing process and application of a nanometer-level multilayer thin-film resistor with high reliability and stability. Background Art

[0002] The current manufacturing of thin film resistors mainly relies on sputtering or vacuum evaporation processes, but the existing technology has the following defects: Insufficient bonding strength: In traditional processes, the energy of sputtered atoms is low (usually less than 100eV), resulting in a chemical bonding strength of only 20-50MPa between the film layer and the substrate, which is far below the mechanical peeling threshold (>100MPa). XPS analysis shows that there is a weak bonding area at the interface, and the bonding energy is reduced by 15-20%.

[0003] Residual stress problem: When using pure metal film (such as nickel-chromium alloy), the difference in thermal expansion coefficient leads to residual stress of up to 200-500MPa, which causes cracking or warping of the film. Finite element simulation shows that the strain in the stress concentration area exceeds 30% of the material yield strength.

[0004] Structural defects: The surface roughness Ra value of the film layer prepared by traditional technology is usually 5-10nm, and the pinhole density is 10^6-10^7 / cm². AFM detection shows that the resistance value of the defective area fluctuates by more than ±15%, and the leakage current density increases by 2-3 orders of magnitude.

[0005] Existing improved methods such as ion beam assisted deposition (IBAD) can improve the bonding strength, but the process cost increases by more than 40%, and the residual stress problem has not been fundamentally solved. Although chemical vapor deposition (CVD) technology can reduce surface roughness, the high temperature process (>500°C) limits its application on flexible substrates. Summary of the invention

[0006] The invention provides a nano-scale multilayer thin film resistor manufacturing process with strong bonding force, controllable stress and compact structure, which solves the peeling, stress and defect problems in the prior art.

[0007] To achieve the above object, the present invention provides the following technical solution: a nanoscale multilayer thin film resistor, comprising: Substrate layer: Sapphire (Al 2 O 3 ) or silicon (Si) substrate, the surface is treated with oxygen plasma (power 500W, time 10min), the roughness Ra ≤ 1nm.

[0008] Buffer layer: TiO deposited by magnetron sputtering 2 -Al 2 O 3Nanocomposite layer (thickness 5-10nm), Ar / O 2 The flow ratio was 3:1, the substrate temperature was 200°C, and the deposition rate was 0.1 nm / s.

[0009] Functional layer: TaN-TiN gradient film (total thickness 50-100nm) was prepared by ion beam sputtering, the Ta:N atomic ratio gradually changed from 1:1 to 1:3, and the residual stress was controlled at ≤50MPa.

[0010] Protective layer: electron beam evaporated SiO 2 -CeO 2 Composite film (thickness 20-30nm), pulsed laser annealing (wavelength 355nm, energy density 2J / cm²) was used to eliminate pinholes.

[0011] The manufacturing process of nano-scale multilayer thin film resistors includes the following steps: Step 1: Substrate pretreatment: The substrate surface is treated with oxygen plasma, and the roughness Ra≤1nm; Step 2: Preparation of buffer layer: magnetron sputtering to deposit a metal oxide nanocomposite layer with a thickness of 5-10 nm; Step 3: Preparation of functional layer: Ion beam sputtering to form gradient nanostructure, residual stress ≤ 50 MPa; Step 4: Preparation of protective layer: electron beam evaporation of composite oxide film and pulsed laser annealing.

[0012] As a preferred embodiment, the buffer layer material is TiO 2 -Al 2 O 3 , atomic ratio 1:1-1:3.

[0013] Preferably, the atomic ratio change rate of the functional layer gradient structure is 0.01-0.1 atomic % / nm.

[0014] Preferably, the laser energy density of the protective layer annealing process is 1-3 J / cm².

[0015] Preferably, the substrate comprises sapphire, silicon or polyimide.

[0016] Preferably, the functional layer has a thickness of 50-100 nm and comprises TaN, TiN or W—SiN material.

[0017] Preferably, the substrate temperature during the deposition of the buffer layer is 150-300°C.

[0018] As a preferred embodiment, the protective layer material is SiO 2 -CeO 2 or Al 2 O 3 -HfO2 .

[0019] Nanoscale multilayer thin film resistors prepared by the manufacturing process are used in smartphones, tablets, high-performance computers, automotive electronic systems, and aerospace electronic equipment.

[0020] Compared with the prior art, the present invention has the following beneficial effects: 1. Improved interface bonding strength: With the gradient buffer layer design, the interface bonding strength reaches 120-150MPa, which is higher than the traditional process. The critical load is verified by the scratch test to be >80N.

[0021] 2. Structural stability optimization: The gradient functional layer reduces the residual stress by 80%. After 1000 hours of environmental testing at 85℃ / 85%RH, the resistance drift is ≤0.1%.

[0022] 3. Defect density control: The protective layer process reduces the pinhole density to <10 3 / cm², surface roughness Ra≤0.5nm, leakage current density<10 -9 A / cm². BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The present invention is further described below in conjunction with the accompanying drawings and embodiments.

[0024] Figure 1 It is a process flow chart of the present invention. DETAILED DESCRIPTION

[0025] The technical solutions in the embodiments of the present invention are described clearly and completely below. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0026] like Figure 1 As shown, the present invention provides the following technical solutions: The manufacturing process steps of nano-scale multilayer thin film resistors are as follows: Step 1: Substrate pretreatment Material selection: Sapphire (Al 2 O 3 ), silicon (Si) or polyimide (PI) substrate, size 50mm×50mm×0.5mm.

[0027] Cleaning process: Ultrasonic cleaning with acetone for 10 min → ultrasonic cleaning with isopropanol for 10 min → rinse with deionized water for 5 min.

[0028] Drying: After purging with nitrogen gun, vacuum oven (120℃, 2h).

[0029] Surface activation: Oxygen plasma treatment: power 600W, Ar / O 2 The flow ratio was 2:1, the treatment time was 15 min, and the surface contact angle was <10°.

[0030] Roughness control: Chemical mechanical polishing (CMP) is used, Ra≤0.8nm (sapphire substrate) or ≤1.2nm (PI substrate).

[0031] Step 2: Preparation of buffer layer Material formula: TiO 2 -Al 2 O 3 Nanocomposite layer (atomic ratio 1:2).

[0032] Deposition process: Equipment: DC magnetron sputtering system (base pressure ≤ 5×10 -6 Pa).

[0033] Target: TiO 2 Target (purity 99.99%) and Al 2 O 3 Target (purity 99.95%).

[0034] parameter: Working gas pressure: 0.6Pa (Ar gas flow rate 15sccm).

[0035] Substrate temperature: 250°C (150°C for PI substrate).

[0036] Sputtering power: TiO 2 Target 150W, Al 2 O 3 Target 200W.

[0037] Deposition rate: 0.08nm / s, total thickness 8nm.

[0038] Post-treatment: in-situ annealing (300°C, 1h) to eliminate interface stress.

[0039] Step 3: Preparation of functional layer Material system: TaN-TiN gradient film (Ta:N atomic ratio changes from 1:1 to 1:3).

[0040] Deposition process: Equipment: ion beam sputtering system (accelerating voltage 1.5 kV, beam current 200 mA).

[0041] Target: Ta target (purity 99.98%) and Ti target (purity 99.99%), N 2 Gas flow rate: 20 sccm.

[0042] parameter: Substrate temperature: 150℃ (sapphire) / 80℃ (PI).

[0043] Gradient control: Ta target current linearly decreased from 1.2A to 0.8A (50nm deposition process), deposition rate 0.2nm / s.

[0044] Residual stress control: By adjusting N 2 The partial pressure is adjusted to make the stress ≤50MPa (XRD measurement).

[0045] Doping optimization (optional): High-frequency application: 0.5wt% graphene quantum dots (GQD) are introduced and dispersed on the target surface by ultrasound.

[0046] Step 4: Preparation of protective layer Material formula: SiO 2 -CeO 2 Composite membrane (mass ratio 3:1).

[0047] Deposition process: Equipment: Electron beam evaporation system (base pressure ≤ 1×10 -6 Pa).

[0048] Evaporation source: SiO 2 and CeO 2 The particles were mixed in proportion, the evaporation rate was 0.2 nm / s, and the total thickness was 25 nm.

[0049] Bug fixes: Pulse laser annealing: wavelength 355nm, frequency 10Hz, energy density 2J / cm², spot diameter 2mm, scanning speed 5mm / s.

[0050] Pinhole elimination rate ≥99% (optical microscope detection).

[0051] Step 5: Electrode preparation and packaging Electrode material: Cr / Au (5nm / 100nm), electron beam evaporation.

[0052] Patterning: Photolithography process (AZ5214E ​​photoresist, exposure time 15s, development 60s).

[0053] Package: Parylene-C coating, thickness 5μm, moisture resistance grade IP67.

[0054] Example 1: Sapphire substrate multilayer resistor Substrate treatment: The sapphire substrate was etched with 5% HF solution for 30 seconds, ultrasonically cleaned and then treated with oxygen plasma (power 600 W, time 15 min).

[0055] Buffer layer preparation: magnetron sputtering deposition of TiO 2 -Al 2 O 3 (atomic ratio 1:2), working gas pressure 0.5Pa, substrate temperature 250℃, deposition rate 0.08nm / s.

[0056] Functional layer preparation: ion beam sputtering TaN-TiN gradient film, Ta target current linearly reduced from 1.2A to 0.8A, N 2 The flow rate was maintained at 15 sccm and the deposition temperature was 150°C.

[0057] Protective layer preparation: electron beam evaporation SiO 2 -CeO 2 (mass ratio 3:1), deposition rate 0.2nm / s, annealing parameters: laser frequency 10Hz, pulse width 10ns.

[0058] Performance test results table:

[0059] Example 2: Flexible substrate resistor Polyimide (PI) substrate is used, and the buffer layer is changed to AlN-ZrO 2 Nanolayer (thickness 8nm), the functional layer is adjusted to W-SiN gradient film, and the protective layer is deposited with Al using ALD technology 2 O 3 (Thickness 15nm). After 1000 bending tests (radius of curvature 2mm), the resistance change rate is <0.5%.

[0060] Example 3: Resistors for high frequency applications Graphene quantum dots (GQD) are introduced into the functional layer to form a TaN-GQD composite film. Tests show that the equivalent series inductance at 10GHz is reduced by 40% and the quality factor Q value is increased to 120 (the traditional process Q=80).

[0061] Example 4: High temperature environment resistor The protective layer is made of HfO 2 -Y 2 O 3 After annealing at 800℃, the composite film works continuously for 1000 hours at 500℃, and the resistance drift is only 0.3%.

[0062] Process parameter summary table:

[0063] Process control formula: Residual stress calculation formula:

[0064] in, is the elastic modulus of the substrate (sapphire: 400 GPa), is Poisson's ratio (0.25), is the substrate thickness (0.5 mm), is the film thickness (8nm), is the radius of curvature (measured by laser interferometry). Gradient atomic ratio control:

[0065] in, is the atomic ratio change (0.2 atomic %), is the gradient transition layer length (50nm).

[0066] Comparative table of embodiments:

[0067] Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the appended claims and their equivalents.

Claims

1. A process for manufacturing a nanoscale multilayer thin film resistor, characterized in that: The following steps are involved: Step 1: Substrate pretreatment: The substrate surface is treated with oxygen plasma, and the roughness Ra≤1nm; Step 2: Preparation of buffer layer: magnetron sputtering to deposit a metal oxide nanocomposite layer with a thickness of 5-10 nm; Step 3: Preparation of functional layer: Ion beam sputtering to form gradient nanostructure, residual stress ≤ 50 MPa; Step 4: Preparation of protective layer: electron beam evaporation of composite oxide film and pulsed laser annealing.

2. The manufacturing process of the nanoscale multilayer thin film resistor according to claim 1, characterized in that: The buffer layer material is TiO2-Al2O3, with an atomic ratio of 1:1-1:

3.

3. The manufacturing process of the nanoscale multilayer thin film resistor according to claim 1, characterized in that: The atomic ratio change rate of the functional layer gradient structure is 0.01-0.1 atomic % / nm.

4. The manufacturing process of the nanoscale multilayer thin film resistor according to claim 1, characterized in that: The laser energy density of the protective layer annealing process is 1-3 J / cm².

5. The manufacturing process of the nanoscale multilayer thin film resistor according to claim 1, characterized in that: The substrate includes sapphire, silicon or polyimide.

6. The manufacturing process of the nanoscale multilayer thin film resistor according to claim 1, characterized in that: The functional layer has a thickness of 50-100 nm and comprises TaN, TiN or W-SiN material.

7. The manufacturing process of the nanoscale multilayer thin film resistor according to claim 1, characterized in that: The substrate temperature during the deposition of the buffer layer is 150-300°C.

8. The manufacturing process of the nanoscale multilayer thin film resistor according to claim 1, characterized in that: The protective layer material is SiO2-CeO2 or Al2O3-HfO2.

9. A nanoscale multilayer thin film resistor prepared according to the manufacturing process according to any one of claims 1 to 8.

10. Application of the nanoscale multilayer thin film resistor according to claim 9 in smart phones, tablet computers, high-performance computers, automotive electronic systems, and aerospace electronic equipment.

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