Multifunctional image generation device and image generation method

Abstract

The invention relates to the technical field of image processing, and particularly provides a multifunctional image generation device and an image generation method.The multifunctional image generation device comprises an FPGA, a DSP, an optical fiber module, a Cameralink video coding chip, a PAL video coding chip, an SDI video coding chip, a control key, MAX3490, a DDR and a crystal oscillator; and the image data is transmitted to the image coding chips corresponding to the images of the different systems according to the time sequences of the images of the different systems, and the images of the different systems are obtained through conversion in a synchronous transmission mode. The device can be applied to a computer with a PCIE interface, can generate and output same images of different standards or different images of different standards at the same time, and can also be independently used without the computer to generate target images of specific sizes and contrast ratios, so that the use flexibility of the whole device is improved, and the use cost is reduced. The method can be applied to evaluation and detection of image target tracking equipment and simulation of video output of an image detector.

Description

Technical Field

[0001] The present invention belongs to the technical field of image processing, and in particular relates to a multifunctional image generating device and an image generating method. Background Art

[0002] With the rapid development of image processing technology, image target tracking and recognition technology is widely used in industrial fields such as airborne, vehicle-mounted and ship-mounted. In order to evaluate and detect the performance of image target tracking and recognition equipment, it is usually necessary to input specific video images. With the continuous improvement and upgrading of industrial equipment, there are often multiple target tracking processing devices with different image formats to process the same scene or target. When evaluating and testing such equipment, it is necessary to input the same target images of different formats at the same time to evaluate the performance parameters between different devices. The traditional image generation device is a single signal of analog video format and cannot achieve the above functions.

[0003] In the field of aerospace or aviation, it is a very common application for the detector to generate images and transmit them to the image processing equipment in real time. Before the image processing equipment is mounted on a carrier such as an aircraft or satellite, the detector cannot output images of the application environment, so the on-site performance of the image processing equipment cannot be verified. Therefore, an image generating device is needed to convert the image video of the detector site saved in the past into a customized image and input it to the image processing equipment to simulate the environment of the detector during actual use, so as to improve the performance and reliability of the entire image processing system. The on-site image video is usually stored in a computer, and the PCIE interface in the computer has the characteristics of wide application, high transmission rate and good reliability, but there is no image generating device applied to PCIE interface computers on the market.

[0004] In summary, developing an image generating device with high reliability, accuracy and complete functions is of great significance in the field of image processing. Summary of the invention

[0005] In view of this, the present invention aims to provide a multifunctional image generating device and method, which can not only convert the existing video images stored in the computer into images of different formats through the PCIE interface, but also directly generate targets of different contrast sizes or shapes under the background of a single grayscale image, generate images of different formats with specific targets through the collaborative work of FPGA and DSP, and can convert and obtain images of different formats in a synchronous transmission manner, which is convenient for application in performance parameter evaluation scenarios between different devices.

[0006] To achieve the above object, the technical solution created by the present invention is implemented as follows: The first aspect of the invention provides a multifunctional image generating device, comprising: an FPGA, and a DDR, a crystal oscillator and a plurality of image encoding chips for performing image encoding of different formats connected to the FPGA; Among them, FPGA is used to obtain image data and store it in DDR, and realize the storage and reading of multiple images according to address partition; FPGA performs frequency multiplication processing based on the clock signal provided by the crystal oscillator to generate the pixel clock signal required by different standard images, and then generates the line synchronization and frame synchronization signals of different standard images through the pixel clock signal to obtain the timing required by different standard images; FPGA includes multiple FIFOs, each FIFO is used for data transmission of images of different formats. The image data required for images of different formats are obtained from the corresponding address area of ​​DDR through FIFO, and the timing of the image data is integrated into the timing corresponding to the images of different formats. The timing of the images of different formats is transmitted to the image encoding chips corresponding to the images of different formats respectively with the timing of different formats. The image encoding chip encodes the image data into an image signal of a specific format, and realizes the conversion of images of different formats in a synchronous transmission manner.

[0007] Preferably, the FPGA is connected to a device storing image data via a PCIE interface.

[0008] Preferably, the FPGA receives the transmitted image data via XDMA.

[0009] Preferably, the encoding chip includes at least one of a Cameralink video encoding chip, a PAL video encoding chip, and an SDI video encoding chip.

[0010] Preferably, it also includes an optical fiber module, which is used to transmit the image data remotely. The FPGA processes the image data into a specific format image required for remote transmission, and converts it into a high-speed differential signal and transmits it to the optical fiber module for remote transmission.

[0011] Preferably, it also includes a communication module and / or an external control button for controlling image parameters.

[0012] Preferably, it also includes a DSP, which is used to generate a target and transmit the target signal to the FPGA. The FPGA generates image data based on the target signal superposition, and then transmits the image data generated by the FPGA to different image encoding chips to convert and generate images of different formats.

[0013] Preferably, the DDR is divided into multiple areas according to the address, and the multiple areas transmit image data corresponding to images of different formats and communication data of the FPGA.

[0014] The second aspect of the invention provides an image generation method, using a multifunctional image generation device, connecting an FPGA to a computer storing image data through a PCIE interface, and the image generation includes: The computer transfers the stored image data to the FPGA via PCIE; FPGA stores the received image data into DDR and manages the multi-channel image data according to the address partition; FPGA generates the timing of different formats of images based on the clock signal provided by the crystal oscillator; FPGA transfers the image data in DDR to the corresponding image encoding chip according to a specific format timing; The image encoding chip encodes the received image data into an image signal of a specific format and outputs it.

[0015] The third aspect of the present invention provides an image generation method, using a multifunctional image generation device, the image generation includes: FPGA generates the timing of different formats of images based on the clock signal provided by the crystal oscillator; DSP generates target signal, which can be the target to be tracked or noise, and FPGA generates image data according to the target signal; The image data generated by the FPGA is transmitted to the corresponding image encoding chip according to a specific format timing; The image encoding chip encodes the received image data into an image signal of a specific format and outputs it.

[0016] Compared with the prior art, the invention can achieve the following beneficial effects: The present invention combines FPGA, video encoding chip, DSP, DDR and other chips to generate specific multi-channel synchronous images of different formats, and can be controlled by industrial control buttons or serial ports. It can also be used independently without a computer to generate target images of specific size and contrast, thereby improving the flexibility of the use of the entire device and effectively solving the problem that the detector cannot generate specific images. The generated images can be used for detection of image target tracking and recognition devices or for remote transmission of images in computers through optical fibers, and have important application value.

[0017] The device of the present invention has different image generation modes, which greatly improves the utilization rate and flexibility of the device. On the one hand, it can be used in conjunction with a computer, receive the existing video image data stored in the computer through the PCIE interface, and convert it into image outputs of different formats to meet the input requirements of multiple devices; on the other hand, it can also run independently, through the collaborative work of FPGA and DSP, directly generate targets of different contrast sizes or shapes under the background of a single grayscale image, generate images with specific targets in real time, and output image signals of different formats; the device of the present invention is used for the image of the application environment that the detector cannot output, and the image video of the detector site saved in the past needs to be made into a special format image input to the image processing device to simulate the application scenario of the environment of the detector during the actual use. In addition, the device of the present invention can simultaneously output multiple channels of images of different formats in a synchronous transmission mode, ensure the synchronization of different devices when receiving images, facilitate the evaluation and comparison of performance parameters, and can be used for performance evaluation and detection of image target tracking equipment, as well as scenarios that need to simulate specific image outputs, which can effectively improve the flexibility and accuracy of equipment testing.

[0018] The present invention has been verified in actual projects and has achieved good application effects. It can stably and reliably realize the functions of generating and transmitting specific images and controlling targets in images. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The drawings constituting part of the present invention are used to provide a further understanding of the present invention. The exemplary embodiments and descriptions of the present invention are used to explain the present invention and do not constitute an improper limitation on the present invention. In the drawings: Figure 1 is a structural diagram of a multifunctional image generating device provided according to an embodiment of the present invention; Figure 2 It is a schematic diagram of an internal unit of an FPGA provided according to an embodiment of the present invention. DETAILED DESCRIPTION

[0020] In order to make the purpose, technical scheme and advantages of the invention clearer, the invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only used to explain the invention and do not constitute a limitation to the invention. Similar components in different embodiments use associated similar component numbers. In the following embodiments, many detailed descriptions are to enable the invention to be better understood. However, those skilled in the art can easily recognize that some of the features can be omitted in different situations, or can be replaced by other components, materials, and methods. In some cases, some operations related to the invention are not shown or described in the specification, in order to avoid the core part of the invention being overwhelmed by too much description, and for those skilled in the art, it is not necessary to describe these related operations in detail, and they can fully understand the related operations according to the description in the specification and the general technical knowledge in the art.

[0021] It should be noted that, in the absence of conflict, the embodiments of the present invention and the features in the embodiments can be combined with each other to form various implementation methods. At the same time, the steps or actions in the method description can also be interchanged or adjusted in a manner that is obvious to those skilled in the art. Therefore, the various sequences in the specification and the drawings are only for the purpose of clearly describing a certain embodiment and are not meant to be a necessary sequence, unless otherwise specified that a certain sequence must be followed.

[0022] In the description of the invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the drawings, and are only for the convenience of describing the invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the invention. In addition, the terms "first", "second", etc. are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first", "second", etc. may explicitly or implicitly include one or more of the features. In the description of the invention, unless otherwise specified, the meaning of "multiple" is two or more.

[0023] In the description of the invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installation", "connection" and "connection" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the invention can be understood according to specific circumstances.

[0024] The present invention will be described in detail below with reference to the accompanying drawings and in combination with embodiments.

[0025] See also Figure 1 In one embodiment of the present invention, a multifunctional image generating device is provided, which can be applied to a computer with a PCIE interface or used independently without a computer. Through the collaborative work of FPGA, DDR and multiple encoding chips of different formats, the device can output multiple images of different formats of the same image at the same time, output different images at the same time, output multiple images of different formats with specific targets superimposed, output video images stored in the computer in different formats, output video images of the target tracked by the detector in different formats, and generate target images of specific size and contrast without a computer. Specifically, the multifunctional image generating device includes: FPGA, DDR, crystal oscillator, DSP, optical fiber module, communication module MAX3490, external control buttons, and multiple image encoding chips for encoding images of different formats. In the embodiment of the present invention, Cameralink video encoding chips, PAL video encoding chips and SDI video encoding chips are specifically used to meet the main application requirements. Specifically, the above encoding chips can be increased, reduced or replaced according to the requirements of the actual application scenario.

[0026] Among them, FPGA, as the core chip in the device, is connected to DDR, crystal oscillator, DSP, optical fiber module, communication module MAX3490, external control button, Cameralink video encoding chip, PAL video encoding chip and SDI video encoding chip respectively, and is used to receive and transmit image data, process and distribute image data, generate image timing signals of different formats, and then each format image encoding chip generates different format images. In the embodiment of the present invention, the FPGA model selected is XC7K325TFFG900, which can realize 8-channel PCIE2.0 data transmission, and the communication rate of each channel can reach 5Gbps, which can meet the application needs for synchronous and rapid transmission of multiple images. For details of the internal unit structure of FPGA, please refer to Figure 2During use, the multifunctional image generating device is usually used in conjunction with a computer, and reads the image video data collected by the detector in the past stored in the computer through the PCIE interface of the computer, and converts it to generate the required images of various different formats.

[0027] The data receiving unit inside the FPGA receives the image data transmitted from the computer through XDMA, and stores the obtained image data in partitions to DDR. The main principle of XDMA is to achieve fast transmission by directly accessing the host memory, then transfer the data to DDR, and accumulate the address to store the data. XDMA can achieve high-speed data transmission through the PCIE interface bus, which can significantly improve data throughput and reduce transmission delay. It supports configurable data width and transmission rate, and can adapt to the needs of different hardware platforms to meet the synchronous transmission of large amounts of image data. The combination of XDMA and FPGA can also achieve the separation of data processing and transmission, and improve the parallel processing capability of the system.

[0028] DDR is used to partition and store the multi-frame image data acquired by FPGA, and to accumulate addresses, and to realize the storage and reading of multiple images according to the address partition. Specifically, in the embodiment of the present invention, the image output part is designed with an optical fiber module for remote transmission, and three different types of image encoding chips, Cameralink video encoding chip, PAL video encoding chip and SDI video encoding chip. Therefore, DDR is divided into 9 areas according to the address, and every 2 areas correspond to the transmission of a standard image (three different types of image encoding chips and optical fiber modules), each area can store one frame of image, and the remaining area is used to store the communication data between FPGA and computer. According to the specific design situation, more encoding chips for standard images can be added, or videos with higher frame rates can be transmitted. At this time, DDR can be divided into more areas to meet the output requirements of more standard images. In addition, it is necessary to read after storing multiple frames of video to prevent data flow errors caused by the read image not being a full frame image due to too fast data transmission. Specifically, since the embodiment of the present invention uses only one DDR, data storage and data reading cannot be performed at the same time, so the priority of storing data is set higher than the priority of reading data, and in the process of interacting with the computer, it is usually necessary to use an 8-channel PCIE2.0 bus transmission, and DDR uses a 32-bit data transmission rate of 800Mhz. This design is sufficient to ensure that the writing and reading time is sufficient to avoid conflicts between writing and reading. In the process of storing images, only when a region completes the storage of a frame of image, can the image of the region be read, and if there is data written to the DDR during the reading process, the process of reading data is interrupted, and the process of writing data is executed to ensure that the image data written to the DDR is correct.

[0029] For the process of FPGA reading data from DDR, the embodiment of the present invention adopts FIFO to realize data reading, so as to integrate the timing of the original image data into the timing of a specific format image, which is convenient for the subsequent encoding and output of different format images. In the embodiment of the present invention, the FPGA adopts 4 FIFO designs, namely FIFO1, FIFO2, FIFO3 and FIFO4, which correspond to Cameralink format video, SDI format video, PAL format video and video required for optical fiber transmission respectively. The image data in DDR is allocated to each FIFO buffer according to the address partition. After the FIFO obtains the image data from the corresponding address area of ​​DDR, the data is transmitted out with the timing of a specific format image. FIFO is mainly used to adjust the timing of image data in different address partitions, and by generating different format image timings, the subsequent transmission requirements of transmitting image data to different format image encoding chips are met. Specifically, the principle of image timing generation is as follows: FPGA receives the clock signal provided by the crystal oscillator, multiplies it to generate pixel clock signals of multiple different formats of images, and then generates and outputs level signals such as line synchronization and frame synchronization (field synchronization) of different formats of images by counting based on the pixel clock signal. The line synchronization signal is used to mark the beginning and end of each line of image data. It is a periodic pulse signal that ensures the correct display of the image in the horizontal direction. The period of the line synchronization signal is related to the horizontal resolution of the image. The line synchronization signal ensures that each line of image data is sampled and displayed at the correct time. The frame synchronization signal is used to mark the beginning and end of each frame of the image. It is a low-frequency pulse signal that ensures the correct display of the image in the vertical direction. The frequency of the frame synchronization signal is related to the frame rate of the image. The frame synchronization signal ensures that each frame of the image is completely transmitted and displayed at the correct time. The pixel clock, line synchronization, and frame synchronization signals constitute the timing of image transmission of different formats. The timing signal ensures that the image data is correctly aligned in time and space to avoid tearing, flickering or distortion of the image. In addition, the timing signal can ensure that the image data is synchronously transmitted between the internal and external devices of the FPGA to avoid data loss or errors. FPGA adjusts the frequency and period of the timing signal to generate image signals of different formats (such as Cameralink, SDI, PAL, etc.) to meet the back-end requirements. The image data required for different format images is obtained from the corresponding address area of ​​DDR through FIFO, and the timing of the image data is integrated into the timing corresponding to the different format images in the above manner, and transmitted to the image encoding chips corresponding to the different format images in different format image timings. The Cameralink, SDI, and PAL image encoding chips encode the image data into specific Cameralink, SDI, and PAL format image signals to obtain the corresponding images, realizing the conversion of images in the computer into images of different formats in a synchronous transmission manner. In addition, in order to meet some specific long-distance transmission requirements, the present invention considers optical fiber transmission of images, using the high-speed serial transceiver (GTX) contained in the FPGA, extracting image data from FIFO4 in the figure and inputting it into the IP core with the timing of the required video format, performing high-speed serial signal conversion, generating a high-speed serial signal corresponding to the video, and then transmitting the high-speed signal to the optical fiber module, converting the high-speed signal into an optical fiber signal output. It should be pointed out that the image format transmitted by the optical fiber is not fixed, and can be converted inside the FPGA as needed to improve the application flexibility of the system.

[0030] In addition, it also includes a communication module and an external control button, which adjusts the image parameters through an external control signal (such as a serial port or a button), respectively used to realize the external communication and manual control functions of the device. In the embodiment of the present invention, the communication module uses a MAX3490 chip, and the MAX3490 chip converts the external RS422 communication signal into a differential level signal and transmits it to the FPGA, which is decoded or encoded by the serial port encoding and decoding unit in the FPGA in the figure to realize the output control of the serial port image. The serial port can realize the functions of switching the frame rate and resolution of the image output, selecting the format of the image transmitted by the optical fiber signal, etc. At the same time, the computer also needs to transmit the image information to the FPGA through the PCIE bus, and then the FPGA transmits it through the serial port. The specific image information includes: the target position, number, contrast and other true value information in the image, so as to cooperate with the generated image. And it can also be manually controlled by an external control button. The external control button is a physical button installed on the outside of the device, which is used to directly operate the device and realize the manual control function. These buttons are usually used to adjust image parameters, switch modes or start / stop the device. Allow users to directly adjust image parameters such as image size, contrast, shape, etc. through external control buttons.

[0031] In addition, in order to realize the independent use of the device of the embodiment of the present invention without the computer, a DSP is also provided, and the FPGA and the DSP work together to generate specific image content, adjust image parameters, and realize complex signal processing functions. The specific target generated in the image data can be a target for subsequent tracking research, such as a moving target, etc., to simulate the target object in the real scene, or it can be a position, shape (such as a circle, a five-pointed star, a ring, etc.) and motion trajectory of the target that can be randomly generated, such as parameter characters, target marks, etc., or interference noise. Specifically, the DSP generates noise signals to simulate interference in the real environment. By randomly generating the position of the noise point and passing these noise signals to the FPGA, the FPGA superimposes the noise signal on the background image. The DSP performs character superposition and information display. The DSP combines the font library in the FPGA to generate pixel data for displaying characters. It can dynamically adjust the position, size and content of the characters (such as target size, contrast, etc.), and superimpose the characters on the image. The DSP performs parameter adjustment and dynamic control. The DSP can dynamically adjust the parameters of the image according to the external control signal (such as the serial port or key) such as the size, contrast, brightness, etc. of the target to meet different test requirements. DSP passes the generated target signal to FPGA, FPGA generates image data based on the target signal, and then transmits the image data after superimposing the generated target signal to different image encoding chips through FPGA to convert and generate images of different formats.

[0032] Based on the above multifunctional image generating device, the embodiment of the present invention further provides two methods for using the device, specifically providing the following two image generating methods to meet the needs of different application scenarios: The first image generation method has an application scenario of using the multifunctional image generation device proposed in the embodiment of the present invention in combination with PCIE interface calculation. When used in conjunction with a computer equipped with a PCIE interface, the multifunctional image generation device of the embodiment of the present invention can transmit the detector video image stored in the computer to the FPGA through the PCIE bus. The FPGA processes and integrates these image data and converts them into image signals of a specific format for output, thereby simulating the video image of the detector. In the embodiment of the present invention, an 8-bit grayscale image is used as an example for data transmission and processing.

[0033] The computer stores the video data collected by the detector. According to the video format, the computer converts the video into an 8-bit grayscale image and stores each frame of the image data in an array. If multiple different images need to be generated, the computer integrates the multiple images and stores them in the same array. Subsequently, the array is transmitted to the FPGA via the PCIE bus in the form of a 32-bit or 64-bit data stream. The FPGA receives the data transmitted by the computer through XDMA, directly accesses the host memory to achieve fast transmission, and then transmits the data to the DDR. The address partitioning function of the DDR memory is used to distinguish the image data of different channels, which is convenient for the subsequent reading and encoding of different format images, and each frame of the image is sent cyclically with a sending cycle of 50Hz. DDR is divided into 9 areas according to the address, and every 2 areas correspond to the transmission of a format image. Each area can store one frame of image, and 1 area is used to store the communication data between FPGA and computer. DDR uses a 32-bit data transmission rate of 800Mhz to ensure that the writing and reading time is sufficient without conflict. During the image storage process, the image in a zone can be read only after a frame of image is stored in the zone. If there is data written to the DDR during the reading process, the reading process is interrupted and the writing process is carried out to ensure that the data written to the DDR is correct.

[0034] The FIFO of FPGA integrates the timing of data into the timing of a specific format image. After the FIFO obtains the image data from the corresponding address area of ​​DDR, it transmits the data in the timing of a specific format image. The process of generating the image timing is as follows: a. First, the crystal oscillator generates a clock frequency, and the FPGA obtains a reference clock signal from the crystal oscillator. In the embodiment of the present invention, the crystal oscillator provides a clock frequency of 27 MHz as the basic clock of the system. The reference clock provides a synchronous basic time reference for the entire system to ensure that all operations are performed according to the predetermined timing.

[0035] b. Inside the FPGA, the reference clock is multiplied by a digital phase-locked loop (PLL) or a clock management module to generate the pixel clock signal required for different image formats. For Cameralink video encoding chips, PAL video encoding chips, and SDI video encoding chips. Since Cameralink is a non-standard format, in the embodiment of the present invention, taking the generation of an 8-bit grayscale image with a frame rate of 50Hz and a resolution of 1920×1080 as an example, the required pixel clock frequency is 148.5MHz, which is obtained by multiplying the reference clock of 27MHz.

[0036] For the SDI standard, the pixel clock frequency is also 148.5MHz, which is compatible with the Cameralink standard.

[0037] For the PAL standard, the PAL standard image is an image with a frame rate of 25Hz and a resolution of 720×576. The PAL standard uses interlaced scanning, and one frame of the image is transmitted through odd and even fields. One field of data is 720*288, and two fields of images are combined into one frame of the image. The field frequency is 50Hz, and the pixel clock uses 27MHz, which is the same as the reference clock.

[0038] As for the long-distance transmission of the optical fiber module, it is necessary to generate the corresponding timing according to the specific standard image required for long-distance transmission.

[0039] c. Use pixel clock to generate and output the line synchronization and frame synchronization (field synchronization) and other levels of different standard images by counting. Since the timing of Cameralink is the same as that of SDI images, but different from that of PAL standard images, but the frame synchronization (field synchronization) to be generated is 50Hz, the 720*576 image of the center part can be cut from the 1080P image as the input of the PAL image, and the three standard images can be generated synchronously in this way.

[0040] d. FIFO obtains image data from DDR, which is image brightness data. During the reading process, when the amount of data in FIFO is less than 1920, data is read from DDR, and the address is accumulated for each reading until the end of the current frame, and then the image of another area in DDR is read to read another frame of image to avoid incomplete reading of each frame of image. At the same time, the data read from FIFO is also counted and the amount of data read from FIFO is compared with the address of the written data to ensure that the data is not lost. If the data is lost, the entire system is reset.

[0041] e. After the above process, the digital quantities required for encoding images of different formats can be obtained, including: pixel clock, pixel brightness data, line synchronization, frame synchronization (field synchronization) data. FPGA transmits the above data to the encoding chips of the corresponding format images, namely, Cameralink video encoding chip, PAL video encoding chip, SDI video encoding chip, and optical fiber module.

[0042] f. When both frame and line synchronization are valid for SDI and Cameralink images, an 8-bit image brightness data is taken from the corresponding FIFO and transmitted to the corresponding encoding chip every pixel clock. For PAL images, because they are YUV image inputs, one pixel clock represents the image brightness data, and the next clock represents the image color data. Then, one pixel clock takes an 8-bit data from the corresponding FIFO and transmits it to the encoding chip. The next clock is set to 128 for color data, and so on for cyclic transmission.

[0043] The corresponding image can be obtained by transmitting the corresponding standard image data from FPGA to the corresponding encoding chip in the above manner. SDI and Cameralink images are 50 frames of 1080P grayscale images, and PAL standard images are 25 frames of 720*576 images. The PAL standard image takes the middle part of the 1080P image to realize the conversion of the image in the computer into different standard images in a synchronous transmission manner. For long-distance transmission, the optical fiber module generates the standard image timing required for long-distance transmission through FPGA, and converts the image data into a high-speed serial high-speed signal of the corresponding standard image with this timing, and then transmits the high-speed signal to the optical fiber conversion module to convert the high-speed signal into an optical fiber signal output.

[0044] In addition, during the generation process, image parameters can be adjusted through the communication module and / or external control buttons, including but not limited to: true value information such as target position, number, contrast, etc. in the image.

[0045] The second image generation method has the following application scenarios: it can be used independently without a computer and can be used in conjunction with some industrial image target tracking devices. Such devices need to detect the size and contrast of the target and the target movement speed. The image generated by the detector cannot quantify the generated target image, so the performance of the tracking device cannot be detected through the image generated by the detector, so a specific target image needs to be generated. The embodiment of the present invention is used to evaluate and detect such devices, so it is necessary to generate target images of different formats to cope with the situation where there are multi-format image target tracking devices that need to track targets at the same time and evaluate the devices.

[0046] This image generation method can be used independently without a computer. Through the collaborative work of FPGA and DSP, an image with a specific target is generated and simultaneously transmitted to the Cameralink video chip, SDI video chip, PAL video chip and optical fiber module to generate Cameralink, SDI, PAL format video and remote transmission type video. This image generation method directly generates targets of different contrast, size or shape on the background of a single grayscale image through FPGA and DSP. FPGA generates the timing of different format images according to the clock signal provided by the crystal oscillator. This process also includes the timing generation steps of a, b and c described in the first image generation method, with the purpose of generating the timing information of the corresponding format image. And also includes the following subsequent processes: d. By generating image brightness data through FPGA, a moving image of a weak target under a single background can be generated. For example, a 5×5 pixel target is generated. When the background brightness is I 1 In this case, when a target is generated, the brightness value of the 5×5 pixel range at that position is set to I 2 The target image contrast C generated by FPGA is: .

[0047] The position of the target changes with time, and the moving speed of the target can be changed by setting the pixel value of the target position change in each frame of the image.

[0048] e. The signal of the interference target can be generated through DSP. DSP is responsible for randomly generating the position of the noise point and transmitting this position information to FPGA. FPGA generates a pixel brightness of I at the corresponding position according to the received position information. 3 The contrast of these noise points is lower than the target contrast, thus simulating the background noise in the real environment. In addition, the DSP can also randomly generate the position of the target and pass this position information to the FPGA. The FPGA generates the target image at the corresponding position based on the received position information. In this way, the random movement of the target in the image can be simulated.

[0049] f. The collaborative work between FPGA and DSP is not limited to the generation of noise and target position, but also extends to the adjustment of target shape and the superposition display of character information, as follows: Create a mif file and a character library in FPGA. The character library contains a variety of target shapes (such as circles, five-pointed stars, rings, etc.), as well as Chinese characters for displaying information (such as "goal", "standard", "comparison", "comparison", "degree", etc.). By programming and controlling the character library address through DSP, the shape, contrast, size and image frame rate of the target can be flexibly adjusted, and these parameter information can be superimposed on the image in the form of characters. The size of the characters displayed in the image is 18pixel×18pixel. In the ROM table, each row (18 cells) represents a character, and each cell stores 18 pixels of a row of character data. FPGA receives the character position and character address information transmitted by DSP and performs address decoding on the DSP data. During the image transmission process, FPGA completes the multiplexing decoding of the rom address line and superimposes the character to the specified position of the image, thereby realizing the simultaneous display of the character and the image target.

[0050] In order to enable the observer to clearly understand the information in the current image, the embodiment of the present invention also sets the character display time to 2 seconds by means of FPGA clock counting. During this period, the target image is continuously displayed. If the target shape or image content changes, the character display time will be reset and displayed for 2 seconds again to ensure timely update and accurate communication of information.

[0051] g. At this time, the size, contrast, shape and other information of the target can be controlled through the communication module and / or external control buttons. FPGA receives differential level signals from external input control through the communication module. These signals are transmitted by the MAX3490 chip, and the FPGA decodes the received signals to obtain a series of control information of image parameters. These parameters include the size, shape, background brightness, target brightness, size of background noise and its brightness, etc. of the target. In this way, the user can externally adjust the generation and display of the image to meet different test requirements. In order to improve the operational convenience and flexibility of the system, the embodiment of the present invention specially designs a communication module and an external control button, which is directly connected to the FPGA through buttons, and realizes real-time adjustment of image parameters through simple physical operations. The specific button functions are as follows: "Target Size +" button: When this button is pressed, the FPGA detects the corresponding level signal change and then increases the size of the target.

[0052] "Target Size -" button: When this button is pressed, the FPGA detects the corresponding level signal change and then reduces the size of the target.

[0053] “Target brightness +” button: When this button is pressed, the FPGA detects the corresponding level signal change and then increases the brightness of the target.

[0054] "Target brightness -" button: When this button is pressed, the FPGA detects the corresponding level signal change and then reduces the brightness of the target.

[0055] "Target shape switching" button: When this button is pressed, the FPGA detects the corresponding level signal change and then switches between the preset target shapes (such as circle, five-pointed star, ring, etc.).

[0056] The FPGA detects the level signal changes generated by the buttons in real time through the built-in logic circuit, and quickly adjusts the image parameters according to these changes. The adjusted image parameters will be immediately reflected in the output image, ensuring that the user can intuitively see the adjustment effect. This instant feedback mechanism greatly improves the system's operational convenience and user experience.

[0057] The multifunctional image generating device of the present invention can generate images in the above two ways to achieve different functional requirements, which greatly improves the application flexibility of the device. In addition, the above device and method have been applied in specific scientific research projects, stably and reliably achieving the functions of generating and transmitting specific images and controlling targets in images.

[0058] In short, the above description is only a preferred embodiment of this specification and is not intended to limit the protection scope of this specification. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of this specification shall be included in the protection scope of this specification.

[0059] The systems, devices, modules or units described in one or more of the above embodiments may be implemented by a computer chip or entity, or by a product having a certain function. A typical implementation device is a computer. Specifically, the computer may be, for example, a personal computer, a laptop computer, a cellular phone, a camera phone, a smart phone, a personal digital assistant, a media player, a navigation device, an email device, a game console, a tablet computer, a wearable device, or a combination of any of these devices.

[0060] It should also be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, commodity or device. In the absence of more restrictions, the elements defined by the sentence "comprises a ..." do not exclude the existence of other identical elements in the process, method, commodity or device including the elements.

[0061] Each embodiment in this specification is described in a progressive manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the system embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0062] The above is a description of a specific embodiment of the specification. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recorded in the claims can be performed in an order different from that in the embodiments and still achieve the desired results. In addition, the processes depicted in the drawings do not necessarily require the specific order or continuous order shown to achieve the desired results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

Claims

1. A multifunctional image generating device, characterized in that: It includes: FPGA, DDR, crystal oscillator and multiple image coding chips for performing image coding of different formats connected to the FPGA; Wherein, the FPGA is used to acquire image data and store it in the DDR, and realize the storage and reading of multiple images according to address partitions; The FPGA performs frequency multiplication processing according to the clock signal provided by the crystal oscillator to generate pixel clock signals required for images of different formats, and then generates line synchronization and frame synchronization signals of images of different formats through the pixel clock signals to obtain the timing required for images of different formats; The FPGA includes multiple FIFOs, each FIFO is used for data transmission of images of different formats. The image data required for images of different formats are obtained from the corresponding address area of ​​DDR through FIFO, and the timing of the image data is integrated into the timing corresponding to the images of different formats, and is transmitted to the image encoding chips corresponding to the images of different formats in the timing of different formats. The image encoding chip encodes the image data into an image signal of a specific format, so as to realize conversion to obtain images of different formats in a synchronous transmission manner.

2. The multifunctional image generating device according to claim 1, characterized in that: The FPGA is connected to a device storing image data via a PCIE interface.

3. The multifunctional image generating device according to claim 2, characterized in that: The FPGA receives the transmitted image data via XDMA.

4. The multifunctional image generating device according to claim 1, characterized in that: The encoding chip includes at least one of a Cameralink video encoding chip, a PAL video encoding chip, and an SDI video encoding chip.

5. The multifunctional image generating device according to claim 4, characterized in that: It also includes an optical fiber module, which is used to transmit the image data remotely. The FPGA processes the image data into a specific format image required for remote transmission, and converts it into a high-speed differential signal and transmits it to the optical fiber module for remote transmission.

6. The multifunctional image generating device according to claim 1, characterized in that: It also includes a communication module and / or an external control button for controlling image parameters.

7. The multifunctional image generating device according to claim 1, characterized in that: It also includes a DSP, which is used to generate a target and transmit the target signal to the FPGA. The FPGA generates image data based on the target signal superposition, and then transmits the image data generated by the FPGA to different image encoding chips to convert and generate images of different formats.

8. The multifunctional image generating device according to claim 2, characterized in that: The DDR is divided into a plurality of areas according to addresses, and the plurality of areas transmit image data corresponding to images of different formats and communication data of the FPGA.

9. A method for generating an image, characterized in that: Using the multifunctional image generating device according to any one of claims 1 to 8, the FPGA is connected to a computer storing image data via a PCIE interface, and the image generation includes: The computer transfers the stored image data to the FPGA via PCIE; FPGA stores the received image data into DDR and manages the multi-channel image data according to the address partition; FPGA generates the timing of different formats of images based on the clock signal provided by the crystal oscillator; FPGA transfers the image data in DDR to the corresponding image encoding chip according to a specific format timing; The image encoding chip encodes the received image data into an image signal of a specific format and outputs it.

10. A method for generating an image, characterized in that: Using the multifunctional image generating device according to any one of claims 1, 3 to 8, image generation includes: FPGA generates the timing of different formats of images based on the clock signal provided by the crystal oscillator; DSP generates target signal, which can be the target to be tracked or noise, and FPGA generates image data according to the target signal; The image data generated by the FPGA is transmitted to the corresponding image encoding chip according to a specific format timing; The image encoding chip encodes the received image data into an image signal of a specific format and outputs it.

Images