Array substrate and display device comprising same

Abstract

The invention discloses an array substrate and a display device comprising the same. The array substrate has a geometric center and a virtual center line passing through the geometric center, and comprises a substrate, a first metal layer, a second metal layer, a plurality of active elements and a shielding pattern layer. The first metal layer is arranged on the substrate and comprises a plurality of first signal lines. The second metal layer is arranged on the first metal layer and comprises a plurality of second signal lines. The active elements are arranged on the substrate, and each active element is electrically connected with one of the first signal lines and one of the second signal lines and comprises a channel layer. The shielding pattern layer is arranged between the first metal layer and the second metal layer, is overlapped with the virtual center line on the normal line of the substrate, and is formed by patterning the same film layer with the channel layers. The array substrate can protect the circuit located at the splicing position of the photomask from being etched and broken, and then the yield is maintained.

Description

Technical Field

[0001] The invention relates to a display, and in particular to a display panel and a pixel array substrate thereof. Background Art

[0002] Display devices have been widely used in various electronic products. In a display device, part of the film layer of the array substrate is formed by exposure and development using a half-tone mask and then etching to reduce the number of masks and simplify the process. However, in response to the size requirements of the display device, exposure and development are performed by splicing masks. The photoresist at the splicing point of the mask may be removed due to repeated exposure, causing the circuit below to be etched and disconnected, thereby reducing the yield. Summary of the invention

[0003] At least one embodiment of the present invention provides an array substrate and a display device including the same, wherein the array substrate includes a patterned shielding pattern layer formed together with an active device channel layer, and the shielding pattern layer overlaps with a virtual center line passing through the geometric center of the array substrate. Therefore, while using a spliced ​​halftone mask to reduce the number of masks and simplify the process, the circuit located at the splicing of the mask can still be protected from being etched and disconnected, thereby maintaining the yield.

[0004] The array substrate provided by at least one embodiment of the present invention has a geometric center and a virtual center line passing through the geometric center and extending along a first direction, and includes a substrate, a first metal layer, a second metal layer, a plurality of active components and a shielding pattern layer. The virtual center line is perpendicular to the normal line of the substrate. The first metal layer is disposed on the substrate and includes a plurality of first signal lines. The second metal layer is disposed on the first metal layer and includes a plurality of second signal lines. These active components are disposed on the substrate, each active component is electrically connected to one of these first signal lines and one of these second signal lines, and includes a channel layer. The shielding pattern layer is disposed between the first metal layer and the second metal layer, and overlaps with the virtual center line on the normal line of the substrate, wherein the shielding pattern layer and these channel layers are formed by patterning the same film layer.

[0005] In at least one embodiment of the present invention, the shielding pattern layer includes a longitudinal portion extending along the first direction, and the longitudinal portion overlaps the virtual center line on the normal line of the substrate.

[0006] In at least one embodiment of the present invention, the array substrate further has a virtual staggered line that intersects with the virtual center line and extends along a second direction perpendicular to the first direction, and the virtual staggered line is perpendicular to the normal of the substrate, and the shielding pattern layer includes a lateral portion extending along the second direction, and the lateral portion overlaps with the virtual staggered line on the normal of the substrate.

[0007] In at least one embodiment of the present invention, the shielding pattern layer includes a cross pattern.

[0008] In at least one embodiment of the present invention, the shielding pattern layer overlaps with one of the first signal line and the second signal line on the normal line of the substrate.

[0009] In at least one embodiment of the present invention, the array substrate further has a display area and a peripheral area surrounding the display area and further includes an insulating layer, the insulating layer is arranged on the second metal layer and includes a protruding shielding portion located in the peripheral area, and the protruding shielding portion overlaps with one of the virtual center line and the virtual staggered line on the normal line of the substrate.

[0010] In at least one embodiment of the present invention, the material of the insulating layer includes photosensitive resin.

[0011] In at least one embodiment of the present invention, the array substrate further has a display area and a peripheral area surrounding the display area, one of the first metal layer and the second metal layer includes an external routing line located in the peripheral area, and the shielding pattern layer overlaps with the external routing line on the normal line of the substrate.

[0012] In at least one embodiment of the present invention, the material of the masking pattern layer and the channel layer includes semiconductor material.

[0013] At least one embodiment of the present invention provides a display device, comprising the array substrate and a display medium, wherein the display medium is disposed on the array substrate.

[0014] In at least one embodiment of the present invention, the display medium includes an electrophoretic electronic ink layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 is a schematic top view of an array substrate according to at least one embodiment of the present invention;

[0016] Figure 2A yes Figure 1 A magnified schematic diagram of the middle area A;

[0017] Figure 2B yes Figure 1 A magnified schematic diagram of the middle area B;

[0018] Figure 2C yes Figure 1 A magnified schematic diagram of the middle area C;

[0019] Figure 3 yes Figure 2A A schematic cross-sectional view drawn along the section line a-a';

[0020] Figure 4A yes Figure 1 A magnified schematic diagram of the middle area D;

[0021] Figure 4B yes Figure 1 A magnified schematic diagram of the middle region E;

[0022] Figure 5 yes Figure 1 A magnified schematic diagram of the middle region F;

[0023] Figure 6 yes Figure 5 A schematic cross-sectional view drawn along the section line b-b';

[0024] Figure 7 is a cross-sectional schematic diagram of a display device according to at least one embodiment of the present invention.

[0025]

Explanation of symbols

[0026] 1: Display device

[0027] 10: Array substrate

[0028] 100:Substrate

[0029] 101: First signal line

[0030] 102: Second signal line

[0031] 103: External wiring

[0032] 20: Display medium

[0033] A, B, C, D, E, F: Area

[0034] AA: Display area

[0035] AL: Channel Layer

[0036] a-a', b-b': hatching line

[0037] BD:Border

[0038] DC: drive circuit

[0039] DE: Drain

[0040] D1: First direction

[0041] D2: Second direction

[0042] EG: Edge

[0043] GC: Geometric Center

[0044] GE: Gate

[0045] GI: Gate Insulation Layer

[0046] HP: Horizontal part

[0047] M1: First metal layer

[0048] M2: Second metal layer

[0049] PA: Peripheral area

[0050] PT: Protruding shield

[0051] PV1: First insulation layer

[0052] PV2: Second insulation layer

[0053] PX: Pixel electrode

[0054] SE: Source

[0055] SP: Masking pattern layer

[0056] T: Active Components

[0057] VI: Virtual Interlaced Lines

[0058] VM: Virtual Center Line

[0059] VP:Vertical part DETAILED DESCRIPTION

[0060] The following is a detailed discussion of the embodiments of the present invention. However, it is to be understood that the embodiments provide many applicable concepts that can be implemented in a variety of specific contexts. The embodiments discussed and disclosed are for illustration only and are not intended to limit the scope of the present invention.

[0061] In order to clearly present the technical features of the present invention, the dimensions of the components in the drawings will be enlarged in a non-proportional manner, and the number of some components will be reduced. Therefore, the description and explanation of the embodiments of the present invention are not limited to the number of components in the drawings and the dimensions and shapes presented by the components, but should cover the dimensions, shapes and deviations of the two caused by actual processes and / or tolerances. For example, the flat surface shown in the drawings may have rough and / or nonlinear features, and the sharp angles shown in the drawings may be rounded. Therefore, the elements presented in the drawings are mainly for illustration, and are not intended to accurately depict the actual shape of the elements, nor are they intended to limit the scope of protection claimed in the present invention.

[0062] Secondly, the words "about", "approximately" or "substantially" used in the present invention not only cover the numerical values ​​and numerical ranges clearly recorded, but also cover the permissible deviation range that can be understood by a person with ordinary knowledge in the technical field to which the invention belongs, wherein the deviation range can be determined by the error generated during measurement, and the error is caused by the limitation of the measurement system or process conditions. For example, two objects (such as the planes or traces of the substrate) are "substantially parallel" or "substantially perpendicular", wherein "substantially parallel" and "substantially perpendicular" respectively represent that the parallelism and perpendicularity between the two objects may include the non-parallelism and non-perpendicularity caused by the permissible deviation range.

[0063] In addition, "approximately" may mean within one or more standard deviations of the above values, such as ±30%, ±20%, ±10% or ±5%. The words "approximately", "approximately" or "substantially" used in the present invention may be selected based on the optical properties, etching properties, mechanical properties or other properties to select an acceptable deviation range or standard deviation, rather than applying a single standard deviation to all properties such as the above optical properties, etching properties, mechanical properties and other properties.

[0064] The spatially relative terms used in the present invention, such as "below", "under", "above", "on", etc., are for the purpose of facilitating the description of the relative relationship between one element or feature and another element or feature, as shown in the figure. The true meaning of these spatially relative terms includes other orientations. For example, when the figure is flipped up and down 180 degrees, the relationship between one element and another element may change from "below" or "under" to "above" or "on". In addition, the spatially relative descriptions used in the present invention should also be interpreted in the same way.

[0065] It should be understood that, although the present invention may use the terms "first", "second", "third" and the like to describe various elements or features, these elements or features should not be limited by these terms. These terms are mainly used to distinguish one element from another element, or one feature from another feature. In addition, the term "or" used in the present invention may include any one or more combinations of the associated listed items depending on the actual situation.

[0066] In addition, the present invention may be implemented or applied through other different specific embodiments, and the details of the present invention may also be combined, modified and changed in various embodiments based on different viewpoints and applications without departing from the concept of the present invention.

[0067] Figure 1 is a schematic top view of an array substrate according to at least one embodiment of the present invention. Figure 2A yes Figure 1 Schematic diagram of the enlarged area A in the middle. Figure 3 yes Figure 2AA schematic cross-sectional view of the diagram along the section line a-a'. Figure 1 and Figure 2A The array substrate 10 has a geometric center GC and a virtual center line VM passing through the geometric center GC and extending along a first direction D1. The array substrate 10 includes a substrate 100, a first metal layer M1, a second metal layer M2, a plurality of active components T and a shielding pattern layer SP. The virtual center line VM is perpendicular to the normal of the substrate 100, that is, the virtual center line VM is parallel to the surface of the substrate 100.

[0068] See also Figure 2A and Figure 3 , the first metal layer M1 is disposed on the substrate 100 and includes a plurality of first signal lines 101. The second metal layer M2 is disposed on the first metal layer M1 and includes a plurality of second signal lines 102. These active elements T are disposed on the substrate 100, each active element T is electrically connected to one of the first signal lines 101 and one of the second signal lines 102, and includes a channel layer AL. The shielding pattern layer SP is disposed between the first metal layer M1 and the second metal layer M2, and overlaps with the virtual center line VM on the normal line of the substrate 100, and is formed by patterning the same film layer as these channel layers AL, that is, the shielding pattern layer SP and the channel layer AL are made of the same material and formed by the same process.

[0069] By providing a patterned shielding pattern layer formed together with the active device channel layer, and the shielding pattern layer overlaps with the virtual center line passing through the geometric center of the array substrate, the number of masks can be reduced and the process can be simplified by using a spliced ​​halftone mask, while the circuits at the mask splicing can still be protected from being etched and disconnected, thereby maintaining the yield.

[0070] Please continue reading Figure 2A and Figure 3 .like Figure 2A As shown, the first signal lines 101 are arranged at intervals along the first direction D1 and extend along the second direction D2, and the second signal lines 102 are arranged at intervals along the second direction D2 and extend along the first direction D1. The array substrate 10 further includes a plurality of pixel electrodes PX, each of which is electrically connected to one of the active elements T. Figure 3 As shown, each active element T further includes a gate GE, a gate insulating layer GI, a source SE and a drain DE. The gate GE is disposed on the substrate 100, the gate insulating layer GI is disposed on the gate GE, the channel layer AL is disposed on the gate insulating layer GI, and the source SE and the drain DE are disposed on the channel layer AL. The array substrate 10 further includes a first insulating layer PV1 disposed on the source SE and the drain DE and a second insulating layer PV2 disposed on the first insulating layer PV1.

[0071] In this embodiment, the active device T is a bottom-gate thin film transistor. However, the present invention is not limited thereto, and in other embodiments, the active device T may be a top-gate thin film transistor, a three-dimensional channel (vertical channel) thin film transistor, other suitable thin film transistors, or other types of active devices.

[0072] like Figure 3 As shown, the first metal layer M1 further includes a gate GE, and the gate GE and the first signal line 101 are formed by patterning the same film layer, and the second metal layer M2 further includes a source SE and a drain DE, and the source SE and the drain DE and the second signal line 102 are formed by patterning the same film layer, that is, the gate GE and the first signal line 101 are made of the same material and are formed by the same process, and the source SE and the drain DE and the second signal line 102 are made of the same material and are formed by the same process.

[0073] In some embodiments, the first signal line 101 may be a scan line, and the second signal line 102 may be a data line. However, the elements included in the first metal layer M1 and the second metal layer M2 are not limited to the above embodiments. For example, the first metal layer M1 may include the second signal line 102, the source SE and the drain DE, and the second metal layer M2 may include the first signal line 101 and the gate GE.

[0074] In some embodiments, the material of the substrate 100 may include quartz, glass, polymer material or other appropriate materials. In some embodiments, the first metal layer M1, the second metal layer M2 and the pixel electrode PX, the first insulating layer PV1 and the second insulating layer PV2 may be formed on the substrate 100 by a deposition process, an inkjet process, a printing process, a coating process, a lithography process and / or other appropriate processes.

[0075] In some embodiments, the first metal layer M1 and the second metal layer M2 may include metals with good conductivity, such as aluminum, molybdenum, titanium, copper, etc. In some embodiments, the material of the channel layer AL and the shielding pattern layer SP may include semiconductor materials, such as silicon semiconductor materials (such as polycrystalline silicon, amorphous silicon, etc.), oxide semiconductor materials, organic semiconductor materials, other appropriate materials, or a single layer, multiple layers, or a combination of the foregoing materials. In some embodiments, the material of the pixel electrode PX may include an opaque conductive material, a transparent conductive material, or a combination thereof, wherein the opaque conductive material may be, for example, molybdenum, molybdenum nitride, molybdenum niobium, etc., and the transparent conductive material may be, for example, indium tin oxide or indium zinc oxide, etc.

[0076] In some embodiments, the first insulating layer PV1 and the second insulating layer PV2 may be a single-layer structure or a multi-layer stacked structure, and their materials may include inorganic insulating materials, organic insulating materials or a combination thereof, wherein the inorganic insulating material may be, for example, silicon oxide, silicon nitride, silicon oxynitride, etc., and the organic insulating material may be, for example, acrylic, siloxane, polyimide, epoxy, photosensitive resin, etc.

[0077] Figure 2B and Figure 2C They are Figure 1 Enlarged diagram of area B and area C. Figure 1 and FIG. 2A to FIG. 2C .like Figure 1 As shown, the array substrate 10 further has a virtual interlaced line VI interlaced with the virtual center line VM and extending along a second direction D2 perpendicular to the first direction D1, and the virtual interlaced line VI is perpendicular to the normal of the substrate 100, that is, the virtual interlaced line VI is parallel to the surface of the substrate 100 and perpendicular to the virtual center line VM.

[0078] like Figure 2A and Figure 2B As shown, the shielding pattern layer SP includes a longitudinal portion VP extending along the first direction D1, and the longitudinal portion VP overlaps with the virtual center line VM on the normal line of the substrate 100. Figure 2A and Figure 2C As shown, the shielding pattern layer SP includes a transverse portion HP extending along the second direction D2 , and the transverse portion HP overlaps with the virtual interlaced line VI on the normal line of the substrate 100 .

[0079] In some embodiments, the mask stitching is on the normal line of the substrate 100 and overlaps with the virtual center line VM. In some embodiments, the mask stitching is on the normal line of the substrate 100 and overlaps with the virtual staggered line VI. In some embodiments, the shielding pattern layer SP includes a cross pattern.

[0080] In addition, if Figure 2A and Figure 3 As shown, the longitudinal portion VP overlaps the second signal line 102 on the normal line of the substrate 100, and the transverse portion HP overlaps the first signal line 101 on the normal line of the substrate 100. Through the above design, the shielding pattern layer SP can protect the circuit located below it from being etched and disconnected. For example, Figure 3 As shown, the lateral portion HP of the shielding pattern layer SP can protect the first signal line 101 thereunder.

[0081] Figure 4A and Figure 4B They are Figure 1Enlarged diagram of area D and area E. Figure 1 , Figure 4A and Figure 4B .like Figure 1 As shown, the array substrate 10 further has a display area AA and a peripheral area PA surrounding the display area AA, and further includes a driving circuit DC and a circuit (not shown). The driving circuit DC is disposed in the peripheral area PA, and the circuit electrically connects the driving circuit DC with a first signal line 101 and a second signal line 102 located in the display area AA. Figure 4A and Figure 4B As shown, one of the first metal layer M1 and the second metal layer M2 may include an external wiring 103 located in the peripheral area PA, and the shielding pattern layer SP overlaps the external wiring 103 on the normal line of the substrate 100 .

[0082] In detail, Figure 4A As shown, the outer wiring 103 of the first metal layer M1 located in the peripheral area PA extends along the second direction D2, and the lateral portion HP of the shielding pattern layer SP extending along the second direction D2 overlaps the outer wiring 103 on the normal line of the substrate 100. Figure 4B As shown, the outer wiring 103 of the second metal layer M2 located in the peripheral area PA extends along the first direction D1 , and the longitudinal portion VP of the shielding pattern layer SP extending along the first direction D1 overlaps the outer wiring 103 on the normal line of the substrate 100 .

[0083] In some embodiments, the driving circuit DC may be disposed in at least one chip, but is not limited thereto. Figure 1 In the embodiment, the driving circuit DC is disposed on the substrate 100, but is not limited thereto. In other embodiments, the driving circuit DC may be disposed on a circuit board and the circuit board is electrically connected to a pad (not shown) disposed on the substrate 100.

[0084] In some embodiments, the width of the shielding pattern layer SP may be greater than, less than, or equal to the width of the first signal line 101, the second signal line 102, and the external wiring 103, or a combination of the aforementioned width relationships, and may be adjusted according to the range of the mask joint and the line width at the mask joint. In some embodiments, the shielding pattern layer SP may be a continuous line segment or a discontinuous line segment, and may be adjusted according to the line layout at the mask joint. In some embodiments, the line segment shape of the shielding pattern layer SP may be a rectangular, circular, elliptical, or circular shape.

[0085] Figure 5 yes Figure 1 The second insulating layer PV2 includes a protruding shielding portion PT located in the peripheral area PA, and the protruding shielding portion PT overlaps with one of the virtual middle line VM and the virtual interlaced line VI on the normal line of the substrate 100. Figure 5As shown, the second insulating layer PV2 has an edge EG parallel to the boundary BD between the display area AA and the peripheral area PA, and includes a protruding shielding portion PT protruding from the edge EG and overlapping with the virtual interlaced line VI on the normal line of the substrate 100 .

[0086] Figure 6 yes Figure 5 A schematic cross-sectional view of the diagram along the section line b-b'. For ease of explanation, Figure 6 Only the substrate 100, the gate insulating layer GI, the second metal layer M2, the first insulating layer PV1 and the second insulating layer PV2 are shown. Figure 5 and Figure 6 The protruding shielding portion PT of the second insulating layer PV2 overlaps with the external wiring 103 of the second metal layer M2 in the peripheral area PA on the normal line of the substrate 100. Through the above design, the protruding shielding portion PT can protect the external wiring 103 from being etched and broken.

[0087] In some embodiments, one of the first insulating layer PV1 and the second insulating layer PV2 may include a protruding shielding portion, for example, one of the first insulating layer PV1 and the second insulating layer PV2 includes a protruding shielding portion and the other of the first insulating layer PV1 and the second insulating layer PV2 does not include a protruding shielding portion, or both the first insulating layer PV1 and the second insulating layer PV2 include a protruding shielding portion.

[0088] In some embodiments, other metal layers including external wiring located in the peripheral area PA may be provided between the second metal layer M2 and the second insulating layer PV2, that is, the protruding shielding portion of one of the first insulating layer PV1 and the second insulating layer PV2 may be used to protect the aforementioned other metal layers. In addition, the external wiring of the array substrate 10 may all be formed by the first metal layer M1, and the first insulating layer PV1 and the second insulating layer PV2 may not include the protruding shielding portion.

[0089] Figure 7 1 is a cross-sectional schematic diagram of a display device of at least one embodiment of the present invention. The display device 1 includes the above-mentioned array substrate 10 and a display medium 20 disposed on the array substrate 10. In some embodiments, the display medium 20 may include a liquid crystal layer, an electrowetting material layer, an electrophoretic electronic ink layer, a plurality of organic light emitting diodes or a plurality of light emitting diodes, wherein the light emitting diodes may be micro light emitting diodes (micro-LED, μLED) or sub-millimeter light emitting diodes (mini-LED). When the display medium 20 is a liquid crystal layer, the substrate 100 may be a light-transmitting substrate. When the display medium 20 is an electrowetting material layer, an electrophoretic electronic ink layer, a plurality of organic light emitting diodes or a plurality of light emitting diodes, the substrate 100 may be an opaque circuit substrate.

[0090] In summary, the present invention forms a shielding pattern layer together with an active device channel layer through patterning, and the shielding pattern layer overlaps with a virtual center line passing through the geometric center of the array substrate. Therefore, while using a spliced ​​halftone mask to reduce the number of masks and simplify the process, the circuit located at the splicing of the mask can still be protected from being etched and disconnected, thereby maintaining the yield.

[0091] Although the present invention has been disclosed as above by way of embodiments, it is not intended to limit the present invention. A person having ordinary knowledge in the technical field may make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be determined by the definition of the attached claims.

Claims

1. An array substrate, It is characterized in that A device having a geometric center and a virtual center line passing through the geometric center and extending along a first direction, comprising: a substrate, wherein the virtual center line is perpendicular to a normal line of the substrate; a first metal layer, disposed on the substrate and comprising a plurality of first signal lines; a second metal layer, disposed on the first metal layer and comprising a plurality of second signal lines; A plurality of active components are disposed on the substrate, wherein each of the active components is electrically connected to one of the plurality of first signal lines and one of the plurality of second signal lines, and comprises a channel layer; and A shielding pattern layer is disposed between the first metal layer and the second metal layer, wherein the shielding pattern layer overlaps with the virtual center line on the normal line of the substrate, and the shielding pattern layer and the plurality of channel layers are formed by patterning the same film layer.

2. The array substrate according to claim 1, It is characterized in that The shielding pattern layer includes a longitudinal portion extending along the first direction, and the longitudinal portion overlaps the virtual center line on the normal line of the substrate.

3. The array substrate according to claim 2, It is characterized in that There is also a virtual interlaced line that intersects with the virtual center line and extends along a second direction perpendicular to the first direction, and the virtual interlaced line is perpendicular to the normal line of the substrate, wherein the shielding pattern layer includes a lateral portion extending along the second direction, and the lateral portion overlaps with the virtual interlaced line on the normal line of the substrate.

4. The array substrate according to claim 3, It is characterized in that The shielding pattern layer includes a cross pattern.

5. The array substrate according to claim 3, It is characterized in that The shielding pattern layer overlaps one of the plurality of first signal lines and the plurality of second signal lines on the normal line of the substrate.

6. The array substrate according to claim 3, It is characterized in that It also has a display area and a peripheral area surrounding the display area, and also includes an insulating layer, wherein the insulating layer is arranged on the second metal layer and includes a protruding shielding portion located in the peripheral area, and the protruding shielding portion overlaps with one of the virtual center line and the virtual staggered line on the normal line of the substrate.

7. The array substrate according to claim 6, It is characterized in that The material of the insulating layer includes a photosensitive resin.

8. The array substrate according to claim 1, It is characterized in that It also has a display area and a peripheral area surrounding the display area, one of the first metal layer and the second metal layer includes an external wiring located in the peripheral area, and the shielding pattern layer overlaps with the external wiring on the normal line of the substrate.

9. The array substrate according to claim 1, It is characterized in that The materials of the shielding pattern layer and the plurality of channel layers include a semiconductor material.

10. A display device, It is characterized in that include: An array substrate as claimed in claim 1; and A display medium is disposed on the array substrate.

11. The display device according to claim 10, It is characterized in that The display medium includes an electrophoretic electronic ink layer.

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