Nitride semiconductor light-emitting device and display device having same

Abstract

The invention provides a nitride semiconductor light emitting device and a display device. The nitride semiconductor light-emitting device includes: a P-type nitride semiconductor layer; an N-type nitride semiconductor layer; an InGaN well layer located between the P-type nitride semiconductor layer and the N-type nitride semiconductor layer; a barrier layer having a band gap wider than that of the InGaN well layer; and a stress relief layer between the barrier layer and the InGaN well layer, wherein the stress relief layer includes a plurality of InN structures spaced apart from each other and distributed on the barrier layer.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application is based on and claims the benefit of priority of Korean Patent Application No. 10-2023-0173375 filed in the Korean Intellectual Property Office on December 4, 2023, and Korean Patent Application No. 10-2024-0019896 filed in the Korean Intellectual Property Office on February 8, 2024, the disclosures of which are incorporated herein in their entirety by reference. Technical Field

[0003] The present disclosure relates to a nitride semiconductor light emitting device and a display device including the nitride semiconductor light emitting device. Background Art

[0004] A semiconductor light emitting device may be a semiconductor device configured to generate light having a specific wavelength through recombination of electrons and holes. A nitride semiconductor light emitting device may be configured to emit blue light, green light, and red light, and may be used as a variety of light sources such as display devices and general lighting.

[0005] In nitride semiconductor light emitting devices, the internal quantum efficiency can decrease rapidly as the wavelength increases. Therefore, a method of improving the internal quantum efficiency is needed. Summary of the invention

[0006] Provided is a nitride semiconductor light emitting device capable of efficiently emitting long-wavelength light.

[0007] Additional aspects will be set forth in part in the description which follows and, in part, will be apparent from the description, or may be learned by practice of the presented embodiments.

[0008] According to one aspect of the present disclosure, a nitride semiconductor light-emitting device includes: a P-type nitride semiconductor layer; an N-type nitride semiconductor layer; an InGaN well layer located between the P-type nitride semiconductor layer and the N-type nitride semiconductor layer; a barrier layer having a wider band gap than the InGaN well layer; and a stress relief layer between the barrier layer and the InGaN well layer, wherein the stress relief layer includes a plurality of InN structures spaced apart from each other and distributed on the barrier layer.

[0009] According to one aspect of the present disclosure, a nitride semiconductor light-emitting device includes: a P-type nitride semiconductor layer; an N-type nitride semiconductor layer; and an active layer, which is between the P-type nitride semiconductor layer and the N-type nitride semiconductor layer, wherein the active layer includes: a plurality of GaN barrier layers; a plurality of InGaN well layers, the plurality of InGaN well layers are arranged between the plurality of GaN barrier layers; and a plurality of stress relief layers, the plurality of stress relief layers are arranged between the plurality of GaN barrier layers and the plurality of InGaN well layers, wherein the plurality of stress relief layers include a plurality of InN structures distributed on the plurality of GaN barrier layers, and a plurality of InGaN intermediate layers between the plurality of InN structures on the plurality of GaN barrier layers, wherein the indium concentration of the plurality of InGaN intermediate layers is lower than the indium concentration of the plurality of InGaN well layers, and wherein the thickness of the plurality of InGaN intermediate layers is less than the thickness of the plurality of InGaN well layers.

[0010] According to one aspect of the present disclosure, a display device includes: a circuit board, which includes a plurality of driving elements; and a pixel array, which is arranged on the circuit board and includes a plurality of light-emitting devices, wherein each of the plurality of light-emitting devices includes: a P-type nitride semiconductor layer; an N-type nitride semiconductor layer; and an active layer, which is between the P-type nitride semiconductor layer and the N-type nitride semiconductor layer, wherein the active layer includes: a plurality of GaN barrier layers; a plurality of InGaN well layers, the plurality of InGaN well layers are arranged between the plurality of GaN barrier layers; and a plurality of stress relief layers, the plurality of stress relief layers are arranged between the plurality of GaN barrier layers and the plurality of InGaN well layers, wherein the plurality of stress relief layers include a plurality of InN structures distributed on the plurality of GaN barrier layers and a plurality of InGaN intermediate layers between the plurality of InN structures on the plurality of GaN barrier layers, wherein the indium concentration of the plurality of InGaN intermediate layers is lower than the indium concentration of the plurality of InGaN well layers, and wherein the thickness of the plurality of InGaN intermediate layers is less than the thickness of the plurality of InGaN well layers. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The above and other aspects, features and advantages of the present disclosure will become more apparent from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0012] Figure 1 is a cross-sectional view of a nitride semiconductor light emitting device according to an embodiment;

[0013] Figure 2A According to the embodiment Figure 1 is a partial enlarged view of portion "A" of Figure 2B yes Figure 1 A top view of a stress relief layer;

[0014] Figure 3 is a diagram showing a method according to an embodiment of the present invention. Figure 1A graph showing the change in the band gap in the stacking direction of a P-type nitride semiconductor layer in a nitride semiconductor light emitting device shown;

[0015] Figure 4 is a cross-sectional view of a nitride semiconductor light emitting device according to an embodiment;

[0016] Figure 5A is a cross-sectional view of a nitride semiconductor light emitting device according to an example embodiment, and Figure 5B is a diagram showing a method according to an embodiment of the present invention. Figure 5A a partial enlarged view of portion "B";

[0017] Figure 6 According to the embodiment, it is applicable to Figure 5A A partial enlarged view of a nitride semiconductor light emitting device of another embodiment of part “B”;

[0018] Figure 7 According to the embodiment, it is applicable to Figure 5A A partial enlarged view of a nitride semiconductor light emitting device of another embodiment of part “B”;

[0019] Fig. 8A is a side cross-sectional view of a nitride semiconductor light emitting device according to another embodiment, and Figure 8B is a diagram showing a method according to an embodiment of the present invention. Fig. 8A a partial enlarged view of portion “C”;

[0020] Fig. 9 is a graph showing wavelength and internal quantum efficiency of a nitride semiconductor light emitting device according to an embodiment;

[0021] Fig.10 is a schematic perspective view of a display device according to an embodiment;

[0022] Fig.11 is a diagram showing a method according to an embodiment of the present invention. Fig.10 A partial enlarged view of portion "D" of the display device is shown;

[0023] Fig.12 is a side sectional view showing a display device according to an embodiment;

[0024] Fig.13 is a driving circuit implemented by a display device according to an embodiment;

[0025] Fig.14 is a cross-sectional view showing a display device according to an embodiment; and

[0026] Fig.15 is a schematic diagram of an electronic device including a display device according to an embodiment. DETAILED DESCRIPTION

[0027] Hereinafter, example embodiments are described with reference to the accompanying drawings.

[0028] According to the tradition of the art, the embodiments are described and illustrated in the form of functional blocks, units and / or modules in the accompanying drawings. It will be understood by those skilled in the art that these blocks, units and / or modules are physically implemented by electronic (or optical) circuits (such as, logic circuits, discrete components, microprocessors, hard-wired circuits, memory elements, wiring connectors, etc.), and semiconductor-based manufacturing techniques or other manufacturing techniques can be used to form electronic (or optical) circuits. In the case of implementing blocks, units and / or modules by microprocessors or the like, they can be programmed with software (e.g., microcode) to perform the various functions discussed herein, and they can be optionally driven by firmware and / or software. Alternatively, each block, unit and / or module can be implemented by dedicated hardware, or can be implemented as a combination of dedicated hardware that performs some functions and processors that perform other functions (e.g., one or more programmed microprocessors and associated circuit systems). In addition, without departing from the scope of the present disclosure, each block, unit and / or module of the embodiment can be physically separated into two or more interacting and discrete blocks, units and / or modules. Furthermore, the blocks, units and / or modules of the embodiments may be physically combined into more complex blocks, units and / or modules without departing from the scope of the present disclosure.

[0029] Figure 1 is a cross-sectional view illustrating a nitride semiconductor light emitting device according to example embodiments.

[0030] The nitride semiconductor light emitting device 100 according to the present embodiment may include a substrate 10 , a first conductive type nitride semiconductor layer 30 , an active layer 40 , and a second conductive type nitride semiconductor layer 80 sequentially disposed on the substrate 10 .

[0031] According to an embodiment, the buffer layer 20 may be disposed between the substrate 10 and the first conductive type nitride semiconductor layer 30. The substrate 10 according to an embodiment may be an insulating substrate such as sapphire. In some embodiments, the buffer layer 20 may be or may include In x Al y Ga 1-x-y N (where 0≤x≤1, 0≤y≤1). For example, the buffer layer 20 may be or may include AlN, AlGaN, or InGaN. In some embodiments, the buffer layer 20 may include a plurality of layers having different compositions, or may include a layer having a gradually changing composition (eg, Al or In).

[0032] The first conductive type nitride semiconductor layer 30 may include N-type In x Aly Ga 1-x-y N-type nitride semiconductor layer (where 0≤x<1, 0≤y<1, 0≤x+y<1), and the N-type impurity may be Si. For example, the first conductive type nitride semiconductor layer 30 may include N-type GaN. Similarly, the second conductive type nitride semiconductor layer 80 may include P-type In x Al y Ga 1-x-y In some embodiments, the second conductive type nitride semiconductor layer 80 may be a nitride semiconductor layer of a low-concentration P-type GaN layer and a high-concentration P-type GaN layer. In this case, the P-type electrode 94 may be formed on the high-concentration P-type GaN layer.

[0033] According to an embodiment, the electron blocking layer 70 may be disposed between the second conductive type nitride semiconductor layer 80 and the active layer 40. The electron blocking layer 70 may have a band gap (or energy band gap) larger than that of the active layer 40 and adjacent layers, and may include Al y Ga (1-y) N represents a nitride single crystal layer. For example, the electron blocking layer 70 can be configured so that the band gap decreases as the distance increases. This grading or gradual change of the band gap can be achieved by adjusting the Al composition ratio. As an example, the electron blocking layer 70 can have a thickness of 5nm to 100nm.

[0034] The active layer 40 may have a multilayer structure including a well layer 60, a barrier layer 41, and a barrier layer 42. The band gaps of the barrier layers 41 and 42 may be greater than the band gap of the well layer 60. The active layer 40 according to the embodiment may be configured to emit light having a relatively long wavelength (e.g., a wavelength in the range of 500 nanometers (nm) to 650 nm). Long wavelength light may refer to green light (e.g., light having a wavelength in the range of 500 nm to 590 nm), orange light (e.g., light having a wavelength in the range of 590 nm to 620 nm), and red light (e.g., light having a wavelength in the range of 620 nm to 650 nm). The nitride semiconductor light emitting device 100 may be configured to emit light having a peak wavelength in the range of 620 nm to 650 nm.

[0035] According to an embodiment, the well layer 60 may include In x1 Ga 1-x1N represents a nitride single crystal. In an embodiment, x1 may represent a first indium composition ratio, which may be in the range of 0.3 to 0.5, and the thickness da of the well layer 60 (eg, Figure 2A The barrier layers 41 and 42 may include In a Ga 1-a N (where 0≤a≤0.2). For example, barrier layers 41 and 42 may include GaN. In some embodiments, barrier layers 41 and 42 may include GaN doped with N-type impurities such as Si. For example, the silicon doping concentration may be 1×10 17 / cm 2 Up to 1×10 19 / cm 2 and the thickness db of the barrier layers 41 and 42 (e.g., Figure 2A As shown) can be in the range of 5nm to 20nm.

[0036] The active layer 40 according to the embodiment may have a unique structure of a light emitting layer including a well layer 60. Figure 1 As shown, the active layer 40 may include a stress relief layer 50 between the well layer 60 and the barrier layer 42 .

[0037] The well layer 60 may have a relatively high indium composition ratio, but when the well layer 60 is formed to have a relatively large thickness and multiple layers during the growth process, excessive stress may be transmitted and the degree of variation of the indium composition may be enhanced, which may lead to an imbalance that produces a deep region (e.g., a deep local state) in which the band gap is locally reduced. Such a deep region may cause crystal defects and may cause a non-luminescent coupling factor within the well layer 60, which may lead to a reduction in internal quantum efficiency. To prevent this, an embodiment may include a stress relief layer 50 located between the barrier layer 42 and the well layer 60 stacked on the barrier layer 42. The stress relief layer 50 may include an InN structure 55, which may have a high concentration of indium and may be spaced apart from each other, and the stress relief layer 50 may also include an intermediate layer 54, which is used to perform lattice buffering between the well layer 60 and the barrier layers 41 and 42 while fixing the plurality of InN structures 55.

[0038] Each of the high-concentration InN structures 55 may be implemented in an island type or island configuration, which may mean that each high-concentration InN structure 55 is not connected to or directly contacts an adjacent high-concentration InN structure 55. The high-concentration InN structures 55 disposed on the barrier layer 42 may have a similar size range and may be uniformly distributed. In this case, "uniform distribution" is not necessarily intended to mean that the arrangement has regularity, but may mean that the size (e.g., diameter W1 and height h1) of each high-concentration InN structure 55 may be substantially the same and may be included in a similar size range. The high-concentration InN structure 55 may be grown as InN by injecting a high-concentration indium-containing gas and ammonia on the barrier layer 42 within a predetermined temperature range. Then, growth may be performed at a temperature of 650 degrees Celsius or lower, which may be lower than the temperature at which the crystal grows to form a high-concentration InN layer, so that the grown crystal may not form a layer. Each of the high-concentration InN structures 55 may have a high density, and therefore a small island-shaped high-concentration InN structure 55 may be formed. When these island-shaped high-concentration InN structures 55 are uniformly distributed throughout the barrier layer 42 and the well layer 60 above is composed of a thick In x1 Ga 1-x1 When N is formed, the local imbalance of the indium content can be offset. For each of the high-concentration InN structures 55, such as Figure 2A and Figure 2B As shown in , when observed in a cross section perpendicular to the upper surface of the substrate 10 in the stacking direction, the cross section may have a partial elliptical shape or, for example, a semi-elliptical shape, which may be a semi-elliptical shape having a first diameter W1 at the bottom, and the first diameter W1 may be equal to or greater than the height h1.

[0039] Therefore, the three-dimensional shape of the high-concentration InN structure 55 may have a dome shape and may be a part of a sphere. The first diameter W1 of each high-concentration InN structure 55 may be in the range of 0.5 nm to 1.0 nm, and the height h1 may be equal to or less than the first diameter W1, and may be in the range of about 0.3 nm to about 0.5 nm. In addition, the first separation distance d1 between the lower ends of two adjacent high-concentration InN structures 55 may be in a similar range, and may be, for example, 1 to 1.5 times the first diameter W1 as the minimum separation distance. When the first separation distance d1 is less than the minimum separation distance, the adjacent high-concentration InN structures 55 may be connected to each other and may grow to form a large structure, and this may act as a defect and may therefore reduce the internal quantum efficiency. Therefore, the size of the high-concentration InN structure 55 can be kept in a predetermined range by spacing them apart from each other, so that the first separation distance d1 is in the range of 1 to 1.5 times the first diameter W1, and 1 to 1.5 times the first diameter W1 may be the minimum separation distance. Therefore, when viewed as a whole, the plurality of island-shaped high-concentration InN structures 55 grown and uniformly distributed on the barrier layer 42 can be formed at 1.6e 17 Pieces / cm 2 To 3.2e 17 Pieces / cm 2 The density of is dispersed in the stress relief layer 50.

[0040] The stress relief layer 50 may further include an intermediate layer 54, which may be disposed on the barrier layer exposed between the plurality of high-concentration InN structures 55 and may also fix or otherwise maintain the plurality of high-concentration InN structures 55. The intermediate layer 54 may include an In x2 Ga 1-x2 N represents a nitride single crystal, and the second indium composition ratio x2 may be at a relatively low concentration, for example, in the range of 0 to 0.1. As an example, the intermediate layer 54 may be GaN, and in this case, the second indium composition ratio x2 may be substantially zero.

[0041] The intermediate layer 54 may have an indium composition ratio that is equal to or greater than the indium composition ratio of the barrier layer 42 and less than the indium composition ratio of the well layer 60, and may have an intermediate lattice that is greater than the lattice of the well layer 60 (which may be InGaN) and less than the lattice of the barrier layer 42 (which may be GaN), and thus may have a lattice relaxation function. In addition, the intermediate layer 54 may be formed on the barrier layer 42 on which a plurality of island-shaped high-concentration InN structures 55 may be grown, so as to simultaneously fix or hold the plurality of island-shaped high-concentration InN structures 55, and during a subsequent high-temperature process for forming the well layer 60, indium may be prevented from volatilizing from the surfaces of the plurality of island-shaped high-concentration InN structures 55. To this end, the thickness dc of the intermediate layer 54 may be equal to or less than the height h1 of the plurality of island-shaped high-concentration InN structures 55. When the midpoint of the height h1 of the plurality of island-shaped high-concentration InN structures 55 is defined as the virtual center line 1c, the upper surface of the intermediate layer 54 may be located at a level higher than the virtual center line 1c.

[0042] According to an embodiment, the upper surface of the intermediate layer 54 may have different levels according to the concentration of indium in the intermediate layer 54. For example, the lower the concentration of indium in the intermediate layer 54, the higher the upper surface of the intermediate layer 54 may be, but the upper surface may not be higher than the highest point n1 of the plurality of island-shaped high-concentration InN structures 55. For example, the maximum thickness dc of the intermediate layer 54 may be equal to the height h1 of the plurality of island-shaped high-concentration InN structures 55. Figure 2A An example in which the indium concentration of the intermediate layer 54 is not 0 (for example, an example in which the second indium composition ratio x2 is greater than 0 and less than 0.1) is shown. The upper surface of the intermediate layer 54 may be located at a level lower than the level of the highest point n1 of the plurality of island-shaped high-concentration InN structures 55 and higher than the level of the virtual center line 1c. As an example, the intermediate layer 54 may have a thickness dc of 2 / 3 to 4 / 5 of the height h1 of the plurality of island-shaped high-concentration InN structures 55. When the height h1 of the plurality of island-shaped high-concentration InN structures 55 is in the range of 0.3 nm to 0.5 nm, the thickness dc of the intermediate layer 54 may be in the range of at least 0.15 nm to 0.5 nm, which may be the same or similar to the thickness range of the stress relief layer 50.

[0043] Therefore, the stress relief layer 50 may include portions of the plurality of island-shaped high-concentration InN structures 55 protruding above the intermediate layer 54 and may have an embossed or raised appearance when viewed in a plan view, such as Figure 2B The portion of the island-shaped high-concentration InN structure 55 protruding above the upper surface of the intermediate layer 54 may be a spherical portion having an upper width W2 smaller than the first diameter W1 at the level of the upper surface of the intermediate layer 54. Therefore, the second separation distance d2 of the upper portion of the island-shaped high-concentration InN structure 55 at the level of the upper surface of the intermediate layer 54 may be greater than the first separation distance d1.

[0044] The well layer 60 may be disposed on the upper surface of the stress relief layer 50, for example, on the intermediate layer 54 on which the relief is formed. Therefore, a portion of the island-shaped high-concentration InN structure 55 may have a structure protruding into the well layer 60. In this way, when the island-shaped high-concentration InN structure 55 protrudes into the well layer 60, the regional imbalance of the indium concentration caused by the well layer 60 formed in multiple layers or formed as a relatively thick well layer 60 can be offset, and the well layer 60 can have an overall uniform indium concentration.

[0045] The barrier layers 41 and 42 may have a thickness db in the range of 5.0 nm to 20.0 nm, and the well layer 60 may have a thickness da smaller than the thickness db, for example, in the range of 2.0 nm to 5.0 nm. The stress relief layer 50 between the barrier layers 41 and 42 and the well layer 60 may have a thickness dc in the range of 0.15 nm to 0.5 nm, which may be similar to the thickness dc of the intermediate layer 54.

[0046] The following describes Figures 1 to 2B An example of the bandgap characteristics of the semiconductor light emitting device 100 of the embodiment shown in FIG.

[0047] like Figure 3 As shown, an InGaN layer having a small band gap can be used as a well layer 60 between barrier layers 42 having a large band gap. In order to be used as the well layer 60, an indium component and a critical value (e.g., in the range of 1 nm to 1.5 nm) or greater thickness may be required. If the critical value or greater thickness is not satisfied, photons may not be generated and an emission peak may not be generated, which may hinder the normal function of the light emitting layer.

[0048] Reference Figure 3 , the semiconductor light emitting device 100 according to the example embodiment may be arranged so that the stress relief layer 50 has a relatively very small thickness dc compared to the well layer 60. The stress relief layer 50 may be created to be very thin compared to the well layer 60, having a thickness dc of, for example, less than 1 nm, or having a thickness dc of, for example, 0.5 nm or less. Therefore, because the high-concentration InN structure 55 may have a higher indium composition than the barrier layer 42, the stress relief layer 50 may not function as a well layer, but the stress relief layer 50 may not form an emission peak (at Figure 3 ), and may not function as a light-emitting layer having a separate wavelength, but may perform lattice relaxation and indium component compensation functions.

[0049] Therefore, the semiconductor light emitting device 100 according to the example embodiment may further include a relatively very thin stress relief layer 50, which may not be used as a well layer between the barrier layer 42 and the well layer 60, and when the local imbalance of the indium composition is thereby resolved, the wavelength of the red light generated in the well layer 60 may be shifted to a longer wavelength, for example, by 40 nm or more, and thus, redder light may be emitted. In addition, since defects may be avoided by lattice buffering, internal photon efficiency may be improved.

[0050] Refer again Figure 1 The nitride semiconductor light emitting device 100 according to the present embodiment may include a first electrode 92 disposed on the first conductive type nitride semiconductor layer 30 , and an ohmic contact layer 90 and a second electrode 94 sequentially disposed on the second conductive type nitride semiconductor layer 80 .

[0051] The ohmic contact layer 90 may have a single layer or a double layer or more layer structure. The ohmic contact layer 90 may be implemented in various ways according to the chip structure. For example, when the nitride semiconductor light emitting device 100 has a flip chip structure (e.g., a structure that emits light in the direction of the substrate 10), the ohmic contact layer 90 may include a reflective metal layer. For example, the reflective metal layer may include Ag, Ni, Al, Rh, Pd, Ir, Ru, Mg, Zn, Pt, and Au. In some embodiments, the ohmic contact layer 90 may also include a light-transmitting electrode for distributing current between the reflective metal layer and the second conductive type nitride semiconductor layer 80.

[0052] As another example, when the nitride semiconductor light emitting device 100 has a structure that emits light in a direction opposite to the substrate 10, the ohmic contact layer 90 may include a light-transmitting electrode. The light-transmitting electrode may be a transparent conductive oxide layer or a nitride layer. The light-transmitting electrode may be, for example, indium tin oxide (ITO), zinc-doped indium tin oxide (ZITO), zinc indium oxide (ZIO), gallium indium oxide (GIO), zinc tin oxide (ZTO), fluorine-doped tin oxide (FTO), aluminum-doped zinc oxide (AZO), gallium-doped zinc oxide (GZO), In 4 Sn 3 O 12 and Zn (1-x) Mg x O (zinc magnesium oxide, 0≤x≤1). In some embodiments, the ohmic contact layer 90 may include graphene.

[0053] For example, similar to the ohmic contact layer 90, the first electrode 92 may include Ag, Ni, Al, Rh, Pd, Ir, Ru, Mg, Zn, Pt and Au, and may have a single layer or a double layer or more layer structure. In some embodiments, the first electrode 92 may include Cr / Au. The second electrode 94 may be a pad electrode located in a partial region of the ohmic contact layer 90. For example, the second electrode 94 may include Au, Sn, or Au / Sn. A pad electrode such as Au, Sn, or Au / Sn may also be provided on the first electrode 92.

[0054] In the following, reference will be made to Figures 4 to 8B Examples of various embodiments are described.

[0055] Reference Figure 4 In addition to the thickness dc being variable according to the composition of the intermediate layer 54 of the stress relief layer 50, the nitride semiconductor light emitting device 100a according to the present embodiment can be similar to Figures 1 to 2B The embodiments are basically similar.

[0056] Figure 4 The nitride semiconductor light-emitting device 100a may include a stress relief layer 50 between a barrier layer 42 and a well layer 60 stacked on the barrier layer 42, and the stress relief layer 50 may include a plurality of island-type InN structures 55 and an intermediate layer 54, wherein the intermediate layer 54 is used for lattice buffering between the well layer 60 and the barrier layer 42 while fixing or maintaining the plurality of island-type InN structures 55 at the same time.

[0057] The high-concentration InN structures 55 may each be implemented as an island type and may not be connected to or directly contact an adjacent high-concentration InN structure 55, and their shape, size, and uniform distribution may be consistent with the above. Figures 1 to 2B are the same or similar to those in .

[0058] When these island-shaped high-concentration InN structures 55 are uniformly distributed throughout the barrier layer 42, and when the well layer 60 formed on the top is composed of InN with a thick high-concentration indium x1 Ga 1-x1 When N is formed, the local imbalance of the indium component can be resolved.

[0059] For example, the first diameter W1 of each high-concentration InN structure 55 may be in the range of 0.5 nm to 1.0 nm, and the height h1 may be equal to or less than the diameter and in the range of about 0.3 nm to 0.5 nm. In an embodiment, the first separation distance d1 between two adjacent high-concentration InN structures 55 may be in a similar range, and the minimum separation distance may be 1 to 1.5 times the first diameter W1.

[0060] exist Figure 4In the example shown, the intermediate layer 54 may include a nitride single crystal containing GaN and not containing indium, and the intermediate layer 54 may have the same indium concentration as the barrier layer 42, but the island-shaped high-concentration InN structure 55 may be dispersed inside, thereby providing a stress relief effect. After a plurality of island-type high-concentration InN structures 55 are formed on the barrier layer 42, when the same GaN as the barrier layer 42 is deposited as the intermediate layer 54 to fix or maintain the plurality of island-type high-concentration InN structures 55, an indium-containing gas may not be introduced as a deposition gas, and the deposition temperature may not reach a temperature at which indium volatilizes from the surface of the high-concentration InN structure 55. However, if a deposition gas containing high-concentration indium is injected when forming the well layer 60 and growth is continued at a high temperature, when the high-concentration InN structure 55 is exposed above the intermediate layer 54, indium may diffuse from the exposed area and flow into the well layer 60. Such indium inflow into the well layer 60 may accelerate local irregularities of the indium component within the well layer 60. Therefore, when the GaN material having the second indium composition ratio x2 of 0 is used as the intermediate layer 54 , in order to cover all the high-concentration InN structures 55 , the height dc of the intermediate layer 54 and the height h1 of the high-concentration InN structures 55 may be substantially the same.

[0061] However, when the overdeposition causes the upper surface of the intermediate layer 54 to be located at a level higher than the highest point n1 of the high-concentration InN structure 55, the function of offsetting the regional imbalance of the indium component of the well layer 60 may be reduced. Therefore, the intermediate layer 54 may be deposited to a height equal to or equivalent to the height h1 of the plurality of island-shaped high-concentration InN structures 55, or may be deposited to substantially the same height. For example, the upper surface of the intermediate layer 54 may be located at a level within a range of ±10% of the total height h1 relative to the highest point n1 of the height h1 of the plurality of island-shaped high-concentration InN structures 55.

[0062] Therefore, when viewed from above the intermediate layer 54, the high-concentration InN structure 55 may not be observed, or may be observed as a relatively very small dot. Due to this minimal exposure, diffusion of indium into the well layer 60 may be minimized or prevented.

[0063] The barrier layer 42 may have a thickness db of 5.0 nm to 20.0 nm, and the well layer 60 may have a thickness da smaller than the thickness db, for example, a thickness da of 2.0 nm to 5.0 nm. The stress relief layer 50 between the barrier layer 42 and the well layer 60 may have a thickness dc of 0.3 nm to 0.5 nm, which may be the height h1 of the high-concentration InN structure 55.

[0064] Figure 5A is a side cross-sectional view of a nitride semiconductor light emitting device according to an example embodiment, Figure 5B It is shown Figure 5A A partial enlarged view of part "B".

[0065] Reference Figure 5A and Figure 5B The nitride semiconductor light emitting device 100b according to the example embodiment may include a plurality of sub-active layers 40a to 40c, wherein the active layer 40 intersects with a plurality of well layers 60 and a plurality of barrier layers 42. The plurality of sub-active layers 40a to 40c may include a multilayer structure including the barrier layer 42, the stress relief layers 50a to 50c, and the well layer 60. FIG. 5A to FIG. 5B An example in which the active layer 40 includes three sub-active layers 40a to 40c is shown, but the embodiment is not limited thereto, and the number of the sub-active layers 40a to 40c may be any desired number, for example, two to five. Each of the sub-active layers 40a to 40c may generate and emit red light having a specific wavelength according to the indium component of the well layer 60 which may serve as a light emitting layer, and within one semiconductor light emitting device 100b, the emission light from each light emitting layer may be synthesized to emit synthesized red light.

[0066] Reference Figure 5B Each barrier layer 42 within the sub-active layers 40a to 40c may have a stacked structure of a first sub-active layer 40a, a second sub-active layer 40b and a third sub-active layer 40c in a direction away from the upper surface of the first conductive type nitride semiconductor layer 30, and an upper barrier layer 41 may also be arranged on the well layer 60 of the third sub-active layer 40c.

[0067] The first sub-active layer 40a, the second sub-active layer 40b, and the third sub-active layer 40c may all include the same barrier layer 42 and the same well layer 60, which may be the same as Figures 1 to 2B The structures of the barrier layer 42 and the well layer 60 in FIG. 6 are basically the same.

[0068] In addition, the stress relief layers 50a to 50c of the first to third sub-active layers 40a to 40c may all have the same or similar structure. For example, the first stress relief layer 50a of the first sub-active layer 40a, the second stress relief layer 50b of the second sub-active layer 40b, and the third stress relief layer 50c of the third sub-active layer 40c may have the same or similar structure. Figures 1 to 2B For example, the high-concentration InN structures 55a to 55c may be formed to be dispersed in an island shape on the GaN barrier layer 42 below, and the intermediate layers 54a to 54c may be provided on the barrier layer 42 while simultaneously fixing the high-concentration InN structures 55a to 55c. The intermediate layers 54a to 54c may include In x2 Ga 1-x2N represents a nitride single crystal, and the second indium composition ratio x2 may be at a relatively low concentration, for example, at a concentration in the range of 0 to 0.1. If the second indium composition ratio x2 is not 0, the upper surface of the intermediate layer (54a to 54c) may be located at a level between the virtual center line 1c and the highest point n1 of the height of the high-concentration InN structures 55a to 55c. However, in some embodiments, as Figure 4 As shown, when the intermediate layers 54a to 54c include GaN having a second indium composition ratio x2 of 0, upper surfaces of the intermediate layers 54a to 54c may be located at substantially the same level as the height h1 of the high-concentration InN structures 55a to 55c.

[0069] According to the embodiment, indium compositions of the well layers 60 of the sub-active layers 40 a to 40 c may be different from each other, but the embodiment is not limited thereto.

[0070] Reference Figure 6 The nitride semiconductor light emitting device 100c according to the example embodiment may include a plurality of sub-active layers 40a to 40c, wherein the active layer 40 intersects with a plurality of well layers 60 and a plurality of barrier layers 42. The plurality of sub-active layers 40a to 40c may include a multilayer structure including the barrier layers 42, stress relief layers 50a to 50c, and the well layers 60, and may be different from each other except that the first to third stress relief layers 50a to 50c of the first to third sub-active layers 40a to 40c may be different from each other. Figure 5A and Figure 5B The examples shown are the same or similar.

[0071] In detail, the first sub-active layer 40a, the second sub-active layer 40b, and the third sub-active layer 40c may all include the same barrier layer 42 and the same well layer 60, and the barrier layer 42 and the well layer 60 may be connected to each other. Figures 1 to 2B The structures of the barrier layer 42 and the well layer 60 are the same or similar.

[0072] In the first stress relief layer 50a of the first sub-active layer 40a, the second stress relief layer 50b of the second sub-active layer 40b, and the third stress relief layer 50c of the third sub-active layer 40c, as the distance from the upper surface of the first conductive type nitride semiconductor layer 30 increases, the indium component of the intermediate layer 54 may decrease. x2 Ga 1-x2When the nitride single crystal represented by N is used, the first stress relief layer 50a has a second indium composition ratio x2 of 0.05 to 0.1, and the second stress relief layer 50b includes a second indium composition ratio x2 lower than the second indium composition ratio x2 of the first stress relief layer 50a, and may satisfy, for example, 0.02 to 0.04. In addition, the third stress relief layer 50c may have a second indium composition ratio x2 lower than the second indium composition ratio x2 of the second stress relief layer 50b, and may include, for example, a GaN material whose second indium composition ratio is substantially 0.

[0073] According to an embodiment, the high-concentration InN structures 55a to 55c of the first to third stress relief layers 50a to 50c may all have the same or similar shapes, and their shapes, sizes, and uniform distribution may all be consistent with each other. Figures 1 to 2B The same or similar to those described in .

[0074] Therefore, when the height h1 of the high-concentration InN structures 55a to 55c is in the range of 0.3nm to 0.5nm, the thicknesses dc1, dc2, and dc3 of the corresponding intermediate layers 54a to 54c of the first to third stress relief layers 50a to 50c may be different from each other according to the indium composition of the intermediate layer 54. The intermediate layers 54a to 54c may be collectively referred to as intermediate layers 54, and the thicknesses dc1, dc2, and dc3 may be collectively referred to as thickness dc.

[0075] For example, as the second indium composition ratio x2 of the intermediate layer 54 decreases, the thickness dc may become larger. Therefore, as the distance from the upper surface of the first conductive type nitride semiconductor layer 30 increases, the second indium composition ratio x2 of the intermediate layers 54a to 54c decreases, and the intermediate layer 54 may include stress relief layers 50a to 50c having large thicknesses dc1 to dc3.

[0076] like Figure 6 As shown, the thickness dc3 of the intermediate layer 54c of the top third sub-active layer 40c may be the largest, and the thickness dc1 of the intermediate layer 54a of the bottom first sub-active layer 40a may be the smallest. Because the upper surface of the intermediate layer 54a of the bottom first sub-active layer 40a may be located at a level higher than the virtual center line 1c of the height h1 of the high-concentration InN structure 55a, the upper surface may not be located at the same level as the virtual center line 1c or lower than the virtual center line 1c. For example, the thickness dc1 of the intermediate layer 54a may be 1 / 2 or higher of the height h1 of the high-concentration InN structure 55a. In addition, the thickness dc3 of the intermediate layer 54c of the top third sub-active layer 40c may not be greater than the height h1 of the high-concentration InN structure 55c, and may have a thickness dc3 substantially equal to the height h1 of the high-concentration InN structure 55c.

[0077] The thickness dc2 of the intermediate layer 54b of the second sub-active layer 40b may have a thickness between the thickness dc1 of the intermediate layer 54a of the first sub-active layer 40a and the thickness dc3 of the intermediate layer 54c of the third sub-active layer 40c. Therefore, as the distance from the upper surface of the first conductive type nitride semiconductor layer 30 increases, the size of the high-concentration InN structures 55a to 55c exposed on the first to third stress relief layers 50a to 50c in the first to third sub-active layers 40a to 40c may be smaller.

[0078] This may be because the stress relief layer 50a at the bottom may receive the greatest stress. To compensate for the stress, an intermediate layer 54 having a relatively large indium content may be applied, but as the need for stress compensation decreases toward the top, the thickness and composition may be adjusted accordingly because the function of removing the local imbalance of the indium content of the well layer 60 is further required.

[0079] Reference Figure 7 The nitride semiconductor light emitting device 100d according to the example embodiment may include a plurality of sub-active layers 40a to 40c, wherein the active layer 40 intersects with a plurality of well layers 60 and a plurality of barrier layers 42. The plurality of sub-active layers 40a to 40c may include a multilayer structure including the barrier layers 42, stress relief layers 50a to 50c, and the well layers 60, and may be different from the first to third sub-active layers 40a to 40c except that the first to third stress relief layers 50a to 50c of the first to third sub-active layers 40a to 40c are partially different. Figure 6 The examples shown are the same or similar.

[0080] In detail, the first sub-active layer 40a, the second sub-active layer 40b, and the third sub-active layer 40c all include the same barrier layer 42 and the same well layer 60, which can be connected to the substrate. Figures 1 to 2B The structures of the barrier layer 42 and the well layer 60 are the same or similar.

[0081] According to an embodiment, the high-concentration InN structures 55a to 55c of the first to third stress relief layers 50a to 50c may all have the same or similar shapes, and their shapes, sizes, and uniform distribution may all be consistent with each other. Figures 1 to 2B The same or similar to those described in .

[0082] Among the first stress relief layer 50a of the first sub-active layer 40a, the second stress relief layer 50b of the second sub-active layer 40b, and the third stress relief layer 50c of the third sub-active layer 40c, only the intermediate layer 54a of the first stress relief layer 50a, which may be the lowermost layer, may have a second indium composition ratio x2 in the range of 0.01 to 0.1, and the intermediate layer 54b of the second stress relief layer 50b and the intermediate layer 54c of the third stress relief layer 50c may all include GaN material whose second indium composition ratio x2 is substantially 0.

[0083] According to an embodiment, the high-concentration InN structures 55a to 55c of the first to third stress relief layers 50a to 50c may all have the same or similar shapes, and their shapes, sizes, and uniform distributions may all be consistent with those of the first to third stress relief layers 50a to 50c. Figures 1 to 2B The same or similar to those described in .

[0084] Therefore, when the height h1 of the high-concentration InN structures 55a to 55c is in the range of 0.3nm to 0.5nm, the thickness dc1 of the intermediate layer 54a of the first stress relief layer 50a may be less than the thicknesses dc2, dc3 of the intermediate layers 54b and 54c of the second stress relief layer 50b and the third stress relief layer 50c. However, the upper surface of the intermediate layer 54a of the first stress relief layer 50a may be higher than the virtual center line 1c of the height h1 of the high-concentration InN structure 55a, and therefore, the stress relief layer 50a may not be placed at the same or lower level than the virtual center line 1c. For example, the thickness dc1 of the intermediate layer 54a may be at least 1 / 2 of the height h1 of the high-concentration InN structure 55a and less than 1 times of the height h1 of the high-concentration InN structure 55a. However, the thicknesses dc2 and dc3 of the intermediate layers 54b and 54c of the second stress relief layer 50b and the third stress relief layer 50c may be substantially the same as each other, and therefore, may not be greater than the height h1 of the high-concentration InN structures 55b and 55c, and the thicknesses dc2 and dc3 may be substantially equal to the height h1 of the high-concentration InN structures 55b and 55c.

[0085] Therefore, the high-concentration InN structure 55a exposed only on the first stress relief layer 50a can be observed within the first to third sub-active layers 40a to 40c, and some of the high-concentration InN structures 55b and 55c can be substantially unobservable above the second and third stress relief layers 50b and 50c.

[0086] The stress relief layer 50a at the bottom receives the greatest stress. To compensate for the stress, an intermediate layer 54 having a relatively large indium content may be applied. As the need for stress compensation decreases toward the top, the thickness and composition may be set accordingly because the function of counteracting the regional imbalance of the indium content of the well layer 60 is further required.

[0087] Fig. 8A is a side cross-sectional view of a nitride semiconductor light emitting device according to another embodiment, Figure 8B It is shown Fig. 8A A partial enlarged view of part “C”.

[0088] Reference Fig. 8A and Figure 8B , the nitride semiconductor light emitting device 100e may include a conductive substrate 10', a buffer layer 20, a first conductive type nitride semiconductor layer 30, an active layer 40, and a second conductive type nitride semiconductor layer 80. The conductive substrate 10' according to the embodiment may be or may include silicon (Si), SiC, or GaN, and may be a substrate doped with first conductive type impurities (e.g., N-type impurities). For example, the conductive substrate 10' may be a silicon substrate used as a growth substrate.

[0089] The conductive substrate 10' can be used as part of a one-side electrode structure. For example, the conductive substrate 10' and the electrode 94 disposed on the second conductive type nitride semiconductor layer 80 can be used as two electrodes for a nitride semiconductor light emitting device. With this electrode arrangement, current flow can be achieved in the vertical direction.

[0090] The active layer 40 may have a multi-layer structure including a well layer 60 and a barrier layer 42 having a band gap larger than that of the well layer 60. The well layer 60 may include a layer composed of In x1 Ga 1-x1 The barrier layer 42 may include a nitride single crystal represented by N, and the first indium composition ratio x1 may be 0.3 to 0.5. a Ga 1-a The barrier layer 42 may include GaN. In some embodiments, the barrier layer 42 may include GaN doped with N-type impurities such as Si.

[0091] The active layer 40 according to the embodiment may include a plurality of sub-active layers 40a to 40c, similar to FIG. 5A to FIG. 7 Each of the sub-active layers 40 a to 40 c may include a stress relief layer 50 a to 50 c between the well layer 60 and the barrier layer 42 .

[0092] In the following, reference Fig. 9 , an example of the effects of an embodiment of the present disclosure is described in detail.

[0093] like Figure 1 and Figure 2B As shown, a nitride semiconductor light-emitting device can be manufactured according to Example 1.

[0094] After forming an N-type GaN layer on the sapphire substrate, an active layer may be formed, and a P-type electron blocking layer and a P-type GaN layer may be formed.

[0095] According to Example 1, according to the above embodiment, the active layer can form two stress relief layers and a well layer between three Si-doped GaN barrier layers. For example, a stress relief layer (having a thickness of about 0.3 nm) and an InGaN well layer (having a thickness of about 5 nm) can be sequentially grown on the barrier layer, the second indium composition ratio x2 of the middle layer of the stress relief layer can be about 0.1, and the first indium composition ratio x1 of the well layer can be about 0.35.

[0096] According to an embodiment, a high-concentration InN structure can be grown on the barrier layer by injecting indium gas and ammonia at a growth temperature of about 650 degrees. Due to the low growth temperature, InN may not form a layer, and each high-concentration InN structure may have a dome shape with a diameter of 0.5nm to 1nm and a height of 0.5nm or less, and may be grown to be uniformly dispersed. An intermediate layer may be grown while fixing a plurality of high-concentration InN structures. In this case, the thickness of the intermediate layer may be formed to be 0.3nm so that it is not greater than the height of the high-concentration InN structure.

[0097] According to Comparative Example 1, a nitride semiconductor light emitting device may be formed to have an active layer without the stress relief layer in Example 1.

[0098] For example, in the semiconductor light emitting device of Comparative Example 1, two well layers may be placed between three barrier layers, and the first indium composition ratio x1 of each of the two well layers may be 0.35, which may be the same as Example 1, and the semiconductor light emitting device may be formed to have a thickness of about 5 nm.

[0099] According to Comparative Example 2, a nitride semiconductor light emitting device may be formed to have an active layer without a stress relief layer as in Comparative Example 1, and two well layers may be formed between three barrier layers in the semiconductor light emitting device of Comparative Example 2. According to Comparative Example 2, in order to achieve a light emission peak similar to that of Example 1 according to the embodiment, a first indium composition ratio x1 of each of the two well layers may be formed to be 0.50, which may be higher than the indium composition ratio in the example according to the embodiment.

[0100] Fig. 9 The emission wavelength and quantum efficiency of Example 1 and Comparative Examples 1 and 2 are shown. Fig. 9 As shown, unlike Example 1 according to the embodiment, in the case of Comparative Example 1 where the stress relief layer does not exist, the emission wavelength may be about 580 nm, and the emission wavelength may thus be extended by about 40 nm to 620 nm.

[0101] In addition, comparing Example 1 with Comparative Example 2, in order to extend the emission wavelength, the thickness of the well layer can be increased or the indium content of the well layer can be made larger. Therefore, according to Comparative Example 2, it can cause an extension similar to that of Example 1 by greatly increasing the indium content of the well layer, which can significantly reduce the quantum efficiency.

[0102] Therefore, when the stress relief layer is formed and the indium composition ratio of the well layer is maintained within the range of 0.3 to 0.5 as in Example 1 according to the embodiment, quantum efficiency can be sufficiently ensured while extending the wavelength of emitted red light.

[0103] Below, reference Figures 10 to 15 Application examples according to the embodiment are described.

[0104] Figures 1 to 8B The light emitting device of the embodiment can also be used as a light source for a display device. Fig.10 is a schematic perspective view of a display device according to an example embodiment, Fig.11 It is shown Fig.10 A partial enlarged view of a portion "D" of the display device shown in FIG. Fig.12 is a side-sectional view illustrating a display device according to example embodiments.

[0105] Reference Figures 10 to 12 The display device 1000 according to the embodiment may include a circuit board 200 including a driving circuit and a pixel array 300 provided on the circuit board 200 and having a plurality of pixels PX arranged therein. The display device 1000 may further include a frame 11 surrounding the circuit board 200 and the pixel array 300.

[0106] The circuit board 200 may be a driving circuit board including a driving element 220. In some embodiments, the circuit board 200 may include only some of the driving circuits for the display device, in which case the display device 1000 may further include another driving element. In some embodiments, the circuit board 200 may implement a flexible or curved display device by including a flexible board.

[0107] The pixel array 300 may further include, in addition to the plurality of pixels PX, a connection pad PAD, a connection region (CR) connecting the plurality of pixels PX and the connection pad PAD, and an edge region (ISO).

[0108] Each of the plurality of pixels PX may include first to third sub-pixels SP1, SP2, and SP3, which are configured to emit light of a specific wavelength (e.g., a specific color) to provide a color image. For example, the first to third sub-pixels SP1, SP2, and SP3 may be configured to emit blue (B) light, green (G) light, and red (R) light, respectively. In each pixel PX, the first to third sub-pixels SP1, SP2, and SP3 may be arranged in, for example, a Bayer pattern. In detail, each pixel PX may include a first sub-pixel SP1 and a third sub-pixel SP3 arranged along a first diagonal direction, and two second sub-pixels SP2 arranged along a second diagonal direction intersecting the first diagonal direction.

[0109] The X direction and the Y direction may be perpendicular to each other and parallel to the upper surface of the display device 1000. The Z direction may be a direction perpendicular to the X direction and the Y direction, for example, may be a direction perpendicular to the upper surface of the display device 1000.

[0110] exist Fig.10 In the example shown, each pixel PX is shown as having a first subpixel SP1, a second subpixel SP2, and a third subpixel SP3 arranged in a 2×2 Bayer pattern, but the embodiment is not limited thereto. For example, in some embodiments, each pixel PX may be configured in a different arrangement (such as 3×3 or 4×4). In addition, in some embodiments, some subpixels may be configured to emit light of a color different from the colors shown (R, G, B), such as yellow light. Fig.10In the pixel array 300, for ease of explanation, a plurality of pixels PX are shown in a 15×15 array, which is a relatively small number of pixels, but it depends on the actual application product, and the size of the rows and columns increases. For example, in order to apply it to a high-resolution display, it is necessary to implement it in an array such as 1920×1080 (FHD), 3840×2160 (UHD), etc. In the case of a smart watch, a plurality of pixels PX has an array of about 400×400. Depending on the size of the display device, the pixel size and the unit LED element size vary. For example, assuming that a display device for a tablet, a smart phone, and a VR device has a vertical size of 152.4 mm, 50.8 mm, and 38.1 mm, various pixel densities ranging from 180 ppi to 1440 ppi may be required. At the same time, a light-emitting device with sufficient luminous efficiency is required. For the present application, an embodiment may provide a light-emitting device 100 having improved luminous efficiency and a size of 200 μm or less. For example, the light-emitting device 100 may have a size of 20 μm or less. As another example, the light emitting device 100 may have a size of 5 nm or more. In addition, a distance between adjacent light emitting devices 100 provided in the display device 1000 according to the embodiment may be in the range of 5 nm to 100 μm.

[0111] The connection pads PAD may be provided on at least one side of the plurality of pixels PX along an edge of the display device 1000. The connection pads PAD may be electrically connected to the plurality of pixels PX and a driving circuit of the circuit board 200. The connection pads PAD may electrically connect an external device and the display device 1000. In some embodiments, the number of connection pads PAD may vary and may be determined, for example, according to the number of pixels PX, a driving method of a driving circuit in the circuit board 200, and the like.

[0112] The connection region CR may be a region located between the plurality of pixels PX and the connection pad PAD. An interconnection structure electrically connected to the plurality of pixels PX, such as a common electrode, may be disposed in the connection region CR.

[0113] The edge area ISO may be an area along the edge of the pixel array 300. The frame 11 may be arranged around the pixel array 300, and serve as a guide for defining an arrangement space of the pixel array 300. For example, the frame 11 may include at least one of materials such as polymer, ceramic, semiconductor, or metal.

[0114] Reference Fig.12 , the display device 1000 may include a circuit board 200 and a pixel array 300 disposed on the circuit board 200 .

[0115] The circuit board 200 may include a semiconductor substrate 201, a driving circuit including a driving element 220 formed on the semiconductor substrate 201, an interconnection 230 electrically connected to the driving element 220, an interconnection line 240 on the interconnection 230, and a first interconnection insulating layer 290 covering the driving circuit. The circuit board 200 may also include a first bonding insulating layer 295 on the first interconnection insulating layer 290, and a first bonding electrode 298 disposed in the first bonding insulating layer 295 and connected to the interconnection line 240.

[0116] The semiconductor substrate 201 may include an impurity region including source / drain regions 205. The semiconductor substrate 201 may include, for example, a semiconductor such as silicon (Si) or germanium (Ge) or a compound semiconductor such as SiGe, SiC, GaAs, InAs, or InP.

[0117] The driving circuit may include a circuit for controlling the driving of pixels (particularly sub-pixels). The source region 205 of the driving element 220 may be electrically connected to an electrode of the light emitting stack 45 through an interconnect 230, an interconnect line 240, and a first bonding electrode 298. For example, the drain region 205 of the driving element 220 may be connected to data lines D1, D2, ..., Dn through an interconnect 230 and an interconnect line 240. The gate electrode 221 of the driving element 220 may be connected to gate lines G1, G2, ..., Gn through an interconnect 230 and an interconnect line 240. Reference will be made to Fig.13 The circuit configuration and operation are described in more detail.

[0118] The upper surface of the first bonding electrode 298 and the upper surface of the first bonding insulating layer 295 may form the upper surface of the circuit board 200. The first bonding electrode 298 may be bonded to the second bonding electrode 198 of the pixel array 300 to provide an electrical connection path. The first bonding electrode 298 may include a conductive material, such as copper (Cu). The first bonding insulating layer 295 may be bonded to the second bonding insulating layer 195 of the pixel array 300. The first bonding insulating layer 295 may include, for example, at least one of SiO, SiN, SiCN, SiOC, SiON, and SiOCN.

[0119] The pixel array 300 may include a plurality of light emitting devices 100 in which one light emitting device 100 is arranged for each sub-pixel SP1, SP2, and SP3. The light emitting device 100 may be configured using Figures 1 to 8B At least some of the first electrodes 92 and the second electrodes 94 of the plurality of light emitting devices 100 may be connected to each other and formed as one body.

[0120] The pixel array 300 may include a plurality of light emitting stacks 45, a passivation layer 120 covering each side of the light emitting stacks 45, and a first electrode 92 and a second electrode 94 electrically connected to the light emitting stacks 45. The pixel array 300 may include wavelength conversion units 160R, 160G, and 160B, color filters 180R and 180G, and a microlens 185 located on the light emitting stacks 45. The pixel array 300 may also include a blocking structure BS surrounding the sides of the wavelength conversion units 160R, 160G, and 160B and separating the wavelength conversion units from each other. In addition, the pixel array 300 may also include a sealing layer 182 and a planarization layer 184, a common electrode 145, a first pad electrode 147, a second interconnection insulating layer 190, a second bonding insulating layer 195, a second bonding electrode 198, and a second pad electrode 199 on the wavelength conversion units 160R, 160G, and 160B.

[0121] The light emitting stack 45 includes a second conductive type nitride semiconductor layer 80 (e.g., a P-type nitride semiconductor layer), a first conductive type nitride semiconductor layer 30 (e.g., an N-type nitride semiconductor layer), and an active layer 40 disposed therebetween, a first electrode 92 may be electrically connected to the first conductive type nitride semiconductor layer 30, and a second electrode 94 may be electrically connected to the second conductive type nitride semiconductor layer 80. The passivation layer 120 may extend to the lower surface of the light emitting stack 45, and the second electrode 94 may penetrate the passivation layer 120 and be connected to the second conductive type nitride semiconductor layer 80.

[0122] The pixel array 300 may further include a P-type contact electrode 85 in contact with the entire lower surface of each second conductive type nitride semiconductor layer 80. At this time, the passivation layer 120 may extend to the lower surface of the light emitting stack 45 while covering the P-type contact electrode 85. The second electrode 94 may contact the P-type contact electrode 85. The P-type contact electrode 85 may have a central portion that is thicker than a peripheral portion.

[0123] The wavelength conversion units 160R, 160G, and 160B may be respectively disposed on the light emitting stack 45. The wavelength conversion units 160R, 160G, and 160B may be regions in which wavelength conversion materials such as quantum dots are dispersed in a liquid binder resin and filled and cured within the blocking structure BS, respectively. The first wavelength conversion unit 160R and the second wavelength conversion unit 160G may include quantum dots capable of converting blue light into red light and green light, respectively, and the third wavelength conversion unit 160B may form a transparent resin unit by including only a binder resin without including separate quantum dots.

[0124] The barrier wall reflective layer 170 may be disposed within the barrier structure BS to surround the side surfaces and the lower surface of the wavelength conversion units 160R, 160G, and 160B. The barrier wall reflective layer 170 may include a first barrier rib insulating layer 172, a barrier metal layer 174, and a second barrier rib insulating layer 176, respectively, which are sequentially arranged from the bottom. The barrier metal layer 174 may be disposed only on the side surfaces of the wavelength conversion units 160R, 160G, and 160B, and may not be disposed below the lower surface. The lower surface of the barrier wall reflective layer 170 may be located at a higher level than the uppermost surface of the first electrode 92. The first barrier rib insulating layer 172 and the second barrier rib insulating layer 176 may include an insulating material, such as SiO 2 The barrier metal layer 174 may include at least one of SiN, SiCN, SiOC, SiON, and SiOCN. The barrier metal layer 174 may include a reflective metal, for example, at least one of silver (Ag), nickel (Ni), and aluminum (Al).

[0125] The sealing layer 182 may be disposed to cover the upper surfaces of the wavelength conversion units 160R, 160G, and 160B. The sealing layer 182 may serve as a protective layer to prevent the wavelength conversion units 160R, 160G, and 160B from being degraded. In some embodiments, the sealing layer 182 may be omitted.

[0126] Color filters 180R and 180G may be disposed in the second subpixel SP2 and the third subpixel SP3 and on the wavelength conversion units 160R, 160G, and 160B. The color filters 180R and 180G may increase the color purity of light emitted by the first wavelength conversion unit 160R and the second wavelength conversion unit 160G. In some embodiments, a color filter may also be disposed on the third wavelength conversion unit 160B.

[0127] The planarization layer 184 may be disposed to cover upper surfaces of the color filters 180R and 180G and the sealing layer 182. The planarization layer 184 may be a transparent layer.

[0128] The microlenses 185 may be arranged to correspond to the wavelength conversion units 160R, 160G, and 160B, respectively, on the planarization layer 184. The microlenses 185 may converge light incident from the wavelength conversion units 160R, 160G, and 160B. For example, the microlenses 185 may have a diameter greater than the width of the light emitting stack 45 in the X and Y directions. The microlenses 185 may be formed of, for example, a transparent photoresist material or a transparent thermosetting resin film.

[0129] The light emitting stack 45 may be formed by deposition on the substrate 10 using a method such as metal organic chemical vapor deposition (MOCVD). In an embodiment, the substrate 10 may be, for example, a growth substrate. When a substrate 10 made of a material different from the light emitting stack 45 is used, after forming the buffer layer 20 on the substrate 10, the light emitting stack 45 may be formed on the buffer layer 20. The light emitting stack 45 may be made of a nitride semiconductor containing Ga.

[0130] During the manufacturing process of the light emitting device 100, the substrate 10 and the buffer layer 20 may be partially or completely removed. Therefore, the light emitting device 100 may further include the substrate 10, and may further include the buffer layer 20 between the substrate 10 and the light emitting stack 45. In some cases, only a portion of the buffer layer 20 may be included without including the substrate 10.

[0131] To create pixel array 300, Figure 1 A buffer layer 20 is formed on a substrate 10 in the same manner as the light emitting device 100 of the present invention, and after forming a light emitting stack 45 by sequentially stacking a first conductive type nitride semiconductor layer 30, an active layer 40, and a second conductive type nitride semiconductor layer 80 on the buffer layer 20, the light emitting stack 45 in the device isolation region DS is removed from the direction of the second conductive type nitride semiconductor layer 80 to create a plurality of light emitting stacks 45. In addition, some or all of the substrate 10 and the buffer layer 20 may be removed from the substrate direction. According to an embodiment, a groove for arranging the wavelength conversion units 160R, 160G, and 160B in a window region corresponding to each light emitting stack 45 is etched away and removed. A barrier structure BS including barrier ribs disposed on the device isolation region DS is formed. In the window region where the wavelength conversion units 160R, 160G, and 160B are to be installed, the substrate 10 may be completely removed, and a portion or all of the buffer layer 20 may be removed. A portion or all of the substrate 10 and the buffer layer 20 may be removed from a portion corresponding to the isolation member on the device isolation region DS. When the substrate 10 is not completely removed, the blocking structure BS of the pixel array 300 includes the substrate 10 , and may further include a portion of the buffer layer 20 .

[0132] Fig.13 is a driving circuit implemented in a display device according to example embodiments.

[0133] Reference Fig.13, a circuit diagram of a display device 1000 in which N×N sub-pixels are arranged is shown. The first to third sub-pixels SP1, SP2, and SP3 may each receive a data signal through data lines D1 to Dn as a vertical path (e.g., a column direction). The first to third sub-pixels SP1, SP2, and SP3 may receive a control signal such as a gate signal through gate lines G1 to Gn as a horizontal path, such as a row direction.

[0134] A plurality of pixels PX including first to third subpixels SP1, SP2, and SP3 provide an active area DA for display, and the active area DA is used as a display area for a user. A non-active area NA may be formed along one or more edges of the active area DA. The non-active area NA may extend along the periphery of the panel of the display device 1000, may be an area where no pixels PX exist, and may correspond to the frame 11 (see FIG. 1 ) of the display device 1000. Fig.10 ).

[0135] The first driver circuit 12 and the second driver circuit 13 may be used to control the operation of the pixel PX (e.g., the first to third sub-pixels SP1, SP2, and SP3). Some or all of the first driver circuit 12 and the second driver circuit 13 may be implemented on the circuit board 200. The first driver circuit 12 and the second driver circuit 13 may be formed by an integrated circuit, a thin film transistor panel circuit, or other suitable circuits, and may be disposed in the non-active area NA of the display device 1000. The first driver circuit 12 and the second driver circuit 13 may include a microprocessor, a memory such as a storage, a processing circuit system, and a communication circuit system.

[0136] In order to display an image through the pixel PX, the first driver circuit 12 supplies image data to the data lines D1 to Dn, and provides a clock signal and other control signals to the second driver circuit 13 as a gate driver circuit. The second driver circuit 13 may be implemented using an integrated circuit and / or a thin film transistor circuit. Gate signals for controlling the first to third sub-pixels SP1, SP2, and SP3 arranged in a row direction may be transmitted through the gate lines G1 to Gn of the display device 1000.

[0137] Fig.14 is a side-sectional view illustrating a display device according to example embodiments.

[0138] Reference Fig.14 The display device 1000a may include a circuit board 200 and a pixel array 300 disposed on the circuit board 200, and may include a plurality of Fig.12However, the display device 1000a according to the present embodiment may have a blocking structure BS' and an interconnection structure that are different from the components of the display device 1000 described above. Fig.12 The barrier structure BS and the resulting interconnect structure are shown.

[0139] According to an embodiment, the pixel array 300 may include a blocking structure BS' formed separately from the light emitting stack 45. The blocking structure BS' may include a conductive material and may simultaneously serve as a portion of the first electrode structure. In this case, the blocking structure BS' may be arranged between each light emitting stack 45 to overlap a portion of the peripheral region of the light emitting stack 45 in the Z-axis direction.

[0140] The blocking structure BS' may be connected to each first conductive type nitride semiconductor layer 30 of the light emitting stack 45 through an N-type contact electrode 83. The N-type contact electrode 83 may be made of a transparent conductive material such as ITO, and may be in direct contact with the first conductive type nitride semiconductor layer 30 without the N-type contact electrode 83. The blocking structure BS' may be formed of a highly reflective material such as Ag, and a first barrier rib insulating layer 172 surrounding the sides of the wavelength conversion units 160R, 160G, and 160B may be disposed on the blocking structure BS'. The pixel array 300 may include a second pad electrode 199 formed on an exposed region of the blocking structure BS'.

[0141] In the example embodiment Figures 10 to 14 The display devices 1000 and 1000a may be full-color monolithic display devices including a light emitting device array formed at a wafer level, and may be characterized in that the light emitting device array is formed at a wafer level without performing a pick and place process on individual chips of individual light emitting devices 100, thereby increasing the density between the light emitting devices. The width of the device isolation region for separating the light emitting devices on the wafer becomes the gap between the light emitting devices 100 in the light emitting device 100.

[0142] The display device according to the embodiment is not limited to the above-mentioned specific display devices 1000 and 1000a, and some configurations may be excluded or modified. For example, a monochrome monolithic display device that does not include the wavelength conversion units 160B, 160G, and 160R or the color filters 180R and 180G may be configured. The display device 1000 may be formed by moving the light emitting device 100 on a circuit board using a pick and place method. Figures 1 to 8B The light emitting devices 100, 100a, 100b, 100c, and 100d of the exemplary embodiment are arranged in an array form and combined with a substrate including a driving element, thereby forming the display device 1000 of the exemplary embodiment.

[0143] Fig.15 is a schematic diagram of an electronic device including a display device according to example embodiments.

[0144] refer to Fig.15 , the electronic device 2000 may be a glasses-type display, which may be a wearable device. The electronic device 2000 may include a pair of temples 1100, a pair of optical coupling lenses 1200, and a bridge 1300. The electronic device 2000 may also include a display device 1000 including an image generator.

[0145] The electronic device 2000 may be a head-mounted, glasses-type, or goggle-type virtual reality (VR) device, an augmented reality (AR) device, or a mixed reality (MR) device, which may provide virtual reality or provide both virtual images and actual external scenes.

[0146] The temples 1100 may extend in one direction. The temples 1100 may be spaced apart from each other and extend in parallel. The temples 1100 may be folded toward the bridge 1300. The bridge 1300 may be disposed between the optical coupling lenses 1200 to connect the optical coupling lenses 1200 to each other. The optical coupling lenses 1200 may include a light guide plate. The display device 1000 may be disposed on each temple 1100, and may generate an image on the optical coupling lenses 1200. The display device 1000 may be the display device according to the above reference. Figures 1 to 14 A display device of an embodiment is described.

[0147] As described above, in the nitride semiconductor light-emitting device according to the above-mentioned embodiment, by introducing a plurality of stress relief layers, and by introducing InN clusters into the stress relief layers, the generation of stress in the active layer can be suppressed, and the wavelength of the red light generated in the well layer can be shifted to the long wavelength side to emit red light with a longer wavelength. Therefore, a nitride semiconductor light-emitting device that emits long-wavelength light with a relatively high internal quantum efficiency can be provided.

[0148] While example embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations may be made without departing from the scope of the present disclosure.

Claims

1. A nitride semiconductor light-emitting device, comprising: P-type nitride semiconductor layer; N-type nitride semiconductor layer; An InGaN well layer located between the P-type nitride semiconductor layer and the N-type nitride semiconductor layer; a barrier layer having a wider bandgap than the InGaN well layer; as well as a stress relief layer between the barrier layer and the InGaN well layer, The stress relief layer includes a plurality of InN structures which are spaced apart from each other and distributed on the barrier layer.

2. The nitride semiconductor light emitting device according to claim 1, wherein: The thickness of the stress relief layer is smaller than the thickness of the InGaN well layer.

3. The nitride semiconductor light emitting device according to claim 1, wherein: The thickness of the stress relief layer is less than 1 nanometer.

4. The nitride semiconductor light emitting device according to claim 1, wherein: The plurality of InN structures are distributed on the barrier layer in an island type arrangement.

5. The nitride semiconductor light emitting device according to claim 4, wherein: Each of the plurality of InN structures is shaped as a portion of a sphere having a surface in contact with the barrier layer, and Wherein, the first diameter of the surface is in the range of 0.5 nanometers to 1.0 nanometers.

6. The nitride semiconductor light emitting device according to claim 5, wherein: Each InN structure is spaced apart from an adjacent InN structure by at least a minimum separation distance.

7. The nitride semiconductor light emitting device according to claim 6, wherein: The minimum separation distance is 1 to 1.5 times the first diameter of the plurality of InN structures.

8. The nitride semiconductor light emitting device according to claim 1, wherein: The stress relief layer includes an InGaN intermediate layer configured to fix the plurality of InN structures on the barrier layer, and The indium concentration of the InGaN intermediate layer is lower than the indium concentration of the InGaN well layer.

9. The nitride semiconductor light emitting device according to claim 8, wherein: The thickness of the InGaN intermediate layer is substantially equal to or less than the height of the plurality of InN structures.

10. The nitride semiconductor light emitting device according to claim 8, wherein: As the indium content of the InGaN intermediate layer decreases, the thickness of the InGaN intermediate layer increases.

11. The nitride semiconductor light emitting device according to claim 10, wherein: The upper surface of the InGaN intermediate layer is above the midpoint of the heights of the plurality of InN structures.

12. The nitride semiconductor light emitting device according to claim 11, wherein: The InGaN well layer includes In x1 Ga 1-x1 N represents a first nitride single crystal, wherein x1 represents a first indium composition ratio, and wherein the first indium composition ratio is in the range of 0.3 to 0.5, and Wherein, the InGaN intermediate layer comprises In x2 Ga 1-x2 N represents a second nitride single crystal, wherein x2 represents a second indium composition ratio, and wherein the second indium composition ratio is in the range of 0 to 0.

1.

13. The nitride semiconductor light emitting device according to claim 12, wherein: The nitride semiconductor light emitting device is configured to emit light having a peak wavelength within a range of 620 nanometers to 650 nanometers.

14. The nitride semiconductor light emitting device according to claim 1, wherein: The InGaN well layer has a thickness of 2 nanometers to 5 nanometers, The barrier layer has a thickness of 5 nanometers to 20.0 nanometers, and The stress relief layer has a thickness of 0.15 nanometers to 0.5 nanometers.

15. A nitride semiconductor light emitting device, comprising: P-type nitride semiconductor layer; N-type nitride semiconductor layer; as well as an active layer between the P-type nitride semiconductor layer and the N-type nitride semiconductor layer, Wherein, the active layer comprises: Multiple GaN barrier layers; a plurality of InGaN well layers, the plurality of InGaN well layers being disposed between the plurality of GaN barrier layers; and a plurality of stress relief layers, the plurality of stress relief layers being disposed between the plurality of GaN barrier layers and the plurality of InGaN well layers, The plurality of stress relief layers include a plurality of InN structures distributed on the plurality of GaN barrier layers, and a plurality of InGaN intermediate layers between the plurality of InN structures on the plurality of GaN barrier layers. The indium concentration of the plurality of InGaN intermediate layers is lower than the indium concentration of the plurality of InGaN well layers, and Wherein, the thickness of the multiple InGaN intermediate layers is smaller than the thickness of the multiple InGaN well layers.

16. The nitride semiconductor light emitting device according to claim 15, wherein: The indium content of the plurality of InGaN intermediate layers decreases as the distance from the upper surface of the N-type nitride semiconductor layer increases.

17. The nitride semiconductor light emitting device according to claim 16, wherein: The thickness of the plurality of InGaN intermediate layers increases as the distance from the upper surface of the N-type nitride semiconductor layer increases.

18. The nitride semiconductor light emitting device according to claim 16, wherein: The plurality of InGaN well layers include In x1 Ga 1-x1 N represents a first nitride single crystal, wherein x1 represents a first indium composition ratio, and wherein the first indium composition ratio is in the range of 0.3 to 0.5, and Wherein, the plurality of InGaN intermediate layers include In x2 Ga 1-x2 N represents a second nitride single crystal, wherein x2 represents a second indium composition ratio, and wherein the second indium composition ratio is in the range of 0 to 0.

1.

19. The nitride semiconductor light emitting device according to claim 18, wherein: The second indium composition ratio of the lowermost InGaN intermediate layer of the plurality of InGaN intermediate layers is in the range of 0.05 to 0.1, and The second indium component ratio of the remaining InGaN intermediate layers among the plurality of InGaN intermediate layers is substantially equal to 0.

20. A display device, comprising: a circuit board including a plurality of driving components; as well as a pixel array, which is arranged on the circuit board and includes a plurality of light emitting devices, Wherein, each of the plurality of light emitting devices comprises: P-type nitride semiconductor layer; N-type nitride semiconductor layer; and an active layer between the P-type nitride semiconductor layer and the N-type nitride semiconductor layer, Wherein, the active layer comprises: Multiple GaN barrier layers; a plurality of InGaN well layers, the plurality of InGaN well layers being disposed between the plurality of GaN barrier layers; and a plurality of stress relief layers, the plurality of stress relief layers being disposed between the plurality of GaN barrier layers and the plurality of InGaN well layers, The plurality of stress relief layers include a plurality of InN structures distributed on the plurality of GaN barrier layers and a plurality of InGaN intermediate layers between the plurality of InN structures on the plurality of GaN barrier layers. The indium concentration of the plurality of InGaN intermediate layers is lower than the indium concentration of the plurality of InGaN well layers, and Wherein, the thickness of the multiple InGaN intermediate layers is smaller than the thickness of the multiple InGaN well layers.

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