Display device

Abstract

The display device includes a pixel electrode disposed on a substrate, a pixel defining layer having an opening exposing a central portion of the pixel electrode, a conductive partition wall disposed on the pixel defining layer and having a height of about # imgabs0 # or greater, an intermediate layer disposed on the pixel electrode and including an emission layer and a plurality of common layers, and a counter electrode disposed on the intermediate layer, in which at least a portion of the intermediate layer is in direct contact with at least a portion of the conductive partition wall.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0175436 filed in the Korean Intellectual Property Office on December 6, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure relates to a display device capable of reducing leakage current and light leakage between sub-pixels. Background Art

[0004] The display device displays data as an image. Such a display device includes a substrate divided into a display area and a peripheral area. Scan lines, data lines, sub-pixels, thin film transistors, sub-pixel electrodes, and counter electrodes are arranged in the display area. The scan lines and the data lines are electrically insulated from each other. The thin film transistors correspond to the sub-pixels, respectively, and the sub-pixel electrodes are electrically connected to the thin film transistors, respectively. The counter electrode is provided in common in the sub-pixel. Various lines configured to transmit electrical signals to the display area, a scan driver, a data driver, a controller, a pad portion, etc. may be provided in the peripheral area.

[0005] The display device includes an organic light emitting display device. The organic light emitting display device may have stacked layers and emit light for each sub-pixel in a display area.

[0006] It will be understood that this background section is intended, in part, to provide a useful background for understanding the present technology. However, this background section may also include ideas, concepts or cognitions that are not part of what a person skilled in the relevant art would understand prior to the corresponding effective filing date of the subject matter disclosed herein. Summary of the invention

[0007] The embodiment provides a display device capable of reducing leakage current between sub-pixels and preventing color mixing between sub-pixels.

[0008] Additional aspects will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the presented embodiments of the disclosure.

[0009] According to one or more embodiments, a display device includes: a pixel electrode disposed on a substrate; a pixel defining layer having an opening exposing a central portion of the pixel electrode; a conductive partition wall disposed on the pixel defining layer, and the conductive partition wall has a thickness of about or greater height; an intermediate layer disposed on the pixel electrode, and the intermediate layer includes an emission layer and a plurality of common layers; and a counter electrode disposed on the intermediate layer, wherein at least a portion of the intermediate layer is in direct contact with at least a portion of the conductive partition wall.

[0010] In an embodiment, the conductive partition wall may surround the opening of the pixel defining layer in a plan view.

[0011] In an embodiment, the conductive partition wall may receive a voltage equal to or lower than a voltage applied to the counter electrode.

[0012] In an embodiment, the conductive partition wall may have a trapezoidal cross-sectional shape.

[0013] In an embodiment, an area of ​​an upper surface of the conductive partition wall may be smaller than an area of ​​a lower surface of the conductive partition wall.

[0014] In an embodiment, the display device may further include: an inorganic insulating layer covering a portion of the conductive partition wall, and the inorganic insulating layer is disposed between the conductive partition wall and the intermediate layer.

[0015] In an embodiment, the conductive partition wall may include a plurality of metal layers sequentially stacked on one another on the pixel defining layer, the inorganic insulating layer may cover at least a portion of the side surface of the conductive partition wall, and at least some of the plurality of common layers may be in direct contact with at least a portion of the upper surface of the conductive partition wall.

[0016] In an embodiment, the pixel electrode may include indium tin oxide (ITO), and at least some of the plurality of metal layers may include aluminum (Al).

[0017] In an embodiment, the emission layer may include: a lower emission layer; and an upper emission layer overlapping the lower emission layer in a plan view, and the intermediate layer may further include a charge generation layer between the lower emission layer and the upper emission layer.

[0018] In an embodiment, the conductive partition wall may include a metal partition wall, and the metal partition wall may include at least one of molybdenum (Mo), titanium (Ti), and aluminum (Al).

[0019] According to one or more embodiments, a display device includes: a first pixel electrode, which is arranged on a substrate; a second pixel electrode, which is spaced apart from the first pixel electrode on the substrate; a pixel defining layer, which has a first opening that exposes a central portion of the first pixel electrode and a second opening that exposes a central portion of the second pixel electrode; a conductive partition wall, which is arranged between the first opening and the second opening on the pixel defining layer, and the conductive partition wall receives a first voltage; a plurality of common layers, which are arranged on the first pixel electrode and the second pixel electrode; and a counter electrode, which is arranged on the plurality of common layers, and the counter electrode receives a second voltage equal to or higher than the first voltage, wherein the conductive partition wall is in direct contact with a hole injection layer or a hole transport layer among the plurality of common layers.

[0020] In an embodiment, the conductive partition wall may have a positively tapered cross-sectional shape.

[0021] In an embodiment, the conductive partition wall may have a thickness of about or greater height.

[0022] In an embodiment, in a plan view, the conductive partition wall may surround each of the first opening and the second opening.

[0023] In an embodiment, the display device may further include: a first lower emission layer disposed on the first pixel electrode; a second lower emission layer disposed on the second pixel electrode; a first upper emission layer disposed on the first lower emission layer; and a second upper emission layer disposed on the second lower emission layer.

[0024] In an embodiment, the plurality of common layers may include: a 1-1th common layer disposed under the first lower emission layer; and a 1-2th common layer disposed under the second lower emission layer, and the 1-1th common layer and the 1-2th common layer may be integrated with each other.

[0025] In an embodiment, the display device may further include: a first charge generation layer between the first lower emission layer and the first upper emission layer; and a second charge generation layer between the second lower emission layer and the second upper emission layer.

[0026] In an embodiment, the conductive partition wall may include a plurality of metal layers sequentially stacked on one another on the pixel defining layer.

[0027] In an embodiment, the display device may further include an inorganic insulating layer covering the conductive partition wall, and the inorganic insulating layer exposes at least a portion of an upper surface or at least a portion of a side surface of the conductive partition wall.

[0028] In an embodiment, the conductive partition wall may include a metal partition wall, and the metal partition wall may include at least one of molybdenum (Mo), titanium (Ti), and aluminum (Al).

[0029] Other aspects, features, and advantages of the present disclosure will become better understood from the detailed description, claims, and accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Additional understanding according to the embodiments of the present disclosure will become more apparent by describing the embodiments of the present disclosure in detail with reference to the accompanying drawings, in which:

[0031] Figure 1A is a schematic perspective view of an electronic device according to an embodiment;

[0032] Figure 1B is a schematic plan view of a display device according to an embodiment;

[0033] Figure 2 According to an embodiment, the Figure 1B A schematic diagram of an equivalent circuit of a pixel circuit in a display device;

[0034] Figure 3 yes Figure 1B A schematic enlarged view of a region A in a display device;

[0035] Figure 4 is a schematic cross-sectional view of a display device according to an embodiment;

[0036] Figure 5A and Figure 5B is a schematic cross-sectional view of a display device according to an embodiment;

[0037] FIG. 6A to FIG. 6C is a schematic cross-sectional view of a display device according to an embodiment;

[0038] FIG. 7A to FIG. 7C is a schematic cross-sectional view of an organic light emitting diode that can be used as a display element according to an embodiment;

[0039] Figure 8 is a schematic cross-sectional view of a display device according to an embodiment;

[0040] Fig. 9 is a schematic cross-sectional view of a display device according to an embodiment; and

[0041] FIG. 10A to FIG. 10F is a schematic cross-sectional view for describing a process of manufacturing a display device according to an embodiment. DETAILED DESCRIPTION

[0042] In the following description, for the purpose of explanation, many specific details are set forth to provide a thorough understanding of various embodiments or implementations of the present disclosure. As used herein, "embodiment" and "implementation" are interchangeable words as non-limiting examples of the device or method disclosed herein. However, it is apparent that various embodiments may be practiced without these specific details or with one or more equivalent arrangements. Here, various embodiments need not be exclusive, nor do they limit the present disclosure. For example, the specific shape, configuration, and characteristics of an embodiment may be used or implemented in another embodiment.

[0043] For the purpose of the present disclosure, the phrase "at least one of A and B" may be interpreted as only A, only B, or any combination of A and B. In addition, "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" may be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z.

[0044] Various embodiments are described herein with reference to cross-sectional views and / or exploded views as schematic illustrations of embodiments and / or intervening structures. Therefore, variations in the shapes of the illustrations as a result of, for example, manufacturing techniques and / or tolerances are anticipated. Therefore, the embodiments disclosed herein need not be construed as limited to the specific illustrated shapes of the regions, but rather include deviations in shapes resulting from, for example, manufacturing. In this manner, the regions shown in the figures may be schematic in nature, and the shapes of these regions may not reflect the actual shapes of the regions of the device, and therefore, are not necessarily intended to be limiting.

[0045] Although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another element. Therefore, without departing from the teachings of the present disclosure, the first element discussed below may be referred to as the second element.

[0046] The terms used in this article are for the purpose of describing specific embodiments and are not intended to be limiting. As used in this article, unless the context clearly indicates otherwise, the singular forms "one", "one (kind / person)" and "the (said)" are also intended to include plural forms. In addition, when the terms "include", "comprise", "contain" and / or "contain" are used in this specification, it is indicated that there are stated features, integers, steps, operations, elements, components and / or combinations thereof, but it does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or combinations thereof.

[0047] When an element (such as a layer) is referred to as being "on," "connected to," or "coupled to" another element or layer, the element may be directly on, directly connected to, or directly coupled to the other element or layer, or there may be intervening elements or layers. However, when an element or layer is referred to as being "directly on," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers. For this purpose, the term "connected" may refer to a physical connection, an electrical connection, and / or a fluid connection with or without intervening elements.

[0048] Unless otherwise specified, the illustrated embodiments will be understood to provide features of the present disclosure. Therefore, unless otherwise specified, the features, components, modules, layers, films, panels, regions and / or aspects, etc. (hereinafter individually or collectively referred to as "elements") of the various embodiments may be combined, separated, interchanged and / or rearranged in other ways without departing from the present disclosure.

[0049] For descriptive purposes, spatially relative terms such as "under," "below," "below," "down," "above," "up," "above," "high," and "side" (e.g., as in "sidewall") may be used herein to describe the relationship of one element to another element as shown in the accompanying drawings. In addition to the orientation depicted in the accompanying drawings, the spatially relative terms are intended to encompass different orientations of the device in use, operation, and / or manufacture. For example, if the device in the accompanying drawings is turned over, an element described as "under" or "beneath" other elements or features would subsequently be oriented as "above" the other elements or features. Thus, the term "below" can encompass both above and below orientations. Furthermore, the device may be otherwise oriented (e.g., rotated 90 degrees or in other orientations), and therefore, the spatially relative descriptors used herein should be interpreted accordingly.

[0050] The use of cross hatching and / or shading is generally provided in the drawings to clarify the boundaries between adjacent elements. Therefore, unless specified, the presence or absence of cross hatching or shading does not convey or indicate any preference or requirement for a particular material, material property, size, ratio, commonality between the elements shown, and / or any other characteristics, attributes, properties, etc. of the elements. In addition, in the drawings, the size and relative size of the elements may be exaggerated for the purpose of clarity and / or description. When the embodiments can be implemented differently, a specific process sequence may be performed differently from the described sequence. For example, two processes described in succession may be performed substantially simultaneously or in an order opposite to the described sequence. Likewise, the same reference numerals represent the same elements.

[0051] According to the practice in the art, some embodiments are described and shown in the form of functional blocks, units and / or modules in the accompanying drawings. It will be understood by those skilled in the art that these blocks, units and / or modules are physically implemented by electronic (or optical) circuits (such as logic circuits, discrete components, microprocessors, hard-wired circuits, memory elements and wiring connections, etc.) that can be formed using semiconductor-based manufacturing technology or other manufacturing technology. In the case where blocks, units and / or modules are implemented by microprocessors or other similar hardware, they can be programmed and controlled using software (e.g., microcode) to perform various functions discussed herein, and can be optionally driven by firmware and / or software. It is also envisioned that each block, unit and / or module can be implemented by dedicated hardware, or implemented as a combination of dedicated hardware that performs some functions and processors (e.g., one or more programmed microprocessors and related circuits) that perform other functions. In addition, without departing from the scope of the present disclosure, each block, unit and / or module of some embodiments can be physically divided into two or more interactive and discrete blocks, units and / or modules. Furthermore, the blocks, units and / or modules of some embodiments may be physically combined into more complex blocks, units and / or modules without departing from the scope of the present disclosure.

[0052] As used herein, the terms "about" or "approximately" include the stated value and mean within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art, taking into account the measurements in question and the errors associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, "about" can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, or ±5% of the stated value.

[0053] Unless otherwise defined or implied herein, all terms (including technical and scientific terms) used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. It will also be understood that, unless explicitly defined as such herein, terms (such as those defined in commonly used dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and the present disclosure, and should not be interpreted in an idealized or overly formal sense.

[0054] Figure 1A is a schematic perspective view of an electronic device 2 according to the embodiment. Figure 1B is a schematic plan view of a display device 1 according to the embodiment.

[0055] refer to Figure 1A and Figure 1B The display device 1 can display a moving image or a still image. The display device 1 can display an image in the electronic device 2, or can input and output data to the electronic device 2.

[0056] exist Figure 1A In the embodiment, the display device 1 can be used in a mobile phone. However, the present disclosure is not limited thereto. For example, the display device 1 can be used as a display screen of a portable electronic device such as a mobile phone, a smart phone, a tablet personal computer (PC), a mobile communication terminal, an electronic organizer, an electronic book, a portable multimedia player (PMP), a navigation system, or an ultra mobile PC (UMPC). For example, the display device 1 can be used as a display screen of various products such as a television, a laptop computer, a monitor, a billboard, or an Internet of Things (IoT) device.

[0057] The display device 1 according to the embodiment can be used in an electronic device such as a wearable device (e.g., a smart watch, a watch phone, a glasses-type display, or a head-mounted display (HMD) etc.). In an embodiment, the display device 1 can be used as a display device of various electronic devices, for example, a dashboard of a car, a central dashboard of a car or a central information display (CID) on the dashboard, a room mirror display replacing a side mirror of a car, and a display on the rear side of a front seat used as an entertainment device for rear seat passengers of a car.

[0058] In an embodiment, the display device 1 may be housed in a housing 3 of an electronic device 2. The housing 3 may be a cover that protects internal components such as the display device 1 and forms an appearance of the electronic device 2. The display device 1 may be electrically connected to an electronic module of the electronic device 2 and may be driven on the electronic device 2. A detailed description of the display device 1 is provided below.

[0059] refer to Figure 1B , the display device 1 may include a display area DA in which the pixels PX are arranged and a peripheral area PA adjacent to the display area DA (or outside the display area DA). For example, the peripheral area PA may surround (e.g., completely surround) the display area DA. The substrate 100 (e.g., referring to Figure 4 ) may have a display area DA and a peripheral area PA.

[0060] Light (e.g., multiple lights) of multiple colors (e.g., specific colors or selectable colors) may be emitted from the pixels PX of the display device 1, and the display device 1 may provide an image by using the multiple lights emitted from the pixels PX. For example, each of the multiple pixels PX may emit green light, red light, or blue light.

[0061] The display area DA may have a polygonal shape including a rectangular shape, such as Figure 1BFor example, the display area DA may have a rectangular shape whose horizontal length is longer than the vertical length, a rectangular shape whose horizontal length is shorter than the vertical length, or a square shape, etc. However, the present disclosure is not limited thereto, and the display area DA may have various shapes such as an elliptical shape or a circular shape.

[0062] The peripheral area PA may be a non-display area in which the pixels PX are not arranged. A driver configured to provide an electrical signal or power to the pixels PX, etc. may be arranged in the peripheral area PA. Pads (not shown) to which various electronic devices or printed circuit boards are electrically connected may be arranged in the peripheral area PA. The pads may be spaced apart from each other in the peripheral area PA and may be electrically connected to a printed circuit board or an integrated circuit device.

[0063] Figure 2 According to an embodiment, the Figure 1B Schematic diagram of an equivalent circuit of a pixel circuit PC in a display device 1. The pixel circuit PC may be electrically connected to an organic light emitting diode OLED. Each organic light emitting diode OLED may correspond to each pixel PX (eg, reference Figure 1B ).

[0064] The pixel circuit PC may include a first transistor T1, a second transistor T2, and a storage capacitor Cst. The second transistor T2 may be used as a switching transistor and may be electrically connected to a scan line SL and a data line DL. The second transistor T2 may be configured to be turned on in response to a switching signal input from the scan line SL and to transmit a data signal input from the data line DL to the first transistor T1. The storage capacitor Cst may have one end electrically connected to the second transistor T2 and the other end electrically connected to the drive voltage line PL. The storage capacitor Cst may store a voltage difference (e.g., a potential difference) between a voltage received from the second transistor T2 and a drive voltage ELVDD supplied to the drive voltage line PL.

[0065] The first transistor T1 may function as a driving transistor and may be electrically connected to the driving voltage line PL and the storage capacitor Cst. The first transistor T1 may be configured to control the amount of driving current flowing from the driving voltage line PL to the organic light emitting diode OLED according to the voltage value stored in the storage capacitor Cst. The organic light emitting diode OLED may be configured to emit light having a brightness (e.g., a specific brightness or a selectable brightness) according to the driving current. The counter electrode 230 (e.g., reference numeral 230) of the organic light emitting diode OLED may be electrically connected to the driving voltage line PL and the storage capacitor Cst. The first transistor T1 may be configured to control the amount of driving current flowing from the driving voltage line PL to the organic light emitting diode OLED according to the voltage value stored in the storage capacitor Cst. Figure 4 ) can be configured to receive the common voltage ELVSS.

[0066] exist Figure 2In the embodiment, the pixel circuit PC may include two transistors and one storage capacitor. However, the present disclosure is not limited thereto. For example, the number of transistors or the number of storage capacitors may be changed differently according to the design of the pixel circuit PC.

[0067] Figure 3 yes Figure 1B Schematic enlarged view of area A in the display device 1. For convenience, Figure 3 2 shows a plan view on the pixel defining layer 215. However, for convenience of explanation, the conductive partition wall may be disposed on the pixel defining layer 215. The conductive partition wall may include at least one conductive material of metal, metal oxide, graphite, conductive polymer, etc. Figure 3 In the embodiment, the conductive partition wall may include a metal partition wall MW.

[0068] refer to Figure 3 , the pixels PX may be arranged on the substrate 100 (eg, referring to Figure 1B ) of the display area DA (for example, reference Figure 1B For example, each of the plurality of pixels PX may be a sub-pixel and may include an organic light emitting diode OLED (eg, reference Figure 2 ) display element. Each pixel PX may emit, for example, green light, red light, or blue light. For example, the pixel PX may include a first pixel PX1 configured to emit green light, a second pixel PX2 configured to emit red light, and a third pixel PX3 configured to emit blue light. The green light may have a wavelength of about 495 nm to about 580 nm, the red light may have a wavelength of about 580 nm to about 780 nm, and the blue light may have a wavelength of about 400 nm to about 495 nm.

[0069] The first pixel electrode 210-1 may be included in the first pixel PX1, the second pixel electrode 210-2 may be included in the second pixel PX2, and the third pixel electrode 210-3 may be included in the third pixel PX3. The first pixel electrode 210-1, the second pixel electrode 210-2, and the third pixel electrode 210-3 may be arranged in the display area DA. For example, the first pixel electrode 210-1, the second pixel electrode 210-2, and the third pixel electrode 210-3 may be spaced apart from each other in a plan view. In the specification, the expression "in a plan view" means the situation when observed from a direction perpendicular to the substrate 100. For example, the expression "in a plan view, A and B are spaced apart from each other" may mean "when observed from a direction perpendicular to the substrate 100, A and B are spaced apart from each other". The first pixel electrode 210-1, the second pixel electrode 210-2, and the third pixel electrode 210-3 may have different sizes, such as Figure 3In another embodiment, the first pixel electrode 210 - 1 , the second pixel electrode 210 - 2 , and the third pixel electrode 210 - 3 may have the same size.

[0070] The pixel defining layer 215 may be disposed on the first pixel electrode 210-1, the second pixel electrode 210-2, and the third pixel electrode 210-3, and may include a first opening OP1, a second opening OP2, and a third opening OP3. For example, the pixel defining layer 215 may include an inner surface defining the first opening OP1, an inner surface defining the second opening OP2, and an inner surface defining the third opening OP3. For example, the first opening OP1, the second opening OP2, and the third opening OP3 may be spaced apart from each other and pass through the pixel defining layer 215.

[0071] The first opening OP1 may expose a central portion of the first pixel electrode 210-1, the second opening OP2 may expose a central portion of the second pixel electrode 210-2, and the third opening OP3 may expose a central portion of the third pixel electrode 210-3. The first opening OP1, the second opening OP2, and the third opening OP3 may have different sizes from each other, such as Figure 3 In another embodiment, the first opening OP1, the second opening OP2 and the third opening OP3 may have the same size. Figure 3 In the embodiment, each of the first opening OP1, the second opening OP2, and the third opening OP3 has a rectangular shape. However, the present disclosure is not limited thereto. For example, each of the first opening OP1, the second opening OP2, and the third opening OP3 may have a hexagonal shape.

[0072] although Figure 3 Although not shown in the figure, the emission layers configured to emit light may be positioned in the first opening OP1, the second opening OP2, and the third opening OP3 of the pixel defining layer 215, respectively. Figure 4 ) may be disposed on the emission layer. The pixel electrode, the intermediate layer 220 including the emission layer (eg, reference Figure 4 ) and the counter electrode 230 may be stacked on each other. The organic light emitting diode OLED may include a pixel electrode, an intermediate layer 220 and a counter electrode 230. Each opening of the pixel defining layer 215 may correspond to each organic light emitting diode OLED and may define an emission area. For example, the organic light emitting diode OLED may be disposed in an emission area defined by each of the first opening OP1, the second opening OP2, and the third opening OP3 of the pixel defining layer 215.

[0073] For example, an emission layer configured to emit green light may be arranged in the first opening OP1, and the first pixel PX1 may be an emission area defined by the first opening OP1. For example, an emission layer configured to emit red light may be arranged in the second opening OP2, and the second pixel PX2 may be an emission area defined by the second opening OP2. For example, an emission layer configured to emit blue light may be arranged in the third opening OP3, and the third pixel PX3 may be an emission area defined by the third opening OP3. However, the present disclosure is not limited thereto. For example, an emission layer configured to emit blue light, green light, and white light may be arranged in the first opening OP1, the second opening OP2, and the third opening OP3, respectively. The display device 1 may include a light-emitting panel and a color panel stacked on each other in a thickness direction (e.g., z direction). Blue light, green light, or white light emitted from the emission layer of the light-emitting panel may be transmitted through the color panel. Light may pass through the color panel and be converted into green light, red light, and blue light.

[0074] The first opening OP1 and the second opening OP2 may be adjacent to each other in a second direction (e.g., y direction or -y direction) intersecting (e.g., crossing) the first direction (e.g., x direction or -x direction), and the first opening OP1 and the third opening OP3 may be adjacent to each other in the first direction (e.g., x direction or -x direction). For example, the x direction may be opposite to the -x direction, and the y direction may be opposite to the -y direction. Figure 3 In the embodiment, each of the size of the first opening OP1 and the size of the second opening OP2 adjacent to the first opening OP1 in the second direction (e.g., the y direction or the -y direction) can be smaller than the size of the third opening OP3, and the third opening OP3 and the second opening OP2 can be adjacent to each other in the first direction (e.g., the x direction or the -x direction).

[0075] The metal partition wall MW may be disposed on the pixel defining layer 215. For example, when viewed from a direction perpendicular to the substrate 100 (e.g., the z direction or the -z direction), the metal partition wall MW may be disposed on the pixel defining layer 215 and surround each of the openings (e.g., the first opening OP1, the second opening OP2, and the third opening OP3) included in the pixel defining layer 215. For example, the metal partition wall MW may have a mesh structure. In a plan view, the first opening OP1 may be positioned within the first metal hole MH1 defined by the metal partition wall MW. For example, in a plan view, the second opening OP2 may be positioned within the second metal hole MH2 defined by the metal partition wall MW, and in a plan view, the third opening OP3 may be positioned within the third metal hole MH3 defined by the metal partition wall MW. Therefore, the metal partition wall MW may be disposed between adjacent openings (or adjacent pixels in the first pixel PX1, the second pixel PX2, and the third pixel PX3) among the first opening OP1, the second opening OP2, and the third opening OP3.

[0076] exist Figure 3 In the embodiment, each of the first metal hole MH1, the second metal hole MH2 and the third metal hole MH3 may have a rectangular shape. However, the present disclosure is not limited thereto. For example, the first metal hole MH1, the second metal hole MH2 and / or the third metal hole MH3 may have a polygonal shape including a rectangular shape. For example, each of the first metal hole MH1, the second metal hole MH2 and the third metal hole MH3 may have a rectangular shape in which the horizontal length is longer than the vertical length, a rectangular shape in which the horizontal length is shorter than the vertical length, or a square shape, etc. In other embodiments, each of the first metal hole MH1, the second metal hole MH2 and the third metal hole MH3 may have various shapes such as an elliptical shape or a circular shape.

[0077] exist Figure 3 In the embodiment, the metal partition wall MW may surround (e.g., may completely surround) each of the openings (e.g., the first opening OP1, the second opening OP2, and the third opening OP3) included in the pixel defining layer 215. For example, the metal partition wall MW may completely surround the first opening OP1, the second opening OP2, and the third opening OP3. However, the present disclosure is not limited thereto. For example, the metal partition wall MW may partially surround each of the openings (e.g., the first opening OP1, the second opening OP2, and the third opening OP3) included in the pixel defining layer 215. For example, the metal partition wall MW may not surround one side of the opening, but surround the rest of the opening. Therefore, in a plan view, the metal partition wall MW may have a U-shape.

[0078] exist Figure 3In the embodiment, the pixels PX may be arranged in a stripe type. However, the present disclosure is not limited thereto, and the pixels PX may be arranged in a stripe type such as an RGBG type (e.g., a so-called structure) or various types of arrangements such as oblique line type.

[0079] Figure 4 is a schematic cross-sectional view of a display device 1 according to an embodiment. For example, Figure 4 It is along Figure 3 The line I-I' intercepts Figure 3 Schematic cross-sectional view of a display device 1 .

[0080] refer to Figure 4 , the display device 1 according to the embodiment may include a substrate 100. The substrate 100 may include various flexible or bendable materials. For example, the substrate 100 may include glass, metal, polymer resin or a combination thereof. The substrate 100 may include a polymer resin such as polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, or cellulose acetate. However, the present disclosure is not limited thereto. In some embodiments, other modifications may be possible. For example, the substrate 100 may have a multilayer structure including two layers and a barrier layer disposed between the two layers, the two layers may include a polymer resin, and the barrier layer may include an inorganic material. For example, the barrier layer may include silicon oxide (SiO X ), Silicon Nitride (SiN X ) and silicon oxynitride (SiO X N Y ) at least one of.

[0081] A display element included in the pixel PX and a pixel circuit PC electrically connected to the display element may be disposed on the substrate 100. Figure 4 In the embodiment, each of the plurality of pixels PX may include an organic light emitting diode OLED (eg, referring to Figure 2 ). For example, the organic light emitting diode OLED may include a first organic light emitting diode OLED1, a second organic light emitting diode OLED2, and a third organic light emitting diode OLED3. For example, the first pixel PX1 may include the first organic light emitting diode OLED1, the second pixel PX2 may include the second organic light emitting diode OLED2, and the third pixel PX3 may include the third organic light emitting diode OLED3.

[0082] The pixel circuit PC may be disposed on the substrate 100. The pixel circuit PC of the pixel PX may have the same structure. Therefore, a detailed description of the same components may be omitted. The pixel circuit PC may include a thin film transistor TFT and a storage capacitor Cst. For ease of description, Figure 4 The thin film transistor TFT is shown in FIG. 1 , and the thin film transistor TFT may correspond to the first transistor T1 described above (eg, referring to FIG. 1 ). Figure 2 ).

[0083] The buffer layer 201 may be disposed between the thin film transistor TFT and the substrate 100. The buffer layer 201 may include an inorganic material such as silicon oxide (SiO X ), Silicon Nitride (SiN X ) and / or silicon oxynitride (SiO X N Y ). The buffer layer 201 may increase the smoothness of the upper surface of the substrate 100. For example, the buffer layer 201 may prevent or minimize the penetration of impurities from the substrate 100 and the like into the semiconductor layer Act of the thin film transistor TFT.

[0084] refer to Figure 4 The thin film transistor TFT may include a semiconductor layer Act, and the semiconductor layer Act includes at least one of amorphous silicon, polycrystalline silicon, an organic semiconductor material, and an oxide semiconductor material. The thin film transistor TFT may include a gate electrode GE, a source electrode SE, and / or a drain electrode DE. The gate electrode GE may include various conductive materials and have various stacked structures. For example, the gate electrode GE may include a molybdenum (Mo) layer and an aluminum (Al) layer. For example, the gate electrode GE may include a TiN X The source electrode SE and the drain electrode DE may include various conductive materials and have various stacked structures. For example, each of the source electrode SE and the drain electrode DE may include a Ti layer, an Al layer and / or a copper (Cu) layer.

[0085] The gate insulating layer 203 may be disposed between the semiconductor layer Act and the gate electrode GE. Therefore, electrical insulation between the semiconductor layer Act and the gate electrode GE may be ensured by the gate insulating layer 203. The gate insulating layer 203 may include an inorganic material such as silicon oxide (SiO X ), Silicon Nitride (SiN X ) and / or silicon oxynitride (SiO X N Y ).exist Figure 4 In the embodiment, the gate insulating layer 203 may have a shape corresponding to the entire area of ​​the surface of the substrate 100, and the contact hole may be formed in a portion (e.g., a preset portion or an optional portion). However, the present disclosure is not limited thereto. For example, the gate insulating layer 203 and the gate electrode GE may be patterned to have the same shape in a plan view.

[0086] The first interlayer insulating layer 205 may be disposed on the gate electrode GE. The first interlayer insulating layer 205 may include an inorganic material such as silicon oxide (SiO X ), silicon nitride (SiN X ) and / or silicon oxynitride (SiO X N Y ). The first interlayer insulating layer 205 may have a single-layer structure or a multi-layer structure including the above-mentioned materials. An insulating layer (e.g., gate insulating layer 203 or first interlayer insulating layer 205, etc.) including the above-mentioned inorganic material may be formed by chemical vapor deposition (CVD) or atomic layer deposition (ALD). However, the present disclosure is not limited thereto, and the first interlayer insulating layer 205 may have various embodiments and modifications. A detailed description of the first interlayer insulating layer 205 is provided below.

[0087] The storage capacitor Cst may include a first capacitor electrode CE1 and a second capacitor electrode CE2 that overlap each other in a plan view. A first interlayer insulating layer 205 may be disposed between the first capacitor electrode CE1 and the second capacitor electrode CE2. The storage capacitor Cst may overlap the thin film transistor TFT in a plan view. Figure 4 In the embodiment of the present invention, the gate electrode GE of the thin film transistor TFT may be the first capacitor electrode CE1 of the storage capacitor Cst. However, the present disclosure is not limited thereto. For example, the storage capacitor Cst may not overlap with the thin film transistor TFT in a plan view. The second capacitor electrode CE2 of the storage capacitor Cst may include a conductive material including at least one of molybdenum (Mo), aluminum (Al), copper (Cu), and titanium (Ti). The second capacitor electrode CE2 of the storage capacitor Cst may include a single layer (single layer structure) or multiple layers (multilayer structure) including the above conductive materials.

[0088] The second interlayer insulating layer 207 may be disposed on the second capacitor electrode CE2 of the storage capacitor Cst. The second interlayer insulating layer 207 may include an inorganic material such as silicon oxide (SiO X ), silicon nitride (SiN X ) and / or silicon oxynitride (SiO X N Y ). The second interlayer insulating layer 207 may have a single layer structure or a multilayer structure including the above-mentioned inorganic material.

[0089] The source electrode SE and the drain electrode DE may be disposed on the second interlayer insulating layer 207. Each of the source electrode SE and the drain electrode DE may include a material having excellent conductivity. Each of the source electrode SE and the drain electrode DE may include a conductive material including at least one of molybdenum (Mo), aluminum (Al), copper (Cu), and titanium (Ti). Each of the source electrode SE and the drain electrode DE may include a single layer (single layer structure) or multiple layers (multilayer structure) including the above conductive materials. For example, each of the source electrode SE and the drain electrode DE may have a multilayer structure (e.g., a three-layer structure) of Ti / Al / Ti.

[0090] However, the present disclosure is not limited thereto. For example, the thin film transistor TFT may have only one of the source electrode SE and the drain electrode DE, or may not have both the source electrode SE and the drain electrode DE. For example, the thin film transistor TFT (for example, a thin film transistor TFT without the drain electrode DE) may not have the drain electrode DE, another thin film transistor TFT electrically connected to the thin film transistor TFT (for example, another thin film transistor TFT without the source electrode SE) may not have the source electrode SE, and the semiconductor layers Act of the plurality of thin film transistors TFT may be electrically connected to each other. The above-mentioned electrical connection structure between the thin film transistor TFT without the drain electrode DE and the other thin film transistor TFT without the source electrode SE may have the same effect as the structure between the thin film transistor TFT with the source electrode SE and the other thin film transistor TFT with the drain electrode DE electrically connected to the source electrode SE of the thin film transistor TFT. For example, the electrical connection between the thin film transistor TFT without the drain electrode DE and the other thin film transistor TFT without the source electrode SE may have the same effect as the electrical connection between the thin film transistor TFT with the drain electrode DE and the other thin film transistor TFT with the source electrode SE.

[0091] refer to Figure 4 , the planarization layer 208 may cover the thin film transistor TFT and the storage capacitor Cst. The planarization layer 208 may include an organic insulating material. For example, the planarization layer 208 may include at least one of a photoresist, benzocyclobutene (BCB), hexamethyldisiloxane (HMDSO), polymethyl methacrylate (PMMA), polystyrene, a polymer derivative having a phenol group, an acrylic polymer, an imide polymer (e.g., polyimide), an aromatic ether polymer, an amide polymer, a fluorine polymer, a paraxylene polymer, and a vinyl alcohol polymer. However, the present disclosure is not limited thereto, and the planarization layer 208 may include various suitable materials. Although not described herein, the planarization layer 208 may include at least one of a photoresist, a benzocyclobutene (BCB), hexamethyldisiloxane (HMDSO), polymethyl methacrylate (PMMA), polystyrene, a polymer derivative having a phenol group, an acrylic polymer, an imide polymer (e.g., polyimide), an aromatic ether polymer, an amide polymer, a fluorine polymer, a paraxylene polymer, and a vinyl alcohol polymer. Figure 4However, a third interlayer insulating layer (not shown) may be further provided below the planarization layer 208. The third interlayer insulating layer may include silicon oxide (SiO X ), Silicon Nitride (SiN X ) and silicon oxynitride (SiO X N Y ) at least one inorganic material.

[0092] Figure 4 Pixel circuit PC formed on substrate 100 is shown. For example, buffer layer 201 may be provided on substrate 100. Semiconductor layer Act may be provided on buffer layer 201. Gate insulating layer 203 may be provided on semiconductor layer Act. Gate electrode GE may be provided on gate insulating layer 203. First interlayer insulating layer 205 may be provided on gate electrode GE. Second capacitor electrode CE2 may be provided on first interlayer insulating layer 205. Second interlayer insulating layer 207 may be provided on second capacitor electrode CE2. Source electrode SE and drain electrode DE may be provided on second interlayer insulating layer 207. Planarization layer 208 may be provided on source electrode SE and drain electrode DE. Therefore, pixel circuit PC may be formed on substrate 100.

[0093] However, the present disclosure is not limited thereto. For example, the display device 1 may include a complementary metal oxide semiconductor (CMOS) circuit formed by using a semiconductor process. The organic light emitting diode OLED may be electrically connected to the CMOS circuit. For example, the organic light emitting diode OLED may be electrically connected to a transistor and a capacitor formed by using a semiconductor process. The substrate 100 may include a silicon substrate (e.g., a silicon semiconductor substrate). For example, the substrate 100 may be a silicon wafer. The silicon wafer may be a monocrystalline silicon wafer, a polycrystalline silicon wafer, or an amorphous silicon wafer.

[0094] The first organic light emitting diode OLED1, the second organic light emitting diode OLED2, and the third organic light emitting diode OLED3 may be spaced apart from each other on the planarization layer 208. The first organic light emitting diode OLED1, the second organic light emitting diode OLED2, and the third organic light emitting diode OLED3 may emit a plurality of lights of different colors. For example, the first organic light emitting diode OLED1 may emit green light, the second organic light emitting diode OLED2 may emit red light, and the third organic light emitting diode OLED3 may emit blue light.

[0095] The first organic light emitting diode OLED1 may include a first pixel electrode 210-1, a first intermediate layer 220-1, and a counter electrode 230. The second organic light emitting diode OLED2 may include a second pixel electrode 210-2, a second intermediate layer 220-2, and a counter electrode 230. The third organic light emitting diode OLED3 may include a third pixel electrode 210-3, a third intermediate layer 220-3, and a counter electrode 230. The counter electrode 230 may extend (or be integrally provided) over the entire surface of the display device 1, and may be provided in common in a plurality of organic light emitting diodes OLED. For example, the counter electrode 230 may extend across the first organic light emitting diode OLED1, the second organic light emitting diode OLED2, and the third organic light emitting diode OLED3.

[0096] Each of the first pixel electrode 210-1, the second pixel electrode 210-2, and the third pixel electrode 210-3 may include a transmissive conductive layer and a reflective layer. The transmissive conductive layer may include, for example, indium tin oxide (ITO), In 2 O 3 The reflective layer may include a metal such as Al or Ag. However, the present disclosure is not limited thereto. For example, each of the first pixel electrode 210-1, the second pixel electrode 210-2, and the third pixel electrode 210-3 may have a three-layer structure of ITO / Ag / ITO. In an embodiment, each of the first pixel electrode 210-1, the second pixel electrode 210-2, and the third pixel electrode 210-3 may include a TiN X Single layer (single layer structure) or multiple layers (multi-layer structure).

[0097] The first pixel electrode 210-1, the second pixel electrode 210-2, and the third pixel electrode 210-3 may be in contact with one of the source electrode SE and the drain electrode DE. Therefore, each of the first pixel electrode 210-1, the second pixel electrode 210-2, and the third pixel electrode 210-3 may be electrically connected to the thin film transistor TFT, such as Figure 4 For example, each of the first pixel electrode 210 - 1 , the second pixel electrode 210 - 2 , and the third pixel electrode 210 - 3 may contact one of the source electrode SE and the drain electrode DE through a contact hole formed in the planarization layer 208 .

[0098] The pixel defining layer 215 may be disposed on the planarization layer 208. Since the pixel defining layer 215 has an opening corresponding to the pixel PX (e.g., an opening exposing at least the central portion of the pixel electrode), the pixel defining layer 215 may define the pixel PX. For example, the pixel defining layer 215 may have a first opening OP1, a second opening OP2, and a third opening OP3. The first opening OP1 may expose the central portion of the first pixel electrode 210-1, the second opening OP2 may expose the central portion of the second pixel electrode 210-2, and the third opening OP3 may expose the central portion of the third pixel electrode 210-3.

[0099] exist Figure 4 In the embodiment, the pixel defining layer 215 can increase the distance between the edge of the first pixel electrode 210-1 and the counter electrode 230 disposed on the first pixel electrode 210-1. For example, the pixel defining layer 215 can increase the distance between the edge of the second pixel electrode 210-2 and the counter electrode 230 disposed on the second pixel electrode 210-2, and can increase the distance between the edge of the third pixel electrode 210-3 and the counter electrode 230 disposed on the third pixel electrode 210-3. Therefore, arcing, etc. can be prevented from occurring at the edge of the first pixel electrode 210-1, the edge of the second pixel electrode 210-2, or the edge of the third pixel electrode 210-3. The pixel defining layer 215 may include an organic material such as polyimide or hexamethyldisiloxane (HMDSO). In an embodiment, the pixel defining layer 215 may include, for example, an inorganic material such as silicon oxide (SiO X ) or silicon nitride (SiN X ). However, the present disclosure is not limited thereto.

[0100] The intermediate layer 220 may be disposed on the first pixel electrode 210-1, the second pixel electrode 210-2, and the third pixel electrode 210-3. The intermediate layer 220 may include a first intermediate layer 220-1 corresponding to the first pixel PX1, a second intermediate layer 220-2 corresponding to the second pixel PX2, and a third intermediate layer 220-3 corresponding to the third pixel PX3. The first intermediate layer 220-1 may be disposed on the first pixel electrode 210-1. The second intermediate layer 220-2 may be disposed on the second pixel electrode 210-2. The third intermediate layer 220-3 may be disposed on the third pixel electrode 210-3.

[0101] The first intermediate layer 220-1 to the third intermediate layer 220-3 may respectively include an emission layer configured to emit a plurality of lights of different wavelength bands. For example, the first intermediate layer 220-1 may include a first emission layer configured to emit green light. The second intermediate layer 220-2 may include a second emission layer configured to emit red light. The third intermediate layer 220-3 may include a third emission layer configured to emit blue light. The green light may be light having a wavelength band of about 495nm to about 580nm, the red light may be light having a wavelength band of about 580nm to about 780nm, and the blue light may be light having a wavelength band of about 400nm to about 495nm.

[0102] Therefore, each of the first to third emission layers may include a high molecular weight organic material or a low molecular weight organic material that emits light of a color (e.g., a certain or selectable color). For example, the first emission layer may be formed by using, for example, a green dopant in a host material (e.g., a certain or selectable host material). The second emission layer may be formed by using, for example, a red dopant in a host material (e.g., a certain or selectable host material). The third emission layer may be formed by using, for example, a blue dopant in a host material (e.g., a certain or selectable host material).

[0103] The intermediate layer 220 may include common layers. At least some common layers may extend across the first organic light emitting diode OLED1, the second organic light emitting diode OLED2, and the third organic light emitting diode OLED3 (or be formed integrally in the first organic light emitting diode OLED1, the second organic light emitting diode OLED2, and the third organic light emitting diode OLED3). For example, the common layers (e.g., specific common layers or selectable common layers) included in the first intermediate layer 220-1, the common layers (e.g., specific common layers or selectable common layers) included in the second intermediate layer 220-2, and the common layers (e.g., specific common layers or selectable common layers) included in the third intermediate layer 220-3 may be arranged continuously. For example, the first intermediate layer 220-1, the second intermediate layer 220-2, and the third intermediate layer 220-3 may form the same common layer. For ease of explanation, in Figure 4 In the embodiment, the intermediate layer 220 may be continuously disposed in the first organic light emitting diode OLED1 , the second organic light emitting diode OLED2 , and the third organic light emitting diode OLED3 .

[0104] The counter electrode 230 may be disposed in the display area DA (eg, referring to Figure 1B) and may cover the display area DA. For example, the counter electrode 230 may extend across the first organic light emitting diode OLED1, the second organic light emitting diode OLED2, and the third organic light emitting diode OLED3 (or be integrally formed in the first organic light emitting diode OLED1, the second organic light emitting diode OLED2, and the third organic light emitting diode OLED3), and may correspond to the first pixel electrode 210-1, the second pixel electrode 210-2, and the third pixel electrode 210-3. For example, in a plan view, the counter electrode 230 may overlap all of the first pixel electrode 210-1, the second pixel electrode 210-2, and the third pixel electrode 210-3. The counter electrode 230 may cover the peripheral area PA (for example, reference Figure 1B ) and display area DA.

[0105] The counter electrode 230 may include, for example, ITO, In 2 O 3 The counter electrode 230 may include a transmissive conductive layer of Mg or IZO, and may also include a semi-transmissive layer including a metal such as Al or Ag. For example, the counter electrode 230 may be a semi-transmissive layer including Mg or Ag. Figure 4 , but a covering layer (not shown) may be disposed on the counter electrode 230. For example, the covering layer may include a material selected from an organic material, an inorganic material, and any mixture thereof. The covering layer may include a single layer (single layer structure) or multiple layers (multilayer structure). In other embodiments, the LiF layer may be disposed on the covering layer.

[0106] However, the interval (e.g., distance) between adjacent pixels in a plurality of pixels (e.g., the first pixel PX1, the second pixel PX2, and the third pixel PX3) can be determined according to the width 215W of the pixel defining layer 215. The width 215W of the pixel defining layer 215 may be about 20 μm or less. In a high-resolution display device, the width 215W of the pixel defining layer 215 may be about 2 μm or less. In the case where the resolution of the display device is increased, the light emitted from the emission layer of the pixel may travel to the adjacent pixel. Therefore, the color of the pixel may be mixed with the color of the adjacent pixel, and an unexpected current may be applied to the adjacent pixel through the common layer. However, the display device 1 according to the embodiment may include a metal partition wall MW between the pixel defining layer 215 and the intermediate layer 220, and light leakage to the adjacent pixel and leakage current flowing between the adjacent pixels can be prevented.

[0107] The metal partition wall MW may be disposed on the pixel defining layer 215. The metal partition wall MW may be disposed between the pixel defining layer 215 and the intermediate layer 220. The metal partition wall MW may define an upper surface US and a side surface SS, wherein the upper surface US is parallel to the upper surface of the substrate 100 and contacts the intermediate layer 220, and the side surface SS is inclined at an angle (e.g., a specific angle or a selectable angle) relative to the upper surface of the substrate 100. The side surface SS of the metal partition wall MW may define Figure 3 The metal holes MH1, MH2 and MH3.

[0108] The metal partition wall MW may be in contact with (e.g., in direct contact with) at least a portion of the intermediate layer 220. For example, the metal partition wall MW may be in contact with (e.g., in direct contact with) at least some of the common layers included in the intermediate layer 220. The lowest layer among the common layers included in the intermediate layer 220 may be in direct contact with the metal partition wall MW. At least some of the common layers included in the intermediate layer 220 may extend on the upper surface US and the side surface SS of the metal partition wall MW (e.g., be continuously disposed on the upper surface US and the side surface SS of the metal partition wall MW). The metal partition wall MW may be disposed between the first opening OP1 and the second opening OP2, between the second opening OP2 and the third opening OP3, and between the first opening OP1 and the third opening OP3. The metal partition wall MW may surround the first opening OP1, the second opening OP2, and the third opening OP3.

[0109] The height H of the metal partition wall MW may be about or greater. The height H of the metal partition wall MW may be a height in a direction perpendicular to the substrate 100, and refers to a height of the display device 1 in a thickness direction. Since the height H of the metal partition wall MW is about or greater, and thus the first light L1 emitted from the first intermediate layer 220-1 of the first pixel PX1 in the high-resolution display device can be prevented from traveling to the second pixel PX2 and the third pixel PX3 adjacent to the first pixel PX1. For example, the second light L2 emitted from the second intermediate layer 220-2 of the second pixel PX2 can be prevented from traveling to the first pixel PX1 and the third pixel PX3 adjacent to the second pixel PX2, and the third light L3 emitted from the third intermediate layer 220-3 of the third pixel PX3 can be prevented from traveling to the first pixel PX1 and the second pixel PX2 adjacent to the third pixel PX3. In an embodiment, since the height H of the metal partition wall MW is about or less, and thus the thickness of the display device 1 can be prevented from increasing.

[0110] The metal partition wall MW may have a single-layer structure or a multi-layer structure. Figure 4In the embodiment, the metal partition wall MW may have a single-layer structure. However, the present disclosure is not limited thereto. For example, the metal partition wall MW may have a multi-layer structure in which metal layers are stacked on each other on the pixel defining layer 215. Fig. 9 A detailed description of the metal partition wall MW having a multi-layer structure is provided. The metal layers may have different material compositions.

[0111] The metal partition wall MW may have a trapezoidal cross-sectional shape. The area of ​​the upper surface US of the metal partition wall MW may be smaller than the area of ​​the lower surface of the metal partition wall MW. The metal partition wall MW may have a side surface of a positively tapered cross-section. Figure 3 and Figure 4 In an embodiment, when the metal partition wall MW includes the first metal hole MH1, the second metal hole MH2 and the third metal hole MH3, the side surface SS of the metal partition wall MW defining the first metal hole MH1, the second metal hole MH2 and the third metal hole MH3 may have a positively tapered angle.

[0112] The metal partition wall MW may include a material having a high reflectivity. For example, the metal partition wall MW may include at least one of aluminum (Al), silver (Ag), molybdenum (Mo), and titanium (Ti). The metal partition wall MW may modify the path of travel of light by reflecting light emitted from a pixel in a direction toward an adjacent pixel back in a direction toward the pixel. For example, the metal partition wall MW may guide light in a direction toward the pixel. For example, a first light L1 emitted from a first pixel PX1 toward a second pixel PX2 and / or a third pixel PX3 adjacent to the first pixel PX1 may be reflected toward the first pixel PX1 from a positively tapered side surface SS of the metal partition wall MW. For example, a second light L2 emitted from a second pixel PX2 toward a first pixel PX1 and / or a third pixel PX3 adjacent to the second pixel PX2 may be reflected toward the second pixel PX2 from a positively tapered side surface SS of the metal partition wall MW. The third light L3 emitted from the third pixel PX3 toward the first pixel PX1 and / or the second pixel PX2 adjacent to the third pixel PX3 may be reflected from the forward tapered side surface SS of the metal partition wall MW toward the third pixel PX3. Therefore, the color purity of the display device 1 may be improved.

[0113] An auxiliary voltage (hereinafter, first voltage) equal to or lower than the voltage (hereinafter, second voltage) applied to the counter electrode 230 may be applied to the metal partition wall MW. In an embodiment, the display device 1 may further include an auxiliary electrode (not shown) configured to supply the auxiliary voltage to the metal partition wall MW. The metal partition wall MW may be electrically connected to the auxiliary electrode. For example, the metal partition wall MW may be electrically connected to the auxiliary electrode through a contact hole (not shown) provided in the pixel defining layer 215. Since an auxiliary voltage equal to or lower than the voltage applied to the counter electrode 230 is applied to the metal partition wall MW, leakage current flowing between adjacent pixels may be reduced. For example, the first voltage may be equal to or lower than the second voltage, and leakage current flowing between adjacent pixels may be reduced. Refer to the following Figure 8 To provide a detailed description of the present disclosure.

[0114] Figure 5A and Figure 5B is a schematic cross-sectional view of a display device according to an embodiment. FIG. 6A to FIG. 6C is a schematic cross-sectional view of a display device according to an embodiment. 5A to 6C , the pixel electrode 210 may correspond to any one of the first pixel electrode 210 - 1 , the second pixel electrode 210 - 2 , and the third pixel electrode 210 - 3 .

[0115] exist Figure 4 In the embodiment, the width of the lower surface of the metal partition wall MW may be smaller than the width of the upper surface of the pixel defining layer 215. However, the present disclosure is not limited thereto. For example, referring to Figure 5A , the width "a" of the lower surface of the metal partition wall MW may be equal to the width "b" of the upper surface of the pixel defining layer 215 (eg, a=b). Figure 5B , the width "a" of the lower surface of the metal partition wall MW may be greater than the width "b" of the upper surface of the pixel defining layer 215 (for example, a>b). In an embodiment, in the case where the pixel defining layer 215 includes an organic layer, due to the difference in etching rate between the metal partition wall MW as a metal layer and the organic layer, the connection portion between the metal partition wall MW and the pixel defining layer 215 may have an undercut shape, such as Figure 5B In an embodiment, even when the pixel defining layer 215 includes an inorganic layer, a connection portion between the metal partition wall MW and the pixel defining layer 215 may have an undercut shape in an etching process.

[0116] refer to FIG. 6A to FIG. 6C, the display device according to the embodiment may include an inorganic insulating layer IL covering at least a portion of the metal partition wall MW. The inorganic insulating layer IL may be disposed between the metal partition wall MW and the intermediate layer 220. The inorganic insulating layer IL may separate at least a portion of the upper surface US and / or at least a portion of the side surface SS of the metal partition wall MW from the intermediate layer 220.

[0117] In the embodiments, reference Fig. 6A , the inorganic insulating layer IL may cover the entire area of ​​the side surface SS of the metal partition wall MW and a portion (eg, edge portion) of the upper surface US of the metal partition wall MW. Figure 6B , the inorganic insulating layer IL may cover the lower side of the side surface SS of the metal partition wall MW and expose the upper side of the side surface SS of the metal partition wall MW and the entire area of ​​the upper surface US of the metal partition wall MW. Figure 6C , the inorganic insulating layer IL may cover only one side of the side surface SS of the metal partition wall MW and a portion of the upper surface US of the metal partition wall MW.

[0118] The surface of the metal partition wall MW covered by the inorganic insulating layer IL may be spaced apart from the intermediate layer 220. The surface of the metal partition wall MW exposed without being covered by the inorganic insulating layer IL may be in direct contact with the intermediate layer 220. Fig. 6A In the embodiment, the intermediate layer 220 may be in direct contact with a portion (eg, a central portion) of the upper surface US of the metal partition wall MW. Figure 6B In the embodiment, the intermediate layer 220 may be in direct contact with the entire area of ​​the upper surface US and the upper portion of the side surface SS of the metal partition wall MW. Figure 6C In the embodiment, the intermediate layer 220 may directly contact the other side of the side surface SS of the metal partition wall MW and a portion of the upper surface US of the metal partition wall MW. Therefore, the position where the metal partition wall MW directly contacts the intermediate layer 220 may be determined according to the position of the inorganic insulating layer IL.

[0119] FIG. 7A to FIG. 7C is a schematic cross-sectional view of an organic light emitting diode that can be used as a display element according to an embodiment.

[0120] refer to Fig. 7A The intermediate layer 220 of the organic light emitting diode according to the embodiment may include an emission layer 222, a charge generation layer 224 and a common layer. The common layer may include a first common layer 221, a second common layer 223, a third common layer 225 and a fourth common layer 227.

[0121] The emission layer 222 may include a first sub-emission layer EML1 and a second sub-emission layer EML2 stacked and spaced apart from each other. Holes and electrons may be recombined with each other in the emission layer 222, and light may be emitted from the emission layer 222. The first sub-emission layer EML1 and the second sub-emission layer EML2 may include materials emitting the same color or materials emitting different colors.

[0122] The charge generation layer 224 can help the movement of electrons and holes. The charge generation layer 224 may include a layer including an N-type charge generation layer and a P-type charge generation layer. The N-type charge generation layer may include an N-type dopant material and an N-type host material, and the P-type charge generation layer may include a P-type dopant material and a P-type host material.

[0123] The first common layer 221 may overlap the charge generation layer 224 in a plan view. The first common layer 221 may include a hole injection layer HIL and a hole transport layer HTL. The hole injection layer HIL may be a layer into which holes transferred from the pixel electrode 210 or the charge generation layer 224 are injected. The hole transport layer HTL may transfer holes transferred from the hole injection layer HIL to the emission layer 222.

[0124] The second common layer 223 may overlap the charge generation layer 224 in a plan view. The second common layer 223 may include an electron transport layer ETL and an electron injection layer EIL. The electron injection layer EIL may be a layer into which electrons transferred from the counter electrode 230 or the charge generation layer 224 are injected. The electron transport layer ETL may transfer electrons transferred from the electron injection layer EIL to the emission layer 222. For example, the hole injection layer HIL, the hole transport layer HTL, the first sub-emission layer EML1, the electron transport layer ETL, and the electron injection layer EIL may be stacked on each other (e.g., sequentially stacked) and emit light.

[0125] The third common layer 225 and the first common layer 221 may have the same stack structure. The fourth common layer 227 and the second common layer 223 may have the same stack structure. Therefore, the hole injection layer HIL, the hole transport layer HTL, the second sub-emission layer EML2, the electron transport layer ETL, and the electron injection layer EIL may be stacked on each other (e.g., sequentially stacked) and emit light.

[0126] In an embodiment, the hole injection layer HIL, the hole transport layer HTL, the first sub-emission layer EML1, the electron transport layer ETL, the electron injection layer EIL, the charge generation layer 224, the hole injection layer HIL, the hole transport layer HTL, the second sub-emission layer EML2, the electron transport layer ETL, the electron injection layer EIL and the counter electrode 230 can be stacked on one another (e.g., stacked in sequence) on the pixel electrode 210.

[0127] exist Fig. 7AIn the embodiment, each of the second common layer 223 and the fourth common layer 227 may include an electron transport layer ETL and an electron injection layer EIL. However, the present disclosure is not limited thereto, and each of the second common layer 223 and the fourth common layer 227 may not include the electron injection layer EIL.

[0128] refer to Figure 7B The intermediate layer 220 of the organic light emitting diode according to the embodiment may include an emission layer 222' (e.g., a first sub-emission layer EML1, a second sub-emission layer EML2, and a third sub-emission layer EML3), a charge generation layer 228, and a common layer. The common layer may include a first common layer 221, a second common layer 223, a third common layer 225, a fourth common layer 227, a fifth common layer 229, and a sixth common layer 2211.

[0129] The emission layer 222' may include a first sub-emission layer EML1, a second sub-emission layer EML2, and a third sub-emission layer EML3 stacked and spaced apart from each other. The first sub-emission layer EML1, the second sub-emission layer EML2, and the third sub-emission layer EML3 may include materials that emit the same color. In other embodiments, the first sub-emission layer EML1, the second sub-emission layer EML2, and the third sub-emission layer EML3 may include materials that emit different colors.

[0130] The charge generation layer 228 may include a first sub-charge generation layer CGL1 and a second sub-charge generation layer CGL2. Each of the first sub-charge generation layer CGL1 and the second sub-charge generation layer CGL2 may include a layer including an N-type charge generation layer and a P-type charge generation layer. The N-type charge generation layer may include an N-type dopant material and an N-type host material, and the P-type charge generation layer may include a P-type dopant material and a P-type host material.

[0131] The common layer may include a first common layer 221, a second common layer 223, a third common layer 225, a fourth common layer 227, a fifth common layer 229, and a sixth common layer 2211. The fifth common layer 229 and the first common layer 221 may have the same stacking structure. The sixth common layer 2211 and the second common layer 223 may have the same stacking structure. For example, the fifth common layer 229 may include a hole injection layer HIL and a hole transport layer HTL, and the sixth common layer 2211 may include an electron transport layer ETL and an electron injection layer EIL.

[0132] exist Figure 7B In the embodiment, each of the second common layer 223, the fourth common layer 227, and the sixth common layer 2211 may include an electron transport layer ETL and an electron injection layer EIL. However, the present disclosure is not limited thereto, and the second common layer 223, the fourth common layer 227, and the sixth common layer 2211 may not include the electron injection layer EIL.

[0133] In an embodiment, a hole injection layer HIL, a hole transport layer HTL, a first sub-emission layer EML1, an electron transport layer ETL, an electron injection layer EIL, a first sub-charge generation layer CGL1, a hole injection layer HIL, a hole transport layer HTL, a second sub-emission layer EML2, an electron transport layer ETL, an electron injection layer EIL, a second sub-charge generation layer CGL2, a hole injection layer HIL, a hole transport layer HTL, a third sub-emission layer EML3, an electron transport layer ETL, an electron injection layer EIL and a counter electrode 230 may be stacked on one another (e.g., stacked in sequence) on a pixel electrode 210.

[0134] exist Fig. 7A In the embodiment, two sub-emission layers (e.g., a first sub-emission layer EML1 and a second sub-emission layer EML2) of the organic light emitting diode may be stacked on each other. However, the present disclosure is not limited thereto. Various modifications are possible. For example, three or more sub-emission layers (e.g., a first sub-emission layer EML1, a second sub-emission layer EML2, and a third sub-emission layer EML3) may be stacked on top of each other. Figure 7B stacked on top of each other as shown in , or can be Figure 7C As shown in FIG. 5 , only one sub-emission layer (eg, the first sub-emission layer EML1 ) is included.

[0135] refer to Figure 7C , a detailed description of the stacking structure of an organic light emitting diode according to another embodiment is provided as follows. The intermediate layer 220 may be disposed between the pixel electrode 210 and the counter electrode 230. The intermediate layer 220 may include a first common layer 221, an emission layer 222" (e.g., a first sub-emission layer EML1), and a second common layer 223. For example, a hole injection layer HIL, a hole transport layer HTL, an emission layer 222" (e.g., a first sub-emission layer EML1), an electron transport layer ETL, an electron injection layer EIL, and the counter electrode 230 may be stacked on one another (e.g., stacked in sequence) on the pixel electrode 210. Figure 7C In the embodiment of the present invention, the charge generating layer may not be stacked (for example, Fig. 7A charge generating layer 224).

[0136] In such Fig. 7A and Figure 7B In the case where the emission layers are stacked on each other in the embodiment of Fig. 7A The charge generation layer 224 or Figure 7B The charge generation layer 228) may be disposed in a plurality of emission layers (eg, Fig. 7A The first sub-emission layer EML1 and the second sub-emission layer EML2 of the emission layer 222 or Figure 7BThe first sub-emission layer EML1, the second sub-emission layer EML2 and the third sub-emission layer EML3 of the emission layer 222' are connected. Leakage current may be generated by the charge generation layer, and the adjacent organic light emitting diode may emit light. For example, in Figure 4 In the embodiment of the present invention, when applying the common voltage ELVSS (eg, reference Figure 2 ) and a driving voltage to make the first organic light emitting diode OLED1 emit light, current (e.g., leakage current) may flow to the second organic light emitting diode OLED2 through the charge generation layer 224 (or the charge generation layer 228). Therefore, the second organic light emitting diode OLED2 may emit subtle light (e.g., dim light or weak light).

[0137] exist Figure 7C In the embodiment of FIG. 2 , the organic light emitting diode may not include the charge generation layer 224 (or the charge generation layer 228 ). However, leakage current may still flow through the common layer (eg, the first common layer 221 ).

[0138] Figure 8 is a schematic cross-sectional view of a display device 1 according to an embodiment, and is a view showing a Figure 3 The line I-I' intercepts Figure 3 Schematic cross-sectional view of an example of a cross section of the display device 1. Figure 8 In the Figure 4 Detailed description of constituent elements that are the same as the constituent elements in .

[0139] exist Figure 8 In the organic light emitting diode, there may be Fig. 7A The stacked structure of the organic light emitting diode shown in FIG. However, the present disclosure is not limited thereto. For example, the organic light emitting diode according to the embodiment may have Figure 7B or Figure 7C The stacked structure of the organic light emitting diode shown in FIG.

[0140] refer to Fig. 7A and Figure 8 , each of the plurality of organic light emitting diodes may include a lower emission layer and an upper emission layer overlapping each other in a plan view. The lower emission layer of the organic light emitting diode may correspond to Fig. 7A The first sub-emission layer EML1, and the upper emission layer may correspond to Fig. 7A The second sub-emission layer EML2.

[0141] For example, the first organic light emitting diode OLED1 may include a first lower emission layer 222L-1 and a first upper emission layer 222U-1. The first upper emission layer 222U-1 may be disposed on the first lower emission layer 222L-1 and overlap the first lower emission layer 222L-1 in a plan view. For example, the first emission layer 222-1 may include a first lower emission layer 222L-1 and a first upper emission layer 222U-1. The first lower emission layer 222L-1 may be disposed on the first pixel electrode 210-1, and the first upper emission layer 222U-1 may be disposed on the first lower emission layer 222L-1.

[0142] The second organic light emitting diode OLED2 may include a second lower emission layer 222L-2 and a second upper emission layer 222U-2. The second upper emission layer 222U-2 may be disposed on the second lower emission layer 222L-2 and overlap the second lower emission layer 222L-2 in a plan view. For example, the second emission layer 222-2 may include a second lower emission layer 222L-2 and a second upper emission layer 222U-2. The second lower emission layer 222L-2 may be disposed on the second pixel electrode 210-2, and the second upper emission layer 222U-2 may be disposed on the second lower emission layer 222L-2.

[0143] The third organic light emitting diode OLED3 may include a third lower emission layer 222L-3 and a third upper emission layer 222U-3. The third upper emission layer 222U-3 may be disposed on the third lower emission layer 222L-3 and overlap the third lower emission layer 222L-3 in a plan view. For example, the third emission layer 222-3 may include a third lower emission layer 222L-3 and a third upper emission layer 222U-3. The third lower emission layer 222L-3 may be disposed on the third pixel electrode 210-3, and the third upper emission layer 222U-3 may be disposed on the third lower emission layer 222L-3.

[0144] Each of the first emission layer 222-1, the second emission layer 222-2, and the third emission layer 222-3 may correspond to Fig. 7A The emission layer 222.

[0145] The intermediate layer 220 of each of the plurality of organic light emitting diodes may include a charge generation layer 224 and a common layer. For example, the first organic light emitting diode OLED1 may include a first pixel electrode 210-1, a 1-1 common layer 221-1, a first lower emission layer 222L-1, a 2-1 common layer 223-1, a first charge generation layer 224-1, a 3-1 common layer 225-1, a first upper emission layer 222U-1, and a 4-1 common layer 227-1 stacked on each other (e.g., stacked in sequence). The second organic light emitting diode OLED2 may include a second pixel electrode 210-2, a 1-2 common layer 221-2, a second lower emission layer 222L-2, a 2-2 common layer 223-2, a second charge generation layer 224-2, a 3-2 common layer 225-2, a second upper emission layer 222U-2, and a 4-2 common layer 227-2 stacked on each other (e.g., stacked in sequence). The third organic light emitting diode OLED3 may include a third pixel electrode 210-3, a 1-3 common layer 221-3, a third lower emission layer 222L-3, a 2-3 common layer 223-3, a third charge generation layer 224-3, a 3-3 common layer 225-3, a third upper emission layer 222U-3 and a 4-3 common layer 227-3 stacked on each other (e.g., stacked in sequence).

[0146] Each of the 1-1 common layer 221 - 1 , the 1-2 common layer 221 - 2 , and the 1-3 common layer 221 - 3 may correspond to Fig. 7A Each of the 2-1st common layer 223-1, the 2-2nd common layer 223-2, and the 2-3rd common layer 223-3 may correspond to Fig. 7A Each of the 3-1st common layer 225-1, the 3-2nd common layer 225-2, and the 3-3rd common layer 225-3 may correspond to Fig. 7A Each of the 4-1st common layer 227-1, the 4-2nd common layer 227-2, and the 4-3rd common layer 227-3 may correspond to Fig. 7A Each of the first charge generation layer 224-1, the second charge generation layer 224-2, and the third charge generation layer 224-3 may correspond to Fig. 7A The charge generating layer 224 is formed by a plurality of electrodes.

[0147] The 1-1st common layer 221-1, the 1-2nd common layer 221-2, and the 1-3rd common layer 221-3, each corresponding to the first common layer 221, can be formed simultaneously from the same material through the same process. The 2-1st common layer 223-1, the 2-2nd common layer 223-2, and the 2-3rd common layer 223-3, each corresponding to the second common layer 223, can be formed simultaneously from the same material through the same process. The 3-1st common layer 225-1, the 3-2nd common layer 225-2, and the 3-3rd common layer 225-3, each corresponding to the third common layer 225, can be formed simultaneously from the same material through the same process. The 4-1st common layer 227-1, the 4-2nd common layer 227-2, and the 4-3rd common layer 227-3, each corresponding to the fourth common layer 227, can be formed simultaneously from the same material through the same process.

[0148] In the case where the display device has a high resolution, the gap between adjacent pixels may be relatively small. In the case where the gap between pixels becomes smaller, the leakage current flowing between adjacent pixels through the common layer included in the intermediate layer may increase. For example, the leakage current may flow between adjacent pixels through the first common layer or the charge generation layer. The embodiment may include a metal partition wall MW, and the leakage current may be prevented by applying a voltage (e.g., a specific voltage or a selectable voltage) to the metal partition wall MW.

[0149] According to an embodiment, the metal partition wall MW, the intermediate layer 220 (e.g., the first intermediate layer 220-1, the second intermediate layer 220-2, and the third intermediate layer 220-3), and the counter electrode 230 may be sequentially stacked on each other on the pixel defining layer 215. For example, the intermediate layer 220 may be disposed between the metal partition wall MW and the counter electrode 230. A first voltage equal to or lower than a second voltage may be applied to the metal partition wall MW. The second voltage may be a voltage applied to the counter electrode 230 (e.g., a common voltage ELVSS (e.g., a reference voltage). Figure 2 Since an auxiliary capacitor Cap_M (eg, reference Figure 4 ), so the RC delay can be increased. Therefore, the response of the adjacent pixels due to the leakage current can be reduced.

[0150] Fig. 9 is a schematic cross-sectional view of a display device 1 according to an embodiment, and is a view showing a Figure 3 The line I-I' intercepts Figure 3 Schematic cross-sectional view of an example of a cross section of the display device 1. Fig. 9 In the Figure 4 Detailed description of constituent elements that are the same as the constituent elements in .

[0151] refer to Fig. 9, the inorganic insulating layer IL may cover a portion of the metal partition wall MW. The inorganic insulating layer IL may be disposed between the metal partition wall MW and the intermediate layer 220. The inorganic insulating layer IL may separate at least a portion of the upper surface US and / or at least a portion of the side surface SS of the metal partition wall MW from the intermediate layer 220. Fig. 9 In the embodiment, since the inorganic insulating layer IL exposes at least a portion of the upper surface US of the metal partition wall MW and covers the side surface SS of the metal partition wall MW, the intermediate layer 220 may be in direct contact with the upper surface US of the metal partition wall MW and may not be in contact with the side surface SS of the metal partition wall MW. However, the embodiment is not limited thereto. The inorganic insulating layer IL may cover only a portion of the side surface SS of the metal partition wall MW, and the intermediate layer 220 may be in contact with the entire area of ​​the upper surface US of the metal partition wall MW and a portion of the side surface SS. In other embodiments, the inorganic insulating layer IL may cover the upper surface US of the metal partition wall MW and expose the side surface SS of the metal partition wall MW. Therefore, the intermediate layer 220 may be in contact only with the side surface SS of the metal partition wall MW. Therefore, the arrangement of the inorganic insulating layer IL can be adjusted, and the portion where the metal partition wall MW and the intermediate layer 220 are in direct contact with each other can be specified (or can be changed).

[0152] refer to Fig. 9 The metal partition wall MW may have a multi-layer structure including metal layers stacked on each other on the pixel defining layer 215. For example, the metal partition wall MW may include a first metal layer M1, a second metal layer M2, and a third metal layer M3, such as Fig. 9 As shown in . For example, the first metal layer M1, the second metal layer M2, and the third metal layer M3 may have different materials from each other. In an embodiment, the first metal layer M1 may include a material different from the material of the second metal layer M2 and / or the third metal layer M3. The second metal layer M2 may include a material different from the material of the first metal layer M1 and / or the third metal layer M3. The third metal layer M3 may include a material different from the material of the first metal layer M1 and / or the second metal layer M2.

[0153] In an embodiment, one of the first metal layer M1, the second metal layer M2, and the third metal layer M3 may include a material that causes galvanic corrosion with the pixel electrode 210. According to an embodiment, the inorganic insulating layer IL may cover the surface of the metal layer and prevent defects caused by corrosion in the galvanic corrosion. For example, the second metal layer M2 may include aluminum (Al), and the pixel electrode 210 may include indium tin oxide (ITO). Since the inorganic insulating layer IL covers the side surface SS of the metal partition wall MW including the surface of the second metal layer M2, as shown in FIG. Fig. 9 As shown in , galvanic corrosion between the second metal layer M2 and the pixel electrode 210 can be prevented.

[0154] FIG. 10A to FIG. 10F is a schematic cross-sectional view for describing a process of manufacturing a display device according to an embodiment. FIG. 10A to FIG. 10F Schematically shows Fig. 9 The manufacturing process of the embodiment.

[0155] refer to Fig. 10A After forming the pixel electrode 210 on the planarization layer 208, the preliminary pixel defining layer 215' may cover the entire area of ​​the pixel electrode 210. The first preliminary metal layer M1', the second preliminary metal layer M2' and the third preliminary metal layer M3' may be sequentially formed on the preliminary pixel defining layer 215'.

[0156] refer to Fig. 10B The first preliminary metal layer M1′ (eg, referring to Fig. 10A ), the second preliminary metal layer M2 '(for example, reference Fig. 10A ) and a third preliminary metal layer M3' (eg, reference Fig. 10A ) portion. The etching process may be dry etching or wet etching. Therefore, the first preliminary metal layer M1' may form the first metal layer M1 of the metal partition wall MW, the second preliminary metal layer M2' may form the second metal layer M2 of the metal partition wall MW, and the third preliminary metal layer M3' may form the third metal layer M3 of the metal partition wall MW. In an embodiment, the second preliminary metal layer M2' may include a metal material different from the metal materials of the first preliminary metal layer M1' and the third preliminary metal layer M3'. For example, the first preliminary metal layer M1', the second preliminary metal layer M2', and the third preliminary metal layer M3' may have materials different from each other. Therefore, after the etching process, the side surface of the metal partition wall MW may not be flat.

[0157] refer to Fig. 10C , an inorganic layer IL' may be formed on the preliminary pixel defining layer 215' and the metal partition wall MW. The inorganic layer IL' may be continuously disposed on the metal partition wall (or bank) MW.

[0158] refer to Fig. 10C and Fig. 10D , the inorganic layer IL' and the preliminary pixel defining layer 215' may be etched by an etching process, and the inorganic insulating layer IL and the pixel defining layer 215 may be formed. The etching process may be dry etching, and the etching process may be performed on the inorganic layer IL' and the preliminary pixel defining layer 215'. Therefore, the inorganic insulating layer IL and the pixel defining layer 215 may be formed at the same time. In the case where the inorganic insulating layer IL and the pixel defining layer 215 are formed at the same time, the inorganic insulating layer IL may be positioned only on the upper side of the pixel defining layer 215. A portion of the inorganic insulating layer IL on the metal partition wall MW may be removed by an etching process.

[0159] refer to Fig.10E , an intermediate layer 220 may be formed on the inorganic insulating layer IL. As described above, the intermediate layer 220 may include a common layer and an emission layer. The hole injection layer HIL (eg, referring to Fig. 7A ) and / or a hole transport layer HTL (eg, reference Figure 7B ) can be in direct contact with the metal partition wall MW.

[0160] refer to Fig.10F , a counter electrode 230 may be disposed on the intermediate layer 220. The counter electrode 230 may be continuously disposed on the metal partition wall (or bank) MW. In an embodiment, a first voltage may be applied to the metal partition wall MW, and a second voltage equal to or higher than the first voltage may be applied to the counter electrode 230. The second voltage may be a common voltage ELVSS (e.g., reference voltage ELVSS). Figure 2 ).

[0161] For convenience, a display device including an organic light emitting diode as a display element has been described. However, the embodiment may be applied to various types of display devices such as a liquid crystal display, an electrophoretic display, and an inorganic electroluminescent (EL) display.

[0162] The above description is an example of the technical features of the present disclosure, and those skilled in the art to which the present disclosure belongs will be able to make various modifications and changes.Therefore, the embodiments of the present disclosure described above can be implemented individually or in combination with each other.

[0163] Therefore, the embodiments disclosed in the present disclosure are not intended to limit the technical spirit of the present disclosure, but to describe the technical spirit of the present disclosure, and the scope of the technical spirit of the present disclosure is not limited by these embodiments. The protection scope of the present disclosure should be interpreted by the attached claims, and should be interpreted as all technical spirits within the equivalent scope are included in the scope of the present disclosure.

Claims

1. A display device, wherein: The display device comprises: A pixel electrode is disposed on the substrate; a pixel defining layer having an opening for exposing a central portion of the pixel electrode; A conductive partition wall is disposed on the pixel defining layer, and the conductive partition wall has or greater height; An intermediate layer is disposed on the pixel electrode, and the intermediate layer includes: Emission layer; and Multiple common layers; and a counter electrode, disposed on the intermediate layer, Wherein, at least a portion of the intermediate layer is in direct contact with at least a portion of the conductive partition wall.

2. The display device according to claim 1, wherein: In a plan view, the conductive partition wall surrounds the opening of the pixel defining layer.

3. The display device according to claim 1, wherein: The conductive partition wall receives a voltage equal to or lower than a voltage applied to the counter electrode.

4. The display device according to claim 1, wherein: The conductive partition wall has a trapezoidal cross-sectional shape.

5. The display device according to claim 1, wherein: An area of ​​an upper surface of the conductive partition wall is smaller than an area of ​​a lower surface of the conductive partition wall.

6. The display device according to claim 1, wherein: The display device further includes: An inorganic insulating layer covers a portion of the conductive partition wall and is disposed between the conductive partition wall and the intermediate layer.

7. The display device according to claim 6, wherein: The conductive partition wall includes a plurality of metal layers sequentially stacked on the pixel defining layer, The inorganic insulating layer covers at least a portion of a side surface of the conductive partition wall, and At least some of the plurality of common layers are in direct contact with at least a portion of an upper surface of the conductive partition wall.

8. The display device according to claim 7, wherein: The pixel electrode comprises indium tin oxide, and At least some of the plurality of metal layers include aluminum.

9. The display device according to claim 1, wherein: The transmitting layer comprises: a lower emission layer; and an upper emission layer overlapping the lower emission layer in a plan view, and The intermediate layer further includes a charge generation layer between the lower emission layer and the upper emission layer.

10. The display device according to claim 1, wherein: The conductive partition wall comprises a metal partition wall, and The metal partition wall includes at least one of molybdenum, titanium and aluminum.

11. A display device, wherein: The display device comprises: A first pixel electrode is disposed on the substrate; a second pixel electrode, spaced apart from the first pixel electrode on the substrate; A pixel defining layer having: a first opening exposing a central portion of the first pixel electrode; and a second opening, exposing a central portion of the second pixel electrode; a conductive partition wall disposed between the first opening and the second opening on the pixel defining layer, and the conductive partition wall receives a first voltage; a plurality of common layers, disposed on the first pixel electrode and the second pixel electrode; and a counter electrode disposed on the plurality of common layers, and the counter electrode receives a second voltage equal to or higher than the first voltage, The conductive partition wall is in direct contact with the hole injection layer or the hole transport layer among the plurality of common layers.

12. The display device according to claim 11, wherein: The conductive partition wall has a positively tapered cross-sectional shape.

13. The display device according to claim 11, wherein: The conductive partition wall has or greater height.

14. The display device according to claim 11, wherein: The conductive partition wall surrounds each of the first opening and the second opening in a plan view.

15. The display device according to claim 11, wherein: The display device further includes: A first lower emission layer, disposed on the first pixel electrode; A second lower emission layer is disposed on the second pixel electrode; A first upper emission layer, disposed on the first lower emission layer; and The second upper emission layer is arranged on the second lower emission layer.

16. The display device according to claim 15, wherein: The plurality of common layers include: A 1-1 common layer, disposed below the first lower emission layer; and A 1-2 common layer is disposed below the second lower emission layer, and The 1-1 common layer and the 1-2 common layer are integrated with each other.

17. The display device according to claim 15, wherein: The display device further includes: a first charge generation layer between the first lower emission layer and the first upper emission layer; and A second charge generation layer is between the second lower emission layer and the second upper emission layer.

18. The display device according to claim 11, wherein: The conductive partition wall includes a plurality of metal layers sequentially stacked on one another on the pixel defining layer.

19. The display device according to claim 18, wherein: The display device further includes: The inorganic insulating layer covers the conductive partition wall, and the inorganic insulating layer exposes at least a portion of an upper surface or at least a portion of a side surface of the conductive partition wall.

20. The display device according to claim 11, wherein The conductive partition wall comprises a metal partition wall, and The metal partition wall includes at least one of molybdenum, titanium and aluminum.

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