Display device and method for manufacturing display device

Abstract

The invention relates to a display device and a manufacturing method of the display device. A display device includes: a first inorganic insulating layer disposed across a display region in which an image is displayed and a peripheral region outside the display region; an organic insulating layer disposed on the first inorganic insulating layer; a lower electrode disposed on the organic insulating layer in the display region; an organic layer disposed on the lower electrode and including a light emitting layer; an upper electrode disposed on the organic layer; a second inorganic insulating layer disposed on the organic insulating layer, the second inorganic insulating layer having, in a peripheral region, an opening that exposes an edge portion of the organic insulating layer; a plurality of wirings disposed between the substrate and the first inorganic insulating layer and intersecting the edge portion in plan view; and a plurality of protective layers that intersect the edge portion in plan view, one of the protective layers facing one of the wirings, and that overlap the first inorganic insulating layer exposed from the organic insulating layer at the opening.

Description

[0001] Cross-references to related applications

[0002] This application claims the priority based on Japanese Patent Application No. 2023-205390 filed on December 5, 2023, and cites all the contents described in the Japanese application. Technical Field

[0003] Embodiments of the present invention relate to a display device and a method for manufacturing the display device. Background Art

[0004] In recent years, display devices using organic light-emitting diodes (OLEDs) as display elements have become practical. The display element includes a pixel circuit including a thin film transistor, a lower electrode connected to the pixel circuit, an organic layer covering the lower electrode, and an upper electrode covering the organic layer. The organic layer includes a light-emitting layer, and functional layers such as a hole transport layer and an electron transport layer.

[0005] In the process of manufacturing such a display element, a technology for suppressing a decrease in reliability is required. Summary of the invention

[0006] An object of the embodiments is to provide a display device and a method for manufacturing the display device that can suppress a decrease in reliability.

[0007] According to one embodiment, a display device comprises:

[0008] A substrate; a first inorganic insulating layer, which is arranged above the aforementioned substrate and covers a display area for displaying an image and a peripheral area outside the aforementioned display area; an organic insulating layer, which is arranged on the aforementioned first inorganic insulating layer; a lower electrode, which is arranged on the aforementioned organic insulating layer in the aforementioned display area; an organic layer, which is arranged on the aforementioned lower electrode and includes a light-emitting layer; an upper electrode, which is arranged on the aforementioned organic layer; a second inorganic insulating layer, which is arranged on the aforementioned organic insulating layer and has an opening in the aforementioned peripheral area to expose an edge of the aforementioned organic insulating layer; a plurality of wirings, which are arranged between the aforementioned substrate and the aforementioned first inorganic insulating layer and intersect the aforementioned edge when viewed from above; and a plurality of protective layers, which intersect the aforementioned edge when viewed from above, one of the aforementioned protective layers is opposite to one of the aforementioned wirings, and one of the protective layers overlaps with the aforementioned first inorganic insulating layer exposed from the aforementioned organic insulating layer at the aforementioned opening.

[0009] According to one embodiment, a method for manufacturing a display device, wherein:

[0010] A wiring is formed above a substrate, a first inorganic insulating layer is formed above the wiring, an organic insulating layer is formed above the first inorganic insulating layer, a lower electrode is formed above the organic insulating layer, a protective layer is formed opposite to the wiring and overlapping with the first inorganic insulating layer exposed from the organic insulating layer, a second inorganic insulating layer is formed covering the organic insulating layer and the protective layer, an opening is formed in the second inorganic insulating layer to overlap with an edge of the organic insulating layer, an organic layer is formed above the lower electrode, and an upper electrode is formed above the organic layer.

[0011] According to the embodiments, it is possible to provide a display device and a method for manufacturing the display device that can suppress a decrease in reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 This is a diagram showing a configuration example of a DSP of a display device.

[0013] Figure 2 It is a diagram showing an example of the layout of sub-pixels SP1 , SP2 , and SP3 .

[0014] Figure 3 It is along Figure 2 A schematic cross-sectional view of the display device DSP taken along line AB in FIG.

[0015] Figure 4 It is along Figure 1 A schematic cross-sectional view of the display device DSP taken along line CD.

[0016] Figure 5 1 is a plan view showing a configuration example of the mother substrate 100 .

[0017] Figure 6 It is shown Figure 5 FIG. 1 is a plan view of a configuration example of a region 100A of a mother substrate 100 shown.

[0018] Figure 7 It is shown along Figure 6 A cross-sectional view of a configuration example of a mother substrate 100 having an EF line.

[0019] Figure 8 It is a diagram for explaining a method of manufacturing the display device DSP.

[0020] Fig. 9 It is a diagram for explaining a method of manufacturing the display device DSP.

[0021] Fig.10 It is a diagram for explaining a method of manufacturing the display device DSP.

[0022] Fig.11 It is a diagram for explaining a method of manufacturing the display device DSP.

[0023] Fig.12 It is a diagram for explaining a method of manufacturing the display device DSP.

[0024] Fig.13 It is a diagram for explaining a method of manufacturing the display device DSP.

[0025] Fig.14 It is a diagram for explaining a method of manufacturing the display device DSP.

[0026] Fig.15 It is a diagram for explaining a method of manufacturing the display device DSP.

[0027] Fig.16 It is a diagram for explaining a method of manufacturing the display device DSP.

[0028] Fig.17 It is a diagram for explaining a method of manufacturing the display device DSP.

[0029] Fig.18 It is a diagram for explaining a method of manufacturing the display device DSP.

[0030] Fig.19 It is a diagram for explaining a method of manufacturing the display device DSP.

[0031] Fig. 20 It is a diagram for explaining a method of manufacturing the display device DSP.

[0032] Fig.21 It is a cross-sectional view for explaining a defect of a comparative example.

[0033] Fig. 22 This is a diagram for explaining one of the effects of this embodiment.

[0034] Fig.23 It is a cross-sectional view for explaining a defect of a comparative example.

[0035] Fig.24 FIG. 1 is a diagram showing another configuration example of the DSP of the display device.

[0036] Fig.25 1 is a plan view showing a configuration example of the mother substrate 100 .

[0037] Fig.26 1 is a plan view showing a mother substrate 100 cut along a primary cutting line CL1 . DETAILED DESCRIPTION

[0038] One embodiment will be described with reference to the drawings.

[0039] The disclosed content is only an example, and for those skilled in the art, the content that can be easily thought of with respect to appropriate changes that maintain the gist of the invention is of course included in the scope of the present invention. In addition, in order to make the description clearer, the drawings sometimes schematically show the width, thickness, shape, etc. of each part compared to the actual method, but this is only an example and does not limit the interpretation of the present invention. In addition, in this specification and each figure, the same reference numerals are sometimes used to mark the constituent elements that perform the same or similar functions as the constituent elements described above with respect to the already appeared figures, and repeated detailed descriptions are appropriately omitted.

[0040] It should be noted that, in the drawings, as needed, for easy understanding, mutually orthogonal X-axis, Y-axis and Z-axis are recorded. The direction along the X-axis is called the first direction X, the direction along the Y-axis is called the second direction Y, and the direction along the Z-axis is called the third direction Z. The situation of observing various elements parallel to the third direction Z is called top view. The first direction X and the second direction Y are directions parallel to the main surface of the substrate constituting the display device, and the third direction Z is equivalent to the thickness direction of the display device (the normal direction of the main surface).

[0041] The display device involved in this embodiment is an organic electroluminescent display device having an organic light emitting diode (OLED) as a display element, and can be mounted on a television, a personal computer, an in-vehicle device, a tablet terminal, a smartphone, a mobile phone terminal, etc.

[0042] Figure 1 This is a diagram showing a configuration example of a DSP of a display device.

[0043] The display device DSP includes a display panel PNL on an insulating substrate 10. The display panel PNL includes a display area DA for displaying an image and a peripheral area SA outside the display area DA. The substrate 10 may be glass or a flexible resin film.

[0044] In the present embodiment, the shape of the substrate 10 when viewed from above is a rectangle. The illustrated example of the substrate 10 has a long side parallel to the first direction X and a short side parallel to the second direction Y. However, the shape of the substrate 10 when viewed from above is not limited to a rectangle, and may also be other shapes such as a square, a circle, or an ellipse.

[0045] The display area DA includes a plurality of pixels PX arranged in a matrix in a first direction X and a second direction Y. The pixel PX includes a plurality of sub-pixels SP. In one example, the pixel PX includes a sub-pixel SP1 of a first color, a sub-pixel SP2 of a second color, and a sub-pixel SP3 of a third color. The first color, the second color, and the third color are different colors from each other. It should be noted that the pixel PX may also include a sub-pixel SP of other colors such as white together with the sub-pixels SP1, SP2, and SP3, or may include a sub-pixel SP of other colors such as white instead of any of the sub-pixels SP1, SP2, and SP3.

[0046] The sub-pixel SP includes a pixel circuit 1 and a display element DE driven by the pixel circuit 1. The pixel circuit 1 includes a pixel switch 2, a driving transistor 3, and a capacitor 4. The pixel switch 2 and the driving transistor 3 are switching elements composed of, for example, thin film transistors.

[0047] The gate electrode of the pixel switch 2 is connected to the scanning line GL. One of the source electrode and the drain electrode of the pixel switch 2 is connected to the signal line SL, and the other is connected to the gate electrode of the driving transistor 3 and the capacitor 4. In the driving transistor 3, one of the source electrode and the drain electrode is connected to the power line PL and the capacitor 4, and the other is connected to the anode of the display element DE.

[0048] It should be noted that the configuration of the pixel circuit 1 is not limited to the illustrated example. For example, the pixel circuit 1 may include more thin film transistors and capacitors.

[0049] The display element DE is an organic light emitting diode (OLED) as a light emitting element, sometimes referred to as an organic EL element.

[0050] The peripheral area SA has a plurality of mounting terminals MT and a plurality of inspection terminals TT. The mounting terminal MT is a terminal electrically connected to a signal source such as a flexible printed circuit substrate and an IC chip, and is electrically connected to various wirings (scanning lines, signal lines, power lines, wirings for touch sensors, etc.) of the display area DA. The inspection terminal TT is a terminal electrically connected to an inspection device that performs short circuits, disconnections, and operation confirmation of various circuits of various wirings. These inspection terminals TT are electrically connected to the mounting terminal MT, for example, via the connecting wiring CN. In addition, the inspection terminal TT is connected to at least one of the plurality of wirings LA and LB extending toward the substrate end 10E. That is, the plurality of inspection terminals TT include an inspection terminal TT connected only to the wiring LA and an inspection terminal TT connected to both the wiring LA and the wiring LB.

[0051] In the example shown in the drawings, the plurality of mounting terminals MT and the plurality of test terminals TT are arranged along the substrate end 10E and aligned in the first direction X.

[0052] Figure 2It is a diagram showing an example of the layout of sub-pixels SP1 , SP2 , and SP3 .

[0053] In the example shown in the figure, the sub-pixel SP2 and the sub-pixel SP3 are arranged in the second direction Y. The sub-pixel SP1 and the sub-pixel SP2 are arranged in the first direction X, and the sub-pixel SP1 and the sub-pixel SP3 are arranged in the first direction X.

[0054] When the sub-pixels SP1, SP2, and SP3 are arranged in this way, columns in which the sub-pixels SP2 and SP3 are alternately arranged in the second direction Y and columns in which a plurality of sub-pixels SP1 are arranged in the second direction Y are formed in the display area DA. These columns are alternately arranged in the first direction X.

[0055] It should be noted that the layout of the sub-pixels SP1, SP2, and SP3 is not limited to Figure 2 As another example, the sub-pixels SP1, SP2, and SP3 in each pixel PX may be arranged in sequence in the first direction X.

[0056] In the display area DA, an insulating layer 5 and partitions 6 are disposed. The insulating layer 5 has openings AP1, AP2, and AP3 in the sub-pixels SP1, SP2, and SP3, respectively. The insulating layer 5 having these openings AP1, AP2, and AP3 is sometimes referred to as a rib.

[0057] The partition wall 6 overlaps with the insulating layer 5 in a plan view. The partition wall 6 is formed in a lattice shape surrounding the openings AP1, AP2, and AP3. It can also be said that the partition wall 6 has openings in the sub-pixels SP1, SP2, and SP3 similarly to the insulating layer 5. The partition wall 6 is conductive and Figure 1 Among the plurality of mounting terminals MT shown, the mounting terminals MT having a common potential are electrically connected.

[0058] The sub-pixels SP1 , SP2 , and SP3 include display elements DE1 , DE2 , and DE3 as display elements DE, respectively.

[0059] The display element DE1 of the sub-pixel SP1 includes a lower electrode LE1, an upper electrode UE1, and an organic layer OR1, which overlap with the opening AP1 respectively. The peripheral portion of the lower electrode LE1 is covered by the insulating layer 5. The lower electrode LE1, the organic layer OR1, and the upper electrode UE1 are surrounded by the partition wall 6 when viewed from above. The peripheral portions of the organic layer OR1 and the upper electrode UE1 overlap with the insulating layer 5 when viewed from above. The organic layer OR1 includes, for example, a light-emitting layer that emits light in a blue wavelength region.

[0060] The display element DE2 of the sub-pixel SP2 includes a lower electrode LE2, an upper electrode UE2, and an organic layer OR2, which overlap with the opening AP2, respectively. The peripheral portion of the lower electrode LE2 is covered by the insulating layer 5. The lower electrode LE2, the organic layer OR2, and the upper electrode UE2 are surrounded by the partition wall 6 when viewed from above. The peripheral portions of the organic layer OR2 and the upper electrode UE2 overlap with the insulating layer 5 when viewed from above. The organic layer OR2 includes, for example, a light-emitting layer that emits light in the green wavelength region.

[0061] The display element DE3 of the sub-pixel SP3 includes a lower electrode LE3, an upper electrode UE3, and an organic layer OR3, which overlap with the opening AP3 respectively. The peripheral portion of the lower electrode LE3 is covered by the insulating layer 5. The lower electrode LE3, the organic layer OR3, and the upper electrode UE3 are surrounded by the partition wall 6 when viewed from above. The peripheral portions of the organic layer OR3 and the upper electrode UE3 overlap with the insulating layer 5 when viewed from above. The organic layer OR3 includes, for example, a light-emitting layer that emits light in the red wavelength region.

[0062] In the example shown in the figure, the outer shapes of the lower electrodes LE1, LE2, LE3 are indicated by single-dot chain lines, and the outer shapes of the organic layers OR1, OR2, OR3 and the upper electrodes UE1, UE2, UE3 are indicated by single-dot chain lines. It should be noted that the outer shapes of the lower electrodes, organic layers, and upper electrodes shown in the figure are not limited to reflecting accurate shapes.

[0063] The lower electrodes LE1 , LE2 , and LE3 correspond to, for example, anodes of the display element, and the upper electrodes UE1 , UE2 , and UE3 correspond to cathodes or common electrodes of the display element and are in contact with the partition wall 6 .

[0064] The lower electrode LE1 and the pixel circuit 1 of the sub-pixel SP1 (see Figure 1 The lower electrode LE2 is electrically connected to the pixel circuit 1 of the sub-pixel SP2. The lower electrode LE3 is electrically connected to the pixel circuit 1 of the sub-pixel SP3.

[0065] In the example shown in the figure, the area of ​​the opening AP1, the area of ​​the opening AP2, and the area of ​​the opening AP3 are different from each other. The area of ​​the opening AP1 is larger than the area of ​​the opening AP2, and the area of ​​the opening AP2 is larger than the area of ​​the opening AP3. In other words, the area of ​​the lower electrode LE1 exposed from the opening AP1 is larger than the area of ​​the lower electrode LE2 exposed from the opening AP2, and the area of ​​the lower electrode LE2 exposed from the opening AP2 is larger than the area of ​​the lower electrode LE3 exposed from the opening AP3.

[0066] Figure 3 It is along Figure 2 A schematic cross-sectional view of the display device DSP taken along line AB in FIG.

[0067] The circuit layer 11 is disposed on the substrate 10. The circuit layer 11 includes Figure 1The circuit layer 11 is covered with an insulating layer 12. The insulating layer 12 is an organic insulating layer that flattens the unevenness generated by the circuit layer 11.

[0068] The lower electrodes LE1, LE2, and LE3 are arranged on the insulating layer 12 and are separated from each other. The insulating layer 5 is an inorganic insulating layer, and is arranged on the insulating layer 12 and the lower electrodes LE1, LE2, and LE3. The opening AP1 of the insulating layer 5 overlaps with the lower electrode LE1, the opening AP2 overlaps with the lower electrode LE2, and the opening AP3 overlaps with the lower electrode LE3. The peripheral portions of the lower electrodes LE1, LE2, and LE3 are covered by the insulating layer 5. The lower electrodes LE1, LE2, and LE3 are connected to the pixel circuits 1 of the sub-pixels SP1, SP2, and SP3 respectively through contact holes provided in the insulating layer 12. It should be noted that the contact holes of the insulating layer 12 are provided in Figure 3 Omitted in .

[0069] The partition wall 6 includes a conductive lower portion 61 disposed on the insulating layer 5 and an upper portion 62 disposed on the lower portion 61. The upper portion 62 has a greater width than the lower portion 61. Both ends of the upper portion 62 protrude from the side surfaces of the lower portion 61. Such a shape of the partition wall 6 is called a cantilever shape.

[0070] In the example shown in the figure, the lower portion 61 includes a conductive layer 63 disposed on the insulating layer 5 and a conductive layer 64 disposed on the conductive layer 63. For example, the conductive layer 63 is formed thinner than the conductive layer 64. In the example shown in the figure, both ends of the conductive layer 63 protrude from the side surfaces of the conductive layer 64.

[0071] The upper portion 62 includes a thin film 65 disposed on the conductive layer 64 and a thin film 66 disposed on the thin film 65. Both ends of the thin films 65 and 66 protrude from the side surfaces of the conductive layer 64. The thin films 65 and 66 may be conductive layers or insulating layers.

[0072] The organic layer OR1 contacts the lower electrode LE1 through the opening AP1, covers the lower electrode LE1 exposed from the opening AP1, and has its peripheral portion located on the insulating layer 5. The upper electrode UE1 covers the organic layer OR1 and contacts the lower portion 61.

[0073] The organic layer OR2 contacts the lower electrode LE2 through the opening AP2, covers the lower electrode LE2 exposed from the opening AP2, and has its peripheral portion located on the insulating layer 5. The upper electrode UE2 covers the organic layer OR2 and contacts the lower portion 61.

[0074] The organic layer OR3 contacts the lower electrode LE3 through the opening AP3 , covers the lower electrode LE3 exposed from the opening AP3 , and its peripheral portion is located on the insulating layer 5 . The upper electrode UE3 covers the organic layer OR3 and contacts the lower portion 61 .

[0075] In the example shown in the figure, the sub-pixel SP1 has a cap layer CP1 and a sealing layer SE1, the sub-pixel SP2 has a cap layer CP2 and a sealing layer SE2, and the sub-pixel SP3 has a cap layer CP3 and a sealing layer SE3. The cap layers CP1, CP2, and CP3 respectively function as optical adjustment layers for improving the extraction efficiency of light emitted from the organic layers OR1, OR2, and OR3. It should be noted that the cap layers CP1, CP2, and CP3 may be omitted.

[0076] The cap layer CP1 is disposed on the upper electrode UE1 .

[0077] The cap layer CP2 is disposed on the upper electrode UE2.

[0078] The cap layer CP3 is disposed on the upper electrode UE3.

[0079] The sealing layer SE1 is disposed on the cap layer CP1 , in contact with the partition wall 6 , and continuously covers each member of the sub-pixel SP1 .

[0080] The sealing layer SE2 is disposed on the cap layer CP2 , in contact with the partition wall 6 , and continuously covers each member of the sub-pixel SP2 .

[0081] The sealing layer SE3 is disposed on the cap layer CP3 , in contact with the partition wall 6 , and continuously covers each component of the sub-pixel SP3 .

[0082] In the example shown in the figure, a portion of each of the organic layer OR1, the upper electrode UE1 and the cover layer CP1 is located on the partition wall 6 around the sub-pixel SP1. These portions are separated from portions of the organic layer OR1, the upper electrode UE1 and the cover layer CP1 located at the opening AP1 (parts constituting the display element DE1).

[0083] Similarly, a portion of the organic layer OR2, the upper electrode UE2 and the cover layer CP2 is located on the partition wall 6 around the sub-pixel SP2, and these portions are separated from the portions of the organic layer OR2, the upper electrode UE2 and the cover layer CP2 located in the opening AP2 (the portions constituting the display element DE2).

[0084] Similarly, a portion of the organic layer OR3, the upper electrode UE3 and the cover layer CP3 is located on the partition wall 6 around the sub-pixel SP3, and these portions are separated from the portion of the organic layer OR3, the upper electrode UE3 and the cover layer CP3 located in the opening AP3 (the portion constituting the display element DE3).

[0085] In the following description, the multilayer body including the organic layer OR1, the upper electrode UE1 and the cover layer CP1 is referred to as the stacked film FL1, the multilayer body including the organic layer OR2, the upper electrode UE2 and the cover layer CP2 is referred to as the stacked film FL2, and the multilayer body including the organic layer OR3, the upper electrode UE3 and the cover layer CP3 is referred to as the stacked film FL3.

[0086] The ends of the sealing layers SE1, SE2, and SE3 and the ends of the laminated films FL1, FL2, and FL3 are respectively located on the partition wall 6. In the example shown in the figure, the laminated film FL1 and the sealing layer SE1 on the partition wall 6 between the sub-pixels SP1 and SP2 are separated from the laminated film FL2 and the sealing layer SE2 on the partition wall 6. In addition, the laminated film FL1 and the sealing layer SE1 on the partition wall 6 between the sub-pixels SP1 and SP3 are separated from the laminated film FL3 and the sealing layer SE3 on the partition wall 6.

[0087] The partition wall 6 and the sealing layers SE1, SE2, and SE3 are covered with a resin layer 13. The resin layer 13 is covered with a sealing layer 14. The sealing layer 14 is covered with a resin layer 15.

[0088] The insulating layer 5, the sealing layers SE1, SE2, SE3 and the sealing layer 14 are made of, for example, silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiON), aluminum oxide (Al 2 O 3 ) and other inorganic insulating materials.

[0089] The lower portion 61 of the partition wall 6 is formed of a conductive material and is electrically connected to the upper electrodes UE1, UE2, and UE3. The conductive layer 63 is formed of a titanium-based material such as titanium or a titanium compound. The conductive layer 64 is formed of a material different from the conductive layer 63 and the upper portion 62, such as aluminum or an aluminum compound.

[0090] The upper portion 62 of the partition wall 6 is formed of, for example, a conductive material, but may also be formed of an insulating material. The upper portion 62 is formed of a material different from that of the lower portion 61. The thin film 65 is formed of, for example, a titanium-based material such as titanium or a titanium compound. The thin film 66 is formed of, for example, an oxide conductive material such as indium tin oxide (ITO).

[0091] The lower electrodes LE1, LE2, and LE3 are, for example, a multilayer body including a transparent layer formed of an oxide conductive material such as indium tin oxide (ITO) and a reflective layer formed of a metal material such as silver. In one example, the lower electrodes LE1, LE2, and LE3 are a multilayer body including a reflective layer between a pair of transparent layers. The lower transparent layer functions as a bonding layer that is bonded to the insulating layer 12.

[0092] The organic layer OR1 includes a light-emitting layer EM1. The organic layer OR2 includes a light-emitting layer EM2. The organic layer OR3 includes a light-emitting layer EM3. The light-emitting layer EM1, the light-emitting layer EM2, and the light-emitting layer EM3 are formed of different materials. In one example, the light-emitting layer EM1 is formed of a material that emits light in a blue wavelength region, the light-emitting layer EM2 is formed of a material that emits light in a green wavelength region, and the light-emitting layer EM3 is formed of a material that emits light in a red wavelength region.

[0093] In addition, each of the organic layers OR1, OR2, and OR3 includes a plurality of functional layers such as a hole injection layer, a hole transport layer, an electron blocking layer, a hole blocking layer, an electron transport layer, and an electron injection layer.

[0094] The upper electrodes UE1 , UE2 , and UE3 are formed of a metal material such as an alloy of magnesium and silver (MgAg).

[0095] The cap layers CP1, CP2, and CP3 are multilayer bodies of a plurality of thin films, all of which are transparent and have different refractive indices.

[0096] The circuit layer 11 , the insulating layer 12 , and the insulating layer 5 shown in the figure are arranged over the display area DA and the peripheral area SA.

[0097] Figure 4 It is along Figure 1 A schematic cross-sectional view of the display device DSP taken along line CD.

[0098] The insulating layer 111 is an inorganic insulating layer, and is disposed on the substrate 10. A plurality of wirings LA are disposed on the insulating layer 111. Such wirings LA are formed of, for example, a semiconductor such as polysilicon. The insulating layer 112 is an inorganic insulating layer, and is disposed on the insulating layer 111, covering the wirings LA. A plurality of wirings LB are disposed on the insulating layer 112. Such wirings LB are formed of, for example, a metal material such as molybdenum, tungsten, titanium, or aluminum. In addition, the wirings LB are, for example, Figure 1 The scanning lines GL shown are formed of the same material. The insulating layer 113 is an inorganic insulating layer, which is disposed on the insulating layer 112 and covers the wiring LB. The insulating layer 114 is an organic insulating layer, which is disposed on the insulating layer 113 .

[0099] The insulating layers 111 , 112 , and 113 are formed of an inorganic insulating material such as silicon nitride (SiNx), silicon oxide (SiOx), or silicon oxynitride (SiON).

[0100] These insulating layers 111, 112, 113, 114 and wirings LA and LB are included in Figure 3 In the circuit layer 11 shown.

[0101] The insulating layer 12 is disposed on the insulating layer 114. The stacked body of the insulating layer 12 and the insulating layer 114 is collectively referred to as an organic insulating layer IL.

[0102] The insulating layer 5 is disposed on the insulating layer 12 .

[0103] Next, a mother substrate for a display device (hereinafter, simply referred to as a mother substrate) 100 for manufacturing a plurality of display device DSPs at a time will be described.

[0104] Figure 5 1 is a plan view showing a configuration example of the mother substrate 100 .

[0105] The mother substrate 100 has a plurality of panel portions PP and a blank portion MP on the outside of the panel portions PP on the large substrate 10. The large substrate 10 is formed in a rectangular shape, for example. In the example shown in the figure, two panel portions PP are shown as the plurality of panel portions PP, but more panel portions may be arranged in a matrix in the first direction X and the second direction Y. Each panel portion PP is removed by cutting the mother substrate 100 along the cutting line CL. Each panel portion PP after removal is equivalent to Figure 1 The display panel PNL shown includes a display area DA and a peripheral area SA.

[0106] The blank portion MP includes, for example, a plurality of TEG terminals TG electrically connected to a test element group (Test Element Group) and the like.

[0107] The connection wiring CA is arranged over the panel portion PP and the blank portion MP, and electrically connects the adjacent test terminals TT. The connection wiring CB is arranged in the blank portion MP, and electrically connects the TEG terminal TG and the test terminal TT.

[0108] When the mother substrate 100 is cut along the cutting line CL, a portion of the connection wiring CA is used as Figure 1 The wiring LA shown in the figure remains in the display panel PNL, and a part of the connecting wiring CB is used as Figure 1 The wiring LB shown remains in the display panel PNL.

[0109] Figure 6 It is shown Figure 5 FIG. 1 is a plan view of a configuration example of a region 100A of a mother substrate 100 shown.

[0110] The cutting line CL represented by the double-dashed line in the figure can be expressed as Figure 1 The outer shape of the display panel PNL is shown. The organic insulating layer IL has an opening OPA along the outer shape of the panel portion PP. The cutting line CL overlaps with the opening OPA. The opening OPA is a through portion of the organic insulating layer IL, exposing the base of the organic insulating layer IL.

[0111] In the illustrated region 100A, the insulating layer 5 has edges E11, E21, E31, and E32. The insulating layer 12 has edges E12 and E22. The insulating layer 114 has edges E13 and E23. The edge E12 is located between the edge E11 and the edge E13. The edge E22 is located between the edge E21 and the edge E23. That is, in the organic insulating layer IL, the insulating layer 114 extends further toward the cutting line CL than the insulating layer 12. The opening OPA is formed between the edge E13 and the edge E23 that are opposite to each other with the cutting line CL sandwiched therebetween.

[0112] The insulating layer 5 has an opening OPB exposing the edges E12 and E22 of the insulating layer 12 and the edges E13 and E23 of the insulating layer 114. A portion of the insulating layer 5 is located in the opening OPA. In a plan view, a portion of the opening OPB overlaps with the opening OPA.

[0113] One connection wiring CA and one connection wiring CB are connected to one inspection terminal TT. The connection wiring CA has a meandering portion and has a high resistance.

[0114] In a plan view, the connection wiring CA and the connection wiring CB intersect the edges E11, E12, E13, E31, E32, E23, E22, and E21, respectively. The connection wiring CA and the connection wiring CB overlap the peripheral partition wall 7 in the region overlapping with the organic insulating layer IL. The connection wiring CA and the connection wiring CB bend in a manner of not overlapping with the peripheral partition wall 7 and detouring from the peripheral partition wall 7 in the region (opening OPA) not overlapping with the organic insulating layer IL. It should be noted that the details of the peripheral partition wall 7 are described below.

[0115] Each protective layer PR intersects with the edge E11, E12, E13, E31 or the edge E32, E23, E22, E21 in a plan view, and overlaps with the connection wiring CA or the connection wiring CB. More specifically, one protective layer PR is arranged at the intersection of one connection wiring CA and the edge E11, E12, E13, E31, and the other protective layers PR are arranged at the intersection of one connection wiring CA and the edge E32, E23, E22, E21. In addition, one protective layer PR is arranged at the intersection of one connection wiring CB and the edge E11, E12, E13, E31, and the other protective layers PR are arranged at the intersection of one connection wiring CB and the edge E32, E23, E22, E21.

[0116] The edge E13 and the edge E31 are opposed to each other with a gap therebetween in a plan view. The edge E13 and the edge E31 are each formed to have a zigzag shape between the connection wiring CA and the connection wiring CB.

[0117] In the example shown in the figure, the edge E31 and the edge E13 extend in the first direction X and are spaced apart from each other in the second direction Y. The edge E31 has a tapered portion TP1 that is bent so as to become sharper toward the edge E13 between the connection wiring CA and the connection wiring CB. The edge E13 has a tapered portion TP2 that is bent so as to become sharper toward the edge E31 between the connection wiring CA and the connection wiring CB. The tapered portion TP1 is located between the two tapered portions TP2 and does not overlap with the tapered portion TP2.

[0118] Similarly, the edge E23 and the edge E32 are opposed to each other with a gap therebetween, and are formed to have a zigzag shape between the connection wiring CA and the connection wiring CB.

[0119] When the region 100A is cut by the cutting line CL, the inspection terminal TT remains on the display panel, the connection wiring CA between the inspection terminal TT and the cutting line CL remains on the display panel as the wiring LA, and the connection wiring CB between the inspection terminal TT and the cutting line CL remains on the display panel as the wiring LB.

[0120] Figure 7 It is shown along Figure 6 1 is a cross-sectional view of a configuration example of a mother substrate 100 having EF lines. Here, a cross section including an overlapping portion of a connection wiring CB and a protection layer PR is shown.

[0121] The connection wiring CA is arranged on the insulating layer 111 and is covered by the insulating layer 112. The connection wiring CB is arranged on the insulating layer 112 and is covered by the insulating layer 113, and intersects with the connection wiring CA.

[0122] The insulating layer 114 included in the organic insulating layer IL is arranged on the insulating layer 113, and the insulating layer 12 is arranged on the insulating layer 114. In one example, the insulating layer 12 is thicker than the insulating layer 114. The insulating layer 12 is formed to have a stepped cross section. Such an insulating layer 12 having a stepped cross section is formed by adjusting the local exposure amount. In addition, the insulating layer 12 is retreated from the insulating layer 114. The inclined surface of the insulating layer 114 and the inclined surface of the insulating layer 12 overlap with the opening OPB. In this way, the organic insulating layer IL has a stepped cross section in the region overlapping with the opening OPB.

[0123] The protective layer PR is opposite to the connection wiring CB via the insulating layer 113 in the third direction Z, and overlaps with the insulating layer 113 exposed from the organic insulating layer IL at the opening OPB. Although not shown in the figure, at the overlapping portion of the connection wiring CA and the protective layer PR, the protective layer PR is also opposite to the connection wiring CA via the insulating layer 113 in the third direction Z, and overlaps with the insulating layer 113 exposed from the organic insulating layer IL at the opening OPB.

[0124] In the present embodiment, the protective layer PR includes a protective layer PR1 and a protective layer PR2 formed of a material different from that of the protective layer PR1. The protective layer PR2 is arranged on the protective layer PR1.

[0125] The protective layer PR1 is formed of a metal material such as molybdenum, tungsten, titanium, aluminum, etc. The protective layer PR1 is in contact with the insulating layer 113 and also in contact with the insulating layer 114. One end of the protective layer PR1 is located between the insulating layer 114 and the insulating layer 12, and the other end of the protective layer PR1 is located between the insulating layer 114 and the protective layer PR2.

[0126] The protective layer PR2 is formed of the same material as the lower electrode LE. The protective layer PR2 is in contact with the insulating layer 113, the protective layer PR1, and the insulating layer 12. One end of the protective layer PR2 is located between the insulating layer 12 and the insulating layer 5, and the other end of the protective layer PR2 is located between the insulating layer 113 and the insulating layer 5.

[0127] A plurality of peripheral partition walls 7 are arranged on the insulating layer 5 in the region overlapping with the organic insulating layer IL and the region (opening OPA) not overlapping with the organic insulating layer IL. Each peripheral partition wall 7 has a lower portion 71 arranged on the insulating layer 5 and an upper portion 72 arranged on the lower portion 71. Although not described in detail, the lower portion 71 is a multilayer body of a conductive layer formed of, for example, a titanium-based material and a conductive layer formed of, for example, an aluminum-based material, as is the lower portion 61. The upper portion 72 is a multilayer body of a thin film formed of, for example, a titanium-based material and a thin film formed of, for example, an oxide conductive material, as is the upper portion 62. The upper portion 72 has a greater width than the lower portion 71. Both ends of the upper portion 72 protrude from the side surfaces of the lower portion 71.

[0128] Like this, the peripheral wall 7 is Figure 3 The partition wall 6 shown is also cantilevered. The peripheral partition wall 7 can be formed in the same process as the partition wall 6. In this case, the lower portion 71 and the lower portion 61 are formed in the same process and from the same material, and the upper portion 72 and the upper portion 62 are formed in the same process and from the same material.

[0129] Next, a method for manufacturing the display device DSP will be described.

[0130] First, if Figure 8 As shown, a part of the circuit layer is formed on the substrate 10. That is, after the insulating layer 111 is formed on the substrate 10, a connection wiring CA (not shown here) is formed of a semiconductor on the insulating layer 111. Then, the insulating layer 112 is formed on the connection wiring CA and the insulating layer 111, and after the connection wiring CB is formed of a metal material on the insulating layer 112, the insulating layer 113 is formed on the connection wiring CB and the insulating layer 112.

[0131] Next, an organic insulating layer IL and a protective layer PR are formed.

[0132] First, if Fig. 9 As shown in FIG. 1 , an insulating layer 114 as a part of the organic insulating layer IL is formed on the insulating layer 113. The edge E13 is formed by patterning the insulating layer 114. Figure 6 As shown, the edge E13 is formed to have a sawtooth shape.

[0133] Then, if Fig.10 As shown in FIG. 1 , as a part of the protective layer PR, a protective layer PR1 intersecting the edge E13 is formed just above the connection wiring CB. The protective layer PR1 is in contact with the insulating layer 113 and extends above the insulating layer 114. Such a protective layer PR1 is formed by forming a metal layer on the insulating layer 113 and the insulating layer 114 and patterning the metal layer. The metal layer used to form the protective layer PR1 is, for example, a multilayer body in which a molybdenum-based metal layer is located between a pair of titanium-based metal layers.

[0134] Then, if Fig.11 As shown, an insulating layer 12 is formed as a part of the organic insulating layer IL. When the insulating layer 12 is patterned, a step-shaped cross section is formed by adjusting the exposure amount. One end of the protective layer PR1 is covered near the edge E12. The edge E12 is retreated from the edge E13. The opening OPA of the organic insulating layer IL is defined by the edge E13.

[0135] Then, if Fig.12 As shown, as a part of the protective layer PR, a protective layer PR2 crossing the edge portions E12 and E13 is formed just above the connection wiring CB. The protective layer PR2 is in contact with the insulating layer 113, overlaps with the protective layer PR1, and extends above the insulating layer 12. Such a protective layer PR2 is formed simultaneously with the lower electrode by forming a conductive layer for forming a lower electrode on the insulating layer 113 and the organic insulating layer IL and patterning the conductive layer. The conductive layer for forming the lower electrode is, for example, a multilayer body in which a silver-based reflective layer is located between a pair of transparent layers (ITO layers).

[0136] Like this, after reference Figures 9 to 12 The described steps form the organic insulating layer IL and the protective layer PR.

[0137] Next, if Fig.13 As shown, the insulating layer 5 is formed to cover the organic insulating layer IL and the protective layer PR. Then, the peripheral partition wall 7 having the lower portion 71 located on the insulating layer 5 and the upper portion 72 located on the lower portion 71 and protruding from the side surface of the lower portion 71 is formed.

[0138] Next, if Fig.14As shown in FIG. 1 , the insulating layer 5 is patterned to form an opening OPB overlapping with the edge portions E12 and E13. Thus, the edge portions E11 and E31 defining the opening OPB are formed. Figure 6 As shown, the edge portion E31 is formed to have a sawtooth shape.

[0139] Such insulating layers 111, 112, 113, 114, 12, and 5 are also formed in the panel portion.

[0140] Next, a method for manufacturing the display element in the panel portion will be described. Note that, in the drawings for describing the following manufacturing method, illustration below the insulating layer 12 is omitted.

[0141] like Fig.15 As shown, the lower electrode LE1 of the sub-pixel SP1, the lower electrode LE2 of the sub-pixel SP2, and the lower electrode LE3 of the sub-pixel SP3 are formed simultaneously with the protective layer PR2 as described above.

[0142] The partition wall 6 is formed simultaneously with the peripheral partition wall 7, and has a lower portion 61 located on the insulating layer 5 and an upper portion 62 located on the lower portion 61 and protruding from the side of the lower portion 61. That is, the lower portion 61 of the partition wall 6 is formed simultaneously with the lower portion 71 of the peripheral partition wall 7, and the upper portion 62 is formed simultaneously with the upper portion 72.

[0143] The openings AP1 , AP2 , and AP3 of the insulating layer 5 are formed simultaneously with the opening OPB.

[0144] It should be noted that the step of forming the openings AP1 , AP2 , AP3 , and OPB in the insulating layer 5 may be performed before forming the partition walls 6 and the peripheral partition walls 7 , or may be performed after forming the partition walls 6 and the peripheral partition walls 7 .

[0145] Next, the display element DE1 is formed.

[0146] First, if Fig.16As shown, a stacked film FL1 including an organic layer OR1, an upper electrode UE1 and a cap layer CP1 is formed. The process of forming the stacked film FL1 includes: a process of forming an organic layer OR1 in contact with the lower electrode LE1 at the opening AP1; a process of forming an upper electrode UE1 covering the organic layer OR1 and in contact with the lower portion 61 of the partition wall 6; and a process of forming a cap layer CP1 located on the upper electrode UE1. In addition, the process of forming the organic layer OR1 includes the process of forming a hole injection layer, a hole transport layer, an electron blocking layer, a light-emitting layer, a hole blocking layer, an electron transport layer, an electron injection layer, etc. respectively. The organic layer OR1, the upper electrode UE1 and the cap layer CP1 are respectively formed by vapor deposition using the partition wall 6 as a mask. That is, the organic layer OR1 including the light-emitting layer EM1, the upper electrode UE1 and the cap layer CP1 are sequentially formed on the lower electrode LE1 to form the stacked film FL1. The stacked film FL1 is partitioned into a plurality of parts by the cantilevered partition wall 6. The organic layer OR1 , the upper electrode UE1 , and the cap layer CP1 are continuously formed while maintaining a vacuum environment.

[0147] Then, an inorganic insulating material is deposited to form a sealing layer SE1 on the laminate film FL1. The sealing layer SE1 is formed by CVD (Chemical Vapor Deposition). The sealing layer SE1 continuously covers each partitioned portion of the laminate film FL1 and the partition wall 6.

[0148] Next, if Fig.17 As shown in FIG. 1 , a resist RS patterned into a predetermined shape is formed on the sealing layer SE1 . The resist RS overlaps the sub-pixel SP1 and a part of the partition wall 6 around it.

[0149] Next, if Fig.18 As shown, etching is performed using the resist RS as a mask, and the sealing layer SE1 and the laminated film FL1 exposed from the resist RS are removed in sequence. In this etching, after the sealing layer SE1 exposed from the resist RS is removed, the cap layer CP1 exposed from the sealing layer SE1 is removed, and further, after the upper electrode UE1 exposed from the cap layer CP1 is removed, the organic layer OR1 exposed from the upper electrode UE1 is removed. As a result, the lower electrode LE2 of the sub-pixel SP2 and the lower electrode LE3 of the sub-pixel SP3 are exposed.

[0150] Then, the resist RS is removed. Thus, the display element DE1 is formed in the sub-pixel SP1.

[0151] Next, if Fig.19As shown, the display element DE2 is formed. The steps for forming the display element DE2 are the same as the steps for forming the display element DE1. That is, an organic layer OR2 including a light-emitting layer EM2, an upper electrode UE2 and a cover layer CP2 are sequentially formed on the lower electrode LE2 to form a laminated film FL2. Then, a sealing layer SE2 is formed on the laminated film FL2. Then, a resist is formed on the sealing layer SE2, and the sealing layer SE2, the cover layer CP2, the upper electrode UE2 and the organic layer OR2 are patterned by etching using the resist as a mask. After the patterning, the resist is removed. Thus, the display element DE2 is formed in the sub-pixel SP2, and the lower electrode LE3 of the sub-pixel SP3 is exposed.

[0152] Next, if Fig. 20 As shown, a display element DE3 is formed. The steps for forming the display element DE3 are the same as the steps for forming the display element DE1. That is, an organic layer OR3 including a light-emitting layer EM3, an upper electrode UE3 and a cover layer CP3 are sequentially formed on the lower electrode LE3 to form a laminated film FL3. Then, a sealing layer SE3 is formed on the laminated film FL3. Then, a resist is formed on the sealing layer SE3, and the sealing layer SE3, the cover layer CP3, the upper electrode UE3 and the organic layer OR3 are patterned by etching using the resist as a mask. After the patterning, the resist is removed. Thus, a display element DE3 is formed in the sub-pixel SP3.

[0153] Then, form Figure 3 The mother substrate 100 is then cut along the cutting line CL, thereby completing the display device DSP. When the mother substrate 100 is cut along the cutting line CL, Figure 6 In the region 100A shown in FIG. 1 , the region on the inspection terminal TT side from the cutting line CL remains in the display device DSP. Figure 7 In the cross-sectional view shown, the area on the left side of the figure from the cutting line CL remains in the display device DSP.

[0154] It should be noted that, in the above manufacturing process, it is assumed that the display element DE1 is formed first, the display element DE2 is formed next, and the display element DE3 is formed last, but the order of forming the display elements DE1, DE2, and DE3 is not limited to this example.

[0155] As described above, by providing the insulating layer 5 with the opening OPB overlapping the edge of the organic insulating layer IL, local stress concentration near the edge E13 can be suppressed. Thus, it is possible to suppress the insulating layer 5 from floating from the organic insulating layer IL.

[0156] In addition, when the laminated film FL1 is formed, the laminated film FL1 is partially partitioned by the cantilevered peripheral partition wall 7. Compared with the case where the laminated film FL1 is not partitioned by the peripheral partition wall 7, the area of ​​the continuous laminated film FL1 is reduced, and the stress that can be generated in the laminated film FL1 is dispersed. In addition, the insulating layer 5 and the laminated film FL1 are pressed by the peripheral partition wall 7 and the sealing layer SE1. Therefore, it is possible to suppress the laminated film FL1 from floating from the insulating layer 5.

[0157] In addition, when the organic insulating layer IL has a stepped cross section whose thickness decreases toward the opening OPA, the formation of a steep step can be suppressed. The thinner the thickness of the organic insulating layer IL, the smaller the elongation. Therefore, when the stacked film FL1 is formed on the organic insulating layer IL, the strain of the stacked film FL1 is small, and the concentration of local stress in the stacked film FL1 can be suppressed. Therefore, when the stacked film FL1 is formed near the opening OPB, it is possible to suppress the stacked film FL1 from floating from the insulating layer 5 and the organic insulating layer IL.

[0158] Here, the following describes the undesirable conditions that may occur when the laminate film FL1 and the insulating layer 5 float or break from the substrate. The insulating layer 5 and the laminate film FL1 that have separated from the substrate become foreign matter and float in the manufacturing device, which may become a contamination source. In addition, if the floating foreign matter adheres to the processing substrate, it may cause various defects.

[0159] In contrast, according to the present embodiment, the detachment of the insulating layer 5 and the laminated film FL1 can be suppressed, thereby suppressing the contamination of the manufacturing equipment and the generation of unwanted foreign matter, thereby suppressing the reduction in reliability.

[0160] In addition, even when the laminated film FL1 is replaced with the laminated film FL2 for forming the display element DE2, or when the laminated film FL1 is replaced with the laminated film FL3 for forming the display element DE3, the same effect can be obtained.

[0161] However, in the region where the organic insulating layer IL does not exist, the insulating layers 111, 112, and 113, which are inorganic insulating layers of the same type as the insulating layer 5, are located directly under the insulating layer 5. Therefore, when the insulating layer 5 is dry-etched to form the opening OPB, there is a risk that the insulating layers 111, 112, and 113 are also removed.

[0162] Fig.21 It is a cross-sectional view for explaining a defect of a comparative example.

[0163] In the comparative example shown in the figure, the protective layer PR is not provided directly above the connection wiring CB. In this case, in the region where the organic insulating layer IL does not exist directly below the insulating layer 5, when the opening OPB is formed in the insulating layer 5, the opening OPC penetrating the insulating layers 111, 112, and 113 is formed, but there is a risk of the connection wiring CB also being penetrated.

[0164] When such an undesirable condition occurs, it will cause the connection wiring CB to be broken. Therefore, the conduction between the TEG terminal TG and the inspection terminal TT cannot be ensured, causing obstacles in the subsequent inspection process. In addition, although not shown in the figure, the connection wiring CA will also cause a break in the same way as the connection wiring CB. Therefore, during the manufacturing process, the function of the connection wiring CA as a short-circuit wiring (short-circuit ring) is impaired. Moreover, the connection wiring CA and the connection wiring CB are exposed at the opening OPC. Therefore, in the subsequent process, when the conductive material remains in the opening OPC, an unexpected short circuit occurs between the connection wiring CA and the connection wiring CB.

[0165] According to this embodiment, Figure 6 and Figure 7 As shown in FIG. 5 , the protective layer PR overlaps with the connection wiring CA and the connection wiring CB, respectively, and covers the insulating layer 113 located directly above these connection wirings. Therefore, when the opening OPB is formed in the insulating layer 5, the insulating layer 113 located directly above the connection wiring is protected, and the formation of the undesired opening OPC can be suppressed. Thus, the disconnection of the connection wiring and the exposure of the connection wiring from the insulating layer 113 can be suppressed. Therefore, the reduction in reliability can be suppressed.

[0166] In addition, the protective layer PR1 and the protective layer PR2 are formed of a material different from the inorganic insulating material, such as a semiconductor or a metal material. Therefore, in the dry etching process for processing the insulating layer 5, the protective layer PR functions as an etching stop layer. In addition, the protective layer PR2 is formed of a material different from the protective layer PR1, such as a material forming the lower electrode, and covers the protective layer PR1. Therefore, when the lower electrode is patterned, the protective layer PR1 is protected by the protective layer PR2.

[0167] In addition, if Figure 6 As shown, in a plan view, the connection wiring CA and the connection wiring CB in the region not overlapping the organic insulating layer IL are bent in a manner detouring from the peripheral partition wall 7. Therefore, even if the connection wiring is exposed, it will not overlap the peripheral partition wall 7, and the occurrence of an undesired short circuit through the peripheral partition wall 7 can be suppressed.

[0168] Next, the effect of the edge E13 and the edge E31 having the sawtooth shape will be described.

[0169] Fig. 22 This is a diagram for explaining one of the effects of this embodiment.

[0170] As shown on the left side of the figure, between the connection wiring CA and the connection wiring CB, the edge E13 and the edge E31 have a zigzag shape.

[0171] As shown on the right side of the figure, in the subsequent manufacturing process, when the conductive material RC remains along the edge E13, the conductive material RC is blocked by the tapered portion TP2. In addition, when the conductive material RC remains along the edge E31, the conductive material RC is blocked by the tapered portion TP1. Fig.21 As described above, even if the connection wiring CA and the connection wiring CB are exposed from the opening OPC, it is possible to suppress an undesired short circuit from occurring through the conductive material RC.

[0172] Fig.23 It is a cross-sectional view for explaining a defect of a comparative example.

[0173] As shown on the left side of the figure, between the connection wiring CA and the connection wiring CB, the edge E13 and the edge E31 are formed in a straight line shape.

[0174] As shown on the right side of the figure, in the subsequent manufacturing process, when the conductive material RC remains along the edge E13 and the edge E31, the conductive material RC is continuously formed between the connection wiring CA and the connection wiring CB. Fig.21 As described above, when the connection wiring CA and the connection wiring CB are exposed from the opening OPC, the connection wiring CA and the connection wiring CB are short-circuited via the conductive material RC.

[0175] Next, another configuration example of a DSP of a display device will be described.

[0176] Fig.24 FIG. 1 is a diagram showing another configuration example of the DSP of the display device.

[0177] and Figure 1 Compared with the configuration example shown, Fig.24 The display area DA is formed as a substantially circular area in the configuration example shown, but the substrate 10 is formed as a substantially arc-shaped outer shape. Figures 1 to 3 As described.

[0178] The peripheral area SA includes a plurality of mounting terminals MT. In the example shown in the figure, the substrate 10 has a linear substrate end 10E, and the plurality of mounting terminals MT are arranged along the substrate end 10E and arranged in the first direction X. It should be noted that, in the example shown in the figure, no mounting terminals MT are provided in the peripheral area SA. Figure 1 Inspection terminal TT shown.

[0179] The mounting terminal MT is a terminal electrically connected to a signal source such as a flexible printed circuit board or an IC chip, and is electrically connected to various wirings (scanning lines, signal lines, power lines, touch sensor wirings, etc.) in the display area DA. In addition, the mounting terminal MT is connected to the wiring LN extending toward the substrate end 10E.

[0180] Next, for one-time manufacturing Fig.24 A mother substrate 100 of a plurality of display devices DSP is shown for explanation.

[0181] Fig.25 1 is a plan view showing a configuration example of the mother substrate 100 .

[0182] The mother substrate 100 includes a plurality of panel portions PP and a margin portion MP on the outside of the panel portions PP on a large substrate 10. The large substrate 10 is formed in a rectangular shape, for example. In the example shown in the figure, two panel portions PP are shown as the plurality of panel portions PP, but more panel portions may be arranged in a matrix in the first direction X and the second direction Y.

[0183] The single-dot chain line in the figure is the first cutting line CL1, and the double-dot chain line in the figure is the final cutting line CL2. Each panel part PP is removed by cutting the mother substrate 100 along the first cutting line CL1 and then cutting it along the final cutting line CL2. Each panel part PP after removal is equivalent to Fig.24 The display panel PNL is shown.

[0184] The blank portion MP includes a test terminal TT and a TEG terminal TG. The test terminal TT is located between the primary cutting line CL1 and the final cutting line CL2. The TEG terminal TG is located outside the primary cutting line CL1.

[0185] The connection wiring CA is arranged in the blank portion MP to electrically connect adjacent test terminals TT. The connection wiring CB is arranged in the blank portion MP to electrically connect the TEG terminal TG and the test terminal TT. The connection wiring CN is arranged over the panel portion PP and the blank portion MP to electrically connect the test terminal TT and the mounting terminal MT.

[0186] Fig.26 1 is a plan view showing the substrate 10 after the mother substrate 100 is cut along the primary cutting line CL1 .

[0187] When the mother substrate 100 is cut along the primary cutting line CL1 , the substrate 10 is formed into a rectangular shape, and a part of the connection wiring CA remains on the substrate 10 as the wiring LA, and a part of the connection wiring CB remains on the substrate 10 as the wiring LB.

[0188] Then, when the mother substrate 100 is cut along the final cutting line CL2, a portion of the connection wiring CN is used as Fig.24 The wiring LN shown remains in the display panel PNL.

[0189] If the vicinity of the intersection of the connection wiring CN and the final cutting line CL2 is enlarged, Figure 6 Similarly to the example shown, each protective layer PR intersects with the edge portions E11, E12, E13, E31, E32, E23, E22, and E21, respectively, and overlaps with the connection wiring CN. In addition, between adjacent connection wirings CN, the edge portions E13, E31, E23, and E32 are bent in a sawtooth shape. Therefore, the same effect as the above-mentioned configuration example can be obtained.

[0190] In the above-mentioned embodiment, for example, a portion of the wiring LA or the connecting wiring CA, a portion of the wiring LB or the connecting wiring CB, and a portion of the wiring LN or the connecting wiring CN are equivalent to a plurality of wirings. In addition, a portion of the wiring LA or the connecting wiring CA is equivalent to the first wiring, and a portion of the wiring LB or the connecting wiring CB is equivalent to the second wiring.

[0191] The insulating layer 113 corresponds to the first inorganic insulating layer, and the insulating layer 5 corresponds to the second inorganic insulating layer. The insulating layer 114 corresponds to the first layer of the organic insulating layer IL, and the insulating layer 12 corresponds to the second layer of the organic insulating layer IL.

[0192] In the protective layer PR, the protective layer PR1 corresponds to the first protective layer, and the protective layer PR2 corresponds to the second protective layer. In the peripheral partition wall 7, the lower portion 71 corresponds to the first lower portion, and the upper portion 72 corresponds to the first upper portion. In the partition wall 6, the lower portion 61 corresponds to the second lower portion, and the upper portion 62 corresponds to the second upper portion.

[0193] As described above, according to the present embodiment, it is possible to provide a display device capable of suppressing a decrease in reliability and a method for manufacturing the same.

[0194] Based on the display device and the manufacturing method thereof described above as the embodiments of the present invention, any display device and the manufacturing method thereof that can be implemented by appropriately designing and modifying by a person skilled in the art also belongs to the scope of the present invention as long as it includes the gist of the present invention.

[0195] Within the scope of the present invention, those skilled in the art can think of various variations, which also belong to the scope of the present invention. For example, embodiments obtained by adding, deleting or designing the above-mentioned embodiments appropriately by those skilled in the art, or embodiments obtained by adding, omitting or changing the conditions of the processes are included in the scope of the present invention as long as they have the gist of the present invention.

[0196] In addition, other effects brought about by the methods described in the above-mentioned embodiments, effects that are clear based on the records in this specification, or effects that can be appropriately thought of by those skilled in the art should of course be understood as effects brought about by the present invention.

Claims

1. A display device comprising: substrate; a first inorganic insulating layer disposed above the substrate over a display region where an image is displayed and a peripheral region outside the display region; an organic insulating layer, disposed on the first inorganic insulating layer; a lower electrode, which is arranged on the organic insulating layer in the display area; an organic layer, which is disposed on the lower electrode and includes a light-emitting layer; An upper electrode, which is disposed on the organic layer; a second inorganic insulating layer disposed on the organic insulating layer and having an opening in the peripheral region for exposing an edge of the organic insulating layer; a plurality of wirings disposed between the substrate and the first inorganic insulating layer and intersecting the edge portion in a plan view; and A plurality of protective layers intersecting the edge portion when viewed from above, One of the protective layers faces one of the wirings, and the one of the protective layers overlaps the first inorganic insulating layer exposed from the organic insulating layer at the opening.

2. The display device according to claim 1, further comprising: A mounting terminal is disposed in the peripheral area and electrically connected to the signal source; and an inspection terminal which is electrically connected to the mounting terminal, At least one of the wirings is connected to the inspection terminal.

3. The display device according to claim 2, wherein: The plurality of wirings include a first wiring formed of a semiconductor and a second wiring formed of a metal material.

4. The display device according to claim 3, wherein: The first wiring and the second wiring are connected to the same inspection terminal, In a plan view, an edge portion of the organic insulating layer and an edge portion of the second inorganic insulating layer face each other and have a zigzag shape between the first wiring and the second wiring.

5. The display device according to claim 1, wherein: The protective layer comprises: a first protective layer formed of a metal material and in contact with the first inorganic insulating layer; and The second protective layer is formed of the same material as the lower electrode and is disposed on the first protective layer.

6. The display device according to claim 5, wherein: The organic insulating layer has: a first layer disposed on the first inorganic insulating layer; and a second layer, which is arranged on the first layer, The first protective layer has one end portion located between the first layer and the second layer and the other end portion located between the first inorganic insulating layer and the second protective layer. The second protective layer has one end portion located between the second layer and the second inorganic insulating layer and the other end portion located between the first inorganic insulating layer and the second inorganic insulating layer.

7. The display device according to claim 1, wherein: The organic insulating layer has a stepped cross-section with a reduced thickness in a region overlapping the opening.

8. The display device according to claim 1, further comprising a plurality of peripheral partition walls arranged in the peripheral area, Each of the plurality of peripheral partition walls has a first lower portion disposed on the second inorganic insulating layer and a first upper portion disposed on the first lower portion and protruding from a side surface of the first lower portion. The wiring in a region not overlapping with the organic insulating layer is bent so as to detour from the peripheral partition wall in a plan view.

9. The display device according to claim 8, further comprising a partition wall in the display region, the partition wall having a second lower portion disposed on the second inorganic insulating layer and formed of a conductive material and a second upper portion disposed on the second lower portion and protruding from a side surface of the second lower portion, The second lower portion is formed of the same material as the first lower portion, The second upper portion is formed of the same material as the first upper portion, The lower electrode, the organic layer and the upper electrode are surrounded by the partition wall. The upper electrode is in contact with the second lower portion of the partition wall.

10. The display device according to claim 9, further comprising: a cap layer disposed on the upper electrode and surrounded by the partition wall; and a sealing layer, which is formed of an inorganic insulating material and is disposed on the cover layer, An end portion of the sealing layer is located on the partition wall.

11. A method for manufacturing a display device, wherein: A wiring is formed on the substrate. forming a first inorganic insulating layer on the wiring, forming an organic insulating layer on the first inorganic insulating layer, forming a lower electrode on the organic insulating layer, forming a protective layer that faces the wiring and overlaps the first inorganic insulating layer exposed from the organic insulating layer, forming a second inorganic insulating layer covering the organic insulating layer and the protective layer, forming an opening in the second inorganic insulating layer so as to overlap with an edge of the organic insulating layer, forming an organic layer on the lower electrode, An upper electrode is formed on the organic layer.

12. The method for manufacturing a display device according to claim 11, wherein: The wiring is formed of a semiconductor or a metal material.

13. The method for manufacturing a display device according to claim 11, wherein: When the organic insulating layer is formed, the edge of the organic insulating layer is formed to have a sawtooth shape, When the opening is formed in the second inorganic insulating layer, an edge portion of the second inorganic insulating layer facing an edge portion of the organic insulating layer is formed to have a zigzag shape.

14. The method for manufacturing a display device according to claim 11, wherein: The process of forming the organic insulating layer includes: forming a first layer on the first inorganic insulating layer; and forming a second layer on the first layer, The process of forming the protective layer includes: Before forming the second layer, forming a first protective layer that is in contact with the first inorganic insulating layer and extends onto the first layer; and After forming the second layer, a step of forming a second protective layer overlapping the first protective layer and extending onto the second layer.

15. The method for manufacturing a display device according to claim 14, wherein: The first protective layer is formed of a metal material, The second protection layer and the lower electrode are formed of the same material.

16. The method for manufacturing a display device according to claim 11, wherein: Further, forming a peripheral partition wall having a first lower portion located on the second inorganic insulating layer and a first upper portion located on the first lower portion and protruding from a side surface of the first lower portion, forming a partition wall having a second lower portion located on the second inorganic insulating layer and a second upper portion located on the second lower portion and protruding from a side surface of the second lower portion, The first lower portion and the second lower portion are formed of the same material in the same process, The first upper portion and the second upper portion are formed of the same material in the same process.

17. The method for manufacturing a display device according to claim 16, wherein: Furthermore, a cap layer is formed on the upper electrode. The organic layer, the upper electrode, and the cap layer are formed by vapor deposition using the partition wall as a mask.

18. The method for manufacturing a display device according to claim 17, wherein: Further, A sealing layer is formed on the cap layer from an inorganic insulating material, forming a resist patterned into a predetermined shape on the sealing layer, Etching is performed using the resist as a mask to remove the sealing layer, the cap layer, the upper electrode, and the organic layer exposed from the resist.

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