Improved method and apparatus for semiconductor inspection image segmentation

Abstract

A method of segmenting an image using anchor features is provided. The method is more flexible and durable than conventional segmentation methods, and requires less user interaction. The method can also be applied to semiconductor features with poor image contrast by using previous cognition. With a system incorporating a new method, inspection work of semiconductor objects of interest is improved, and training data for training a machine learning method may be provided.

Description

Technical Field

[0001] The present invention relates to a method for pattern measurement of semiconductor objects in a semiconductor wafer, and more specifically, to a method for performing segmentation of an inspection image of a semiconductor object of interest, a computer program product, and a corresponding semiconductor inspection device. The semiconductor inspection device and method of the present invention can improve the inspection work of the semiconductor object of interest, or can provide training data for training a machine learning method for wafer inspection. The method, computer program product, and semiconductor inspection device can be used for different inspection tasks, such as quantitative metrology, defect detection, process monitoring, or defect review of integrated circuits in a semiconductor wafer. Background Art

[0002] Semiconductor structures are among the finest man-made structures. Semiconductor manufacturing involves precise manipulation of materials such as silicon or oxides at very fine scales in the nm range, such as photolithography or etching. Wafers made of thin slices of silicon serve as substrates for microelectronic devices, which contain semiconductor structures built in and on the wafer. Semiconductor structures are built layer by layer using repeated processing steps involving repeated chemical, mechanical, thermal and optical processes. The size, shape and layout of semiconductor structures and patterns are subject to multiple influences. For example, during the manufacture of 3D memory devices, the key processes are currently etching and deposition. Other involved process steps, such as photolithography exposure or implantation, also have an impact on the characteristics of the integrated circuit elements. As a result, the manufactured semiconductor structures have rare and different defects. Devices for quantitative metrology, defect detection or defect review are looking for these defects. These devices are not only needed in wafer manufacturing. Since this process is complex and highly nonlinear, the optimization of production process parameters is difficult. As a remedy, an iterative approach called process window qualification (PWQ) can be applied. In each iteration, test wafers are manufactured according to the current best process parameters, with different dies of the wafer exposed to different manufacturing conditions. The best process parameters can be selected by inspecting and analyzing the test structures using devices for quantitative metrology and defect detection. In this way, the production process parameters can be adjusted to achieve the best conditions. After this, high-precision quality control processes and devices are required for metrology of semiconductor structures in the wafer.

[0003] The manufactured semiconductor structure is based on prior knowledge. The semiconductor structure is manufactured by a series of layers parallel to the substrate. For example, in a logic type sample, the metal lines are parallel to the metal layer or HAR (high aspect ratio) structure, and the metal vias are perpendicular to the metal layer. The angle between the metal lines in different layers is 0° or 90°. On the other hand, for the VNAND type structure, it is known that its cross section is spherical on average. In addition, the semiconductor wafer has a diameter of 300 mm and consists of a plurality of locations (so-called bare cores), each of which contains at least one integrated circuit pattern, such as, for example, for a memory chip or for a processor chip. During manufacturing, the semiconductor wafer undergoes about 1000 process steps to form about 100 and more parallel layers in the semiconductor wafer, including transistor layers, layers between lines and interconnect layers, and in memory devices, multiple 3D arrays of memory cells.

[0004] The aspect ratio and number of layers of integrated circuits are increasing, and the structures are growing towards the third (vertical) dimension. The current height of memory stacks exceeds tens of microns. In contrast, feature sizes are getting smaller. The minimum feature size or critical dimension is actually below 10nm, such as 7nm or 5nm, and will approach below 3nm in the near future. Although the complexity and size of semiconductor structures are growing in the third dimension, the lateral dimensions of integrated semiconductor structures are getting smaller. Therefore, it becomes challenging to measure the shape, size and orientation of 3D features and patterns and their overlap with high precision. The lateral measurement resolution of charged particle systems is usually limited by the sampling grating of each image point or the residence time of each pixel on the sample and the diameter of the charged particle beam. The sampling grating resolution can be set in the imaging system and can be adapted to the diameter of the charged particle beam on the sample. The typical grating resolution is 2nm or less, but the grating resolution limit can be reduced without physical limitations. The charged particle beam diameter has a limited size, which depends on the operating conditions and lens of the charged particle beam. The beam resolution is limited by about half of the beam diameter. The lateral resolution can be lower than 2nm, for example even lower than 1nm.

[0005] A common method for generating nanoscale 3D tomographic data from semiconductor samples is the so-called slicing and imaging method, such as obtained by a dual-beam device. The slicing and imaging method is described in WO 2020 / 244795A1, according to which a 3D volume inspection is obtained at an inspection sample extracted from a semiconductor wafer. In another example, the slicing and imaging method is applied to the surface of a semiconductor wafer at an inclined angle, as described in WO 2021 / 180600 A1. According to this method, a 3D volume image of the inspection volume is obtained by slicing and imaging multiple cross sections within the inspection volume. For precise measurement, a large number of N cross sections are generated in the inspection volume, where N exceeds 100 or even more image slices. For example, in a volume with a lateral dimension of 5 μm and a slice distance of 5 nm, 1000 slices are milled and imaged. For a typical sample of multiple HAR structures with a spacing of, for example, 70 nm, there are approximately 5,000 HAR structures in a field of view, and a total of more than 5 million cross-sections of HAR structures are generated. In order to reduce the huge amount of computation required to extract the required measurement results, some improvements are proposed. WO 2021 / 180600 A1 illustrates some methods using reduced image slicing. In one example, the method applies prior information.

[0006] An important task in semiconductor inspection is to determine a set of specific parameters of semiconductor objects, such as high aspect ratio (HAR) - structures within the inspection volume. These parameters are, for example, size, area, shape or other measurement parameters. Typically, the measurement work of the prior art involves multiple computational steps, like object detection, feature extraction and any type of metrology operation, such as calculating distance, radius or area based on the extracted features. Each of these many steps requires a lot of computational work.

[0007] Generally, semiconductors contain many repetitive three-dimensional structures. During process or technology development, some selected physical or geometric parameters of representative multiple three-dimensional structures must be measured with high accuracy and high throughput. In order to monitor manufacturing, an inspection volume is defined, containing representative multiple three-dimensional structures. This inspection volume is then analyzed, for example, by slicing and imaging methods, resulting in a high-resolution 3D volume image of the inspection volume.

[0008] The multiple repetitive three-dimensional structures within the examination volume may exceed hundreds or even thousands of individual structures. As a result, a large number of cross-sectional images are generated, for example, at least 100 three-dimensional semiconductor objects of interest are investigated by, for example, 100 cross-sectional image slices, so that the number of cross-sectional image segments of the semiconductor objects of interest to be detected can easily reach 10,000 or more. In order to minimize the measurement time, the image acquisition time of the charged particle beam device can be reduced as much as possible, but at the expense of a higher noise level, making the object detection more difficult and prone to errors.

[0009] Machine learning is a field of artificial intelligence. Machine learning algorithms are usually based on training data consisting of a large number of training samples to build machine learning models. After training, the algorithm is able to generalize the knowledge gained from the training data to new samples that have not been encountered before, thereby making predictions about new data. There are many machine learning algorithms, such as linear regression k-means or neural networks. For example, deep learning is a type of machine learning that uses an artificial neural network with many hidden layers between the input layer and the output layer. Due to this extensive internal structure, the network is able to gradually extract higher-level features from the original input data. Each level learns to transform its input data into a slightly more abstract and complex representation, thereby obtaining low-level and high-level knowledge from the training data. The hidden layers can have different sizes and work, such as convolutional layers or pooling layers. Machine learning is often applied to object detection or object classification during semiconductor inspection. For example, a machine learning algorithm is trained to detect features of semiconductor objects of interest in cross-sectional image segments. Training data usually requires many images of identified and segmented cross-sectional images, such as images with pixel-by-pixel annotations.

[0010] Typical machine learning algorithms require a large amount of training data to be generated, including a lot of interaction from an operator or user. Users need to annotate a large number of images with annotation tags in order to successfully train the machine learning algorithm. This is rarely feasible due to the large amount of annotation work. A recent example of training data for generating inspection work for semiconductor objects of interest is shown in U.S. Application No. 17 / 701,054, filed on March 22, 2022, which is incorporated herein by reference. A method according to U.S. Application No. 17 / 701,054 utilizes a parametric description of a semiconductor object of interest, and a method for adjusting the parametric description to adapt to a cross-sectional image measured for the semiconductor object of interest.

[0011] It is an object of the present invention to provide an efficient method to perform segmentation and annotation of large data sets of cross-sectional images of semiconductor objects of interest. It is an object of the present invention to provide a method of segmentation and annotation that is more robust to imaging noise or low image contrast. It is another object of the present invention to improve the prior art methods for segmenting and annotating HAR channels. It is another object of the present invention to reduce the amount of user interaction during segmentation and annotation. In general, it is an object of the present invention to provide a wafer inspection system for inspecting semiconductor structures in an inspection volume with high throughput and high accuracy. It is an object of the present invention to provide a wafer inspection method for measuring semiconductor structures in an inspection volume that can be quickly adapted to changes in the measurement work, the measurement system, or changes in the semiconductor object of interest. Summary of the invention

[0012] The objectives are solved by the present invention. The invention is described by the claims and the details are provided by specific embodiments and examples. The present disclosure provides an improved method for performing segmentation and annotation of a large data set of cross-sectional images of a semiconductor object of interest. The present disclosure provides an inspection system configured to perform an improved segmentation and annotation method. The improved segmentation and annotation method is more robust to imaging noise or low image contrast. In one example, a method for segmenting and annotating a HAR channel is provided. The amount of user interaction is reduced by the improved segmentation and annotation method. The present disclosure provides a wafer inspection system for inspecting semiconductor structures in an inspection volume with high throughput and high accuracy, and a wafer inspection method for inspecting semiconductor structures in an inspection volume, which can quickly adapt to changes in inspection work, inspection systems, or changes in semiconductor objects of interest.

[0013] According to a specific embodiment, a method for extracting a contour of a semiconductor object of interest comprises the step of selecting a first feature of the semiconductor object of interest as an anchor feature. The method further comprises the step of defining a transfer property from the first contour of the anchor feature to a second contour of a second feature of the semiconductor object of interest. The method further comprises the step of obtaining at least one cross-sectional image or image segment, which comprises at least one cross section of the semiconductor object of interest. The method further comprises the step of generating a first contour of the anchor feature in the cross-sectional image, and the step of determining a second contour from the first contour using the transfer property. Thus, even if the image noise is very large or the second feature is imaged with low imaging contrast, the second contour can be determined with improved accuracy. By selecting the anchor feature to provide, for example, a large image contrast during imaging, or by selecting the anchor feature as a clearly detectable semiconductor feature of interest, the detection of the first feature of the semiconductor object of interest is ensured. The first contour can be transferred to a second or further contour of the semiconductor object of interest using predefined transfer properties, for example derived from CAD data. By selecting the anchor feature as a feature of the semiconductor object of interest having high image contrast and large edge slope, a first profile of a first or anchor feature can be stably determined and transferable to a second profile of a second or further feature.

[0014] In one example, the generation of the first contour comprises generating an initial contour proposal from the cross-sectional image by image processing, the image processing comprising at least one component of the group consisting of intensity calibration, threshold operation, calculation of intensity gradient, or calculation of NILS. In one example, the generation of the first contour comprises modifying the initial contour proposal by image processing, the image processing comprising at least one component of the group consisting of smoothing, interpolation, contour closure, contour vector extraction, or active contour model. The image processing may be based on prior knowledge of the contour shape of the anchor feature.

[0015] In one example, the transfer attribute used to determine the second contour includes at least one member of the group consisting of scaling, anisotropic scaling, deformation operation, displacement, rotation, shearing, or template scaling. The step of determining the second contour may further include an image processing, the image processing including at least one member of the group consisting of smoothing, interpolation, contour closure, contour vector extraction, or active contour modeling. Template scaling relies on prior knowledge of the shape of the semiconductor object of interest, wherein the second contour is predefined as a template with predefined scaling attributes, such as scaling relative to the diameter or area of ​​the first contour of the anchor feature.

[0016] In one example, the method further comprises detecting at least one instance of a semiconductor object of interest within the cross-sectional image by a method comprising means from the group consisting of template matching, threshold processing, or correlation techniques. The method may further comprise at least one means from the group consisting of registration, distortion correction, magnification adjustment, depth map calculation, contrast enhancement, and noise filtering of the cross-sectional image.

[0017] In one example, a method for iteratively repeating contour extraction includes repeatedly acquiring cross-sectional images, generating a plurality of first contours, and determining a plurality of second contours from the plurality of first contours using transfer attributes. At least one cross-sectional image with the determined contours can be annotated with pixel values ​​according to the plurality of first and second contours and used for training an object detector. Thus, a large amount of training data can be generated with reduced user interaction, and the acquisition speed of cross-sectional images can be increased with increased noise levels.

[0018] In one example, the method of contour extraction includes determining an attribute of the second feature. The attribute may be at least one member of the group consisting of diameter, area, center of gravity, shape deviation, eccentricity, and distance. Thus, measurement work or defect detection can be achieved with less user interaction and at a faster speed of cross-sectional image acquisition with an increased noise level.

[0019] In a second embodiment, a wafer inspection system is provided. The wafer inspection system includes a dual beam system and an operation control unit, the unit including at least one processing engine and a memory. The processing engine is configured to execute software instructions stored in the memory, including instructions according to the method of the first embodiment. In one example, the wafer inspection system further includes an interface unit and a user interface, which are configured to receive, display, transmit or store information, the information including the selection and transfer properties of the anchor feature of the semiconductor object of interest.

[0020] A wafer inspection system for performing semiconductor object inspection tasks includes the following features: an imaging device adapted to provide at least one cross-section of a wafer; a graphical user interface configured to present data to a user and obtain input data from the user; one or more processing devices; one or more machine-readable hardware storage devices containing instructions executable by the one or more processing devices to perform operations including one of the plurality of methods disclosed herein. The present invention also relates to one or more machine-readable hardware storage devices containing instructions executable by the one or more processing devices to perform operations according to a first specific embodiment.

[0021] In one example, the dual beam system comprises a focused ion beam (FIB) system and a charged particle beam imaging system, which are configured at an angle such that during use, the focused ion beam and the charged particle beam form an intersection. The dual beam system is configured such that during use, at least one cross-sectional image is formed through an inspection volume of a wafer at a tilt angle GF relative to a wafer surface. Preferably, the dual beam system is configured for a slicing and imaging generation process at a wafer with a wedge-cut geometry, wherein the tilt angle GF is less than 45°, such as 30° or even less.

[0022] By using the system and method according to the first or second specific embodiment, the wafer inspection of the semiconductor object inside the inspection volume has high throughput, high accuracy and reduced damage to the wafer. Further, the wafer inspection work of the semiconductor object of interest can be quickly adapted to changing situations, such as changes in measurement work, changes in the charged particle beam imaging system, or changes in the semiconductor object of interest itself. Therefore, a general wafer inspection method with high flexibility is provided. The method and system can be used for defect detection, process monitoring, defect review, quantitative measurement and inspection of integrated circuits in semiconductor wafers.

[0023] Although examples and specific embodiments are described in the example of a semiconductor wafer, it should be understood that the present invention is not limited to semiconductor wafers, but may also be applied, for example, to reticles or masks for semiconductor manufacturing. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The present invention described by examples and specific embodiments is not limited to the specific embodiments and examples, but can be implemented by those skilled in the art through various combinations or modifications thereof. The present invention will be even better understood with reference to the following figures:

[0025] Figure 1 Diagram showing a wafer inspection or metrology system using a dual beam apparatus for 3D volume inspection.

[0026] Figure 2 Schematic representation of the slicing and imaging method for intra-wafer volume inspection.

[0027] Figure 3 An example of obtaining a cross-sectional image by the slicing and imaging method is illustrated.

[0028] Figure 4 is a diagram of a method according to a specific embodiment.

[0029] Figure 5a , Figure 5b , Figure 5c Illustrate a cross section through a semiconductor object of interest.

[0030] Figures 6a to 6e The results of some method steps according to a specific embodiment are illustrated.

[0031] Figures 7a to 7d Figure 6 shows the noise-free result.

[0032] Figure 8a , Figure 8b Another example of a method according to a specific embodiment is illustrated.

[0033] Figures 9a to 9d Another example of a method according to a specific embodiment is illustrated.

[0034] Fig.10 An inspection method is described as an example.

[0035] Fig.11a , Fig.11b Displays a check result.

[0036] Fig.12 An inspection system according to a specific embodiment is shown. DETAILED DESCRIPTION

[0037] Throughout the drawings and description, like reference numerals are used to describe like features or components.A coordinate system is selected in which the wafer surface 55 coincides with the XY plane.

[0038] Recently, in order to study the 3D inspection volume in a semiconductor wafer, a slicing and imaging method suitable for the inspection volume inside the wafer has been proposed. Thus, a 3D volume image is generated at the inspection volume inside the wafer in a so-called "wedge cutting" method or a wedge cutting geometry without removing the sample from the wafer. The slicing and imaging method is suitable for inspection volumes with a size of several microns, such as 5 to 10 microns in a lateral extension in a wafer with a diameter of 200 mm or 300 mm. The lateral extension can also be larger, reaching tens of microns. A V-shaped groove or edge is milled in the top surface of the integrated semiconductor wafer so that a cross section at an angle to the top surface can be accessed. The 3D volume image of the inspection volume is acquired at a limited number of inspection positions, such as a representative position of a bare core, such as at a process control monitor (PCM), or at a position identified by other inspection tools. The slicing and imaging method will only locally destroy the wafer, and other bare cores can still be used, or the wafer can still be used for further processing. The method and inspection system generated according to the 3D volume image are described in WO 2021 / 180600 A1, which is incorporated herein by reference in its entirety. Figure 1An example of a wafer inspection system 1000 for 3D volume inspection is illustrated. The wafer inspection system 1000 is configured for performing a slicing and imaging method under a wedge-cutting geometry using a dual-beam device 1. For a wafer 8, a plurality of inspection positions are defined in a position map or inspection list generated by an inspection tool or design information, including inspection positions 6.1 and 6.2. The wafer 8 is placed on a wafer support table 15. The wafer support table 15 is mounted on a platform 155 with actuators and position control. Actuators and components for precise control of the wafer stage, such as laser interferometers, are known in the art. A control unit 16 is configured to control the wafer stage 155 and adjust the inspection position 6.1 of the wafer 8 at the intersection 43 of the dual-beam device 1. The dual-beam device 1 includes a FIB column 50 having a FIB optical axis 48 and a charged particle beam (CPB) imaging system 40 having an optical axis 42. At the intersection 43 of the two optical axes of the FIB and the CPB imaging system, the wafer surface 55 is configured to be at an inclination angle GF with the FIB axis 48. The FIB axis 48 and the CPB imaging system axis 42 include an angle GFE, and the CPB imaging system axis forms an angle GE with the normal to the wafer surface 55. Figure 1 In the coordinate system of , the normal to the wafer surface 55 is given by the z-axis. A focused ion beam (FIB) 51 is generated by a FIB column 50 and impinges on the surface 55 of the wafer 8 at an angle GF. By ion beam milling at the inspection position 6.1, an inclined cross-sectional surface is milled into the wafer at approximately an inclined angle GF. Figure 1 In the example of FIG. 4 , the tilt angle GF is about 30°. Due to the beam divergence of a focused ion beam (e.g., a gallium ion beam), the actual tilt angle of the tilted cross-sectional surface may deviate from the tilt angle GF by 1° to 4°. An image of the milled surface is obtained using a charged particle beam imaging system 40 tilted at an angle GE relative to the wafer normal. Figure 1 In the example of , the angle GE is about 15°. However, other configurations are possible, such as GE=GF, such that the CPB imaging system axis 42 is perpendicular to the FIB axis 48, or GE=0°, such that the CPB imaging system axis 42 is perpendicular to the wafer surface 55.

[0039] During imaging, a beam of charged particles 44 is scanned by a scanning unit of a charged particle beam imaging system 40 along a scanning path over the cross-sectional surface of the wafer at the inspection position 6.1 and secondary particles as well as scattered particles are generated. A particle detector 17 collects at least some of the secondary particles and scattered particles and communicates the particle count to a control unit 19. Detectors of other interaction products may also be present. The control unit 19 controls the charged particle beam imaging column 40 of the FIB column 50 and is connected to the control unit 16 to control the position of the wafer 8 mounted on the wafer support table 15 via the wafer stage 155. The control unit 19 communicates with the operation control unit 2, which triggers, for example, placement and alignment of the inspection position 6.1 of the wafer 8 at the intersection 43 via wafer stage movement and repeatedly triggers the operations of FIB milling, image acquisition and stage movement.

[0040] Each new interaction surface is milled by the FIB beam 51 and imaged by the charged particle imaging beam 44, which is, for example, a scanning electron beam or a helium ion beam of a helium ion microscope (HIM). In one example, the dual beam system includes a first focused ion beam system 50 configured at a first angle GF1 and a second focused ion column configured at a second angle GF2, and the wafer is rotated between milling at the first angle GF1 and milling at the second angle GF2 while imaging is performed by the imaging charged particle beam column 40, which is, for example, configured perpendicular to the wafer surface 55.

[0041] Figure 2 Shows the wedge-cut geometry in a 3D memory stack example. Figure 2 The case is illustrated when the surface 52 is a new cross-sectional surface that was last milled by the FIB 51. The cross-sectional surface 52 is scanned, for example, by the SEM beam 44, which is Figure 2In the example of , the FIB beam 51 is configured to be incident perpendicularly to the wafer surface 55 and to produce high-resolution cross-sectional image slices. The cross-sectional surfaces 53.1 ... 53.N are then milled with the FIB beam 51 at an angle GF of about 30° to the wafer surface 9, but other angles GF may also be used, for example between GF = 20° and GF = 60°. The cross-sectional image slices include first cross-sectional image features formed by intersections with high aspect ratio (HAR) structures or vias (such as first cross-sectional image features of HAR structures 4.1, 4.2 and 4.3) and second cross-sectional image features formed by intersections with layers L.1 ... LM (including, for example, SiO2, SiN- or tungsten lines). Some lines are also referred to as "word lines". The maximum number of layers M is typically greater than 50, for example greater than 100 or even greater than 200. The HAR structures and layers extend throughout most of the volume in the wafer, but may include gaps. The HAR structures typically have a diameter below 100 nm, for example about 80 nm, or for example 40 nm. Thus, the cross-sectional image slices contain first cross-sectional image features as intersections or cross-sections of the HAR structure at different depths (Z) corresponding to the XY positions. In the case of a cylindrical vertical memory HAR structure, the first cross-sectional image features obtained are circular or elliptical structures at different depths determined by the location of the structure on the inclined cross-sectional surface 52. The memory stack extends in the Z direction perpendicular to the wafer surface 55. The thickness d or the minimum distance d between two adjacent cross-sectional image slices is adjusted to a value that is typically on the order of a few nm, such as 30 nm, 20 nm, 10 nm, 5 nm, 4 nm or even less. Once the material layer of a predetermined thickness d is removed using the FIB, the next cross-sectional surface 53.i...53.J is exposed and can be used for imaging using the charged particle imaging beam 44. During repeated milling imaging, multiple cross-sections are formed and multiple cross-sectional images are obtained, so that an inspection volume of size LX×LY×LZ is appropriately sampled, and a 3D volume image can be generated, for example. Therefore, damage to the wafer is limited to the inspection volume plus a damage volume of length LYO in the y direction. When the inspection depth LZ is about 10 μm, the additional damage volume in the y direction is usually limited to less than 20 μm.

[0042] Figure 3 An example of a cross-sectional image slice 311 corresponding to the cross-sectional surface 52 generated by the imaging charged particle beam 44 is shown. The cross-sectional image slice 311 includes an edge line 315 at the edge coordinate y1 between the oblique cross section and the wafer surface 55. Up to the edge, the image slice 311 shows a number of cross sections 307.1 ... 307.S through the HAR structure, which intersect the cross-sectional surface 52. In addition, the image slice 311 includes cross sections of a plurality of word lines 313.1 to 313.3 at different depths or z positions. Using these word lines 313.1 to 313.3, a depth map Z of the oblique cross-sectional surface 52 can be generated.1 (x,y).

[0043] According to a first specific embodiment, a fast and robust method for performing segmentation and annotation of a cross-sectional image of a semiconductor object of interest is provided. For example, the semiconductor object of interest is a HAR structure of a NAND device, whose cross-section is 307.1 ... 307.S, such as Figure 3 For example, segmentation and annotation are needed to produce annotated training image data to train a machine learning method to detect and attribute new instances of cross sections of semiconductor objects of interest in, for example, routine inspection work.

[0044] A typical method for performing inspection work is to use a two-step method. This two-step method is disclosed in the international patent application PCT / EP2022 / 057656 with priority on April 21, 2021, which is incorporated herein by reference. In the first step, a new instance of a cross section of a semiconductor object of interest is detected by a first machine learning method, which has been trained by training image data with annotations. The first machine learning method is sometimes also referred to as an object detector. In the second step, the detected instance of the cross section of the semiconductor object of interest is analyzed, for example, by image processing (including performing measurements) or a second machine learning method (for example, by training to classify defects or deviations). The method according to the first specific embodiment improves the step of generating training data for the first machine learning method or the object detector. As the method for generating training data for the object detector is improved, the wafer inspection method is generally improved. However, the proposed improved segmentation method is not limited to the case where training data for the object detector must be generated. This result segmentation method can also be directly applied to the measurement work of defect inspection work.

[0045] The method according to the first specific embodiment comprises a two-step solution for generating the contour of the feature of interest. First, a first contour corresponding to the distinct edges of the anchor feature is extracted using standard methods. Secondly, the second contour of the feature of interest is generated using the first contour. The method calls for known transfer properties between the first contour of the anchor feature and the second contour proposal. Finally, the second contour proposal is refined around the feature of interest. Prior knowledge about the geometry of, for example, repeated features can be used to generate the second contour proposal based on the position of any detected portion of the feature of interest. For example, if the position of the feature of interest or any portion thereof is determined by an object detection method (e.g., by cross-correlation with a template), the second contour proposal can be generated based solely on the determined feature centroid. Figure 4An example of a method according to a first specific embodiment is shown. A method for extracting a contour of a semiconductor object of interest comprises the following steps: selecting a first feature of the semiconductor object of interest as an anchor feature, and defining a transfer attribute from a first contour of the anchor feature of the semiconductor object of interest to a second contour of the second feature. After obtaining a cross-sectional image of the semiconductor object of interest, a first contour of the anchor feature in the cross-sectional image is generated by a standard method. The second contour is derived from the first contour using the transfer attribute.

[0046] In step S0, an object detection task is specified and further processing information corresponding to the semiconductor object of interest is collected. For example, a template of the semiconductor object of interest is specified, such as Figure 3 The HAR structure 307 shown. The semiconductor object of interest includes multiple features with multiple contours or edges, which define a template of the semiconductor object of interest. The specification may, for example, include a desired value for the number of concentric rings within the HAR structure 307, and a desired diameter for each ring. In addition, the regularity of the multiple HAR structures 307 is specified, such as a hexagonal grid with a desired value for the grid grid spacing. In general, the template of the semiconductor object of interest may include several features of the semiconductor object of interest, and the relationship between these features or between at least one feature and a reference feature. The specification of the object detection work can be obtained from the memory of the input device as a predetermined specification of the HAR object detection work. The specification of the object detection work can also be obtained or modified via the user interface.

[0047] Some contours are distinct and can be more easily detected, for example, by standard image processing techniques such as threshold operations or contrast slope operations. During a given target detection job, a feature is selected whose contour or edge is more easily detected by image processing techniques. This feature is also referred to as an "anchor feature". FIG. 5 shows an example of an image segment 309 comprising a cross-sectional image slice 311 of a cross section through a semiconductor object of interest. Figure 5a An idealized cross-sectional image is shown through a single HAR structure containing only two features or annular regions 317.1 and 317.2. Figure 5a Image segment 309a is shown with an ideal contrast of the SEM image, which is determined by the material contrast corresponding to the material within the annular regions 317.1 and 317.2. Figure 5bThe image intensity I(x) along the line AB passing through the cross-sectional image segment 309a is displayed. The image intensity I(x) is shown in arbitrary units with three intensity levels: a background intensity level Ib, a first intensity level I1 of the first annular region 317.1, and a second intensity level I2 of the second annular region 317.2. The radii r1 and r2 of the first annular region 317.1 and the second annular region 317.2 correspond to the intensity values ​​c1 and c2. The intensity thresholds C1 and C2 may be predetermined, for example by prior knowledge of the radius from, for example, CAD data. The threshold intensity values ​​C1 and C2 may also be selected by a user, for example via user input. For example, a user may determine the threshold based on the normalized image slope I'(x) or the normalized image logarithmic slope (NILS) of the cross-sectional image, such that the intensity threshold C1 corresponds to the maximum NILS value. Typically, the NILS(x) displays a maximum value at the transition of the annular regions, for example from the first annular region 317.1 to the second annular region 317.2.

[0048] Figure 5c A more realistic image segment 309b with the real contrast of the SEM image is shown. Due to, for example, limited image acquisition time, the SEM image is affected by image noise or shot noise and additional signals from the background 318 (e.g., generated by the underlying layer). The interaction area of ​​the primary electron beamlet typically has an extension of about 5nm to 20nm within the wafer sample, so secondary electrons are also collected from deeper underlying structures. The inner channel edge around the dark core or first annular region 317.1 is still obvious and can be detected using, for example, threshold processing. Therefore, the inner channel edge around the first annular region 317.1 can form an anchor feature for this inspection work. Due to image noise and the poor contrast of the second outer ring 317.2, the contour extraction of the outer contour of the second ring 317.2 is prone to errors or even impossible. The outer contour of the second ring 317.2 may even appear to merge with the adjacent HAR structure part, such as shown by the bridge 320. The outer edge contour of the second annular region 317.2 cannot be easily generated by threshold processing. However, the outer edge of the second annular region 317.2 is usually the main focus of the inspection work of the HAR channel.

[0049] After selecting and defining the anchor feature, a transfer property of the contours of other features in the semiconductor object of interest is defined. The transfer property may be, for example, a simple scaling property of a first contour of a first annular region to a second contour of a second annular region. The scaling property is derived, for example, from different radii r1 and r2 provided by the design information, such that a second contour line with a radius r2 is derived by scaling a first contour line with a radius r1 by a scaling factor r2 / r1. For example, a first contour line is extracted at the anchor feature, and contour lines of other features are derived by scaling.

[0050] In a first step S1, a cross-sectional image slice 311 of a semiconductor object of interest is obtained. The cross-sectional image slice 311 is generated, for example, by a slicing and imaging process of the dual-beam system 1. The cross-sectional image slice 311 may also be obtained from a data memory of a data processing system. The cross-sectional image slice 311 may be registered according to predetermined registration features such as a reference. The cross-sectional image slice 311 may further undergo image processing, including, for example, intensity calibration, distortion correction, magnification adjustment, depth map calculation, global or local contrast enhancement, noise filtering. Optionally, the cross-sectional image slice 311 is displayed using a display of a user interface.

[0051] In one example, during step S1, an instance of the semiconductor object of interest 307 is detected, for example, by matched filter or template matching, threshold processing or other related techniques known in the art. The detection of the instance of the semiconductor object of interest 307 may also follow previous information, for example if a repeated semiconductor object of interest 307 such as a HAR structure is studied, or based on the registration of the cross-sectional image slice 311 relative to CAD information or an alignment fiducial.

[0052] In a second step S2, a first contour of an anchor feature is generated. The anchor feature is, for example, the anchor feature selected in step S0. In step S2.1, an initial contour proposal is generated by a fast and simple image processing operation. Such an operation may be, for example, a simple truncation or thresholding operation of the image intensity level C1 of the appropriate intensity calibration cross-sectional image segment 309. Another example is the calculation of the intensity gradient I'(x) or NILS(x), such as Figure 5b shown.

[0053] FIG. 6 illustrates the results of the method steps in the example of a SEM image segment 309 of a semiconductor object of interest in the example of the HAR channel in FIG. 5 with two annular areas 317 . 1 and 317 . 2 . Figure 6a ) to 6d) provide SEM image fragments 309, in order to see more clearly, the image noise is not shown. Figure 6a An example of the result of step S2.1 is shown. An initial contour proposal 381 is displayed at each image pixel according to the criterion selected for each image pixel. The selected criterion may be, for example, an intensity threshold or a local maximum of a NILS value. The contour proposal 381 consists of individually labeled pixels and there may be missing pixels, such as contour gaps 379.

[0054] In optional step S2.2, the initial pixelated contour proposal 381 is analyzed and modified, and the contour 383 of the anchor feature is determined. The analysis and modification may include image processing methods, such as smoothing operations, interpolation between pixels, contour closing to fill gaps 379. Further steps may include determining a contour vector representing the contour 383, and determining a geometric description of the contour 383, for example by spline interpolation. The analysis and modification of the initial pixelated contour proposal 381 is given by a so-called "active contour model", also known as a "snake model" in the computer vision framework. According to the method, a deformable model of the contour is matched to the image by optimization. The deformable model is, for example, derived from a spline interpolation of the initial pixelated contour proposal 381. For the optimization goal, a prior knowledge of the contour shape is applied, which can be provided, for example, from CAD information or by user specifications.

[0055] In one example, contour line 383 is used as the first contour of the anchor feature. However, contour proposal 381 can also be directly used as the first contour of the anchor feature.

[0056] In step S3, a second contour of a second feature different from the anchor feature is determined. In step 3.1, a second contour proposal of the second feature is determined based on the first contour of the anchor feature determined in step S2. The second contour proposal is determined based on the transfer attribute defined in step S0. Figure 6c . The transfer properties in this example are determined based on the scaling of the first to second contours, where the scaling factor r2 / r1 is based on the designed radii r1 and r2 of the annular regions in the HAR channel. The first contour line 381 or 383 is scaled (shown by the scaling vector 391) to form a second contour proposal 385 of a second feature (here, the second annular region 317.2). Other transformations are also possible, including shifts, rotations, shear operations, deformation operations, anisotropic scaling, or relative scaling of a contour template including a second feature having a different shape than the anchor feature. For template scaling, a template for the second feature is defined in step S0, and the transfer properties of the template are defined based on the first contour properties of the anchor feature. For example, the template for the second feature is defined based on the designed shape of the semiconductor object of interest and a predefined scaling characteristic, such as the diameter or area of ​​the first contour of the anchor feature.

[0057] In step 3.2, similar to step S2.1, the second contour proposal 385 is analyzed and modified, and a second contour line of the second feature is determined. The analysis and modification may include the methods described in conjunction with step S2.2, such as by applying an active contour model, using prior knowledge of the contour shape of the second feature. Figure 6d An example result is shown, where a second contour line 387 is generated from the second contour proposal 383 .

[0058] Step S4 includes multiple selections.

[0059] In optional step S4.1, the cross-sectional image segment 309 is automatically annotated pixel by pixel according to the area bounded by the first contour 381 or 383 and the second contour 385 or 387. This annotated image is needed, for example, as training data for an object detector.

[0060] In optional step S4.2, a parameter or attribute of the second feature is determined, such as diameter, area, center of gravity, deviation from a designed shape, eccentricity, distance to another semiconductor object of interest, such as distance to a second feature of a second HAR channel. The type of determination may be selected by user input and performed by operations known in the art. The determined parameter or attribute may be used as an annotation label for the cross-sectional image segment as training data for training a machine learning algorithm for wafer inspection.

[0061] In optional step S4.3, the results of step S4.1 or step 4.2 or both are stored in a memory for later use.

[0062] The method iteratively continues with step N, where the next cross-sectional image slice of the semiconductor object of interest is obtained and used as input to step S1. In one example, each cross-sectional image slice contains multiple instances of the semiconductor object of interest, and method steps S1 to S4 are repeated for each detected instance of the semiconductor object of interest within each cross-sectional image slice.

[0063] Iterations continue until an interruption criterion is determined in step Q. For example, the interruption criterion is reached when a sufficient amount or training data has been generated for training the object detector. In optional step S5, the training data is then used to train the object detector OD. The trained object detector can be used for object detection during wafer inspection operations.

[0064] FIG8 illustrates another example of this method. In this paper, the initial contour proposal 381 ( Figure 8a ) to generate the profile of the second feature 387 according to step S3 ( Figure 8b ) and skip step S2.2. In another example, the center point 321 of the HAR structure 307 is taken as an anchor feature, and a plurality of second contour lines 387 are directly obtained from the center point 321 as anchor features. The center point can be generated, for example, by template matching technology or related correlation technology.

[0065] FIG9 shows another method example according to the first specific embodiment. Figure 9a, a cross-sectional image segment 309 of a HAR channel 307 containing six annular regions 317.1 to 317.6 is shown. In step S0, two anchor features are selected: a central annular region 317.6 and a second annular region 317.2. In step S2, contours 383.1 and 383.2 of the two anchor features are determined. In step S3.1, the contours 383.1 and 383.2 are scaled to conform to the contour of the second feature. For the outer annular regions 317.1 to 317.4, the first contour 383.1 is scaled to obtain contour proposals 385.1, 385.3 and 385.4. The contour 383.2 of the second anchor feature 317.6 is scaled to obtain a contour proposal of the next adjacent contour 385.2 of the annular region 317.5. In step 3.2, the final contours 387.1 to 387.5 of the annular regions 317.1, 317.3 to 317.5 are determined. For example, the inner deformation 325 of the annular regions is thereby determined.

[0066] Fig.10 The application of the object detector OD implemented by the method according to the first specific embodiment is illustrated. In step M1, a new cross-sectional image slice is received. In step M2, multiple instances of the semiconductor object of interest are detected in the new cross-sectional image slice by the object detector OD, and the segmentation of each instance of the semiconductor object of interest is performed by the object detector. In step M3, a measurement is performed on each instance of the semiconductor object of interest, and the measurement results are stored in a memory. In step M4, multiple measurement results from multiple cross-sectional image slices are analyzed, and, for example, statistical analysis of the characteristics of the semiconductor object of interest during the semiconductor process is performed. In step M5, the results of the analysis are used to modify the semiconductor process.

[0067] Figure 11 shows the result of step MA. Fig.11a , the trajectory of the HAR channel center coordinates is shown. Each horizontal line corresponds to a profile of the second feature 387 measured at a depth z within the wafer inspection volume. Thus, the HAR channel can be analyzed and, for example, the average tilt angle γ of the average channel trajectory 363 can be determined. Fig.11b The distribution of the measured radius r2 for multiple wafer samples is illustrated. The radius r2 shows a significant drift across the wafer samples, which can be used as an indicator of process drift in the wafer manufacturing process.

[0068] In a second embodiment, a wafer inspection system configured to perform the method according to the first embodiment is described. Fig.12 An example of such a wafer inspection system is shown. Wafer inspection system 1000 includes a dual beam system 1 . Figure 1 A dual beam system is illustrated in more detail and reference is made to Figure 1Description of the invention. The basic features of the dual beam system 1 are a first charged particle or FIB column 50 for milling, and a second charged particle beam imaging system 40 for high resolution imaging of cross-sectional surfaces. The dual beam system 1 comprises at least one detector 17 for detecting secondary particles, which may be electrons or photons. The dual beam system 1 further comprises a wafer support table 15, which is configured to carry a wafer 8 during use. The wafer support table 15 is positionally controlled by a table control unit 16 connected to a control unit 19 of the dual beam system 1. The control unit 19 is configured with memory and logic to control the operation of the dual beam system 1.

[0069] The wafer inspection system 1000 further includes an operation control unit 2. The operation control unit 2 includes at least one processing engine 201, which may be formed by a plurality of parallel processors including a GPU processor and a general unified memory. The operation control unit 2 further includes an SSD memory and a disk memory or storage device 203 for storing training data, a trained machine learning algorithm, and a plurality of cross-sectional images. The operation control unit 2 further includes a user interface 205, which includes a user interface display 400 and a user command device 401, which is configured to receive input from a user. The operation control unit 2 further includes a memory or storage device 219 for storing processing information of an image generation process of the dual beam device 1, and for storing software instructions executable by the processing engine 201. The process information of the image generation process using the dual beam device 1 may, for example, include a database of effects during image generation and a list of predetermined material comparisons. The software instructions include software for executing the method according to the first specific embodiment.

[0070] The operation control unit 2 is also connected to an interface unit 231, which is configured to receive further commands or data, such as CAD data, from an external device or network. The interface unit 231 is further configured to exchange information, such as receiving instructions from an external device or providing measurement results to an external device, or storing a set of training data or a trained machine learning algorithm or a plurality of cross-sectional images in an external storage device.

[0071] The processing engine 201 is configured to take into account process information of the image generation process using, for example, the dual beam device 1, including, for example, selected imaging parameters of the dual beam system. The imaging parameters may be selected by the user, for example, depending on the speed or accuracy required for the measurement job.

[0072] The inspection system 1000 is configured to receive user information as specified in step S0 of the method according to the first embodiment, for example including CAD information of a semiconductor object of interest and a selection of anchor features. The inspection system 1000 may be configured to combine the user information with process information of an image generation process. The processing engine 201 is further configured to perform method steps S1 to S5 of the above method. The processing engine 201 is thereby configured to display information via a user display 400 and to receive user input via a user interface 401. The processing engine 201 is further configured to train an object detector OD using training data generated during iterative operations of steps S1 to S4. For a second embodiment, an inspection system 1000 configured to segment and annotate images with high throughput is provided.

[0073] The above examples are described for the segmentation and annotation of HAR channels. These methods can of course also be applied to other semiconductor objects of interest. The method can further be applied to, for example, a raster of a repeated semiconductor object of interest.

[0074] The method and inspection system can be used for quantitative metrology, but can also be used for defect detection, process monitoring, defect review and inspection of integrated circuits in semiconductor wafers. The first step of wafer inspection work using machine learning algorithms is improved by the image segmentation and annotation method according to the first specific embodiment. The present invention provides, for example, a method and an apparatus for generating training data with reduced user interaction. The method and inspection apparatus for generating training data rely on previous knowledge of the object to be measured, including the selection of anchor features and the determination of transfer properties. The previous knowledge is given, for example, by CAD information.

[0075] The present invention can be described by the following clauses:

[0076] Clause 1: A method for contour extraction of a semiconductor object of interest, comprising:

[0077] - selecting a first feature of the semiconductor object of interest (307) as an anchor feature (317.1);

[0078] - defining transfer properties from a first contour (381, 383) of the anchor feature (317.1) to a second contour (385) of a second feature (317.2) of the semiconductor object of interest (307);

[0079] - obtaining at least one cross-sectional image (309, 311) comprising at least one cross-section of the semiconductor object of interest (307);

[0080] - generating a first outline (381, 383) of the anchor feature (317.1) in the cross-sectional image (309, 311);

[0081] - Determining a second contour (385, 387) from the first contour (381, 383) using the transfer property.

[0082] Item 2: A method as in Item 1, wherein generating the first contour (381, 383) comprises generating an initial contour proposal (381) from a cross-sectional image (309, 311) by image processing, wherein the image processing comprises at least one component of a group consisting of intensity calibration, critical operation, calculation of intensity gradient, or calculation of NILS.

[0083] Item 3: A method as described in Item 2, wherein generating the first contour (383) includes modifying the initial contour proposal (381) by image processing, the image processing including at least one component of the group consisting of smoothing, interpolation, contour closure, contour vector extraction, or active contour modeling.

[0084] Clause 4: A method as described in Clause 3, wherein the image processing is based on previous knowledge of the contour shape of the anchor feature (317.1).

[0085] Clause 5: A method as described in any of clauses 1 to 4, wherein the transfer attribute used to determine the second contour (385, 387) includes at least one component from the group consisting of scaling, anisotropic scaling, deformation operation, displacement, rotation, shearing or template scaling.

[0086] Item 6: A method as described in any one of items 1 to 5, wherein determining the second contour (387) further includes an image processing, wherein the image processing includes at least one component selected from the group consisting of smoothing, interpolation, contour closure, contour vector extraction, or an active contour model.

[0087] Item 7: A method as described in any of Items 1 to 6, further comprising detecting at least one instance of the semiconductor object of interest (307) within the cross-sectional image (309, 311) by a method comprising components in a group consisting of template matching, critical processing or correlation techniques.

[0088] Clause 8: The method of any one of clauses 1 to 7, further comprising at least one component from the group consisting of registration, distortion correction, magnification adjustment, depth map calculation, contrast enhancement, and noise filtering of the cross-sectional images (309, 311).

[0089] Clause 9: The method of any one of clauses 1 to 8, comprising iteratively repeating obtaining cross-sectional images (309, 311), generating a first contour (381, 383), and determining a second contour (385, 387) using the transferred properties.

[0090] Clause 10: The method of any one of clauses 1 to 8, further comprising annotation of at least one cross-sectional image (309, 311) with pixel values ​​according to the first and second contours (381, 383, 385, 387).

[0091] Clause 11: The method of clause 10, further comprising training the object detector OD using the at least one annotated cross-sectional image (309, 311).

[0092] Clause 12: The method of any one of clauses 1 to 9, comprising determining an attribute of the second feature (317.2), the attribute comprising at least one member of the group consisting of diameter, area, center of gravity, shape deviation, eccentricity, distance.

[0093] Item 13: A wafer inspection system (1000) comprising a dual beam system (1) and an operation control unit (2), comprising at least one processing engine (201) and a memory (219), wherein the processing engine (201) is configured to execute software instructions stored in the memory (219), which include instructions according to a method as described in any one of embodiments 1 to 12.

[0094] Item 14: The wafer inspection system (1000) further comprises an interface unit 231; and a user interface 205, which is configured to receive, display, transmit or store information.

[0095] Item 15: A wafer inspection system (1000) as described in Item 13 or 14, wherein the dual beam system (1) includes a focused ion beam (FIB) system and a charged particle beam imaging system, which are configured at an angle so that during use, the focused ion beam and the charged particle beam form an intersection, and are configured so that during use, at least one cross-sectional image (309, 311) is formed through the inspection volume of the wafer at an inclination angle GF relative to the wafer surface (55).

[0096] However, the present invention described through examples and specific embodiments is not limited to these terms, and those skilled in the art can implement the present invention through various combinations or modifications thereof.

[0097] A list of reference numerals is provided below:

[0098] 1 Dual beam system

[0099] 2 Operating the control unit

[0100] 4. First cross-sectional image features

[0101] 6 Measurement location

[0102] 8 chips

[0103] 15 Wafer support

[0104] 16 control units

[0105] 17 Secondary Electron Detector

[0106] 19 Control Unit

[0107] 40 Charged Particle Beam (CPB) Imaging System

[0108] 42 Optical axis of imaging system

[0109] 43 Intersection

[0110] 44 Imaging Charged Particle Beams

[0111] 48 FIB optical axis

[0112] 50 FIB column

[0113] 51 Focused Ion Beam

[0114] 52 Cross-sectional surface

[0115] 53 Cross-sectional surface

[0116] 55 Wafer top surface

[0117] 155 Wafer stage

[0118] 160 Check volume

[0119] 201 Processing Engine

[0120] 203 Memory

[0121] 205 User Interface

[0122] 219 Memory

[0123] 231 Interface Unit

[0124] Measured cross-sectional image of 307 HAR structure

[0125] 309 Image fragments

[0126] 311 cross-sectional image slices

[0127] 313 Word Line

[0128] 315 Surface Edge

[0129] 317 Semiconductor object of interest, here the annular region of the HAR structure

[0130] 318 Noise

[0131] 320 Partially merged outer contours

[0132] 321 Central Location

[0133] 325 Defects or deviations

[0134] 327 pixels annotated ring

[0135] 363 Average HAR channel trajectory

[0136] 379 Profile Clearance

[0137] 381 Initial outline proposal

[0138] 383 Contour of the first feature

[0139] 385 Second Outline Proposal

[0140] 387 Outline of the Second Feature

[0141] 391 Transfer attribute, here is the scaling vector

[0142] 400 User Interface Display

[0143] 401 User Command Device

[0144] 1000 Wafer Inspection System

Claims

1. A method for contour extraction of a semiconductor object of interest, comprising: - selecting a first feature of the semiconductor object of interest as an anchor feature; - defining a transfer property from a first contour of the anchor feature to a second contour of a second feature of the semiconductor object of interest; - obtaining at least one cross-sectional image comprising at least one cross-section of the semiconductor object of interest; - generating a first outline of the anchor feature in the cross-sectional image; and - Determining a second contour from the first contour using the transfer property.

2. The method according to claim 1, in, Generating the first contour comprises generating an initial contour proposal from the cross-sectional image by image processing comprising at least one component of the group consisting of intensity calibration, threshold operation, calculation of intensity gradient, or calculation of NILS.

3. The method according to claim 2, in, Generating the first contour includes modifying the initial contour proposal by image processing, the image processing including at least one component selected from the group consisting of smoothing, interpolation, contour closure, contour vector extraction, or active contour modeling.

4. The method according to claim 3, in, The image processing is based on prior knowledge of the contour shape of the anchor feature.

5. The method according to any one of claims 1 to 4, in, The transfer attribute for determining the second contour includes at least one member of the group consisting of scaling, anisotropic scaling, deformation operation, translation, rotation, shearing, or template scaling.

6. The method according to any one of claims 1 to 5, in, Determining the second contour further comprises image processing, wherein the image processing comprises at least one component selected from the group consisting of smoothing, interpolation, contour closure, contour vector extraction, or active contour modeling.

7. The method of any one of claims 1 to 6, further comprising detecting at least one instance of a semiconductor object of interest within the cross-sectional image by a method comprising components from the group consisting of template matching, threshold processing, or correlation techniques.

8. The method of any one of claims 1 to 7, further comprising at least one component from the group consisting of registration, distortion correction, magnification adjustment, depth map calculation, contrast enhancement, and noise filtering of the cross-sectional image.

9. The method of any one of claims 1 to 8, comprising iteratively repeating acquiring cross-sectional images, generating a plurality of first contours, and determining a plurality of second contours from the plurality of first contours using the transfer properties.

10. The method of any one of claims 1 to 9, further comprising annotating at least one cross-sectional image with pixel values ​​according to the first and second contours.

11. The method of claim 10, further comprising training an object detector (OD) using the at least one annotated cross-sectional image.

12. The method of any one of claims 1 to 11, comprising determining a property of the second feature, the property comprising at least one member of the group consisting of diameter, area, center of gravity, shape deviation, eccentricity, distance.

13. A wafer inspection system having a dual beam system and an operation control unit, comprising at least one processing engine and a memory, wherein the processing engine is configured to execute software instructions stored in the memory, wherein the software instructions include instructions that, when executed by the processing engine, cause the wafer inspection system to perform the method of any one of claims 1 to 12.

14. The wafer inspection system of claim 13, further comprising an interface unit; and a user interface configured to receive, display, transmit or store information.

15. The wafer inspection system according to claim 13, in, The dual beam system comprises a focused ion beam (FIB) system and a charged particle beam imaging system, wherein the charged particle beam imaging system is configured at an angle such that during use, the focused ion beam and the charged particle beam form an intersection, and wherein the charged particle beam imaging system is configured such that during use, at least one cross-sectional image is formed through an inspection volume of the wafer at an inclination angle GF relative to the wafer surface.

Images