Shifting register unit, driving control circuit, display device and driving method

Abstract

A shift register unit, a driving control circuit, a display device and a driving method wherein the shift register unit comprises: an input circuit (10) coupled to a first node (N1) and configured to provide a signal of an input signal terminal (IP) to the first node (N1) in response to a signal of a first clock signal terminal (CK); the control circuit (20) is coupled with the first node (N1), the second node (N2), a control signal end (CT) and a first reference signal end (VGL) and is configured to respond to a signal of the first node (N1), signals of the first clock signal end (CK) and the first reference signal end (VGL) are provided for the third node (N3) and the second node (N2) respectively, and the first node (N1) is not controlled by the second node (N2) or the third node (N3); and an output circuit (30) coupled with the first node (N2) and the second node (N2) and configured to provide a signal of the first reference signal end (VGL) to the output signal end (OT) in response to a signal of the second node (N2) and provide a signal of the second reference signal end (VGH) to the output signal end (OT) in response to a signal of the first node (N1).

Description

Shift register unit, drive control circuit, display device and driving method Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a shift register unit, a drive control circuit, a display device, and a driving method. Background Art

[0002] With the rapid development of display technology, display devices are increasingly moving towards high integration and low cost. Gate Driver on Array (GOA) technology integrates thin-film transistor (TFT) drive control circuitry onto the array substrate of a display device to drive the display. This drive control circuit typically consists of multiple cascaded shift register units. However, the output of these shift register units is unstable, leading to display anomalies.

[0003] Summary of the Invention

[0004] The present disclosure provides a shift register unit, a drive control circuit, a display device, and a drive method. The specific solutions are as follows:

[0005] An embodiment of the present disclosure provides a shift register unit, comprising:

[0006] an input circuit coupled to the first node and configured to provide a signal from an input signal terminal to the first node in response to a signal from a first clock signal terminal;

[0007] a control circuit coupled to the first node, the second node, the control signal terminal, and the first reference signal terminal, and configured to provide signals from the first clock signal terminal and the first reference signal terminal to a third node and the second node, respectively, in response to a signal from the first node, wherein the first node is not controlled by the second node or the third node;

[0008] The output circuit is coupled to the first node and the second node, and is configured to provide the signal of the first reference signal terminal to the output signal terminal in response to the signal of the second node, and to provide the signal of the second reference signal terminal to the output signal terminal in response to the signal of the first node.

[0009] Optionally, in an embodiment of the present disclosure, the control circuit includes a first control module, a second control module and a third control module;

[0010] The first control module is coupled to the first node and the third node, and is configured to provide the signal of the first clock signal terminal to the third node in response to the signal of the first node, and to provide the signal of the control signal terminal to the third node in response to the signal of the first clock signal terminal;

[0011] The second control module is coupled to the second node and the third node, and is configured to provide the signal of the second clock signal terminal to the second node in response to the signal of the third node and the second clock signal terminal;

[0012] The third control module is coupled to the first node and the second node, and is configured to provide a signal at the first reference signal terminal to the second node in response to a signal at the first node.

[0013] Optionally, in the embodiment of the present disclosure, a voltage stabilizing circuit is further included;

[0014] The voltage stabilizing circuit is coupled to the third node and configured to maintain the potential of the third node.

[0015] Optionally, in the embodiment of the present disclosure, the voltage stabilizing circuit includes a first capacitor;

[0016] A first electrode of the first capacitor is coupled to the third node, and a second electrode of the first capacitor is coupled to the second reference signal terminal.

[0017] Optionally, in the embodiment of the present disclosure, a protection circuit is further included;

[0018] The third node is coupled to the second control module through the protection circuit, and the protection circuit is configured to control conduction and disconnection between the third node and the second control module.

[0019] Optionally, in an embodiment of the present disclosure, the control signal terminal and the first clock signal terminal are the same signal terminal.

[0020] Optionally, in an embodiment of the present disclosure, the control signal terminal and the second reference signal terminal are the same signal terminal.

[0021] Optionally, in an embodiment of the present disclosure, the input circuit includes a first transistor;

[0022] A gate of the first transistor is coupled to the first clock signal terminal, a first electrode of the first transistor is coupled to the first node, and a second electrode of the first transistor is coupled to the input signal terminal.

[0023] Optionally, in an embodiment of the present disclosure, the first control module includes a second transistor and a third transistor;

[0024] The gate of the second transistor is coupled to the first node, the first electrode of the second transistor is coupled to the first clock signal terminal, and the second electrode of the second transistor is coupled to the third node;

[0025] A gate of the third transistor is coupled to the first clock signal terminal, a first electrode of the third transistor is coupled to the third node, and a second electrode of the third transistor is coupled to the control signal terminal.

[0026] Optionally, in the embodiment of the present disclosure, the second control module includes a fourth transistor and a fifth transistor;

[0027] The gate of the fourth transistor is coupled to the third node, the first electrode of the fourth transistor is coupled to the fourth node, and the second electrode of the fourth transistor is coupled to the second clock signal terminal;

[0028] A gate of the fifth transistor is coupled to the second clock signal terminal, a first electrode of the fifth transistor is coupled to the second node, and a second electrode of the fifth transistor is coupled to the fourth node.

[0029] Optionally, in the embodiment of the present disclosure, a reset circuit is further included;

[0030] The reset circuit is coupled to the first node and a fourth node, and is configured to provide the signal of the first reference signal terminal to the first node in response to a signal of the fourth node.

[0031] Optionally, in the embodiment of the present disclosure, the third control module includes a sixth transistor;

[0032] A gate of the sixth transistor is coupled to the first node, a first electrode of the sixth transistor is coupled to the first reference signal terminal, and a second electrode of the sixth transistor is coupled to the second node.

[0033] Optionally, in the embodiment of the present disclosure, the output circuit includes a seventh transistor, a second capacitor, an eighth transistor and a third capacitor;

[0034] The gate of the seventh transistor is coupled to the second node, the first electrode of the seventh transistor is coupled to the output signal terminal, and the second electrode of the seventh transistor is coupled to the second reference signal terminal;

[0035] A first electrode of the second capacitor is coupled to the second node, and a second electrode of the second capacitor is coupled to the first reference signal terminal;

[0036] The gate of the eighth transistor is coupled to the first node, the first electrode of the eighth transistor is coupled to the second reference signal terminal, and the second electrode of the eighth transistor is coupled to the output signal terminal;

[0037] A first electrode of the third capacitor is coupled to the first node, and a second electrode of the third capacitor is coupled to the output signal terminal.

[0038] Optionally, in the embodiment of the present disclosure, the protection circuit includes a ninth transistor;

[0039] A gate of the ninth transistor is coupled to the second reference signal terminal, a first electrode of the ninth transistor is coupled to the gate of the fourth transistor, and a second electrode of the ninth transistor is coupled to the third node.

[0040] Optionally, in the embodiment of the present disclosure, the reset circuit includes a tenth transistor;

[0041] A gate of the tenth transistor is coupled to the fourth node, a first electrode of the tenth transistor is coupled to the first node, and a second electrode of the tenth transistor is coupled to the first reference signal terminal.

[0042] Accordingly, an embodiment of the present disclosure provides a shift register unit, comprising:

[0043] a first transistor, wherein a first electrode of the first transistor is directly connected to the first node;

[0044] a second transistor, wherein a gate of the second transistor is directly connected to the first node, and a second electrode of the second transistor is coupled to a third node;

[0045] a sixth transistor, wherein a gate of the sixth transistor is directly connected to the first node, and a second electrode of the sixth transistor is coupled to the second node;

[0046] an eighth transistor, wherein a gate of the eighth transistor is directly connected to the first node, a first electrode of the eighth transistor is coupled to the second reference signal terminal, and a second electrode of the eighth transistor is coupled to the output signal terminal;

[0047] The first node is not controlled by the second node or the third node.

[0048] Optionally, in the embodiment of the present disclosure, the method further includes:

[0049] A first capacitor; a first electrode of the first capacitor is coupled to the third node, and a second electrode of the first capacitor is coupled to the second reference signal terminal.

[0050] Optionally, in the embodiment of the present disclosure, a ninth transistor is further included;

[0051] A gate of the ninth transistor is coupled to the second reference signal terminal, and a second electrode of the ninth transistor is coupled to the third node.

[0052] Optionally, in the embodiment of the present disclosure, a tenth transistor is further included;

[0053] A gate of the tenth transistor is coupled to the fourth node, a first electrode of the tenth transistor is coupled to the first node, and a second electrode of the tenth transistor is coupled to the first reference signal terminal.

[0054] Optionally, in the embodiment of the present disclosure, the method further includes:

[0055] a third transistor, wherein a first electrode of the third transistor is coupled to the third node, and a second electrode of the third transistor is coupled to the control signal terminal;

[0056] a fourth transistor, wherein a gate of the fourth transistor is coupled to the third node, and a first electrode of the fourth transistor is coupled to the fourth node;

[0057] a fifth transistor, wherein a first electrode of the fifth transistor is coupled to the second node, and a second electrode of the fifth transistor is coupled to the fourth node;

[0058] a seventh transistor, wherein a gate of the seventh transistor is coupled to the second node, and a first electrode of the seventh transistor is coupled to the output signal terminal;

[0059] a second capacitor, wherein a first electrode of the second capacitor is coupled to the second node, and a second electrode of the second capacitor is coupled to the first reference signal terminal;

[0060] A third capacitor, wherein a first electrode of the third capacitor is coupled to the first node, and a second electrode of the third capacitor is coupled to the output signal terminal.

[0061] Optionally, in an embodiment of the present disclosure,

[0062] The gate of the first transistor is coupled to the first clock signal terminal, and the second electrode of the first transistor is coupled to the input signal terminal;

[0063] A first electrode of the second transistor is coupled to the first clock signal terminal;

[0064] The gate of the third transistor is coupled to the first clock signal terminal;

[0065] The second electrode of the fourth transistor is coupled to the second clock signal terminal;

[0066] The gate of the fifth transistor is coupled to the second clock signal terminal;

[0067] The first electrode of the sixth transistor is coupled to the first reference signal terminal;

[0068] The second electrode of the seventh transistor is coupled to the second reference signal terminal;

[0069] The second electrode of the eighth transistor is coupled to the output signal terminal.

[0070] Optionally, in an embodiment of the present disclosure, the control signal terminal and the first clock signal terminal are the same signal terminal.

[0071] Optionally, in an embodiment of the present disclosure, the control signal terminal and the second reference signal terminal are the same signal terminal.

[0072] Accordingly, an embodiment of the present disclosure provides a drive control circuit, which includes:

[0073] A plurality of cascaded shift register units as described in any one of the above items;

[0074] The input signal terminal of the first stage shift register unit is coupled to the frame trigger signal terminal;

[0075] In every two adjacent stages of shift register units, the input signal terminal of the next stage shift register unit is coupled to the output signal terminal of the previous stage shift register unit.

[0076] Accordingly, an embodiment of the present disclosure provides a display device, comprising:

[0077] Drive control circuit as described above.

[0078] Accordingly, an embodiment of the present disclosure provides a driving method of a shift register unit as described in any one of the above items, comprising:

[0079] In the first stage, the input circuit responds to the signal of the first clock signal terminal and provides the signal of the input signal terminal to the first node; the control circuit responds to the signal of the first node and provides the signal of the first clock signal terminal and the signal of the first reference signal terminal to the third node and the second node, controlling the potential of the second node to be opposite to the potential of the first node; the output circuit responds to the signal of the first node and provides the signal of the second reference signal terminal to the output signal terminal. BRIEF DESCRIPTION OF THE DRAWINGS

[0080] FIG1 is a schematic structural diagram of a shift register unit in the related art;

[0081] FIG2 is a schematic diagram of voltage simulation waveforms of various nodes of the shift register unit shown in FIG1 in a working state;

[0082] FIG3 is a schematic diagram of some structures of a shift register unit provided by an embodiment of the present disclosure;

[0083] FIG4 is another schematic diagram of the structure of a shift register unit provided by an embodiment of the present disclosure;

[0084] FIG5 is a schematic diagram of another structure of a shift register unit provided by an embodiment of the present disclosure;

[0085] FIG6 is a schematic diagram of another structure of a shift register unit provided by an embodiment of the present disclosure;

[0086] FIG7 is a timing diagram of some signals provided by an embodiment of the present disclosure;

[0087] FIG8 is a schematic diagram of another structure of a shift register unit provided by an embodiment of the present disclosure;

[0088] FIG9 is a schematic diagram of another structure of a shift register unit provided by an embodiment of the present disclosure;

[0089] FIG10 is a schematic diagram of another structure of a shift register unit provided by an embodiment of the present disclosure;

[0090] FIG11 is a schematic diagram of another structure of a shift register unit provided by an embodiment of the present disclosure;

[0091] FIG12 is a schematic diagram of another structure of a shift register unit provided by an embodiment of the present disclosure;

[0092] FIG13 is a schematic diagram of another structure of a shift register unit provided by an embodiment of the present disclosure;

[0093] FIG14 is a schematic diagram of another structure of a shift register unit provided by an embodiment of the present disclosure;

[0094] FIG15 is a schematic diagram of another structure of a shift register unit provided by an embodiment of the present disclosure;

[0095] FIG16 is a schematic diagram of another structure of a shift register unit provided by an embodiment of the present disclosure;

[0096] FIG17 is a schematic diagram of another structure of a shift register unit provided by an embodiment of the present disclosure;

[0097] FIG18 is a schematic diagram of some structures of a drive control circuit provided by an embodiment of the present disclosure;

[0098] FIG19 is a flow chart of a method for driving a shift register unit provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0099] In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. And in the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be combined with each other. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0100] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by people with ordinary skills in the field to which this disclosure belongs. The words "first", "second" and similar terms used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Inside", "outside", "upper", "lower" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0101] It should be noted that the sizes and shapes of the figures in the accompanying drawings do not reflect the actual scale and are only for the purpose of illustrating the present disclosure. The same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions.

[0102] In the related art, as shown in Figures 1 and 2, Figure 1 is a schematic diagram of the structure of a shift register unit in a light-emitting driver circuit, which includes transistors M1 to M10 and capacitors C01 to C03. Figure 2 is a schematic diagram of the simulated waveforms of the voltages at various nodes of the shift register unit shown in Figure 1 when in operation. During the t04 phase, the potential at point n2 is pulled high by the ecb, causing the voltage at point n2 to reach 35V. This causes the bias voltages at M2, M3, M4, and M9 to be excessive. For example, at this time, the VDS of M2 is as high as 40V, and the VGS of M4 is 19V. Once these transistors are biased too much, it is easy to cause device characteristics to shift, thereby affecting the performance of the light-emitting driver circuit.

[0103] In view of this, an embodiment of the present disclosure provides a shift register unit, as shown in FIG3 , the shift register unit includes:

[0104] The input circuit 10 is coupled to the first node N1 and is configured to provide a signal from the input signal terminal IP to the first node N1 in response to a signal from the first clock signal terminal CK;

[0105] a control circuit 20 coupled to the first node N1, the second node N2, the control signal terminal CT, and the first reference signal terminal VGL, and configured to provide signals from the first clock signal terminal and the first reference signal terminal to a third node and the second node, respectively, in response to a signal from the first node N1, wherein the first node is not controlled by the second node or the third node;

[0106] The output circuit 30 is coupled to the first node N1 and the second node N2, and is configured to provide the signal of the first reference signal terminal VGL to the output signal terminal OT in response to the signal of the second node N2, and to provide the signal of the second reference signal terminal VGH to the output signal terminal OT in response to the signal of the first node N1.

[0107] In the disclosed embodiment, the signal at the first node N1 is controlled by the input circuit 10; the signals at the second node N2 and the third node N3 are controlled by the control circuit 20, and the signals at the second node N2 or the third node N3 do not affect the signal at the first node N1; and the signal at the output signal terminal OT is controlled by the output circuit 30. The entire shift register unit employs a small number of components and has low circuit complexity, resulting in low production costs, a simple circuit structure, and a small footprint, facilitating narrow-frame designs. Furthermore, the coordination of these components improves the stability of the signal outputted by the output signal terminal OT.

[0108] In the embodiment of the present disclosure, as shown in FIG4 , the control circuit 20 includes a first control module 21 , a second control module 22 and a third control module 23 ;

[0109] The first control module 21 is coupled to the first node N1 and the third node N3, and is configured to provide the signal of the first clock signal terminal CK to the third node N3 in response to the signal of the first node N1, and to provide the signal of the control signal terminal CT to the third node N3 in response to the signal of the first clock signal terminal CK;

[0110] The second control module 22 is coupled to the second node N2 and the third node N3, and is configured to provide the signal of the second clock signal terminal CB to the second node N2 in response to the signal of the third node N3 and the second clock signal terminal CB;

[0111] The third control module 23 is coupled to the first node N1 and the second node N2 , and is configured to provide a signal from the first reference signal terminal VGL to the second node N2 in response to a signal from the first node N1 .

[0112] In the embodiment of the present disclosure, as shown in Figure 5, the control signal terminal CT and the first clock signal terminal CK are the same signal terminal. For example, the control signal terminal CT and the first clock signal terminal CK can be coupled together, which can reduce the number of signal lines and reduce wiring difficulty.

[0113] In the embodiment of the present disclosure, as shown in FIG5 , the input circuit 10 includes a first transistor T1;

[0114] A gate of the first transistor T1 is coupled to the first clock signal terminal CK, a first electrode of the first transistor T1 is coupled to the first node N1, and a second electrode of the first transistor T1 is coupled to the input signal terminal IP.

[0115] In a specific implementation, the first transistor T1 can be turned on under the control of the active level of the first clock signal transmitted by the first clock signal terminal CK, and can be turned off under the control of the inactive level of the first clock signal. For example, if the first transistor T1 is configured as an N-type transistor, the active level of the first clock signal is a high level, and the inactive level of the first clock signal is a low level. When the first transistor T1 is in the on state, the input signal terminal IP can be connected to the first node N1; when the first transistor T1 is in the off state, the input signal terminal IP can be disconnected from the first node N1.

[0116] In the embodiment of the present disclosure, as shown in FIG5 , the first control module 21 includes a second transistor T2 and a third transistor T3;

[0117] The gate of the second transistor T2 is coupled to the first node N1, the first electrode of the second transistor T2 is coupled to the first clock signal terminal CK, and the second electrode of the second transistor T2 is coupled to the third node N3;

[0118] A gate of the third transistor T3 is coupled to the first clock signal terminal CK, a first electrode of the third transistor T3 is coupled to the third node N3, and a second electrode of the third transistor T3 is coupled to the control signal terminal CT.

[0119] In a specific implementation, the gate of the second transistor T2 is coupled to the first node N1. Thus, the second transistor T2 can be turned on by the active level of the signal transmitted by the first node N1 and turned off by the inactive level of the signal transmitted by the first node N1. Exemplarily, the second transistor T2 is configured as an N-type transistor, where the active level of the signal transmitted by the first node N1 is a high level, and the inactive level of the signal transmitted by the first node N1 is a low level. When the second transistor T2 is in the on state, the first clock signal terminal CK can be connected to the third node N3; when the second transistor T2 is in the off state, the first clock signal terminal CK can be disconnected from the third node N3.

[0120] In a specific implementation, the gate of the third transistor T3 is coupled to the first clock signal terminal CK. Thus, the third transistor T3 can be turned on by the active level of the first clock signal transmitted by the first clock signal terminal CK, and can be turned off by the inactive level of the first clock signal. For example, if the third transistor T3 is an N-type transistor, the active level of the first clock signal is a high level, and the inactive level of the first clock signal is a low level.

[0121] In the embodiment of the present disclosure, as shown in FIG5 , the second control module 22 includes a fourth transistor T4 and a fifth transistor T5 ;

[0122] The gate of the fourth transistor T4 is coupled to the third node N3, the first electrode of the fourth transistor T4 is coupled to the fourth node N4, and the second electrode of the fourth transistor T4 is coupled to the second clock signal terminal CB;

[0123] A gate of the fifth transistor T5 is coupled to the second clock signal terminal CB, a first electrode of the fifth transistor T5 is coupled to the second node N2, and a second electrode of the fifth transistor T5 is coupled to the fourth node N4.

[0124] In a specific implementation, the fourth transistor T4 is turned on when the active level of the signal transmitted by the third node N3 is controlled, and is turned off when the inactive level of the signal transmitted by the third node N3 is controlled. Exemplarily, the fourth transistor T4 is configured as an N-type transistor, so that the active level of the signal transmitted by the third node N3 is a high level, and the inactive level of the signal transmitted by the third node N3 is a low level. When the fourth transistor T4 is in the on state, the second clock signal terminal CB can be connected to the fourth node N4; when the fourth transistor T4 is in the off state, the second clock signal terminal CB can be disconnected from the fourth node N4.

[0125] In a specific implementation, the fifth transistor T5 is turned on when the second clock signal provided by the second clock signal terminal CB is at an active level, and is turned off when the second clock signal provided by the second clock signal terminal CB is at an inactive level. Exemplarily, the fifth transistor T5 is configured as an N-type transistor, and the active level of the second clock signal is a high level, and the inactive level of the second clock signal is a low level.

[0126] In the embodiment of the present disclosure, as shown in FIG5 , the third control module 23 includes a sixth transistor T6;

[0127] A gate of the sixth transistor T6 is coupled to the first node N1 , a first electrode of the sixth transistor T6 is coupled to the first reference signal terminal VGL, and a second electrode of the sixth transistor T6 is coupled to the second node N2 .

[0128] In a specific implementation, the sixth transistor T6 is turned on when the active level of the signal transmitted by the first node N1 is controlled, and is turned off when the inactive level of the signal transmitted by the first node N1 is controlled. Exemplarily, the sixth transistor T6 is configured as an N-type transistor, so that the active level of the signal transmitted by the first node N1 is a high level, and the inactive level of the signal transmitted by the first node N1 is a low level. When the sixth transistor T6 is in the on state, the first reference signal terminal VGL can be electrically connected to the second node N2; when the sixth transistor T6 is in the off state, the first reference signal terminal VGL can be disconnected from the second node N2.

[0129] In the embodiment of the present disclosure, as shown in FIG5 , the output circuit 30 includes a seventh transistor T7 , a second capacitor C2 , an eighth transistor T8 , and a third capacitor C3 ;

[0130] The gate of the seventh transistor T7 is coupled to the second node N2, the first electrode of the seventh transistor T7 is coupled to the output signal terminal OT, and the second electrode of the seventh transistor T7 is coupled to the second reference signal terminal VGH;

[0131] A first electrode of the second capacitor C2 is coupled to the second node N2, and a second electrode of the second capacitor C2 is coupled to the first reference signal terminal VGL;

[0132] The gate of the eighth transistor T8 is coupled to the first node N1, the first electrode of the eighth transistor T8 is coupled to the second reference signal terminal VGH, and the second electrode of the eighth transistor T8 is coupled to the output signal terminal OT;

[0133] A first electrode of the third capacitor C3 is coupled to the first node N1 , and a second electrode of the third capacitor C3 is coupled to the output signal terminal OT.

[0134] In a specific implementation, the seventh transistor T7 is turned on when the active level of the signal transmitted from the second node N2 is controlled, and is turned off when the inactive level of the signal transmitted from the second node N2 is controlled. Exemplarily, the seventh transistor T7 is configured as an N-type transistor, and the active level of the signal transmitted from the second node N2 is a high level, and the inactive level of the signal transmitted from the second node N2 is a low level.

[0135] In a specific implementation, the eighth transistor T8 is turned on under the control of the active level of the signal transmitted by the first node N1, and is turned off under the control of the inactive level of the signal transmitted by the first node N1. Exemplarily, the eighth transistor T8 is configured as an N-type transistor, and the active level of the signal transmitted by the first node N1 is a high level, and the inactive level of the signal transmitted by the first node N1 is a low level.

[0136] In the specific implementation process, according to the flow direction of the signal, the first electrode of the above-mentioned transistor can be used as its source, and the second electrode can be used as its drain; or, the first electrode can be used as its drain, and the second electrode can be used as its source, without making a specific distinction here.

[0137] It should be noted that the transistors mentioned in the embodiments of the present disclosure may be thin film transistors (TFTs) or metal oxide semiconductor field effect transistors (MOSs), which are not limited here.

[0138] In the embodiment of the present disclosure, the active layer of each transistor in the above-mentioned transistors can be a metal oxide semiconductor material, and accordingly, each transistor can be an N-type transistor using a metal oxide semiconductor material as an active layer; the first reference signal terminal VGL can be configured to load a constant first reference voltage, and the first reference voltage is generally a negative value, such as -9V. And, the second reference signal terminal VGH can load a constant second reference voltage, and the second reference voltage can generally be a positive value, such as 7V. In actual applications, the specific values ​​of the above voltages can be designed and determined according to the actual application environment, and are not limited here. In addition, the above-mentioned transistors can all be set as P-type transistors, which are not limited here.

[0139] The present disclosure also provides another structural diagram of a shift register unit, as shown in Figure 6, which is a modification of the embodiment described above. The following only describes the differences between this embodiment and the above embodiment, and the similarities are not repeated here.

[0140] In the embodiment of the present disclosure, as shown in FIG6 , the shift register unit further includes a voltage stabilizing circuit 40 ; the voltage stabilizing circuit 40 is coupled to the third node N3 and configured to maintain the potential of the third node N3 .

[0141] In the exemplary embodiment shown in FIG6 , the voltage stabilizing circuit 40 includes a first capacitor C1;

[0142] A first electrode of the first capacitor C1 is coupled to the third node N3 , and a second electrode of the first capacitor C1 is coupled to the second reference signal terminal VGH.

[0143] In a specific implementation process, the first capacitor C1 can maintain the potential of the third node N3, thereby improving the stability of the voltage of the third node N3 and effectively avoiding the problem of excessive bias voltage of the third node N3.

[0144] In an embodiment of the present disclosure, as shown in FIG6 , the control signal terminal CT and the first clock signal terminal CK are the same signal terminal.

[0145] For example, the control signal terminal CT and the first clock signal terminal CK may be coupled together, which can reduce the number of signal lines and reduce wiring difficulty.

[0146] The following describes the working process of the above-mentioned shift register unit provided by the embodiment of the present disclosure, taking the shift register unit shown in Figure 6 as an example and combining it with the signal timing diagram shown in Figure 7. In the following description, "1" represents a high-level signal, "0" represents a low-level signal, ip represents the input signal of the input signal terminal IP, ck represents the first clock signal of the first clock signal terminal CK, cb represents the second clock signal of the second clock signal terminal CB, and ot represents the output signal of the output signal terminal OT. It should be noted that 1 and 0 are logic levels, which are only for better explanation of the specific working process of the embodiment of the present disclosure, rather than the voltage applied to the gate of each transistor during specific implementation.

[0147] Specifically, the voltage value of the first reference signal vgl outputted from the first reference signal terminal VGL is a negative voltage, the voltage value of the second reference signal vgh outputted from the second reference signal terminal VGH is a positive voltage, and all transistors are N-type transistors. For illustration, the four stages of the signal timing diagram shown in FIG7 , namely, the first stage f1, the second stage f2, the third stage f3, and the fourth stage f4, are selected. It should be noted that the signal timing diagram shown in FIG7 only represents the operating process of a certain shift register unit in the current frame. The operating processes of the shift register unit in other frames are substantially the same as the operating process in the current frame, and are not further described herein.

[0148] In the first stage f1, ip=1, ck=1, cb=0;

[0149] Since the input signal ip provides a high level, the first clock signal ck provides a high level, and the second clock signal cb provides a low level, the first transistor T1 and the third transistor T3 are both turned on, the high level of the input signal ip is provided to the first node N1, the second transistor T2, the sixth transistor T6, and the eighth transistor T8 are all turned on, the high level of the first clock signal ck is provided to the third node N3, the fourth transistor T4 is turned on, the low level of the second clock signal cb is provided to the fourth node N4, the fifth transistor T5 is turned off, the low level of the first reference signal vgl is provided to the second node N2, the seventh transistor T7 is turned off, and the high level of the second reference signal vgh is provided to the output signal terminal OT, and the output signal terminal OT outputs a high level.

[0150] In the second stage f2, ip = 0, ck = 0, cb = 1;

[0151] Since the input signal ip provides a low level, the first clock signal ck provides a low level, and the second clock signal cb provides a high level, the first transistor T1 and the third transistor T3 are both turned off, the first node N1 maintains a high level, the second transistor T2, the sixth transistor T6, and the eighth transistor T8 are all turned on, the low level of the first clock signal ck is provided to the third node N3, the fourth transistor T4 is turned off, the fifth transistor T5 is turned on, the second node N2 maintains a low level, the seventh transistor T7 is turned off, the low level of the second node N2 is provided to the fourth node N4, the high level of the second reference signal vgh is provided to the output signal terminal OT, and the output signal terminal OT outputs a high level.

[0152] In the third stage f3, ip = 0, ck = 1, cb = 0;

[0153] Since the input signal ip provides a low level, the first clock signal ck provides a high level, and the second clock signal cb provides a low level, the first transistor T1 and the third transistor T3 are both turned on, the low level of the input signal ip is provided to the first node N1, the second transistor T2, the sixth transistor T6, and the eighth transistor T8 are all turned off, the third node N3 is at a high level, the fourth transistor T4 is turned on, the low level of the second clock signal cb is provided to the fourth node N4, the fifth transistor T5 is turned off, the second node N2 maintains a low level, the seventh transistor T7 is turned off, and the output signal terminal OT outputs a high level.

[0154] In the fourth stage f4, ip = 0, ck = 0, cb = 1;

[0155] Since the input signal ip provides a low level, the first clock signal ck provides a low level, and the second clock signal cb provides a high level, the first transistor T1 and the third transistor T3 are both turned off, the first node N1 maintains a low level, the second transistor T2, the sixth transistor T6, and the eighth transistor T8 are all turned off, the third node N3 maintains a high level, the fourth transistor T4 is turned on, the high level of the second clock signal cb is provided to the fourth node N4, the fifth transistor T5 is turned on, the second node N2 is a high level, the seventh transistor T7 is turned on, the low level of the first reference signal vgl is provided to the output signal terminal OT, and the output signal terminal OT outputs a low level.

[0156] It should be noted that in the exemplary embodiment shown in FIG6 , the potential of the third node N3 can be reduced from 35V to 17V, thereby significantly reducing the bias voltage environment of the related transistors and improving the stability of the shift register unit. The disclosed embodiment also provides another structural schematic diagram of a shift register unit, as shown in FIG8 , which is a modification of the embodiment described above. The following only describes the differences between this embodiment and the above-described embodiment, and the similarities thereto are not repeated here.

[0157] In the embodiment of the present disclosure, as shown in FIG8 , the shift register unit further includes a voltage stabilizing circuit 40 ;

[0158] The voltage stabilizing circuit 40 is coupled to the third node N3 and configured to maintain the potential of the third node N3.

[0159] In the exemplary embodiment shown in FIG8 , the voltage stabilizing circuit 40 includes a first capacitor C1;

[0160] A first electrode of the first capacitor C1 is coupled to the third node N3 , and a second electrode of the first capacitor C1 is coupled to the second reference signal terminal VGH.

[0161] In a specific implementation process, the first capacitor C1 can maintain the potential of the third node N3, thereby improving the stability of the voltage of the third node N3 and effectively avoiding the problem of excessive bias voltage of the third node N3.

[0162] In an embodiment of the present disclosure, as shown in FIG8 , the control signal terminal CT and the second reference signal terminal VGH are the same signal terminal.

[0163] For example, the control signal terminal CT and the second reference signal terminal VGH may be coupled together, which can reduce the number of signal lines and ease wiring difficulty.

[0164] The present disclosure also provides another structural diagram of a shift register unit, as shown in Figure 9, which is a modification of the embodiment described above. The following only describes the differences between this embodiment and the above embodiment, and the similarities are not repeated here.

[0165] In an embodiment of the present disclosure, as shown in FIG9 , the control signal terminal CT and the second reference signal terminal VGH are the same signal terminal.

[0166] For example, the control signal terminal CT and the second reference signal terminal VGH may be coupled together, which can reduce the number of signal lines and ease wiring difficulty.

[0167] The present disclosure also provides another structural diagram of a shift register unit, as shown in Figure 10, which is a modification of the embodiment described above. The following only describes the differences between this embodiment and the above embodiment, and the similarities are not repeated here.

[0168] In the embodiment of the present disclosure, as shown in FIG10 , the shift register unit further includes a protection circuit 50 ;

[0169] The third node N3 is coupled to the second control module 22 via the protection circuit 50 . The protection circuit 50 is configured to control conduction and disconnection between the third node N3 and the second control module 22 .

[0170] In an embodiment of the present disclosure, as shown in FIG10 , the control signal terminal CT and the second reference signal terminal VGH are the same signal terminal.

[0171] For example, the control signal terminal CT and the second reference signal terminal VGH may be coupled together, which can reduce the number of signal lines and ease wiring difficulty.

[0172] In the embodiment of the present disclosure, as shown in FIG10 , the protection circuit 50 includes a ninth transistor T9;

[0173] A gate of the ninth transistor T9 is coupled to the second reference signal terminal VGH, a first electrode of the ninth transistor T9 is coupled to the gate of the fourth transistor T4, and a second electrode of the ninth transistor T9 is coupled to the third node N3.

[0174] In a specific implementation, the ninth transistor T9 is turned on under the control of the active level of the second reference signal provided by the second reference signal terminal VGH, and is turned off under the control of the inactive level of the second reference signal. Exemplarily, the ninth transistor T9 is configured as an N-type transistor, in which case the active level of the second reference signal is a high level, and the inactive level of the second reference signal is a low level. When the ninth transistor T9 is in the on state, the gate of the fourth transistor T4 can be electrically connected to the third node N3; when the ninth transistor T9 is in the off state, the gate of the fourth transistor T4 can be disconnected from the third node N3.

[0175] The present disclosure also provides another structural diagram of a shift register unit, as shown in Figure 11, which is a modification of the embodiment described above. The following only describes the differences between this embodiment and the above embodiment, and the similarities are not repeated here.

[0176] In the embodiment of the present disclosure, as shown in FIG11 , the shift register unit further includes a protection circuit 50 ;

[0177] The third node N3 is coupled to the second control module 22 via the protection circuit 50 . The protection circuit 50 is configured to control conduction and disconnection between the third node N3 and the second control module 22 .

[0178] In an embodiment of the present disclosure, as shown in FIG11 , the control signal terminal CT and the first clock signal terminal CK are the same signal terminal.

[0179] For example, the control signal terminal CT and the first clock signal terminal CK may be coupled together, which can reduce the number of signal lines and reduce wiring difficulty.

[0180] In the embodiment of the present disclosure, as shown in FIG11 , the protection circuit 50 includes a ninth transistor T9;

[0181] A gate of the ninth transistor T9 is coupled to the second reference signal terminal VGH, a first electrode of the ninth transistor T9 is coupled to the gate of the fourth transistor T4, and a second electrode of the ninth transistor T9 is coupled to the third node N3.

[0182] In a specific implementation, the ninth transistor T9 is turned on under the control of the active level of the second reference signal provided by the second reference signal terminal VGH, and is turned off under the control of the inactive level of the second reference signal. Exemplarily, the ninth transistor T9 is configured as an N-type transistor, in which case the active level of the second reference signal is a high level, and the inactive level of the second reference signal is a low level. When the ninth transistor T9 is in the on state, the gate of the fourth transistor T4 can be electrically connected to the third node N3; when the ninth transistor T9 is in the off state, the gate of the fourth transistor T4 can be disconnected from the third node N3.

[0183] The present disclosure also provides another structural diagram of a shift register unit, as shown in Figure 12, which is a modification of the embodiment described above. The following only describes the differences between this embodiment and the above embodiment, and the similarities are not repeated here.

[0184] In the embodiment of the present disclosure, as shown in FIG12 , the shift register unit further includes a voltage stabilizing circuit 40 ;

[0185] The voltage stabilizing circuit 40 is coupled to the third node N3 and configured to maintain the potential of the third node N3.

[0186] In the embodiment of the present disclosure, as shown in FIG12 , the voltage stabilizing circuit 40 includes a first capacitor C1;

[0187] A first electrode of the first capacitor C1 is coupled to the third node N3 , and a second electrode of the first capacitor C1 is coupled to the second reference signal terminal VGH.

[0188] In a specific implementation process, the first capacitor C1 can maintain the potential of the third node N3, thereby improving the stability of the voltage of the third node N3 and effectively avoiding the problem of excessive bias voltage of the third node N3.

[0189] In the embodiment of the present disclosure, as shown in FIG12 , the shift register unit further includes a reset circuit 60 ;

[0190] The reset circuit 60 is coupled to the first node N1 and the fourth node N4 , and is configured to provide the signal of the first reference signal terminal VGL to the first node N1 in response to the signal of the fourth node N4 .

[0191] In the embodiment of the present disclosure, as shown in FIG12 , the reset circuit 60 includes a tenth transistor T10 ;

[0192] A gate of the tenth transistor T10 is coupled to the fourth node N4 , a first electrode of the tenth transistor T10 is coupled to the first node N1 , and a second electrode of the tenth transistor T10 is coupled to the first reference signal terminal VGL.

[0193] In a specific implementation, the tenth transistor T10 is turned on when the active level of the signal transmitted by the fourth node N4 is controlled, and is turned off when the inactive level of the signal transmitted by the fourth node N4 is controlled. Exemplarily, the tenth transistor T10 is configured as an N-type transistor, and the active level of the signal transmitted by the fourth node N4 is a high level, and the inactive level of the signal transmitted by the fourth node N4 is a low level. When the tenth transistor T10 is in the on state, the first node N1 and the fourth node N4 can be connected; when the tenth transistor T10 is in the off state, the first node N1 and the fourth node N4 can be disconnected.

[0194] The above is merely an example to illustrate the specific structure of the shift register unit provided in the embodiment of the present disclosure. In specific implementation, the specific structure of the above circuits is not limited to the above structure provided in the embodiment of the present disclosure, and can also be other structures known to those skilled in the art, which is not limited here.

[0195] Based on the same disclosed concept, as shown in FIG13 to FIG17 , the embodiment of the present disclosure further provides a shift register unit, including:

[0196] a first transistor T1, wherein a first electrode of the first transistor T1 is directly connected to the first node N1;

[0197] a second transistor T2, wherein a gate of the second transistor T2 is directly connected to the first node N1, and a second electrode of the second transistor T2 is coupled to a third node N3;

[0198] a sixth transistor T6, wherein a gate of the sixth transistor T6 is directly connected to the first node N1, and a second electrode of the sixth transistor T6 is coupled to the second node N2;

[0199] an eighth transistor T8, wherein a gate of the eighth transistor T8 is directly connected to the first node N1, a first electrode of the eighth transistor T8 is coupled to the second reference signal terminal VGH, and a second electrode of the eighth transistor T8 is coupled to the output signal terminal OT;

[0200] The first node N1 is not controlled by the second node N2 or the third node N3.

[0201] In the exemplary embodiments shown in FIG. 14 and FIG. 15 , the shift register unit further includes:

[0202] A first capacitor C1; a first electrode of the first capacitor C1 is coupled to the third node N3, and a second electrode of the first capacitor C1 is coupled to the second reference signal terminal VGH.

[0203] In the embodiment of the present disclosure, as shown in FIG14 and FIG15 , the shift register unit further includes:

[0204] a third transistor T3, wherein a first electrode of the third transistor T3 is coupled to the third node N3, and a second electrode of the third transistor T3 is coupled to the control signal terminal CT;

[0205] a fourth transistor T4, wherein a gate of the fourth transistor T4 is coupled to the third node N3, and a first electrode of the fourth transistor T4 is coupled to the fourth node N4;

[0206] a fifth transistor T5, wherein a first electrode of the fifth transistor T5 is coupled to the second node N2, and a second electrode of the fifth transistor T5 is coupled to the fourth node N4;

[0207] a seventh transistor T7, wherein a gate of the seventh transistor T7 is coupled to the second node N2, and a first electrode of the seventh transistor T7 is coupled to the output signal terminal OT;

[0208] a second capacitor C2, wherein a first electrode of the second capacitor C2 is coupled to the second node N2, and a second electrode of the second capacitor C2 is coupled to the first reference signal terminal VGL;

[0209] A third capacitor C3 , wherein a first electrode of the third capacitor C3 is coupled to the first node N1 , and a second electrode of the third capacitor C3 is coupled to the output signal terminal OT.

[0210] In the embodiment of the present disclosure, as shown in FIG14 and FIG15 , the gate of the first transistor T1 is coupled to the first clock signal terminal CK, and the second electrode of the first transistor T1 is coupled to the input signal terminal IP;

[0211] A first electrode of the second transistor T2 is coupled to the first clock signal terminal CK;

[0212] The gate of the third transistor T3 is coupled to the first clock signal terminal CK;

[0213] The second electrode of the fourth transistor T4 is coupled to the second clock signal terminal CB;

[0214] The gate of the fifth transistor T5 is coupled to the second clock signal terminal CB;

[0215] A first electrode of the sixth transistor T6 is coupled to the first reference signal terminal VGL;

[0216] The second electrode of the seventh transistor T7 is coupled to the second reference signal terminal VGH;

[0217] A second electrode of the eighth transistor T8 is coupled to the output signal terminal OT.

[0218] In an embodiment of the present disclosure, as shown in FIG14 , the control signal terminal CT and the first clock signal terminal CK are the same signal terminal.

[0219] In an embodiment of the present disclosure, as shown in FIG15 , the control signal terminal CT and the second reference signal terminal VGH are the same signal terminal.

[0220] In the embodiment of the present disclosure, as shown in FIG16 , the shift register unit further includes a ninth transistor T9;

[0221] A gate of the ninth transistor T9 is coupled to the second reference signal terminal VGH, and a second electrode of the ninth transistor T9 is coupled to the third node N3.

[0222] In the embodiment of the present disclosure, as shown in FIG17 , the shift register unit further includes a tenth transistor T10 ;

[0223] A gate of the tenth transistor T10 is coupled to the fourth node N4 , a first electrode of the tenth transistor T10 is coupled to the first node N1 , and a second electrode of the tenth transistor T10 is coupled to the first reference signal terminal VGL.

[0224] The above is merely an example to illustrate the specific structure of the shift register unit provided in the embodiment of the present disclosure. In specific implementation, the specific structure of the above circuits is not limited to the above structure provided in the embodiment of the present disclosure, and can also be other structures known to those skilled in the art, which is not limited here.

[0225] In a specific implementation process, the principle of solving the problem by the shift register unit is similar to that of the aforementioned shift register unit. Therefore, the implementation of the shift register unit can refer to the description of the aforementioned part, and the repeated parts will not be repeated.

[0226] Based on the same disclosed concept, an embodiment of the present disclosure also provides a drive control circuit, comprising a plurality of cascaded shift register units; the input signal end of the first-stage shift register unit is coupled to the frame trigger signal end; in each two adjacent stages of shift register units, the input signal end of the next-stage shift register unit is coupled to the output signal end of the previous-stage shift register unit.

[0227] For example, as shown in FIG18 , the drive control circuit includes a plurality of cascaded shift register units SR1, SR2, SR3, ..., SRn-2, SRn-1, and SRn; wherein n is a natural number greater than 6. The value of n depends on actual design requirements. The shift register unit can adopt the shift register unit shown in FIG6 , and each shift register unit includes an input signal terminal, an output signal terminal, a first clock signal terminal, and a second clock signal terminal. Each endpoint receives the signal marked in the timing diagram shown in Figure 7: the input signal terminal of shift register unit SR1 is coupled to the frame trigger signal terminal, where stv represents the frame trigger signal provided by the frame trigger signal terminal. For each of the remaining shift register units, the signal output terminal of the previous shift register unit is coupled to the input signal terminal of the next shift register unit. That is, the signal output from the output signal terminal of shift register unit SR1 can serve as the signal for the input signal terminal of shift register unit SR2, the signal output from the output signal terminal of shift register unit SR2 can serve as the signal for the input signal terminal of shift register unit SR3, and so on. The signal output from the output signal terminal of shift register unit SRn-1 can serve as the signal for the input signal terminal of shift register unit SRn, and so on, until there are no more shift register units in the next stage. The first clock signal terminal receives the first clock signal, and the second clock signal terminal receives the second clock signal. The timing of other drive control circuits can be inferred based on the connection relationship between the shift register units and the timing diagram shown in Figure 7 and will not be further described here. This drive control circuit can be configured in a liquid crystal display panel or an electroluminescent display panel, without limitation.

[0228] Specifically, the specific structure of each shift register unit in the above-mentioned drive control circuit is the same as the above-mentioned shift register unit in the present disclosure in terms of function and structure, and the repeated parts are not repeated here. The drive control circuit can be configured in a liquid crystal display panel or an electroluminescent display panel, without limitation here.

[0229] Based on the same disclosed concept, embodiments of the present disclosure further provide a display device, including the aforementioned drive control circuit provided in embodiments of the present disclosure. The principles underlying the problem solved by this display device are similar to those of the aforementioned drive control circuit. Therefore, the implementation of this display device can refer to the implementation of the aforementioned drive control circuit, and any repetitions will not be repeated here.

[0230] In specific implementations, in the embodiments of the present disclosure, the display device can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigation system, or the like. Other essential components of the display device are well understood by those skilled in the art and are not detailed here, nor should they be construed as limitations of the present disclosure.

[0231] In a specific implementation, the display device may include multiple pixel units, multiple gate lines, and data lines. Each pixel unit may include multiple sub-pixels, such as red sub-pixels, green sub-pixels, and blue sub-pixels. The display device provided in the embodiments of the present disclosure may be an organic light-emitting display device or a liquid crystal display device, without limitation.

[0232] In an embodiment of the present disclosure, a display device includes a plurality of scan lines; each of the plurality of scan lines is provided with a corresponding drive control circuit; and one scan line is electrically connected to a signal output terminal of a first-stage shift register unit in the drive control circuit. For example, when the display device provided in an embodiment of the present disclosure is a liquid crystal display device, the TFT in the sub-pixel can be electrically connected to the scan line, and the drive control circuit can function as a gate drive circuit, and the gate drive circuit is electrically connected to the scan line and is used to provide a gate scan signal to the TFT in the sub-pixel. It should be noted that the TFT in the sub-pixel can be an N-type transistor or a P-type transistor, and this is not limited here.

[0233] In an embodiment of the present disclosure, a display device includes multiple light-emitting control signal lines and multiple scan lines; a drive control circuit is provided for each of the multiple light-emitting control signal lines; one light-emitting control signal line is electrically connected to the signal output terminal of a first-stage shift register unit in the drive control circuit. Furthermore, a drive control circuit is also provided for each of the multiple scan lines; one scan line is electrically connected to the signal output terminal of a first-stage shift register unit in the drive control circuit. For example, an organic light-emitting display device generally includes multiple organic light-emitting diodes and pixel circuits connected to each organic light-emitting diode. The pixel circuits generally include a light-emitting control transistor for controlling the light emission of the organic light-emitting diodes and a scan control transistor for controlling the input of data signals.

[0234] In a specific implementation, when the display device provided in the embodiment of the present disclosure is an organic light-emitting display device, the light-emitting control transistor can be electrically connected to the light-emitting control signal line, and the scan control transistor can be electrically connected to the scan line. The organic light-emitting display device can include the above-mentioned drive control circuit provided in the embodiment of the present disclosure, and the drive control circuit can serve as a light-emitting drive circuit, and the light-emitting drive circuit is electrically connected to the light-emitting control transistor, and is used to provide a light-emitting control signal for the light-emitting control transistor; or the drive control circuit can also serve as a gate drive circuit, and the gate drive circuit is electrically connected to the scan line, and is used to provide a gate scan signal for the scan control transistor. Of course, the organic light-emitting display device can also include two of the above-mentioned drive control circuits provided in the embodiment of the present disclosure, one of which can serve as a light-emitting drive circuit, and is electrically connected to the light-emitting control transistor, and is used to provide a light-emitting control signal for the light-emitting control transistor; and the other drive control circuit serves as a gate drive circuit, and is electrically connected to the scan line, and is used to provide a gate scan signal for the scan control transistor. This is not limited here.

[0235] Based on the same disclosed concept, as shown in FIG19 , an embodiment of the present disclosure further provides a driving method of the above-mentioned shift register unit, including:

[0236] S101: In the first stage, the input circuit responds to the signal of the first clock signal end and provides the signal of the input signal end to the first node; the control circuit responds to the signal of the first node and provides the signal of the first clock signal end and the signal of the first reference signal end to the third node and the second node, and controls the potential of the second node to be opposite to the potential of the first node; the output circuit responds to the signal of the first node and provides the signal of the second reference signal end to the output signal end.

[0237] In the embodiment of the present disclosure, still referring to FIG19 , after the first stage, the driving method further includes:

[0238] S102: In a second stage, the control circuit provides the signal of the first clock signal terminal and the signal of the first reference signal terminal to the third node and the second node in response to the signal of the first node, and controls the potential of the second node to be opposite to the potential of the first node; the output circuit provides the signal of the second reference signal terminal to the output signal terminal in response to the signal of the first node;

[0239] S103: In a third stage, the input circuit provides the signal of the input signal terminal to the first node in response to the signal of the first clock signal terminal; the control circuit provides the signal of the first clock signal terminal and the signal of the first reference signal terminal to the third node and the second node in response to the signal of the first node, controlling the potential of the second node to be opposite to the potential of the first node; the output circuit provides the signal of the second reference signal terminal to the output signal terminal in response to the signal of the first node;

[0240] S104: In the fourth stage, the control circuit responds to the signal of the first node, provides the signal of the first clock signal end and the signal of the first reference signal end to the third node and the second node, and controls the potentials of the first node and the second node to be opposite; the output circuit responds to the signal of the second node, provides the signal of the first reference signal end to the output signal end.

[0241] The driving principle and specific implementation of the driving method are the same as those of the shift register unit in the above embodiment. Therefore, the driving method can be implemented with reference to the specific implementation of the shift register unit in the above embodiment, which will not be repeated here.

[0242] The shift register unit, drive control circuit, display device, and drive method provided by the embodiments of the present disclosure control the signal at the first node via an input circuit; control the signals at the second and third nodes via a control circuit, without affecting the signal at the first node; and control the signal at the output signal terminal via an output circuit. The entire shift register unit utilizes a small number of components and low circuit complexity, resulting in low production costs, a simple circuit structure, and a small footprint, facilitating narrow-frame designs. Furthermore, the coordination of these components improves the stability of the signal outputted from the output signal terminal.

[0243] Although the preferred embodiments of the present disclosure have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concepts. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present disclosure.

[0244] Obviously, those skilled in the art may make various changes and modifications to the present disclosure without departing from the spirit and scope of the present disclosure. Thus, if these modifications and variations of the present disclosure fall within the scope of the claims of the present disclosure and their equivalents, the present disclosure is intended to include these modifications and variations.

Claims

1. A shift register unit, wherein: include: an input circuit coupled to the first node and configured to provide a signal at an input signal terminal to the first node in response to a signal at a first clock signal terminal; a control circuit coupled to the first node, the second node, the control signal terminal and the first reference signal terminal, and configured to provide the signals of the first clock signal terminal and the first reference signal terminal to a third node and the second node respectively in response to the signal of the first node, wherein the first node is not controlled by the second node or the third node; The output circuit is coupled to the first node and the second node, and is configured to provide the signal of the first reference signal terminal to the output signal terminal in response to the signal of the second node, and to provide the signal of the second reference signal terminal to the output signal terminal in response to the signal of the first node.

2. The shift register unit according to claim 1, wherein: The control circuit includes a first control module, a second control module and a third control module; The first control module is coupled to the first node and the third node, and is configured to provide the signal of the first clock signal terminal to the third node in response to the signal of the first node, and to provide the signal of the control signal terminal to the third node in response to the signal of the first clock signal terminal; The second control module is coupled to the second node and the third node, and is configured to provide the signal of the second clock signal terminal to the second node in response to the signal of the third node and the second clock signal terminal; The third control module is coupled to the first node and the second node, and is configured to provide a signal at a first reference signal terminal to the second node in response to a signal at the first node.

3. The shift register unit according to claim 1, wherein: Also includes a voltage stabilizing circuit; The voltage stabilization circuit is coupled to the third node and is configured to maintain the potential of the third node.

4. The shift register unit according to claim 3, wherein: The voltage stabilizing circuit includes a first capacitor; A first electrode of the first capacitor is coupled to the third node, and a second electrode of the first capacitor is coupled to the second reference signal terminal.

5. The shift register unit according to claim 2 or 4, wherein: Also includes protection circuits; The third node is coupled to the second control module through the protection circuit, and the protection circuit is configured to control conduction and disconnection between the third node and the second control module.

6. The shift register unit according to claim 1, wherein: The control signal terminal and the first clock signal terminal are the same signal terminal.

7. The shift register unit according to claim 1, wherein: The control signal terminal and the second reference signal terminal are the same signal terminal.

8. The shift register unit according to claim 1, wherein: The input circuit includes a first transistor; A gate of the first transistor is coupled to the first clock signal terminal, a first electrode of the first transistor is coupled to the first node, and a second electrode of the first transistor is coupled to the input signal terminal.

9. The shift register unit according to claim 2, wherein: The first control module includes a second transistor and a third transistor; The gate of the second transistor is coupled to the first node, the first electrode of the second transistor is coupled to the first clock signal terminal, and the second electrode of the second transistor is coupled to the third node; A gate of the third transistor is coupled to the first clock signal terminal, a first electrode of the third transistor is coupled to the third node, and a second electrode of the third transistor is coupled to the control signal terminal.

10. The shift register unit according to claim 2, wherein: The second control module includes a fourth transistor and a fifth transistor; The gate of the fourth transistor is coupled to the third node, the first electrode of the fourth transistor is coupled to the fourth node, and the second electrode of the fourth transistor is coupled to the second clock signal terminal; A gate of the fifth transistor is coupled to the second clock signal terminal, a first electrode of the fifth transistor is coupled to the second node, and a second electrode of the fifth transistor is coupled to the fourth node.

11. The shift register unit according to claim 1, wherein: Also includes a reset circuit; The reset circuit is coupled to the first node and the fourth node, and is configured to provide the signal of the first reference signal terminal to the first node in response to a signal of the fourth node.

12. The shift register unit according to claim 2, wherein: The third control module includes a sixth transistor; A gate of the sixth transistor is coupled to the first node, a first electrode of the sixth transistor is coupled to the first reference signal terminal, and a second electrode of the sixth transistor is coupled to the second node.

13. The shift register unit according to claim 1, wherein: The output circuit includes a seventh transistor, a second capacitor, an eighth transistor and a third capacitor; The gate of the seventh transistor is coupled to the second node, the first electrode of the seventh transistor is coupled to the output signal terminal, and the second electrode of the seventh transistor is coupled to the second reference signal terminal; A first electrode of the second capacitor is coupled to the second node, and a second electrode of the second capacitor is coupled to the first reference signal terminal; The gate of the eighth transistor is coupled to the first node, the first electrode of the eighth transistor is coupled to the second reference signal terminal, and the second electrode of the eighth transistor is coupled to the output signal terminal; A first electrode of the third capacitor is coupled to the first node, and a second electrode of the third capacitor is coupled to the output signal terminal.

14. The shift register unit according to claim 5, wherein: The protection circuit includes a ninth transistor; The gate of the ninth transistor is coupled to the second reference signal terminal, the first electrode of the ninth transistor is coupled to the gate of the fourth transistor, and the second electrode of the ninth transistor is coupled to the third node.

15. The shift register unit according to claim 11, wherein: The reset circuit includes a tenth transistor; The gate of the tenth transistor is coupled to the fourth node, and the first electrode of the tenth transistor is connected to the The first node is coupled to the first reference signal terminal, and the second electrode of the tenth transistor is coupled to the first reference signal terminal.

16. A shift register unit, wherein: include: a first transistor, wherein a first electrode of the first transistor is directly connected to the first node; a second transistor, wherein a gate of the second transistor is directly connected to the first node, and a second electrode of the second transistor is coupled to a third node; a sixth transistor, wherein a gate of the sixth transistor is directly connected to the first node, and a second electrode of the sixth transistor is coupled to the second node; an eighth transistor, wherein a gate of the eighth transistor is directly connected to the first node, a first electrode of the eighth transistor is coupled to the second reference signal terminal, and a second electrode of the eighth transistor is coupled to the output signal terminal; The first node is not controlled by the second node or the third node.

17. The shift register unit according to claim 16, wherein: Also includes: a first capacitor; A first electrode of the first capacitor is coupled to the third node, and a second electrode of the first capacitor is coupled to the second reference signal terminal.

18. The shift register unit according to claim 16 or 17, wherein: Also included is a ninth transistor; A gate of the ninth transistor is coupled to the second reference signal terminal, and a second electrode of the ninth transistor is coupled to the third node.

19. The shift register unit according to claim 18, wherein: Also including a tenth transistor; A gate of the tenth transistor is coupled to the fourth node, a first electrode of the tenth transistor is coupled to the first node, and a second electrode of the tenth transistor is coupled to the first reference signal terminal.

20. The shift register unit according to claim 16, wherein: Also includes: a third transistor, a first electrode of the third transistor being coupled to the third node, and a second electrode of the third transistor being coupled to the control signal terminal; a fourth transistor, a gate of the fourth transistor being coupled to the third node, and a first electrode of the fourth transistor being coupled to the fourth node; a fifth transistor, a first electrode of the fifth transistor being coupled to the second node, and the fifth transistor The second electrode of the transistor is coupled to the fourth node; a seventh transistor, a gate of the seventh transistor being coupled to the second node, and a first electrode of the seventh transistor being coupled to the output signal terminal; a second capacitor, wherein a first electrode of the second capacitor is coupled to the second node, and a second electrode of the second capacitor is coupled to the first reference signal terminal; A third capacitor, wherein a first electrode of the third capacitor is coupled to the first node, and a second electrode of the third capacitor is coupled to the output signal terminal.

21. The shift register unit as claimed in claim 20, wherein: The gate of the first transistor is coupled to the first clock signal terminal, and the second electrode of the first transistor is coupled to the input signal terminal; A first electrode of the second transistor is coupled to the first clock signal terminal; The gate of the third transistor is coupled to the first clock signal terminal; The second electrode of the fourth transistor is coupled to the second clock signal terminal; The gate of the fifth transistor is coupled to the second clock signal terminal; The first electrode of the sixth transistor is coupled to the first reference signal terminal; The second electrode of the seventh transistor is coupled to the second reference signal terminal; The second electrode of the eighth transistor is coupled to the output signal terminal.

22. The shift register unit as claimed in claim 21, wherein: The control signal terminal and the first clock signal terminal are the same signal terminal.

23. The shift register unit according to claim 21, wherein: The control signal terminal and the second reference signal terminal are the same signal terminal.

24. A drive control circuit, wherein: include: A plurality of cascaded shift register units according to any one of claims 1 to 15 and 16 to 23; The input signal terminal of the first-stage shift register unit is coupled to the frame trigger signal terminal; In each of two adjacent shift register units, the input signal terminal of the next shift register unit is coupled to the output signal terminal of the previous shift register unit.

25. A display device, wherein: include: A drive control circuit as claimed in claim 24.

26. A method for driving a shift register unit according to any one of claims 1 to 15 and 16 to 23, wherein: include: In the first stage, the input circuit provides the signal at the input signal terminal to the first node in response to the signal at the first clock signal terminal; The control circuit provides the signal of the first clock signal terminal and the signal of the first reference signal terminal to the third node and the second node in response to the signal of the first node, and controls the potential of the second node to be opposite to the potential of the first node; The output circuit provides the signal of the second reference signal terminal to the output signal terminal in response to the signal of the first node.

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