Display substrate and display device

Abstract

According to the display substrate and the display device, in the display substrate, a grid electrode of a first reset transistor (T1) is coupled with a corresponding first reset signal line (Rst1), a first pole of the first reset transistor (T1) is coupled with a corresponding first initialization signal line (Vinit1), and a second pole of the first reset transistor (T1) is coupled with a grid electrode (T3-g) of a driving transistor (T3); the grid electrode of the compensation transistor (T2) is coupled with the corresponding first scanning line (GA1), the first pole of the compensation transistor (T2) is coupled with the second pole of the driving transistor (T3), and the second pole of the compensation transistor (T2) is coupled with the grid electrode (T3-g) of the driving transistor (T3); the first reset transistor (T1) comprises a first reset active layer (21), the compensation transistor (T2) comprises a compensation active layer (22), the first reset active layer (21) comprises at least a part extending along a first direction, the compensation active layer (22) comprises at least a part extending along the first direction, and the first reset active layer (21) and the compensation active layer (22) are arranged along the first direction.

Description

Display substrate and display device Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display substrate and a display device. Background Art

[0002] Low-temperature polycrystalline silicon oxide (LTPO) technology, with its advantages of high charge mobility, fast pixel response speed, and low power consumption, is increasingly being used in display products. With the development of mobile phones and wearable devices, the demand for higher display resolution is increasing. The higher the resolution of LTPO displays, the smaller the layout space occupied by sub-pixel driver circuits.

[0003] Summary of the Invention

[0004] An object of the present disclosure is to provide a display substrate and a display device.

[0005] In order to achieve the above objectives, the present disclosure provides the following technical solutions:

[0006] A first aspect of the present disclosure provides a display substrate, comprising: a base substrate and a plurality of sub-pixels each disposed on the base substrate, a plurality of first reset signal lines, a plurality of first scan lines, and a plurality of first initialization signal lines; the sub-pixels comprising a sub-pixel driving circuit, the sub-pixel driving circuit comprising a driving transistor, a first reset transistor, and a compensation transistor;

[0007] The gate of the first reset transistor is coupled to the corresponding first reset signal line, the first electrode of the first reset transistor is coupled to the corresponding first initialization signal line, and the second electrode of the first reset transistor is coupled to the gate of the driving transistor; the gate of the compensation transistor is coupled to the corresponding first scan line, the first electrode of the compensation transistor is coupled to the second electrode of the driving transistor, and the second electrode of the compensation transistor is coupled to the gate of the driving transistor;

[0008] The first reset transistor includes a first reset active layer, the compensation transistor includes a compensation active layer, the first reset active layer includes at least a portion extending along a first direction, the compensation active layer includes at least a portion extending along the first direction, and the first reset active layer and the compensation active layer are arranged along the first direction.

[0009] Optionally, the display substrate further comprises a plurality of power lines, and the power lines include at least a portion extending along the first direction;

[0010] The orthographic projection of the power line on the base substrate at least partially overlaps with the orthographic projection of the first reset active layer on the base substrate; and / or the orthographic projection of the power line on the base substrate at least partially overlaps with the orthographic projection of the compensation active layer on the base substrate.

[0011] Optionally, the first reset active layer includes a first reset channel portion, an orthographic projection of the first reset channel portion on the base substrate overlaps with an orthographic projection of the gate of the first reset transistor on the base substrate; the compensation active layer includes a compensation channel portion, an orthographic projection of the compensation channel portion on the base substrate overlaps with an orthographic projection of the gate of the compensation transistor on the base substrate;

[0012] The orthographic projection of the power line on the base substrate covers the orthographic projection of the first reset channel portion on the base substrate; and / or the orthographic projection of the power line on the base substrate covers the orthographic projection of the compensation channel portion on the base substrate.

[0013] Optionally, the gate of the driving transistor is coupled to the second electrode of the first reset transistor and the second electrode of the compensation transistor through a first conductive connection portion; the orthographic projection of the power line on the substrate at least partially overlaps with the orthographic projection of the first conductive connection portion on the substrate.

[0014] Optionally, the orthographic projection of the power line on the base substrate completely covers the orthographic projection of the first conductive connection portion on the base substrate.

[0015] Optionally, the display substrate further includes a plurality of second scan lines and a plurality of data lines, the data lines including at least a portion extending along the first direction; the sub-pixel driving circuit further includes a data writing transistor, a gate of the data writing transistor being coupled to the corresponding second scan line, a first electrode of the data writing transistor being coupled to the corresponding data line, and a second electrode of the data writing transistor being coupled to the first electrode of the driving transistor;

[0016] At least a portion of an orthographic projection of the first conductive connection portion on the base substrate is located between an orthographic projection of the compensation active layer on the base substrate and an orthographic projection of the data line on the base substrate.

[0017] Optionally, the second scanning line includes a plurality of first scanning portions and a plurality of second scanning portions, the first scanning portions and the second scanning portions are alternately arranged along a second direction, the second direction intersects the first direction, and along the first direction, a width of the first scanning portion is greater than a width of the second scanning portion;

[0018] The orthographic projection of the first scanning portion on the substrate at least partially overlaps with the orthographic projection of the first end of the first conductive connection portion on the substrate, and the first end of the first conductive connection portion is coupled to the second electrode of the first reset transistor and the second electrode of the compensation transistor.

[0019] Optionally, the display substrate further includes a light shielding layer, and the driving transistor includes a driving active layer;

[0020] The light-shielding layer includes a plurality of light-shielding main body portions, a plurality of first light-shielding connecting portions and a plurality of second light-shielding connecting portions. The light-shielding main body portions adjacent to each other along the first direction are coupled to each other through the corresponding first light-shielding connecting portions, and the light-shielding main body portions adjacent to each other along the second direction are coupled to each other through the corresponding second light-shielding connecting portions, and the second direction intersects with the first direction; the orthographic projection of the light-shielding main body portion on the base substrate at least partially overlaps with the orthographic projection of the corresponding driving active layer on the base substrate.

[0021] Optionally, the first light-shielding connecting portion includes a strip structure extending along the first direction.

[0022] Optionally, at least a portion of the orthographic projection of the first light-shielding connection portion on the base substrate is located between the orthographic projection of the compensation active layer on the base substrate and the orthographic projection of the first conductive connection portion on the base substrate.

[0023] Optionally, an orthographic projection of the first light-shielding connection portion on the base substrate at least partially overlaps with an orthographic projection of the power line on the base substrate.

[0024] Optionally, an orthographic projection of the first light-shielding connection portion on the base substrate and an orthographic projection of the power line on the base substrate have a first overlapping area, and the first overlapping area is greater than or equal to 90% of an area of ​​the first light-shielding connection portion.

[0025] Optionally, the display substrate further includes a plurality of light-emitting control signal lines; the sub-pixel further includes a light-emitting element; the sub-pixel driving circuit further includes a light-emitting control transistor, the gate of the light-emitting control transistor is coupled to the corresponding light-emitting control signal line, the first electrode of the light-emitting control transistor is coupled to the second electrode of the driving transistor, and the second electrode of the light-emitting control transistor is coupled to the anode of the light-emitting element in sequence through the second conductive connection part and the third conductive connection part; the power line includes a groove, and at least a portion of the third conductive connection part is located in the groove.

[0026] Optionally, the orthographic projection of the second conductive connection portion on the base substrate at least partially overlaps with the orthographic projection of the light-emitting control signal line on the base substrate; and / or the orthographic projection of the third conductive connection portion on the base substrate at least partially overlaps with the orthographic projection of the light-emitting control signal line on the base substrate.

[0027] Optionally, the sub-pixel driving circuit further includes a power control transistor, wherein a gate of the power control transistor is coupled to a corresponding light emitting control signal line, a first electrode of the power control transistor is coupled to the corresponding power line, and a second electrode of the power control transistor is coupled to the first electrode of the driving transistor;

[0028] The power control transistor includes a power control active layer, and at least part of the orthographic projection of the bottom of the groove on the base substrate is located between the orthographic projection of the third conductive connection portion on the base substrate and the orthographic projection of the power control active layer on the base substrate.

[0029] Optionally, the display substrate further includes a plurality of data lines, and the orthographic projection of the power control active layer on the base substrate at least partially overlaps with the orthographic projection of the data lines on the base substrate.

[0030] Optionally, the display substrate further includes a plurality of second reset signal lines and a plurality of second initialization signal lines; the sub-pixel driving circuit further includes a second reset transistor, wherein a gate of the second reset transistor is coupled to the corresponding second reset signal line, a first electrode of the second reset transistor is coupled to the corresponding second initialization signal line, and a second electrode of the second reset transistor is coupled to the anode of the light-emitting element;

[0031] The light emission control transistor includes a light emission control active layer; the second reset transistor includes a second reset active layer, and the second reset active layer and the light emission control active layer are arranged along the first direction.

[0032] Optionally, the first scanning line includes a plurality of third scanning portions and a plurality of fourth scanning portions, the third scanning portions and the fourth scanning portions are alternately arranged along a second direction, the second direction intersects the first direction, and along the first direction, a width of the third scanning portion is greater than a width of the fourth scanning portion;

[0033] The orthographic projection of the third scanning portion on the base substrate at least partially overlaps with the orthographic projection of the compensation active layer on the base substrate; the orthographic projection of the fourth scanning portion on the base substrate at least partially overlaps with the orthographic projection of the first conductive connecting portion on the base substrate.

[0034] Optionally, the display substrate further includes a plurality of power compensation lines arranged along the first direction, the power compensation lines including a plurality of first compensation portions and a plurality of second compensation portions, the first compensation portions and the second compensation portions being alternately arranged along the second direction, the first compensation portions including at least a portion extending along the first direction, the second compensation portions including at least a portion extending along the second direction, and adjacent first compensation portions and second compensation portions being coupled;

[0035] The second compensation portion is coupled to the power line; at least part of the orthographic projection of the first compensation portion on the base substrate is located between the orthographic projection of the data line on the base substrate and the orthographic projection of the first conductive connection portion on the base substrate.

[0036] Based on the technical solution of the above-mentioned display substrate, a second aspect of the present disclosure provides a display device including the above-mentioned display substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] The drawings described herein are used to provide a further understanding of the present disclosure and constitute a part of the present disclosure. The exemplary embodiments of the present disclosure and their descriptions are used to explain the present disclosure and do not constitute an improper limitation of the present disclosure. In the drawings:

[0038] FIG1 is a schematic diagram of a circuit structure of a sub-pixel driving circuit provided in an embodiment of the present disclosure;

[0039] FIG2 is a schematic cross-sectional view of a portion of a film layer of a display substrate provided by an embodiment of the present disclosure;

[0040] FIG3 is a schematic diagram of the layout of a light shielding layer in a display substrate provided by an embodiment of the present disclosure;

[0041] FIG4 is a schematic diagram of the layout of a polysilicon active layer in a display substrate provided by an embodiment of the present disclosure;

[0042] FIG5 is a schematic diagram of the layout of the first gate metal layer in the display substrate provided by an embodiment of the present disclosure;

[0043] FIG6 is a schematic diagram of the layout of the second gate metal layer in the display substrate provided by an embodiment of the present disclosure;

[0044] FIG7 is a schematic diagram of the layout of an oxide active layer in a display substrate provided by an embodiment of the present disclosure;

[0045] FIG8 is a schematic diagram of the layout of the third gate metal layer in the display substrate provided by an embodiment of the present disclosure;

[0046] FIG9 is a schematic diagram showing the layout of some via holes on an interlayer insulating layer in a display substrate according to an embodiment of the present disclosure;

[0047] FIG10 is a schematic diagram showing the layout of some via holes on an interlayer insulating layer in a display substrate according to an embodiment of the present disclosure;

[0048] FIG11 is a schematic diagram of the layout of a first source / drain metal layer in a display substrate provided by an embodiment of the present disclosure;

[0049] FIG12 is a schematic diagram of a via hole formed on a passivation layer in a display substrate according to an embodiment of the present disclosure;

[0050] FIG13 is a schematic diagram of a via hole formed on a first planar layer in a display substrate provided by an embodiment of the present disclosure;

[0051] FIG14 is a schematic diagram showing the layout of a second source / drain metal layer in a display substrate provided by an embodiment of the present disclosure;

[0052] FIG15 is a schematic diagram showing the layout of a polysilicon active layer and a first gate metal layer in a display substrate provided by an embodiment of the present disclosure;

[0053] FIG16 is a schematic diagram of a layout with a light shielding layer added based on FIG15;

[0054] FIG17 is a schematic diagram of a layout in which a second gate metal layer is added on the basis of FIG15;

[0055] FIG18 is a schematic diagram showing the layout of an oxide active layer, a second gate metal layer, and a third gate metal layer in a display substrate provided by an embodiment of the present disclosure;

[0056] FIG19 is a schematic diagram of a layout in which a first source / drain metal layer is added on the basis of FIG15 ;

[0057] FIG20 is a schematic diagram of a layout in which an interlayer insulating layer and a first source / drain metal layer are added on the basis of FIG18 ;

[0058] FIG21 is a schematic diagram of a layout in which an oxide active layer and a third gate metal layer are added to FIG17;

[0059] FIG22 is a schematic diagram of a layout in which an interlayer insulating layer and a first source / drain metal layer are added on the basis of FIG21;

[0060] FIG23 is a schematic diagram of a layout in which a second source / drain metal layer is added on the basis of FIG22;

[0061] FIG24 is a schematic diagram showing the layout of the first source-drain metal layer and the second source-drain metal layer in the display substrate provided by an embodiment of the present disclosure;

[0062] FIG25 is a schematic diagram showing the layout of the light shielding layer and the second source / drain metal layer in the display substrate provided by an embodiment of the present disclosure;

[0063] FIG26 shows a Just Contact connection method between the first source / drain metal layer and the polysilicon active layer in a display substrate provided by an embodiment of the present disclosure;

[0064] FIG27 shows a side contact connection method between the first source / drain metal layer and the polysilicon active layer in the display substrate provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0065] In order to further illustrate the display substrate and the display device provided by the embodiments of the present disclosure, a detailed description is given below with reference to the accompanying drawings.

[0066] Given a fixed display product size, the higher the resolution, the smaller the layout space occupied by the sub-pixel driver circuit, and the greater the difficulty in laying out the sub-pixel driver circuit. Therefore, how to reduce the difficulty of laying out the sub-pixel driver circuit within the limited layout space has become a pressing technical issue.

[0067] Referring to Figures 1, 6 to 8, and 18 to 23, an embodiment of the present disclosure provides a display substrate, including: a base substrate and a plurality of sub-pixels each disposed on the base substrate, a plurality of first reset signal lines Rst1, a plurality of first scan lines GA1, and a plurality of first initialization signal lines Vinit1; the sub-pixels include a sub-pixel driving circuit, the sub-pixel driving circuit including a driving transistor T3, a first reset transistor T1, and a compensation transistor T2;

[0068] The gate of the first reset transistor T1 is coupled to the corresponding first reset signal line Rst1, the first electrode of the first reset transistor T1 is coupled to the corresponding first initialization signal line Vinit1, and the second electrode of the first reset transistor T1 is coupled to the gate T3-g of the driving transistor T3; the gate of the compensation transistor T2 is coupled to the corresponding first scan line GA1, the first electrode of the compensation transistor T2 is coupled to the second electrode of the driving transistor T3, and the second electrode of the compensation transistor T2 is coupled to the gate T3-g of the driving transistor T3;

[0069] The first reset transistor T1 includes a first reset active layer 21, and the compensation transistor T2 includes a compensation active layer 22. The first reset active layer 21 includes at least a portion extending along a first direction, and the compensation active layer 22 includes at least a portion extending along the first direction. The first reset active layer 21 and the compensation active layer 22 are arranged along the first direction.

[0070] Exemplarily, the display substrate includes a plurality of sub-pixels, and the plurality of sub-pixels include a plurality of sub-pixel driving circuits distributed in an array. The plurality of sub-pixel driving circuits are divided into a plurality of rows of sub-pixel driving circuits and a plurality of columns of sub-pixel driving circuits. The plurality of rows of sub-pixel driving circuits are arranged along a first direction, and each row of sub-pixel driving circuits includes a plurality of sub-pixel driving circuits arranged along a second direction. The plurality of columns of sub-pixel driving circuits are arranged along a second direction, and each column of sub-pixel driving circuits includes a plurality of sub-pixel driving circuits arranged along the first direction. Exemplarily, the first direction and the second direction intersect. For example, the first direction includes a longitudinal direction, and the second direction includes a transverse direction.

[0071] Exemplarily, the sub-pixel includes a sub-pixel driving circuit and a light-emitting element. The sub-pixel driving circuit is coupled to an anode of the light-emitting element and is configured to provide a driving signal to the light-emitting element to drive the light-emitting element to emit light.

[0072] Exemplarily, the plurality of first reset signal lines Rst1 are arranged along the first direction, include at least a portion extending along the second direction, and are used to transmit a first reset signal. The plurality of first reset signal lines Rst1 correspond one-to-one to the plurality of rows of sub-pixel drive circuits, and are coupled to the gates of the first reset transistors T1 in the corresponding row of sub-pixel drive circuits. The first reset signal line Rst1 includes a first reset signal layer Rst11 and a second reset signal layer Rst12. The first reset signal layer Rst11 includes a fifth reset portion 55 and a sixth reset portion 56. Along the first direction, the width L5 of the fifth reset portion 55 is greater than the width L6 of the sixth reset portion 56. The orthographic projection of the fifth reset portion 55 on the substrate at least partially overlaps with the orthographic projection of the first reset active layer 21 on the substrate. The second reset signal layer Rst12 can also be configured in the same manner as the width of the first reset signal layer Rst11, which will not be further described here. This configuration ensures the channel width of the transistors and the yield rate of the transistor characteristics.

[0073] Exemplarily, the plurality of first initialization signal lines Vinit1 are arranged along the first direction, include at least a portion extending along the second direction, and are configured to transmit a first initialization signal. The plurality of first initialization signal lines Vinit1 correspond one-to-one to the plurality of rows of sub-pixel driver circuits, and are coupled to the first electrode of each first reset transistor T1 in a corresponding row of sub-pixel driver circuits.

[0074] Exemplarily, the plurality of first scan lines GA1 are arranged along the first direction, include at least a portion extending along the second direction, and are configured to transmit first scan signals. The plurality of first scan lines GA1 correspond one-to-one to the plurality of rows of sub-pixel driver circuits, and are coupled to the gates of the compensation transistors T2 in the corresponding row of sub-pixel driver circuits.

[0075] Exemplarily, both the first reset transistor T1 and the compensation transistor T2 include oxide transistors, but are not limited thereto.

[0076] Exemplarily, the first reset active layer 21 and the compensation active layer 22 are made of indium gallium zinc oxide (IGZO), but are not limited thereto.

[0077] Exemplarily, the first reset active layer 21 includes a first reset body portion, a first reset end portion, and a second reset end portion. The first reset body portion is coupled to the first reset end portion and the second reset end portion, respectively. The first reset body portion includes a first reset channel portion 210. The orthographic projection of the first reset channel portion 210 on the base substrate overlaps the orthographic projection of the gate of the first reset transistor T1 on the base substrate. The first reset body portion extends along the first direction.

[0078] Exemplarily, the compensation active layer 22 includes a compensation main portion, a first compensation end portion, and a second compensation end portion. The compensation main portion is coupled to the first compensation end portion and the second compensation end portion, respectively. The compensation main portion includes a compensation channel portion 220. The orthographic projection of the compensation channel portion 220 on the base substrate overlaps with the orthographic projection of the gate of the compensation transistor T2 on the base substrate. The compensation main portion extends along the first direction.

[0079] According to the specific structure of the display substrate described above, in the display substrate provided by the embodiments of the present disclosure, the first reset transistor T1 includes a first reset active layer 21, and the compensation transistor T2 includes a compensation active layer 22. The first reset active layer 21 includes at least a portion extending along a first direction, and the compensation active layer 22 includes at least a portion extending along the first direction. The first reset active layer 21 and the compensation active layer 22 are arranged along the first direction. This arrangement enables the first reset transistor T1 and the compensation transistor T2 to be arranged along the first direction, which helps narrow the width of the layout space occupied by the sub-pixel drive circuit in other directions intersecting the first direction. Furthermore, this arrangement can further concentrate the layout of the various structures included in the sub-pixel drive circuit along the first direction, thereby narrowing the width of the layout space occupied by the sub-pixel drive circuit in other directions.

[0080] Therefore, in the display substrate provided in the embodiment of the present disclosure, the layout space occupied by the sub-pixel driving circuit in other directions intersecting with the first direction can be narrowed, the layout space occupied by the sub-pixel driving circuit as a whole can be reduced, and the layout difficulty of the sub-pixel driving circuit in a limited layout space can be reduced, so that the display substrate meets the development needs of high resolution.

[0081] As shown in Figures 14, 18, and 20 to 23, in some embodiments, the display substrate further includes a plurality of power lines VDD, and the power line VDD includes at least a portion extending along the first direction; the orthographic projection of the power line VDD on the base substrate at least partially overlaps with the orthographic projection of the first reset active layer 21 on the base substrate; and / or the orthographic projection of the power line VDD on the base substrate at least partially overlaps with the orthographic projection of the compensation active layer 22 on the base substrate.

[0082] Exemplarily, the plurality of power lines VDD are arranged along the second direction, each power line VDD includes at least a portion extending along the first direction, and each of the plurality of power lines VDD corresponds one-to-one to each of the plurality of columns of sub-pixel driver circuits. Each power line VDD is coupled to a first electrode of each power control transistor T5 in a corresponding column of sub-pixel driver circuits. The power line VDD is configured to transmit a power signal.

[0083] As shown in FIG2 , the display substrate exemplarily includes a buffer layer BF, a light shielding layer BSM, a polysilicon active layer poly, a first gate insulating layer GI1, a first gate metal layer gate1, a second gate insulating layer GI2, a second gate metal layer gate2, a third gate insulating layer GI3, an oxide active layer ACT, a fourth gate insulating layer GI4, a third gate metal layer gate3, an interlayer insulating layer ILD, a first source / drain metal layer SD1, a first planarization layer PLN1, a second source / drain metal layer SD2, a second planarization layer PLN2, an anode layer ANO, a pixel defining layer PDL, a light emitting functional layer EL, a cathode layer cath, a first inorganic encapsulation layer CVD1, an organic encapsulation layer IJP, and a second inorganic encapsulation layer CVD2. A passivation layer PVX may also be provided on the display substrate as needed. The passivation layer PVX may be located between the first source / drain metal layer SD1 and the first planarization layer PLN1, or between the first planarization layer PLN1 and the second source / drain metal layer SD2.

[0084] Exemplarily, the power line VDD and the second source / drain metal layer are provided in the same layer and made of the same material, but the present invention is not limited thereto.

[0085] Exemplarily, the orthographic projection of the power line VDD on the base substrate completely covers the orthographic projection of the first reset active layer 21 on the base substrate; and / or, the orthographic projection of the power line VDD on the base substrate completely covers the orthographic projection of the compensation active layer 22 on the base substrate.

[0086] Illustratively, an overlapping area between an orthographic projection of the power line VDD on the base substrate and an orthographic projection of the first reset active layer 21 on the base substrate is greater than or equal to 95% of the area of ​​the first reset active layer 21. And / or an overlapping area between an orthographic projection of the power line VDD on the base substrate and an orthographic projection of the compensation active layer 22 on the base substrate is greater than or equal to 95% of the area of ​​the compensation active layer 22.

[0087] Exemplarily, the first reset active layer 21 includes a first reset channel portion 210, and the orthographic projection of the first reset channel portion 210 on the base substrate overlaps with the orthographic projection of the gate of the first reset transistor T1 on the base substrate; the compensation active layer 22 includes a compensation channel portion 220, and the orthographic projection of the compensation channel portion 220 on the base substrate overlaps with the orthographic projection of the gate of the compensation transistor T2 on the base substrate;

[0088] The orthographic projection of the power line VDD on the base substrate covers the orthographic projection of the first reset channel portion 210 on the base substrate; and / or the orthographic projection of the power line VDD on the base substrate covers the orthographic projection of the compensation channel portion 220 on the base substrate.

[0089] It is worth noting that due to the characteristics of IGZO, the active layer formed by it needs to be shielded with a metal film layer to prevent light from affecting the characteristics of the transistor.

[0090] In the display substrate provided in the above embodiment, the orthographic projection of the power line VDD on the base substrate is set to at least partially overlap with the orthographic projection of the first reset active layer 21 on the base substrate; and / or the orthographic projection of the power line VDD on the base substrate is set to at least partially overlap with the orthographic projection of the compensation active layer 22 on the base substrate. This allows the power line VDD to block light from irradiating the first reset active layer 21 and / or the compensation active layer 22, thereby ensuring the stability of the first reset transistor T1 and the compensation transistor T2.

[0091] Moreover, since the first reset active layer 21 includes at least a portion extending along the first direction, and the compensation active layer 22 includes at least a portion extending along the first direction, the first reset active layer 21 and the compensation active layer 22 are arranged along the first direction; the width of the layout space occupied by the sub-pixel driving circuit in other directions intersecting with the first direction is narrowed. In this case, the power line VDD is used to shield the first reset active layer 21 and / or the compensation active layer 22, which can narrow the size of the power line VDD in other directions intersecting with the first direction, reduce the layout space occupied by the power line VDD in the first direction, and at the same time improve the transmittance of the display substrate.

[0092] As shown in Figures 5, 11, 14, 15, 19, 22 and 23, in some embodiments, the gate T3-g of the driving transistor T3 is coupled to the second electrode of the first reset transistor T1 and the second electrode of the compensation transistor T2 through a first conductive connection portion 31; the orthographic projection of the power line VDD on the substrate at least partially overlaps with the orthographic projection of the first conductive connection portion 31 on the substrate.

[0093] Exemplarily, the orthographic projection of the power line VDD on the base substrate completely covers the orthographic projection of the first conductive connection portion 31 on the base substrate.

[0094] Exemplarily, the first conductive connection portion 31 and the first source / drain metal layer are provided in the same layer and made of the same material, but the present invention is not limited thereto.

[0095] It is worth noting that the first conductive connection portion 31 is formed as the N1 node in the sub-pixel driving circuit.

[0096] The above-mentioned setting sets the orthographic projection of the power line VDD on the substrate to at least partially overlap with the orthographic projection of the first conductive connection part 31 on the substrate, so that the power line VDD can simultaneously block the first conductive connection part 31 and form a parasitic capacitance between the power line VDD and the first conductive connection part 31 to stabilize the voltage of the N1 node.

[0097] As shown in Figures 4, 5, 11, 14, 15, 19, and 23, in some embodiments, the display substrate further includes a plurality of second scan lines GA2 and a plurality of data lines DA, wherein the data lines DA include at least a portion extending along the first direction; the sub-pixel driving circuit further includes a data writing transistor T4, wherein a gate of the data writing transistor T4 is coupled to the corresponding second scan line GA2, a first electrode of the data writing transistor T4 is coupled to the corresponding data line DA, and a second electrode of the data writing transistor T4 is coupled to the first electrode of the driving transistor T3;

[0098] At least a portion of the orthographic projection of the first conductive connection portion 31 on the base substrate is located between the orthographic projection of the compensation active layer 22 on the base substrate and the orthographic projection of the data line DA on the base substrate.

[0099] As shown in FIG. 4 , illustratively, the data writing transistor T4 includes a data writing active layer 24 .

[0100] Exemplarily, the plurality of second scan lines GA2 are arranged along the first direction, include at least a portion extending along the second direction, and are configured to transmit second scan signals. The plurality of second scan lines GA2 correspond one-to-one to the plurality of rows of sub-pixel driver circuits, and are coupled to the gates of the data write transistors T4 in a corresponding row of sub-pixel driver circuits.

[0101] Exemplarily, the plurality of data lines DA are arranged along the second direction, each data line DA including at least a portion extending along the first direction, and are configured to transmit data signals. The plurality of data lines DA correspond one-to-one to the plurality of columns of sub-pixel driver circuits, and each data line DA is coupled to the first electrode of each data write transistor T4 in the corresponding column of sub-pixel driver circuits.

[0102] The above-mentioned setting method can arrange the first conductive connection part 31, the compensation active layer 22 and the data line DA in an orderly manner, which not only reduces the difficulty of connecting the first conductive connection part 31 with the second electrode of the first reset transistor T1 and the second electrode of the compensation transistor T2, but also helps to narrow the layout space occupied by the sub-pixel driving circuit in the first direction.

[0103] As shown in FIG5 , FIG15 , FIG21 , and FIG22 , in some embodiments, the second scanning line GA2 includes a plurality of first scanning portions GA21 and a plurality of second scanning portions GA22 . The first scanning portions GA21 and the second scanning portions GA22 are alternately arranged along a second direction, the second direction intersecting the first direction. Along the first direction, a width L1 of the first scanning portion GA21 is greater than a width L2 of the second scanning portion GA22 .

[0104] The orthographic projection of the first scanning portion GA21 on the base substrate at least partially overlaps with the orthographic projection of the first end portion of the first conductive connecting portion 31 on the base substrate, and the first end portion of the first conductive connecting portion 31 is coupled to the second electrode of the first reset transistor T1 and the second electrode of the compensation transistor T2.

[0105] Exemplarily, the adjacent first scanning portion GA21 and the second scanning portion GA22 form an integrated structure, and the second scanning line GA2 is provided in the same layer and material as the first gate metal layer.

[0106] Exemplarily, the orthographic projection of the first scanning portion GA21 on the base substrate at least partially overlaps with the orthographic projection of the first reset active layer 21 on the base substrate, and the orthographic projection of the first scanning portion GA21 on the base substrate at least partially overlaps with the orthographic projection of the compensation active layer 22 on the base substrate.

[0107] As shown in FIG6 to FIG8, FIG11, FIG18 and FIG20, in some embodiments, the first scanning line GA1 includes a plurality of third scanning portions 53 and a plurality of fourth scanning portions 54, the third scanning portions 53 and the fourth scanning portions 54 are alternately arranged along a second direction, the second direction intersecting the first direction, and along the first direction, a width L3 of the third scanning portion 53 is greater than a width L4 of the fourth scanning portion 54;

[0108] The orthographic projection of the third scanning portion 53 on the substrate at least partially overlaps with the orthographic projection of the compensation active layer 22 on the substrate; the orthographic projection of the fourth scanning portion 54 on the substrate at least partially overlaps with the orthographic projection of the first conductive connecting portion 31 on the substrate.

[0109] Exemplarily, the first scan line GA1 includes a first scan layer GA11 and a second scan layer GA12. The first scan layer GA11 is formed from the same layer and material as the second gate metal layer, and the second scan layer GA12 is formed from the same layer and material as the third gate metal layer. The first scan layer GA11 includes multiple third scan sections 53 and multiple fourth scan sections 54. The second scan layer GA12 includes multiple third scan sections 53 and multiple fourth scan sections 54. The third scan sections 53 and the fourth scan sections 54, which are adjacent to each other and belong to the same layer, form an integrated structure.

[0110] Exemplarily, the orthographic projection of the third scanning portion 53 on the substrate does not overlap with the orthographic projection of the first conductive connection portion 31 on the substrate, and the orthographic projection of the fourth scanning portion 54 on the substrate at least partially overlaps with the orthographic projection of the first conductive connection portion 31 on the substrate.

[0111] In the above arrangement, the orthographic projection of the fourth scanning portion 54 on the substrate at least partially overlaps with the orthographic projection of the first conductive connection portion 31 on the substrate; and the orthographic projection of the first scanning portion GA21 on the substrate at least partially overlaps with the orthographic projection of the first end portion of the first conductive connection portion 31 on the substrate. Because the scanning signals transmitted by the first scanning line GA1 and the second scanning line GA2 have opposite effects on the potential of the first conductive connection portion 31, this arrangement can offset the effects of the scanning signals transmitted by the first scanning line GA1 and the second scanning line GA2 on the potential of the first conductive connection portion 31, thereby ensuring the stability of the potential of the first conductive connection portion 31.

[0112] As shown in Figures 3, 4, 15 and 16, in some embodiments, the display substrate further includes a light-shielding layer BSM, and the driving transistor T3 includes a driving active layer 23; the light-shielding layer BSM includes a plurality of light-shielding main body portions BSM0, a plurality of first light-shielding connection portions BSM1 and a plurality of second light-shielding connection portions BSM2, the light-shielding main body portions BSM0 adjacent along the first direction are coupled to each other through the corresponding first light-shielding connection portions BSM1, and the light-shielding main body portions BSM0 adjacent along the second direction are coupled to each other through the corresponding second light-shielding connection portions BSM2, and the second direction intersects with the first direction; the orthographic projection of the light-shielding main body portion BSM0 on the base substrate at least partially overlaps with the orthographic projection of the corresponding driving active layer 23 on the base substrate.

[0113] Exemplarily, the multiple light-shielding main body portions BSM0 correspond one-to-one to the multiple driving active layers 23 included in the multiple sub-pixel driving circuits in the multiple sub-pixels, and the orthographic projection of the light-shielding main body portion BSM0 on the substrate at least partially overlaps with the orthographic projection of the corresponding driving active layer 23 on the substrate. For example, the driving active layer 23 includes a driving channel portion, and the orthographic projection of the driving channel portion on the substrate overlaps with the orthographic projection of the gate T3-g of the driving transistor T3 on the substrate. The orthographic projection of the light-shielding main body portion BSM0 on the substrate completely covers the orthographic projection of the driving channel portion of the corresponding driving active layer 23 on the substrate.

[0114] In the display substrate provided in the above embodiment, by setting the orthographic projection of the light-shielding main body portion BSM0 on the base substrate to at least partially overlap with the orthographic projection of the corresponding driving active layer 23 on the base substrate, the light-shielding main body portion BSM0 can block the light from irradiating the driving active layer 23, thereby ensuring the characteristics of the driving transistor T3.

[0115] As shown in FIG. 3 , FIG. 4 , FIG. 15 and FIG. 16 , in some embodiments, the first light-shielding connection portion BSM1 includes a strip structure extending along the first direction.

[0116] Exemplarily, at least a portion of the orthographic projection of the first light-shielding connection portion BSM1 on the base substrate is located between the orthographic projection of the compensation active layer 22 on the base substrate and the orthographic projection of the first conductive connection portion 31 on the base substrate.

[0117] Exemplarily, at least a portion of the orthographic projection of the first light-shielding connection portion BSM1 on the base substrate is located between the orthographic projection of the first reset active layer 21 on the base substrate and the orthographic projection of the data line DA on the base substrate.

[0118] The above-mentioned setting method enables the first light-shielding connection part BSM1 to avoid the channel part included in the transistor, that is, the orthographic projection of the first light-shielding connection part BSM1 on the substrate does not overlap with the orthographic projection of the channel part included in the transistor on the substrate, thereby avoiding the first light-shielding connection part BSM1 from affecting the operation of the transistor.

[0119] The above-mentioned setting method enables the first light-shielding connection part BSM1 to avoid the via hole that penetrates the interlayer insulating layer, thereby ensuring the manufacturing yield of the display substrate. In more detail, as shown in Figures 26 and 27, the specific methods of achieving connection between the first source and drain metal layer SD1 and the polysilicon active layer poly through via holes include Side Contact and Just Contact. The resistance and fluctuation of the Side Contact method are relatively good (the fluctuation is only 1 / 6) and Just Contact requires surface management of the overlapping area on the upper part of the polysilicon active layer poly, and also ensures a high-precision etching process. In comparison, Side Contact is better. When using the Side Contact method, the polysilicon active layer poly needs to be broken down. If the light-shielding layer BSM is located below the broken-down polysilicon active layer poly and is close to the broken-down polysilicon active layer poly, there is a risk of a short circuit between the first source and drain metal layer SD1 and the polysilicon active layer poly.

[0120] The display substrate adopts the above-mentioned layout method so that the first light-shielding connection part BSM1 can be routed vertically without bending. This layout method can narrow the layout space occupied by the sub-pixel driving circuit in other directions intersecting with the first direction, reduce the overall layout space occupied by the sub-pixel driving circuit, and reduce the layout difficulty of the sub-pixel driving circuit within the limited layout space, so that the display substrate meets the development needs of high resolution.

[0121] As shown in FIG. 25 , in some embodiments, the orthographic projection of the first light-shielding connection portion BSM1 on the base substrate at least partially overlaps with the orthographic projection of the power line VDD on the base substrate.

[0122] Exemplarily, an orthographic projection of the first light-shielding connection portion BSM1 on the base substrate and an orthographic projection of the power line VDD on the base substrate have a first overlapping area, and the first overlapping area is greater than or equal to 90% of an area of ​​the first light-shielding connection portion BSM1.

[0123] Illustratively, the orthographic projection of the first light-shielding connecting portion BSM1 on the base substrate completely covers the orthographic projection of the power line VDD on the base substrate.

[0124] In the display substrate provided by the above embodiment, the orthographic projection of the first light-shielding connection portion BSM1 on the base substrate is set to at least partially overlap with the orthographic projection of the power line VDD on the base substrate, so that the first light-shielding connection portion BSM1 can be blocked by the power line VDD. While improving the transmittance of the display substrate, it can also reduce the layout space occupied by the first light-shielding connection portion BSM1 itself in the horizontal direction. This design is very helpful for high-resolution projects, especially for optimizing the horizontal space of Real RGB projects.

[0125] As shown in Figures 14, 21, 23, 24 and 25, in some embodiments, the display substrate further includes a plurality of light-emitting control signal lines EM; the sub-pixel further includes a light-emitting element; the sub-pixel driving circuit further includes a light-emitting control transistor T6, the gate of the light-emitting control transistor T6 is coupled to the corresponding light-emitting control signal line EM, the first electrode of the light-emitting control transistor T6 is coupled to the second electrode of the driving transistor T3, and the second electrode of the light-emitting control transistor T6 is coupled to the anode of the light-emitting element through the second conductive connection portion 32 and the third conductive connection portion 33 in sequence; the power line VDD includes a groove 40, and at least a portion of the third conductive connection portion 33 is located in the groove 40.

[0126] Exemplarily, the plurality of emission control signal lines EM are arranged along the first direction, and the emission control signal lines EM include at least a portion extending along the second direction. The plurality of emission control signal lines EM correspond one-to-one with the plurality of rows of sub-pixel driving circuits. The emission control signal lines EM are respectively coupled to the gates of each power control transistor T5 and each emission control transistor T6 in a corresponding row of sub-pixel driving circuits. The emission control signal lines EM are used to transmit emission control signals.

[0127] Exemplarily, the second conductive connection portion 32 is provided in the same layer and material as the first source-drain metal layer, the third conductive connection portion 33 is provided in the same layer and material as the second source-drain metal layer, and the power line VDD is provided in the same layer and material as the second source-drain metal layer.

[0128] By arranging the power line VDD to include a groove 40, at least a portion of the third conductive connection portion 33 is located within the groove 40, which can narrow the layout space occupied by the third conductive connection portion 33 and the power line VDD in other directions intersecting with the first direction, thereby reducing the difficulty of layout of the sub-pixel driving circuit within the limited layout space, so that the display substrate meets the development requirements of high resolution.

[0129] As shown in Figures 19, 20, 23 and 24, in some embodiments, the orthographic projection of the second conductive connection portion 32 on the substrate at least partially overlaps with the orthographic projection of the light-emitting control signal line EM on the substrate; and / or the orthographic projection of the third conductive connection portion 33 on the substrate at least partially overlaps with the orthographic projection of the light-emitting control signal line EM on the substrate.

[0130] The above configuration is beneficial to improving the transmittance of the display substrate.

[0131] As shown in Figures 14, 21, 23, 24 and 25, in some embodiments, the sub-pixel driving circuit further includes a power control transistor T5, a gate of the power control transistor T5 is coupled to the corresponding light emitting control signal line EM, a first electrode of the power control transistor T5 is coupled to the corresponding power line VDD, and a second electrode of the power control transistor T5 is coupled to the first electrode of the driving transistor T3; the power control transistor T5 includes a power control active layer 25, and at least a part of the positive projection of the bottom of the groove 40 on the substrate is located between the positive projection of the third conductive connection portion 33 on the substrate and the positive projection of the power control active layer 25 on the substrate.

[0132] The above-mentioned setting method rationally utilizes the layout space of the display substrate, can narrow the layout space occupied by the sub-pixel driving circuit in other directions intersecting with the first direction, reduce the overall layout space occupied by the sub-pixel driving circuit, and reduce the layout difficulty of the sub-pixel driving circuit within the limited layout space, so that the display substrate meets the development needs of high resolution.

[0133] As shown in FIG4 , FIG15 and FIG23 , in some embodiments, the display substrate further includes a plurality of data lines DA, and the orthographic projection of the power control active layer 25 on the base substrate at least partially overlaps with the orthographic projection of the data lines DA on the base substrate.

[0134] This arrangement can narrow the layout space occupied by the sub-pixel driver circuit in directions other than the first direction, reducing the overall layout space occupied by the sub-pixel driver circuit and lowering the difficulty of laying out the sub-pixel driver circuit within this limited layout space, thereby enabling the display substrate to meet the development requirements of high resolution. Furthermore, this arrangement is also beneficial in improving the transmittance of the display substrate.

[0135] As shown in Figures 4, 15 and 19, in some embodiments, the display substrate further includes a plurality of second reset signal lines Rst2 and a plurality of second initialization signal lines Vinit2; the sub-pixel driving circuit further includes a second reset transistor T7, a gate of the second reset transistor T7 is coupled to the corresponding second reset signal line Rst2, a first electrode of the second reset transistor T7 is coupled to the corresponding second initialization signal line Vinit2, and a second electrode of the second reset transistor T7 is coupled to the anode of the light-emitting element; the light-emitting control transistor T6 includes a light-emitting control active layer 26; the second reset transistor T7 includes a second reset active layer 27, and the second reset active layer 27 and the light-emitting control active layer 26 are arranged along the first direction.

[0136] Exemplarily, the plurality of second reset signal lines Rst2 are arranged along the first direction, and the second reset signal lines Rst2 include at least a portion extending along the second direction. The plurality of second reset signal lines Rst2 correspond one-to-one to the plurality of rows of sub-pixel driving circuits, and the second reset signal lines Rst2 are respectively coupled to the gates of the second reset transistors T7 in the corresponding row of sub-pixel driving circuits. The second reset signal lines Rst2 are used to transmit a second reset signal.

[0137] Exemplarily, the plurality of second initialization signal lines Vinit2 are arranged along the first direction, and the second initialization signal lines Vinit2 include at least a portion extending along the second direction. The plurality of second initialization signal lines Vinit2 correspond one-to-one to the plurality of rows of sub-pixel driver circuits, and each second initialization signal line Vinit2 is coupled to the first electrode of each second reset transistor T7 in a corresponding row of sub-pixel driver circuits. The second initialization signal line Vinit2 is configured to transmit a second initialization signal.

[0138] Exemplarily, the second initialization signal line Vinit2 is provided in the same layer and with the same material as the first source / drain metal layer.

[0139] The above-mentioned arrangement of the second reset active layer 27 and the light-emitting control active layer 26 along the first direction can narrow the layout space occupied by the sub-pixel driving circuit in other directions intersecting with the first direction, reduce the overall layout space occupied by the sub-pixel driving circuit, and reduce the layout difficulty of the sub-pixel driving circuit within the limited layout space, so that the display substrate meets the development requirements of high resolution.

[0140] The specific structure of the sub-pixel driving circuit is varied.

[0141] As shown in Figures 1 to 25, in some embodiments, the display substrate includes a first reset signal line Rst1, a second reset signal line Rst2, an emission control signal line EM, a first scan line GA1, a second scan line GA2, a first initialization signal line, a second initialization signal line Vinit2, a power line VDD, and a data line DA. The sub-pixel driving circuit includes a driving transistor T3, a compensation transistor T2, a data writing transistor T4, a first reset transistor T1, a second reset transistor T7, a power control transistor T5, an emission control transistor T6, and a storage capacitor Cst.

[0142] The gate of the first reset transistor T1 is coupled to the corresponding first reset signal line Rst1, the first electrode of the first reset transistor T1 is coupled to the first initialization signal line, and the second electrode of the first reset transistor T1 is coupled to the gate T3-g of the driving transistor T3 (ie, the first node N1).

[0143] The gate of the compensation transistor T2 is coupled to the corresponding first scan line GA1, the first electrode of the compensation transistor T2 is coupled to the second electrode of the driving transistor T3 (ie, the third node N3), and the second electrode of the compensation transistor T2 is coupled to the gate T3-g of the driving transistor T3.

[0144] The gate of the data writing transistor T4 is coupled to the corresponding second scan line GA2, the first electrode of the data writing transistor T4 is coupled to the corresponding data line DA, and the second electrode of the data writing transistor T4 is coupled to the first electrode of the driving transistor T3 (i.e., the second node N2).

[0145] The gate of the power control transistor T5 is coupled to the corresponding light emitting control signal line EM, the first electrode of the power control transistor T5 is coupled to the corresponding power line VDD, and the second electrode of the power control transistor T5 is coupled to the first electrode of the driving transistor T3.

[0146] The gate of the light-emitting control transistor T6 is coupled to the corresponding light-emitting control signal line EM, the first electrode of the light-emitting control transistor T6 is coupled to the second electrode of the driving transistor T3, and the second electrode of the light-emitting control transistor T6 is coupled to the anode of the corresponding light-emitting element (i.e., node N4). The cathode of the light-emitting element receives a negative power supply signal VSS.

[0147] The first plate Cst1 of the storage capacitor Cst is coupled to the gate T3 - g of the driving transistor T3 , and the second plate Cst2 of the storage capacitor Cst is coupled to the corresponding power line VDD.

[0148] Exemplarily, the first reset transistor T1 and the compensation transistor T2 include oxide transistors, and the driving transistor T3, the data writing transistor T4, the power control transistor T5, the light emission control transistor T6 and the second reset transistor T7 include low-temperature polysilicon transistors.

[0149] As shown in FIG11 , FIG23 and FIG24 , in some embodiments, the display substrate further includes a plurality of power compensation lines VDD0 arranged along the first direction, the power compensation line VDD0 including a plurality of first compensation portions VDD01 and a plurality of second compensation portions VDD02, the first compensation portions VDD01 and the second compensation portions VDD02 being alternately arranged along the second direction, the first compensation portions VDD01 including at least a portion extending along the first direction, the second compensation portions VDD02 including at least a portion extending along the second direction, and adjacent first compensation portions VDD01 and second compensation portions VDD02 being coupled;

[0150] The second compensation part VDD02 is coupled to the power line VDD; at least part of the orthographic projection of the first compensation part VDD01 on the base substrate is located between the orthographic projection of the data line DA on the base substrate and the orthographic projection of the first conductive connection part 31 on the base substrate.

[0151] Exemplarily, the first compensation part VDD01 and the second compensation part VDD02 are formed into an integrated structure. The power compensation line VDD0 and the first source-drain metal layer are provided in the same layer and made of the same material.

[0152] Exemplarily, the second compensation part VDD02 is coupled to the second plate Cst2 of the storage capacitor Cst and the first electrode of the power control transistor T5 respectively.

[0153] The display substrate is configured to further include a power compensation line VDD0, so that a grid structure is formed between the power compensation line VDD0 and the power line VDD, thereby effectively reducing the overall load of the film layer for transmitting the power signal and improving the uniformity of the power signal.

[0154] At least part of the orthographic projection of the first compensation part VDD01 on the base substrate is located between the orthographic projection of the data line DA on the base substrate and the orthographic projection of the first conductive connection part 31 on the base substrate, so that the first compensation part VDD01 can effectively shield the interference of the data signal transmitted by the data line DA on the signal on the first conductive connection part 31, thereby well ensuring the stability of the N1 node.

[0155] The power compensation line VDD0 is configured to include a first compensation portion VDD01 , so that the first compensation portion VDD01 can well compensate for the flatness of the anode in the display substrate.

[0156] As shown in FIG9 , FIG10 , FIG11 , FIG12 , FIG13 , FIG15 , FIG19 and FIG22 , the first electrode of the second reset transistor T7 is coupled to the second initialization signal line Vinit2 through the first via Via1 .

[0157] A first electrode of the power control transistor T5 is coupled to the first compensation portion VDD01 through a second via Via2 , and a second compensation portion VDD02 is coupled to the power line VDD through a fifteenth via Via15 and an eighteenth via Via18 .

[0158] The second electrode of the second reset transistor T7 and the second electrode of the light emission control transistor T6 are coupled to the second conductive connection portion 32 through the third via Via3. The second conductive connection portion 32 is coupled to the third conductive connection portion 33 through the fourteenth via Via14 and the seventeenth via Via17.

[0159] The second plate Cst2 of the storage capacitor Cst is coupled to the first compensation portion VDD01 through a fourth via Via4 and a fifth via Via5 .

[0160] The first conductive connection portion 31 is coupled to the gate T3 - g of the driving transistor T3 through the sixth via Via6 , and to the second electrode of the first reset transistor T1 and the second electrode of the compensation transistor T2 through the twelfth via Via12 .

[0161] The first electrode of the compensation transistor T2 is coupled to the fourth conductive connection portion 34 through the eleventh via hole Via11. The fourth conductive connection portion 34 is coupled to the second electrode of the driving transistor T3 through the seventh via hole Via7.

[0162] The first electrode of the data writing transistor T4 is coupled to the fifth conductive connection portion 35 through the eighth via Via8. The fifth conductive connection portion 35 is coupled to the data line DA through the sixteenth via Via16 and the nineteenth via Via19.

[0163] The sixth conductive connection portion 36 is coupled to the first initialization signal line Vinit1 through the ninth via Via9 , and the sixth conductive connection portion 36 is coupled to the first electrode of the first reset transistor T1 through the thirteenth via Via13 .

[0164] An embodiment of the present disclosure further provides a display device, comprising the display substrate provided by the above embodiment.

[0165] It should be noted that the display device can be any product or component with a display function, such as a television, a monitor, a digital photo frame, a mobile phone, a tablet computer, etc., wherein the display device also includes a flexible circuit board, a printed circuit board and a backplane.

[0166] In the display substrate provided by the above embodiment, the first reset transistor includes a first reset active layer, the compensation transistor includes a compensation active layer, the first reset active layer includes at least a portion extending along a first direction, the compensation active layer includes at least a portion extending along the first direction, and the first reset active layer and the compensation active layer are arranged along the first direction. This arrangement enables the first reset transistor and the compensation transistor to be arranged along the first direction, which helps narrow the width of the layout space occupied by the sub-pixel drive circuit in directions other than the first direction. Furthermore, this arrangement can further concentrate the various structures included in the sub-pixel drive circuit along the first direction, thereby narrowing the width of the layout space occupied by the sub-pixel drive circuit in other directions. Therefore, the display substrate provided by the above embodiment can narrow the layout space occupied by the sub-pixel drive circuit in directions other than the first direction, reducing the overall layout space occupied by the sub-pixel drive circuit and lowering the difficulty of arranging the sub-pixel drive circuit within a limited layout space, thereby enabling the display substrate to meet the development needs of high resolution.

[0167] Therefore, the display device provided by the embodiment of the present disclosure also has the above-mentioned beneficial effects when it includes the above-mentioned display substrate, which will not be described in detail here.

[0168] It should be noted that the signal line extending along the X-direction means that the signal line includes a main portion and a secondary portion connected to the main portion, the main portion is a line, a line segment, or a strip-shaped body, the main portion extends along the X-direction, and the length of the main portion extending along the X-direction is greater than the length of the secondary portion extending along other directions.

[0169] It should be noted that the layout area occupied by each sub-pixel driving circuit may be an area that can accommodate the sub-pixel driving circuit. Exemplarily, the area may be a rectangular area, but is not limited thereto.

[0170] It should be noted that the "same layer" in the embodiment of the present disclosure may refer to a film layer on the same structural layer. Or, for example, a film layer in the same layer may be a film layer formed by using the same film forming process to form a specific pattern, and then patterning the film layer using the same mask through a single composition process to form a layer structure. Depending on the specific pattern, a single composition process may include multiple exposure, development or etching processes, and the specific pattern in the formed layer structure may be continuous or discontinuous. These specific patterns may also be at different heights or have different thicknesses.

[0171] In the various method embodiments of the present disclosure, the serial numbers of the steps cannot be used to limit the order of the steps. For ordinary technicians in this field, without paying any creative work, changes to the order of the steps are also within the scope of protection of the present disclosure.

[0172] It should be noted that the various embodiments in this specification are described in a progressive manner. Similar parts between the various embodiments can be referred to in conjunction with each other. Each embodiment focuses on the differences from other embodiments. In particular, the method embodiments are described briefly because they are generally similar to the product embodiments. For relevant parts, refer to the description of the product embodiments.

[0173] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by persons of ordinary skill in the field to which this disclosure belongs. The words "first", "second" and similar terms used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect", "couple" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0174] It will be understood that when an element such as a layer, film, region, or substrate is referred to as being “on” or “under” another element, it can be “directly on” or “under” the other element or intervening elements may be present.

[0175] In the description of the above embodiments, specific features, structures, materials or characteristics may be combined in an appropriate manner in any one or more embodiments or examples.

[0176] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A display substrate, comprising: A base substrate and a plurality of sub-pixels, a plurality of first reset signal lines, a plurality of first scan lines and a plurality of first initialization signal lines, all of which are arranged on the base substrate; the sub-pixels include a sub-pixel driving circuit, and the sub-pixel driving circuit includes a driving transistor, a first reset transistor and a compensation transistor; The gate of the first reset transistor is coupled to the corresponding first reset signal line, the first electrode of the first reset transistor is coupled to the corresponding first initialization signal line, and the second electrode of the first reset transistor is coupled to the gate of the driving transistor; the gate of the compensation transistor is coupled to the corresponding first scan line, the first electrode of the compensation transistor is coupled to the second electrode of the driving transistor, and the second electrode of the compensation transistor is coupled to the gate of the driving transistor; The first reset transistor includes a first reset active layer, the compensation transistor includes a compensation active layer, the first reset active layer includes at least a portion extending along a first direction, the compensation active layer includes at least a portion extending along the first direction, and the first reset active layer and the compensation active layer are arranged along the first direction.

2. The display substrate according to claim 1, wherein: The display substrate further comprises a plurality of power lines, wherein the power lines include at least a portion extending along the first direction; The orthographic projection of the power line on the substrate at least partially overlaps with the orthographic projection of the first reset active layer on the substrate; And / or, an orthographic projection of the power line on the substrate at least partially overlaps with an orthographic projection of the compensation active layer on the substrate.

3. The display substrate according to claim 2, wherein: The first reset active layer includes a first reset channel portion, the orthographic projection of the first reset channel portion on the substrate overlaps with the orthographic projection of the gate of the first reset transistor on the substrate; the compensation active layer includes a compensation channel portion, the orthographic projection of the compensation channel portion on the substrate overlaps with the orthographic projection of the gate of the compensation transistor on the substrate; The orthographic projection of the power line on the base substrate covers the orthographic projection of the first reset channel portion on the base substrate; And / or, the orthographic projection of the power line on the base substrate covers the orthographic projection of the compensation channel portion on the base substrate.

4. The display substrate according to claim 2 or 3, wherein: The gate of the driving transistor is coupled to the second electrode of the first reset transistor and the second electrode of the compensation transistor through a first conductive connection portion; the orthographic projection of the power line on the substrate at least partially overlaps with the orthographic projection of the first conductive connection portion on the substrate.

5. The display substrate according to claim 4, wherein: The orthographic projection of the power line on the base substrate completely covers the orthographic projection of the first conductive connection portion on the base substrate.

6. The display substrate according to claim 4, wherein: The display substrate further includes a plurality of second scan lines and a plurality of data lines, wherein the data lines include at least a portion extending along the first direction; the sub-pixel driving circuit further includes a data writing transistor, wherein a gate of the data writing transistor is coupled to the corresponding second scan line, a first electrode of the data writing transistor is coupled to the corresponding data line, and a second electrode of the data writing transistor is coupled to the first electrode of the driving transistor; At least a portion of an orthographic projection of the first conductive connection portion on the base substrate is located between an orthographic projection of the compensation active layer on the base substrate and an orthographic projection of the data line on the base substrate.

7. The display substrate according to claim 6, wherein: The second scanning line includes a plurality of first scanning portions and a plurality of second scanning portions, the first scanning portions and the second scanning portions are alternately arranged along a second direction, the second direction intersects the first direction, and along the first direction, the width of the first scanning portion is greater than the width of the second scanning portion; The orthographic projection of the first scanning portion on the substrate at least partially overlaps with the orthographic projection of the first end of the first conductive connection portion on the substrate, and the first end of the first conductive connection portion is coupled to the second electrode of the first reset transistor and the second electrode of the compensation transistor.

8. The display substrate according to claim 4, wherein: The display substrate further includes a light shielding layer, and the driving transistor includes a driving active layer; The light shielding layer includes a plurality of light shielding main body parts, a plurality of first light shielding connecting parts and a plurality of second light shielding connecting parts, the light shielding main body parts adjacent to each other along the first direction are coupled through the corresponding first light shielding connecting parts, and the light shielding main body parts adjacent to each other along the second direction are coupled through the corresponding second light shielding connecting parts, and the second direction intersects with the first direction; An orthographic projection of the light-shielding main body portion on the base substrate at least partially overlaps with an orthographic projection of the corresponding driving active layer on the base substrate.

9. The display substrate according to claim 8, wherein: The first light-shielding connecting portion includes a strip structure extending along the first direction.

10. The display substrate according to claim 9, wherein: At least a portion of the orthographic projection of the first light-shielding connection portion on the base substrate is located between the orthographic projection of the compensation active layer on the base substrate and the orthographic projection of the first conductive connection portion on the base substrate.

11. The display substrate according to claim 9, wherein: The orthographic projection of the first light-shielding connecting portion on the base substrate at least partially overlaps with the orthographic projection of the power line on the base substrate.

12. The display substrate according to claim 11, wherein: An orthographic projection of the first light-shielding connection portion on the base substrate has a first overlapping area with an orthographic projection of the power line on the base substrate, and the first overlapping area is greater than or equal to 90% of an area of ​​the first light-shielding connection portion.

13. The display substrate according to claim 2, wherein: The display substrate also includes a plurality of light-emitting control signal lines; the sub-pixel also includes a light-emitting element; the sub-pixel driving circuit also includes a light-emitting control transistor, a gate of the light-emitting control transistor is coupled to the corresponding light-emitting control signal line, a first electrode of the light-emitting control transistor is coupled to the second electrode of the driving transistor, and the second electrode of the light-emitting control transistor is coupled to the anode of the light-emitting element via a second conductive connection portion and a third conductive connection portion in sequence; the power line includes a groove, and at least a portion of the third conductive connection portion is located within the groove.

14. The display substrate according to claim 13, wherein: The orthographic projection of the second conductive connection portion on the base substrate at least partially overlaps with the orthographic projection of the light emitting control signal line on the base substrate; And / or, an orthographic projection of the third conductive connection portion on the base substrate at least partially overlaps with an orthographic projection of the light emitting control signal line on the base substrate.

15. The display substrate according to claim 13, wherein: The sub-pixel driving circuit further includes a power control transistor, a gate of the power control transistor is coupled to a corresponding light emitting control signal line, a first electrode of the power control transistor is coupled to the corresponding power line, and a second electrode of the power control transistor is coupled to a first electrode of the driving transistor; The power control transistor includes a power control active layer, at least a portion of an orthographic projection of a bottom of the groove on the substrate is located on the third conductive connection portion on the substrate. The orthographic projection is between the orthographic projection of the power control active layer on the substrate.

16. The display substrate according to claim 15, wherein: The display substrate further includes a plurality of data lines, and an orthographic projection of the power control active layer on the base substrate at least partially overlaps with an orthographic projection of the data lines on the base substrate.

17. The display substrate according to claim 13, wherein: The display substrate further includes a plurality of second reset signal lines and a plurality of second initialization signal lines; the sub-pixel driving circuit further includes a second reset transistor, a gate of the second reset transistor is coupled to the corresponding second reset signal line, a first electrode of the second reset transistor is coupled to the corresponding second initialization signal line, and a second electrode of the second reset transistor is coupled to the anode of the light-emitting element; The light emission control transistor includes a light emission control active layer; the second reset transistor includes a second reset active layer, and the second reset active layer and the light emission control active layer are arranged along the first direction.

18. The display substrate according to claim 4, wherein: The first scanning line includes a plurality of third scanning portions and a plurality of fourth scanning portions, the third scanning portions and the fourth scanning portions are alternately arranged along a second direction, the second direction intersects the first direction, and along the first direction, the width of the third scanning portion is greater than the width of the fourth scanning portion; The orthographic projection of the third scanning portion on the substrate at least partially overlaps with the orthographic projection of the compensation active layer on the substrate; The orthographic projection of the fourth scanning portion on the base substrate at least partially overlaps with the orthographic projection of the first conductive connecting portion on the base substrate.

19. The display substrate according to claim 4, wherein: The display substrate further includes a plurality of power compensation lines arranged along the first direction, the power compensation lines include a plurality of first compensation parts and a plurality of second compensation parts, the first compensation parts and the second compensation parts are alternately arranged along the second direction, the first compensation parts include at least a portion extending along the first direction, the second compensation parts include at least a portion extending along the second direction, and adjacent first compensation parts and second compensation parts are coupled; The first compensation portion is coupled to the power line; at least part of the orthographic projection of the second compensation portion on the base substrate is located between the orthographic projection of the data line on the base substrate and the orthographic projection of the first conductive connection portion on the base substrate.

20. A display device comprising the display substrate according to any one of claims 1 to 19.

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