Array substrate, display panel and display device

Abstract

The embodiment of the invention provides an array substrate, a display panel and a display device. The array substrate includes: a plurality of active patterns; the active pattern comprises a first part and a second part; a plurality of first signal lines; at least part of the orthographic projection of the first part on the substrate is overlapped with at least part of the orthographic projection of the first signal line on the substrate; the first insulating layer is provided with a first via hole at the position of the second part; a first pole; the first pole is in contact with the second part through the first via hole; the second insulating layer is provided with a second via hole at the position of the first pole, and at least part of the second via hole on the orthographic projection of the substrate is located on one side, close to the first signal line, of the orthographic projection of the first via hole on the substrate; the first conductive layer is positioned on one side, far away from the second metal layer, of the second insulating layer and comprises a plurality of first electrodes; and the first electrode is in contact with the first pole through the second via hole.

Description

Array substrate, display panel, and display device Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to an array substrate, a display panel, and a display device. Background Art

[0002] In recent years, driven by consumers' demand for a better viewing experience, the requirements for display quality have become increasingly higher. For displays, resolution and frame rate are their main parameters, where resolution represents the number of pixels on the display and frame rate represents the number of images displayed on the display per second. Obviously, it is easier to get a better viewing experience at high resolution and high frame rate. As the resolution increases, the gating time decreases, which requires the transistor to provide a larger driving current to complete the charging of the capacitor. Similarly, as the frame frequency increases, the current driving capability of the transistor is also required to be higher. Mobility is a key parameter to measure the current driving capability of the transistor, and the situation of each transistor technology meeting the display requirements at different resolutions and frame rates. The mobility of mainstream metal oxide transistors represented by amorphous indium gallium zinc oxide (a-IGZO) (generally <30cm 2 / Vs), which can meet the requirements of high-definition displays.

[0003] Summary of the Invention

[0004] The present disclosure provides an array substrate, a display panel, and a display device. The array substrate includes:

[0005] substrate;

[0006] The active layer is located on one side of the substrate and includes: a plurality of active patterns; the active patterns include: a first portion and a second portion;

[0007] a first metal layer, located on a side of the active layer facing away from the substrate, comprising a plurality of first signal lines; at least a portion of the first portion in an orthographic projection of the substrate overlaps with at least a portion of the first signal line in an orthographic projection of the substrate;

[0008] a first insulating layer, located on a side of the first metal layer away from the active layer, and having a first via hole at a location of the second portion;

[0009] a second metal layer located on a side of the first insulating layer away from the first metal layer; the second metal layer comprising: a first electrode; the first electrode being in contact with the second portion through the first via hole;

[0010] a second insulating layer, located on a side of the second metal layer away from the first insulating layer, having a second via hole at a location of the first electrode, and the second via hole being located on a side of the substrate orthographic projection of the first via hole close to the first signal line;

[0011] The first conductive layer is located on a side of the second insulating layer away from the second metal layer, and includes: a plurality of first electrodes; the first electrodes are in contact with the first electrode through the second via holes.

[0012] In a possible implementation manner, the second via hole is located at the center of the substrate orthographic projection, and on a side of the first via hole at the center of the substrate orthographic projection close to the first signal line.

[0013] In a possible implementation manner, at least a portion of the orthographic projection of the substrate of the second via hole has an overlapping area with at least a portion of the orthographic projection of the substrate of the first via hole.

[0014] In a possible implementation manner, the second via hole has an overlapping area with the second portion in at least a portion of the orthographic projection of the substrate.

[0015] In a possible implementation manner, the second metal layer further includes: a plurality of second signal lines extending along the first direction, and a second electrode connected to the second signal lines;

[0016] The active pattern further includes: a third portion;

[0017] The first insulating layer further has a third via hole at the location of the third portion, and the second electrode contacts the third portion through the third via hole.

[0018] In a possible implementation manner, the second portion has a first outer edge extending along the first direction;

[0019] The first outer edge extension line is projected onto the substrate and is located on a side of the second via hole projected onto the substrate away from the second signal line.

[0020] In one possible implementation, the array substrate further includes: a third metal layer located between the active layer and the substrate; the third metal layer includes: a plurality of third metal patterns; an orthographic projection of the third metal pattern on the substrate at least covers an orthographic projection of the first portion on the substrate;

[0021] At least a portion of the orthographic projection of the substrate of the second via hole overlaps with at least a portion of the orthographic projection of the third metal pattern of the substrate.

[0022] In one possible implementation, the first electrode has a second outer edge extending along the first direction and away from the second signal line, and the third metal pattern has a third outer edge extending along the first direction and away from the second signal line;

[0023] The distance between the second outer edge and the second signal line on the substrate orthographic projection thereof is substantially equal to the distance between the third outer edge and the second signal line on the substrate orthographic projection thereof.

[0024] In a possible implementation manner, a distance between an orthographic projection of the second outer edge on the substrate and an orthographic projection of the second signal line on the substrate is 10 μm to 15 μm.

[0025] In a possible implementation manner, the first signal line extends along the second direction; the third portion, the first portion, and the second portion are sequentially distributed along the first direction;

[0026] The third portion includes: a first sub-portion and a second sub-portion, wherein the first sub-portion extends along the first direction, and one end of the first sub-portion is connected to the first portion, and the other end is connected to the second sub-portion; the second sub-portion extends from the first sub-portion along a direction perpendicular to the first direction toward a side close to the second signal line;

[0027] The second portion includes: a third sub-portion and a fourth sub-portion, wherein the third sub-portion extends along the first direction, and one end is connected to the first portion, and the other end is connected to the fourth sub-portion; the fourth sub-portion extends from the third sub-portion along a direction perpendicular to the first direction toward a side away from the second signal line.

[0028] In one possible implementation, the third via and the first via are located on different sides of the first signal line, respectively; and the second via is located at the center of the orthographic projection of the substrate, in an area between the center of the third via on the orthographic projection of the substrate and the center of the first via on the orthographic projection of the substrate.

[0029] In a possible implementation manner, the orthographic projection of the first via on the substrate partially overlaps with the orthographic projection of the third sub-portion on the substrate, and partially overlaps with the orthographic projection of the fourth sub-portion on the substrate.

[0030] In a possible implementation manner, the orthographic projection of the second via on the substrate partially overlaps with the orthographic projection of the third sub-portion on the substrate, and partially overlaps with the orthographic projection of the fourth sub-portion on the substrate.

[0031] In a possible implementation, the first signal line includes: first signal portions and second signal portions alternately distributed in sequence along the second direction; an orthographic projection of the second signal portion on the substrate overlaps with an orthographic projection of the active pattern on the substrate;

[0032] The second signal portion includes: a first sub-signal portion extending along the third direction, and two second sub-signal portions extending along the fourth direction; one of the second sub-signal portions has one end electrically connected to the first signal portion on one side, and the other end electrically connected to one end of the first sub-signal portion; the other of the second sub-signal portions has one end electrically connected to the first signal portion on the other side, and the other end electrically connected to the other end of the first sub-signal portion;

[0033] The third portion, the first portion, and the second portion are sequentially distributed along the fourth direction; the orthographic projection of the third via hole and the orthographic projection of the first via hole on the substrate are respectively located on different sides of the first sub-signal portion.

[0034] In one possible implementation, the array substrate further includes: a third metal layer located between the active layer and the substrate; the third metal layer includes: a plurality of third metal patterns; an orthographic projection of the third metal pattern on the substrate at least covers an orthographic projection of the first portion on the substrate;

[0035] The orthographic projection of the third metal pattern on the substrate also covers the orthographic projection of the second signal portion on the substrate.

[0036] In a possible implementation manner, the first signal line includes: a first main portion extending along a first direction, and a first branch portion extending from the first main portion along the second direction;

[0037] The orthographic projection of the active pattern on the substrate and the orthographic projection of the first branch on the substrate are located on the same side of the first main portion; the third portion, the first portion, and the second portion are sequentially distributed along the second direction, and at least a portion of the orthographic projection of the first portion on the substrate overlaps with at least a portion of the orthographic projection of the first branch on the substrate;

[0038] The first via and the second via are located on the same side of the substrate orthographic projection of the first branch in the substrate orthographic projection, and the center of the first via is located on the side of the substrate orthographic projection of the second via away from the center of the substrate orthographic projection of the first branch in the substrate orthographic projection.

[0039] In one possible implementation, the array substrate further includes: a third metal layer located between the active layer and the substrate; the third metal layer includes: a plurality of third metal patterns; an orthographic projection of the third metal pattern on the substrate at least covers an orthographic projection of the first portion on the substrate;

[0040] The orthographic projection of the third metal pattern on the substrate also covers the orthographic projection of the first branch on the substrate.

[0041] In a possible implementation, the array substrate further includes: a second conductive layer located between the first conductive layer and the second metal layer, and a fourth metal layer located between the second conductive layer and the first conductive layer; the second conductive layer includes: a plurality of second electrode blocks; the fourth metal layer includes: a plurality of third signal lines;

[0042] The second electrode block is electrically connected to the third signal line through a via hole; and at least a portion of the third signal line on the substrate is overlapped with at least a portion of the second signal line on the substrate.

[0043] In a possible embodiment, the first conductive layer further includes: a overlapping portion; the overlapping portion has an overlapping area with the orthographic projection of the third signal line on the substrate, and has an overlapping area with the orthographic projection of the second electrode block on the substrate; the second electrode block is electrically connected to the third signal line through the overlapping portion.

[0044] In a possible implementation manner, the array substrate further includes: a protrusion connected to the third signal line and extending from one side of the third signal line;

[0045] The third signal line is electrically connected to the second electrode block at the convex portion through the overlapping portion.

[0046] An embodiment of the present disclosure further provides a display panel, which includes the array substrate provided in the embodiment of the present disclosure.

[0047] An embodiment of the present disclosure further provides a touch display device, which includes the display panel provided in the embodiment of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] FIG1A is a schematic diagram of an array substrate according to an embodiment of the present disclosure;

[0049] FIG1B is a schematic diagram of a single film layer of the third metal layer in FIG1A ;

[0050] FIG1C is a schematic diagram of a single film layer of the active layer in FIG1A ;

[0051] FIG1D is a schematic diagram of a single film layer of the first metal layer in FIG1A ;

[0052] FIG1E is a schematic diagram of a single film layer of the second metal layer in FIG1A ;

[0053] FIG2 is a schematic diagram corresponding to a cross section along dotted line EF in FIG1A ;

[0054] FIG3 is a schematic diagram corresponding to a cross section along dotted line GH in FIG1A ;

[0055] FIG4 is a second schematic diagram of an array substrate provided in an embodiment of the present disclosure;

[0056] FIG5 is a third schematic diagram of an array substrate provided in an embodiment of the present disclosure;

[0057] FIG6A is a schematic diagram of forming a third metal pattern according to an embodiment of the present disclosure;

[0058] FIG6B is a schematic diagram of forming a buffer layer according to an embodiment of the present disclosure;

[0059] FIG6C is a schematic diagram of forming an active pattern according to an embodiment of the present disclosure;

[0060] FIG6D is a schematic diagram of forming a first signal line according to an embodiment of the present disclosure;

[0061] FIG6E is a schematic diagram of forming a first insulating layer according to an embodiment of the present disclosure;

[0062] FIG6F is a schematic diagram of forming a second electrode and a first electrode according to an embodiment of the present disclosure;

[0063] FIG6G is a schematic diagram of forming a first passivation layer according to an embodiment of the present disclosure;

[0064] FIG6H is a schematic diagram of forming a second electrode according to an embodiment of the present disclosure;

[0065] FIG6I is a schematic diagram of forming a third signal line according to an embodiment of the present disclosure;

[0066] FIG6J is a schematic diagram of forming a third passivation layer according to an embodiment of the present disclosure;

[0067] FIG6K is a schematic diagram of forming a first electrode according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0068] In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0069] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by persons of ordinary skill in the field to which this disclosure belongs. The words "first", "second" and similar terms used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0070] As used herein, "about" or "approximately the same" is inclusive of the stated value and means within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system). For example, "approximately the same" can mean that the difference relative to the stated value is within one or more standard deviations, or within ±30%, 20%, 10%, 5%.

[0071] In the accompanying drawings, the thickness of layers, films, panels, regions, etc. are exaggerated for clarity. Exemplary embodiments are described herein with reference to cross-sectional views that are schematic representations of idealized embodiments. As such, deviations from the shapes of the figures are to be expected as a result of, for example, manufacturing techniques and / or tolerances. Thus, the embodiments described herein should not be construed as limited to the specific shapes of the regions as shown herein, but rather include deviations in shape that result from, for example, manufacturing. For example, a region illustrated or described as flat may typically have rough and / or nonlinear features. Furthermore, sharp corners illustrated may be rounded. Thus, the regions illustrated in the figures are schematic in nature, and their shapes are not intended to illustrate the precise shape of the regions and are not intended to limit the scope of the claims.

[0072] In order to keep the following description of the embodiments of the present disclosure clear and concise, the present disclosure omits detailed descriptions of known functions and known components.

[0073] The pixel aperture ratio is affected by the length of the source and drain metal on both sides of the gate. After the equipment precision reaches its limit in the current bottom-gate transistor process, it is difficult to further reduce the source and drain metal length. The electrical characteristics of common semiconductor transistors are directly affected by the channel width. Generally speaking, the transistor channel width is limited by the precision of the exposure machine and the size of the pattern on the photomask. Currently, the use of phase shift mask (PSM Mask) technology to expose and develop smaller channels is a well-known solution for various transistor manufacturers. However, when the precision of the exposure machine and the size of the pattern on the mask plate reach their limits, it is difficult to further reduce the channel width. In other words, after the channel width reaches its limit due to process reasons, it is difficult to further increase the aperture ratio of the display panel.

[0074] In view of this, an embodiment of the present disclosure provides an array substrate, as shown in Figures 1A to 1E, 2, and 3, wherein Figure 1B is a schematic diagram of a single film layer of the third metal layer in Figure 1A, Figure 1C is a schematic diagram of a single film layer of the active layer in Figure 1A, Figure 1D is a schematic diagram of a single film layer of the first metal layer in Figure 1A, Figure 1E is a schematic diagram of a single film layer of the second metal layer in Figure 1A, Figure 2 is a schematic diagram corresponding to a cross section along dotted line EF in Figure 1A, and Figure 3 is a schematic diagram corresponding to a cross section along dotted line GH in Figure 1A, which includes:

[0075] Substrate 1;

[0076] The active layer 2 is located on one side of the substrate 1 and includes: a plurality of active patterns 20; the active pattern 20 includes: a first portion 21 and a second portion 22;

[0077] The first metal layer L1 is located on a side of the active layer 3 facing away from the substrate 1 and includes a plurality of first signal lines 3. At least a portion of the orthographic projection of the first portion 21 on the substrate 1 overlaps with at least a portion of the orthographic projection of the first signal line 3 on the substrate 1. Specifically, the entire orthographic projection of the first portion 21 on the substrate 1 overlaps with at least a portion of the orthographic projection of the first signal line 3 on the substrate 1. Specifically, the region of the active pattern 20 that overlaps with the first signal line 3 may be the first portion 21. Specifically, the first signal line 3 may be a gate line.

[0078] The first insulating layer 91 is located on a side of the first metal layer L1 away from the active layer 5 and has a first via hole K1 at the location of the second portion 22. A hole is punched at a position corresponding to the second portion 22 to form the first via hole K1. Specifically, the orthographic projection of the second portion 22 on the substrate 1 covers the first via hole K1, that is, the first via hole K1 is formed only at a portion corresponding to the second portion 22.

[0079] The second metal layer L2 is located on a side of the first insulating layer 91 away from the first metal layer L1. The second metal layer L2 includes a first electrode 41. The first electrode 41 contacts the second portion 22 through a first via K1. The orthographic projection of the first electrode 41 on the substrate 1 may overlap with the orthographic projection of the second portion 22 on the substrate 1.

[0080] The second insulating layer 92 is located on a side of the second metal layer L2 away from the first insulating layer 91, and has a second via K2 at the location of the first electrode 41, and at least a portion of the orthographic projection of the second via K2 on the substrate 1 is located on a side of the orthographic projection of the first via K1 on the substrate 1 close to the first signal line 3; specifically, the entire orthographic projection of the second via K2 on the substrate 1 may be located on a side of the orthographic projection of the first via K1 on the substrate 1 close to the first signal line 3, that is, the entire second via K2 is located between the first via K1 and the first signal line 3; specifically, the orthographic projection of the second via K2 on the substrate 1 may have a partial overlapping area with the orthographic projection of the first via K1 on the substrate 1, and the portion of the orthographic projection of the second via K2 on the substrate 1 that does not overlap with the orthographic projection of the first via K1 on the substrate 1 is located between the first via K1 and the first signal line 3; specifically, the second insulating layer 92 may be a laminated structure including multiple film layers;

[0081] The first conductive layer 5 is located on a side of the second insulating layer 92 away from the second metal layer L1 and includes a plurality of first electrodes 50. The first electrodes 50 contact the first electrode 41 through the second via K2. Specifically, the first conductive layer 5 can be a pixel electrode layer, and the first electrodes 50 can be pixel electrodes.

[0082] In the embodiment of the present disclosure, the first signal line 3 is located on the side of the active layer 2 away from the substrate 1, and the first signal line 3 is reused as a gate. The transistor can be a top-gate transistor. Compared with the bottom-gate transistor, the gate needs to also serve as a shading structure of the active pattern, and the gate needs to be manufactured in a larger area. In the embodiment of the present disclosure, the transistor is a top-gate transistor, and the active pattern can be shielded by setting a shading layer. The area of ​​the gate does not need to be limited by the shading effect and can be made smaller; moreover, at least part of the positive projection of the second via K2 on the substrate 1 is located on the side of the positive projection of the first via K1 on the substrate 1 close to the first signal line 3, that is, the second via K2 that conducts the first electrode 50 with the first pole 41 can be arranged close to the first signal line 3 with the first via K1 that conducts the first pole 41 with the second part 22, which can reduce the area of ​​the first pole 41 in the first direction X and increase the aperture ratio of the display panel.

[0083] In one possible embodiment, as shown in Figures 1A-1E, 2, and 3, the second metal layer L2 further includes: a plurality of second signal lines 4 extending along the first direction X, and a second electrode 42 connected to the second signal lines 4; the active pattern 20 further includes: a third portion 23; the first insulating layer 91 further includes a third via K3 at the location of the third portion 23, and the second electrode 42 contacts the third portion 23 through the third via K3. The second signal lines 4 intersect the first signal lines 3.

[0084] Specifically, the second signal line 4 may be a data line; the second electrode 42 may be a source electrode of a transistor; and the first electrode 41 may be a drain electrode of the transistor.

[0085] In the embodiment of the present disclosure, as shown in Figure 1A, the first electrode 41, the second electrode 42, and the third metal pattern 6 are all roughly concentrated at the intersection of the first signal line 3 and the second signal line 4. Compared with the first electrode 41, the second electrode 42, and the third metal pattern 6 being scattered in multiple areas and requiring a larger area of ​​black matrix for shading, the embodiment of the present disclosure can perform centralized shading through the black matrix, which is beneficial to increase the aperture ratio of the display panel.

[0086] It should be noted that Figure 1A is intended to clearly illustrate the various structures of the transistor, and does not show the other film layers in Figures 2 and 3. However, the embodiments of the present disclosure are not limited to this. In specific implementation, the array substrate may include the various film layers as shown in Figures 2 and 3.

[0087] In the embodiment of the present disclosure, the array substrate includes a transistor, and the transistor may include: an active pattern 20 , a gate (a portion that reuses the first signal line 3 ), a first electrode 41 , and a second electrode 42 .

[0088] In a possible embodiment, referring to FIG. 1A-FIG . 1E , FIG. 2 and FIG. 3 , the second via K2 is located at the orthographic projection center O2 of the substrate 1 , on a side of the orthographic projection center O1 of the first via K1 close to the first signal line 3 .

[0089] In a possible implementation, referring to FIG. 1A to FIG. 1E , FIG. 2 and FIG. 3 , the orthographic projection area of ​​the second via hole K2 on the substrate 1 may be larger than the orthographic projection area of ​​the first via hole K1 on the substrate 1 .

[0090] In one possible embodiment, referring to Figures 1A-1E, 2, and 3, at least a portion of the orthographic projection of the second via K2 on the substrate 1 overlaps with at least a portion of the orthographic projection of the first via K1 on the substrate 1. Specifically, for example, referring to Figures 1A-1E, 2, and 3, a portion of the orthographic projection of the second via K2 on the substrate 1 away from the first signal line 3 overlaps with a portion of the orthographic projection of the first via K1 on the substrate 1 close to the first signal line 3.

[0091] In a possible embodiment, referring to Figures 1A-1E, 2 and 3, at least a portion of the orthographic projection of the second via K2 on the substrate 1 has an overlapping area with at least a portion of the orthographic projection of the second portion 22 on the substrate 1, that is, the second via K2 is arranged at the position of the second portion 22, which can reduce the area of ​​the first pole 41 and thereby increase the aperture ratio of the display panel.

[0092] In one possible embodiment, as shown in Figures 1A-1E, 2, and 3, the second portion 22 has a first outer edge w1 extending along the first direction X. The extended line of the first outer edge w1 is projected onto the substrate 1 on a side of the second via K2 projected onto the substrate 1 away from the second signal line 4. That is, the second via K2 is located between the first outer edge w1 and the second signal line 4, which can reduce the length of the first electrode 41 perpendicular to the first direction X (i.e., the second direction Y), further reducing the area of ​​the first electrode 41 and further increasing the aperture ratio of the display panel.

[0093] In a possible embodiment, referring to Figures 1A-1E, 2 and 3, the array substrate further includes: a third metal layer L3 located between the active layer 2 and the substrate 1; the third metal layer L3 includes: a plurality of third metal patterns 6; the orthographic projection of the third metal pattern 6 on the substrate 1 at least covers the orthographic projection of the first portion 21 on the substrate 1, so as to avoid external light irradiating the first portion 21 and affecting the transistor performance; at least a portion of the orthographic projection of the second via K2 on the substrate 1 overlaps with at least a portion of the orthographic projection of the third metal pattern 6 on the substrate 1.

[0094] In a possible embodiment, referring to Figures 1A-1E, 2 and 3, the first pole 41 has a second outer edge w2 extending along the first direction X and away from the second signal line 4, and the third metal pattern 6 has a third outer edge w3 extending along the first direction X and away from the second signal line 4; the distance d1 between the second outer edge w2 and the second signal line 4 on the orthographic projection of the substrate 1 may be greater than the distance d2 between the third outer edge w3 and the second signal line 4 on the orthographic projection of the substrate 1.

[0095] In one possible embodiment, the distance d1 between the orthographic projection of the second outer edge w2 on the substrate 1 and the second signal line 4 can be approximately equal to the distance d2 between the orthographic projection of the third outer edge w3 on the substrate 1 and the second signal line 4. In this way, the first electrode 41 can have a smaller area, thereby reducing the aperture ratio of the display panel.

[0096] Specifically, the distance d1 between the orthographic projection of the second outer edge w2 on the substrate 1 and the second signal line 4 may be the average distance between the orthographic projection of the second outer edge w2 on the substrate 1 and the second signal line 4; the distance d2 between the orthographic projection of the third outer edge w3 on the substrate 1 and the second signal line 4 may be the average distance between the orthographic projection of the third outer edge w3 on the substrate 1 and the second signal line 4; specifically, the distance d1 between the orthographic projection of the second outer edge w2 on the substrate 1 and the second signal line 4 may also be the maximum distance between the orthographic projection of the second outer edge w2 on the substrate 1 and the second signal line 4; the distance d2 between the orthographic projection of the third outer edge w3 on the substrate 1 and the second signal line 4 may also be the maximum distance between the orthographic projection of the third outer edge w3 on the substrate 1 and the second signal line 4.

[0097] In a possible implementation, at least a portion of the orthographic projection of the second outer edge w2 on the substrate 1 may overlap with at least a portion of the orthographic projection of the third outer edge w3 on the substrate 1 .

[0098] It should be noted that, in the embodiment of the present disclosure, the relative positional relationship between the first via K1, the second via K2, the third via K3, the first portion 21, the second portion 22, the third portion 23, the third metal pattern 6, the first pole 41, the second pole 42, the first signal line 3, and the second signal line 4 can be the structure of a transistor, and the positional relationship between the first signal line 3 and the second signal line 4 connected to the transistor.

[0099] In one possible embodiment, referring to Figures 1A to 1E, 2, and 3, a distance d1 between the orthographic projection of the second outer edge w2 on the substrate 1 and the projection of the second signal line 4 on the substrate 1 is 10 μm to 15 μm. In one possible embodiment, the distance d1 between the orthographic projection of the second outer edge w2 on the substrate 1 and the projection of the second signal line 4 on the substrate 1 can be 10 μm, 11 μm, 12 μm, 13 μm, 14 μm, or 15 μm.

[0100] In a conventional bottom-gate transistor, in order to ensure the distance between the first electrode 41 and the second signal line 4, the second via K2 is placed on the left side of the transistor. In the embodiment of the present disclosure, a top-gate structure is used to transfer the transistor channel region (i.e., the area where the first part 21 is located) to directly below the first signal line 3 (i.e., the position overlapping with the first signal line 3), and the second via K2 can be moved right to the side of the second signal line 4. The distance d1 from the leftmost side of the first electrode 41 (i.e., the second outer edge w2) to the right side of the second signal line 4 can be reduced by more than 6.5μm compared with a conventional bottom-gate transistor, and can be reduced by 10μm to 15μm (for example, 12μm) compared with a conventional top-gate transistor, thereby greatly improving the aperture ratio.

[0101] In a possible embodiment, referring to Figures 1A to 1E, the first signal line 3 extends along the second direction Y; the third portion 23, the first portion 21, and the second portion 22 are distributed in sequence along the first direction X; the third via K3 is projected on the substrate 1 and the first via K1 is projected on the substrate 1, and are respectively located on different sides of the first signal line 3; and the second via K2 is located at the center O2 of the orthographic projection of the substrate 1, in an area between the center O3 of the third via K3 and the center O1 of the orthographic projection of the first via K1.

[0102] In a possible implementation, referring to FIG. 1A to FIG. 1E , the orthographic projection of the third portion 23 on the substrate 1 and the orthographic projection of the second portion 22 on the substrate 1 may be located on different sides of the first signal line 3 .

[0103] In a possible embodiment, referring to Figures 1A to 1E, the third portion 23 includes: a first sub-portion 231, and a second sub-portion 232, wherein the first sub-portion 231 extends along the first direction X, and one end is connected to the first portion 21, and the other end is connected to the second sub-portion 232; the second sub-portion 232 extends from the first sub-portion 231 along a side perpendicular to the first direction X toward the second signal line 4; the second portion 22 includes: a third sub-portion 223, and a fourth sub-portion 224, wherein the third sub-portion 223 extends along the first direction X, and one end is connected to the first portion 21, and the other end is connected to the fourth sub-portion 224; the fourth sub-portion 224 extends from the third sub-portion 223 along a side perpendicular to the first direction X toward the second signal line 4. In the embodiment of the present disclosure, since the second portion 22 and the first pole 41 need to have an overlapping area, and the first pole 41 needs to maintain a certain distance from the second signal line 4, in order to avoid photoresist residue between the first pole 41 and the second signal line 4 during photolithography patterning, resulting in connection between the first pole 41 and the second signal line 4, in the embodiment of the present disclosure, the second portion 22 includes: a third sub-portion 223, and a fourth sub-portion 224, wherein the fourth sub-portion 224 extends from the third sub-portion 223 along a side perpendicular to the first direction X toward a side away from the second signal line 4, and then when the first pole 41 and the second signal line 4 have a certain distance, the second portion 22 can also ensure that it has an overlapping area with the first pole 41, so as to be electrically connected through the first via K1.

[0104] In a possible embodiment, referring to FIG. 1A to FIG. 1E , the orthographic projection of the first via K1 on the substrate 1 partially overlaps with the orthographic projection of the third sub-portion 223 on the substrate 1 , and partially overlaps with the orthographic projection of the fourth sub-portion 224 on the substrate 1 .

[0105] In a possible embodiment, referring to FIG. 1A to FIG. 1E , the orthographic projection of the second via K2 on the substrate 1 partially overlaps with the orthographic projection of the third sub-portion 223 on the substrate 1 , and partially overlaps with the orthographic projection of the fourth sub-portion 224 on the substrate 1 .

[0106] In a possible embodiment, referring to FIG. 1A to FIG. 1E , the orthographic projection of the second via K2 on the substrate 1 does not overlap with the orthographic projection of the third sub-portion 223 on the substrate 1 and the orthographic projection of the fourth sub-portion 224 on the substrate 1 .

[0107] Specifically, the active pattern 20 may be a zigzag pattern.

[0108] In a possible embodiment, as shown in Figure 4, the first signal line 3 includes: a first signal portion 31 and a second signal portion 32, which are alternately distributed in sequence along the second direction Y; the orthographic projection of the second signal portion 32 on the substrate 1 has an overlapping area with the orthographic projection of the active pattern 20 on the substrate 1; the second signal portion 32 includes: a first sub-signal portion 321 extending along the third direction Z1, and two second sub-signal portions 322 extending along the fourth direction Z2; one end of one second sub-signal portion 322 is electrically connected to the first signal portion 31 on one side, and the other end is electrically connected to one end of the first sub-signal portion 321; one end of the other second sub-signal portion 322 is electrically connected to the first signal portion 31 on the other side, and the other end is electrically connected to the other end of the first sub-signal portion 321; the third portion 23, the first portion 21, and the second portion 22 are distributed in sequence along the fourth direction Z2; the orthographic projection of the third via K3 on the substrate 1 and the orthographic projection of the first via K1 on the substrate 1 are respectively located on different sides of the first sub-signal portion 321.

[0109] In the embodiment of the present disclosure, the third part 23, the first part 21, and the second part 22 are distributed in sequence along the fourth direction Z2. The second signal part 32 includes: a first sub-signal part 321 extending along the third direction Z1, and two second sub-signal parts 322 extending along the fourth direction Z2. The third via K3 is projected on the substrate 1, and the first via K1 is projected on the substrate 1, and they are respectively located on different sides of the first sub-signal part 321. That is, by tilting the transistor, the aperture ratio of the pixel in the first direction X can be increased.

[0110] In a possible embodiment, as shown in Figure 4, the array substrate also includes: a third metal layer L3 located between the active layer 2 and the substrate 1; the third metal layer L3 includes: a plurality of third metal patterns 6; the orthographic projection of the third metal pattern 6 on the substrate 1 at least covers the orthographic projection of the first part 21 on the substrate 1; the orthographic projection of the third metal pattern 6 on the substrate 1 also covers the orthographic projection of the second signal part 32 on the substrate 1.

[0111] In one possible embodiment, referring to FIG5 , the first signal line 3 includes: a first main portion 30 extending along a first direction, and a first branch portion 301 extending from the first main portion 30 along a second direction Y; the orthographic projection of the active pattern 20 on the substrate 1 and the orthographic projection of the first branch portion 301 on the substrate 1 are located on the same side of the first main portion 30; and the third portion 23, the first portion 21, and the second portion 22 are distributed in sequence along the second direction Y, and at least a portion of the orthographic projection of the first portion 21 on the substrate 1 overlaps with at least a portion of the orthographic projection of the first branch portion 301 on the substrate 1. Specifically, , the area of ​​the active pattern 20 overlapping with the first branch 301 can be used as the first portion 21; the first via K1 and the second via K2 are located on the same side of the orthographic projection of the first branch 301 on the substrate 1, the third via K3 and the first via K1 are located on different sides of the orthographic projection of the first branch 301 on the substrate 1, and the center O2 of the first via K1 is located on the side of the orthographic projection of the substrate 1 that is away from the center O3 of the orthographic projection of the second via K2 on the substrate 1.

[0112] In the embodiment of the present disclosure, the first signal line 3 includes: a first main portion 30 extending along the first direction, and a first branch portion 301 extending from the first main portion 30 along the second direction Y; the orthographic projection of the active pattern 20 on the substrate 1 and the orthographic projection of the first branch portion 301 on the substrate 1 are located on the same side of the first main portion 30; and the third portion 23, the first portion 21, and the second portion 22 are distributed in sequence along the second direction Y. That is, by arranging the transistors on the same side of the first signal line 3, the aperture ratio of the pixel in the first direction X can be further increased.

[0113] In a possible embodiment, as shown in Figure 5, the array substrate also includes: a third metal layer L3 located between the active layer 2 and the substrate 1; the third metal layer L3 includes: a plurality of third metal patterns 6; the orthographic projection of the third metal pattern 6 on the substrate 1 at least covers the orthographic projection of the first portion 21 on the substrate 1; the orthographic projection of the third metal pattern 6 on the substrate 1 also covers the orthographic projection of the first branch 301 on the substrate 1.

[0114] In one possible embodiment, referring to Figures 1A-1E, 2, and 3, the array substrate further includes: a second conductive layer located between the first conductive layer 5 and the second metal layer L2, and a fourth metal layer located between the second conductive layer and the first conductive layer 5; the second conductive layer includes: a plurality of second electrode blocks 70; the fourth metal layer includes: a plurality of third signal lines 8; the second electrode blocks 70 are electrically connected to the third signal lines 8 through vias; and at least a portion of the orthographic projection of the third signal lines 8 on the substrate 1 overlaps with at least a portion of the orthographic projection of the second signal lines 4 on the substrate 1. Specifically, the entire orthographic projection of the third signal lines 8 on the substrate 1 overlaps with the entire orthographic projection of the second signal lines 4 on the substrate 1. Specifically, the second conductive layer can be a common electrode layer, which can be reused as a touch electrode layer; the second electrode blocks can be touch electrode blocks; and the third signal lines 8 can be touch traces. The touch electrode blocks and touch traces can be electrically connected in a one-to-one correspondence.

[0115] In the related art, the data line and the touch line are located on the same layer and are arranged alternately. The touch line is generally located between two pixels, which causes the aperture ratio of the display panel to decrease. In the embodiment of the present disclosure, the third signal line 8 (touch line) and the second signal line 4 (data line) are located on different layers, and the third signal line 8 is projected on the substrate 1 and overlaps with the second signal line 4 on the substrate 1, thereby reducing the occupied area of ​​the metal line and improving the aperture ratio of the display panel.

[0116] In a possible embodiment, referring to Figures 1A-1E, 2, 3 and 6K, the first conductive layer 5 further includes: a overlapping portion 51; the overlapping portion 51 has an overlapping area with the orthographic projection of the third signal line 8 on the substrate 1, and has an overlapping area with the orthographic projection of the second electrode block 70 on the substrate 1; the second electrode block 70 is electrically connected to the third signal line 8 through the overlapping portion 51.

[0117] In a possible embodiment, the array substrate further includes: a protrusion (not shown in the figure) connected to the third signal line 8 and extending along one side of the third signal line 8 (for example, it can be perpendicular to the extension direction of the third signal line 8); the third signal line 8 is electrically connected to the second electrode block 70 at the position of the protrusion through the overlapping portion 51.

[0118] In one possible embodiment, the material of the active layer 2 includes: a metal oxide semiconductor material; the metal oxide semiconductor material may include any one or more of indium gallium zinc oxide (IGZO), indium gallium oxide (IGO), indium gallium zinc tin oxide (IGZTO), indium zinc oxide (IZO), and rare earth element-doped metal oxide (RE-OS), wherein the rare earth element-doped metal oxide may include lanthanide-doped metal oxide (Ln-OS); the crystalline state of the active layer material may be amorphous, partially crystalline, or polycrystalline.

[0119] In order to more clearly understand the structure of the array substrate provided by the embodiment of the present disclosure, the manufacturing process of the array substrate provided by the embodiment of the present disclosure is described below with reference to FIG. 6A to FIG. 6K :

[0120] The specific process is as follows:

[0121] Step 1: forming a third metal layer L3 on a substrate 1 (specifically, the substrate 1 may be glass), and patterning the layer to form a third metal pattern 6, as shown in FIG6A ;

[0122] Step 2: Cover the third metal pattern 6 with a buffer layer 93 . The material of the buffer layer 93 may be SiO or a SiN / SiO composite film layer, as shown in FIG6B .

[0123] Step 3: fabricate an active layer 2, the bottom layer of which is a high-mobility oxide material, such as IGZTO, IGO, etc., and then perform conventional annealing and patterning processes to form an active pattern 20, as shown in FIG6C ;

[0124] Step 4: Deposit a gate insulating layer 94 and a first metal layer L1 (also known as a gate metal layer). The first metal layer L1 is then patterned to form a first signal line 3 (part of which is reused as a gate). The gate insulating layer 94 is etched using the gate as a mask to expose the active pattern 20, which is then used for conductorization. The gate insulating layer 94 can be made of SiO; the first metal layer L1 can be made of a Mo-based alloy and a corresponding Cu composite metal. The conductorization process can use gases such as He, Ar, H2, NH3 (including mixed gases) for conductorization, as shown in FIG6D .

[0125] Step 5: Deposit a first insulating layer 91 (specifically, an interlayer dielectric layer). The first insulating layer 91 may include SiO or a SiO / SiN composite structure. Perform photolithography and etching on the first insulating layer 91 to form connecting vias to the active pattern 20. The connecting vias may include: a third via K3 and a first via K1, as shown in FIG6E .

[0126] Step 6: Deposit a second metal layer L2 (specifically, a source-drain metal layer) on the first insulating layer 91 and pattern it to form a second signal line 4 (i.e., a data line), a second electrode 42 (i.e., a source electrode), and a first electrode 41 (i.e., a drain electrode), and connect them to the active pattern 20. The material of the second metal layer L2 may include a Mo-based alloy and a corresponding Cu composite metal structure, as shown in FIG6F .

[0127] Step 7: depositing an isolation layer 921 and a first passivation layer 922 on the second metal layer L2, and performing organic material photolithography, as shown in FIG6G ;

[0128] Step 8: Prepare a second conductive layer and pattern it to form a plurality of second electrodes 70. The second conductive layer can be a common electrode and is made of a transparent conductive material such as ITO, as shown in FIG6H .

[0129] Step nine, depositing a second passivation layer 923;

[0130] Step 10: Deposit a fourth metal layer L4 and pattern it to form a third signal line 8 (specifically, a touch line). The material of the fourth metal layer L4 may include a Mo-based alloy and a corresponding Cu-Al composite metal structure, as shown in FIG6I .

[0131] Step 11: deposit a third passivation layer 924 and open a hole to the first electrode 41, as shown in FIG6J ;

[0132] Step 11: Prepare the first conductive layer 5 and pattern it to form multiple first electrodes 50 (specifically, pixel electrodes), and connect the first electrode 41 through the second via K2. The first electrode 50 has multiple slits and forms an electric field with the common electrode, as shown in Figure 6K.

[0133] Based on the same inventive concept, an embodiment of the present disclosure further provides a display panel, which includes the array substrate provided by the embodiment of the present disclosure.

[0134] Based on the same inventive concept, an embodiment of the present disclosure further provides a touch display device, which includes a display panel provided by the embodiment of the present disclosure.

[0135] Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present invention.

[0136] Obviously, those skilled in the art may make various changes and modifications to the embodiments of the present invention without departing from the spirit and scope of the embodiments of the present invention. Thus, if such changes and modifications of the embodiments of the present invention fall within the scope of the claims and their equivalents, the present invention is intended to include such changes and modifications.

Claims

1. An array substrate, wherein: include: substrate; The active layer is located on one side of the substrate and includes: a plurality of active patterns; the active patterns include: a first portion and a second portion; A first metal layer is located on a side of the active layer away from the substrate, and includes a plurality of first signal lines; at least a portion of the first portion in an orthographic projection of the substrate overlaps with at least a portion of the first signal line in an orthographic projection of the substrate; A first insulating layer, located on a side of the first metal layer away from the active layer, and having a first via hole at a location where the second portion is located; A second metal layer is located on a side of the first insulating layer away from the first metal layer; the second metal layer comprises: a first electrode; the first electrode is in contact with the second portion through the first via hole; A second insulating layer is located on a side of the second metal layer away from the first insulating layer, and has a second via hole at the location of the first electrode, and at least a portion of the second via hole is located on a side of the first via hole on the substrate orthographic projection close to the first signal line; The first conductive layer is located on a side of the second insulating layer away from the second metal layer, and includes: a plurality of first electrodes; the first electrodes are in contact with the first electrodes through the second via holes.

2. The array substrate according to claim 1, wherein: The second via hole is located at the center of the substrate orthographic projection, and is located on a side of the first via hole at the center of the substrate orthographic projection close to the first signal line.

3. The array substrate according to claim 1 or 2, wherein: The second via hole has an overlapping area with at least a portion of the orthographic projection of the substrate and at least a portion of the orthographic projection of the first via hole.

4. The array substrate according to any one of claims 1 to 3, wherein: The second via hole has an overlapping area with the second portion in at least a portion of the orthographic projection of the substrate.

5. The array substrate according to any one of claims 1 to 4, wherein: The second metal layer further includes: a plurality of second signal lines extending along the first direction, and a second electrode connected to the second signal line; The active pattern further comprises: a third part; The first insulating layer further has a third via hole at the location of the third portion, and the second electrode contacts the third portion through the third via hole.

6. The array substrate according to claim 5, wherein: The second portion has a first outer edge extending along the first direction; The first outer edge extension line is projected on the substrate and is located on a side of the second via hole projected on the substrate away from the second signal line.

7. The array substrate according to claim 5 or 6, wherein: The array substrate further comprises: a third metal layer located between the active layer and the substrate; the third metal layer comprises: a plurality of third metal patterns; the orthographic projection of the third metal pattern on the substrate at least covers the orthographic projection of the first portion on the substrate; At least a portion of the orthographic projection of the substrate by the second via hole overlaps with at least a portion of the orthographic projection of the third metal pattern by the third metal pattern.

8. The array substrate according to claim 7, wherein: The first electrode has a second outer edge extending along the first direction and away from the second signal line, and the third metal pattern has a third outer edge extending along the first direction and away from the second signal line; The distance between the second outer edge and the second signal line on the substrate orthographic projection is substantially equal to the distance between the third outer edge and the second signal line on the substrate orthographic projection.

9. The array substrate according to claim 8, wherein: The distance between the second outer edge and the orthographic projection of the second signal line on the substrate is 10 μm to 15 μm.

10. The array substrate according to any one of claims 5 to 9, wherein: The first signal line extends along a second direction; the third portion, the first portion, and the second portion are sequentially distributed along the first direction; The third part includes: a first sub-part and a second sub-part, wherein the first sub-part is along the The second sub-portion extends from the first sub-portion along a direction perpendicular to the first direction toward a side close to the second signal line; The second part includes: a third sub-part, and a fourth sub-part, wherein the third sub-part extends along the first direction, and one end of the third sub-part is connected to the first part, and the other end is connected to the fourth sub-part; the fourth sub-part extends from the third sub-part along a direction perpendicular to the first direction toward a side away from the second signal line.

11. The array substrate according to claim 10, wherein: The third via and the first via are respectively located on different sides of the first signal line; and the second via is located at the center of the orthographic projection of the substrate, and is located in the area between the center of the third via on the orthographic projection of the substrate and the center of the first via on the orthographic projection of the substrate.

12. The array substrate according to claim 10 or 11, wherein: The orthographic projection of the first via hole on the substrate partially overlaps with the orthographic projection of the third sub-portion on the substrate, and partially overlaps with the orthographic projection of the fourth sub-portion on the substrate.

13. The array substrate according to any one of claims 10 to 12, wherein: The orthographic projection of the second via hole on the substrate partially overlaps with the orthographic projection of the third sub-portion on the substrate, and partially overlaps with the orthographic projection of the fourth sub-portion on the substrate.

14. The array substrate according to claim 5, wherein: The first signal line comprises: a first signal portion and a second signal portion which are alternately distributed in sequence along the second direction; the orthographic projection of the second signal portion on the substrate and the orthographic projection of the active pattern on the substrate have an overlapping area; The second signal part comprises: a first sub-signal part extending along the third direction, and two second sub-signal parts extending along the fourth direction; one end of the second sub-signal part is electrically connected to the first signal part on one side, and the other end is electrically connected to one end of the first sub-signal part; the other end of the second sub-signal part is electrically connected to the first signal part on the other side, and the other end is electrically connected to the other end of the first sub-signal part; The third portion, the first portion, and the second portion are sequentially distributed along the fourth direction; the orthographic projection of the third via hole on the substrate and the orthographic projection of the first via hole on the substrate are respectively located at Different sides of the first sub-signal portion.

15. The array substrate according to claim 14, wherein: The array substrate further comprises: a third metal layer located between the active layer and the substrate; the third metal layer comprises: a plurality of third metal patterns; the orthographic projection of the third metal pattern on the substrate at least covers the orthographic projection of the first portion on the substrate; The orthographic projection of the third metal pattern on the substrate also covers the orthographic projection of the second signal portion on the substrate.

16. The array substrate according to claim 5, wherein: The first signal line includes: a first main portion extending along a first direction, and a first branch portion extending from the first main portion along the second direction; The orthographic projection of the active pattern on the substrate and the orthographic projection of the first branch on the substrate are located on the same side of the first main portion; the third portion, the first portion, and the second portion are sequentially distributed along the second direction, and at least a portion of the orthographic projection of the first portion on the substrate overlaps with at least a portion of the orthographic projection of the first branch on the substrate; The first via hole and the second via hole are located on the same side of the first branch's orthographic projection on the substrate, and the center of the first via hole is located on the side of the second via hole's orthographic projection on the substrate away from the center of the first branch's orthographic projection on the substrate.

17. The array substrate according to claim 16, wherein: The array substrate further comprises: a third metal layer located between the active layer and the substrate; the third metal layer comprises: a plurality of third metal patterns; the orthographic projection of the third metal pattern on the substrate at least covers the orthographic projection of the first portion on the substrate; The orthographic projection of the third metal pattern on the substrate also covers the orthographic projection of the first branch on the substrate.

18. The array substrate according to any one of claims 5 to 17, wherein: The array substrate further comprises: a second conductive layer located between the first conductive layer and the second metal layer, and a fourth metal layer located between the second conductive layer and the first conductive layer; the second conductive layer comprises: a plurality of second electrode blocks; the fourth metal layer comprises: a plurality of third signal lines; The second electrode block is electrically connected to the third signal line through a via hole; and at least a portion of the third signal line in an orthographic projection of the substrate overlaps with at least a portion of the second signal line in an orthographic projection of the substrate.

19. The array substrate according to claim 18, wherein: The first conductive layer also includes: a overlapping portion; the overlapping portion has an overlapping area with the orthographic projection of the third signal line on the substrate, and has an overlapping area with the orthographic projection of the second electrode block on the substrate; the second electrode block is electrically connected to the third signal line through the overlapping portion.

20. The array substrate according to claim 18 or 19, wherein: The array substrate further includes: a protrusion connected to the third signal line and extending from one side of the third signal line; The third signal line is electrically connected to the second electrode block at the position of the protrusion through the overlapping portion.

21. A display panel, wherein: The invention comprises an array substrate as described in any one of claims 1 to 20.

22. A touch display device, wherein: Comprising the display panel as claimed in claim 21.

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