Display substrate and display device

Abstract

The display panel comprises a substrate, the substrate comprises at least one side edge area and a display area, and the side edge area comprises a first sub side edge area; the first conductive layer, the second conductive layer and the third conductive layer are sequentially arranged on the substrate; the display panel further includes: a plurality of terminals located in the first sub-side area; the at least one signal wire comprises a first sub-signal wire, a second sub-signal wire and a third sub-signal wire which are electrically connected with one another, and the first sub-signal wire is located in the first conductive layer and extends in the first direction; the second sub-signal wire is located in the second conductive layer and extends along a second direction; the third sub-signal wire is located in the third conductive layer and extends along the second direction; the end, connected with the terminal, of the second sub-signal wire is closer to the display area than the end, connected with the terminal, of the third sub-signal wire, and orthographic projections of the second sub-signal wire and the terminal on the substrate base plate are arranged at intervals in the second direction.

Description

Display substrate and display device Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display substrate and a display device. Background Art

[0002] With the advancement of display technology, public demands for the size, form, and display effects of electronic display devices are becoming increasingly diverse, placing greater demands on display panel routing design. Designing routing structures that meet these diverse display product requirements while also improving product yield is a key concern for display product developers.

[0003] The above information disclosed in this section is only for understanding the background of the inventive concept of the present disclosure and therefore the above information may contain information that does not constitute prior art.

[0004] Summary of the Invention

[0005] In one aspect, a display panel is provided, wherein the display panel comprises: a substrate, the substrate comprising at least one side region and a display region, the at least one side region being closer to a side edge of the substrate than the display region, the at least one side region comprising a first sub-side region and a second sub-side region, the first sub-side region being closer to a side edge of the substrate than the second sub-side region; a plurality of pixel units arranged in the display region, the plurality of pixel units being distributed in an array on the substrate along a first direction and a second direction, at least one of the pixel units comprising a light-emitting diode and a pixel driving circuit for driving the light-emitting diode, wherein the first direction and the second direction intersect; a plurality of terminals arranged on the substrate and located in the first sub-side region; and at least one signal trace arranged on the substrate, at least a portion of the at least one signal trace extending from the first sub-side region through the second sub-side region to the display region, one end of the at least one signal trace being electrically connected to the terminal, and the other end being electrically connected to the pixel driving circuit; wherein the display The panel also includes: a first conductive layer arranged on the base substrate; a second conductive layer arranged on a side of the first conductive layer away from the base substrate; and a third conductive layer arranged on a side of the second conductive layer away from the base substrate, wherein the at least one signal trace includes a first sub-signal trace, a second sub-signal trace and a third sub-signal trace electrically connected to each other; the first sub-signal trace is located in the first conductive layer and extends along the first direction; the second sub-signal trace is located in the second conductive layer and extends along the second direction; the third sub-signal trace is located in the third conductive layer and extends along the second direction; the orthographic projection of at least one of the second sub-signal trace and the third sub-signal trace on the base substrate overlaps with the orthographic projection of the first sub-signal trace on the base substrate; and the orthographic projection of the second sub-signal trace on the base substrate is closer to the display area than the orthographic projection of one end of the third sub-signal trace connected to at least one of the terminals on the base substrate, and the orthographic projection of the second sub-signal trace on the base substrate and the orthographic projection of the terminal on the base substrate are spaced apart in the second direction.

[0006] According to some exemplary embodiments, a portion of the third sub-signal route has its orthographic projection on the substrate falling into the first sub-side area, one end of the third sub-signal route is connected to at least one of the terminals; and the second sub-signal route is electrically connected to the third sub-signal route through the first sub-signal route.

[0007] According to some exemplary embodiments, the second sub-signal trace is electrically connected to the first sub-signal trace through at least one first via.

[0008] According to some exemplary embodiments, the display panel further includes a conductive transition portion located in the second conductive layer; and the third sub-signal trace is electrically connected to one end of the conductive transition portion through a second via hole.

[0009] According to some exemplary embodiments, the other end of the conductive transition portion is electrically connected to the first sub-signal trace through a third via.

[0010] According to some exemplary embodiments, the display panel further includes m data lines and n signal lines, the multiple terminals include m data terminals and n signal terminals, one end of the m data lines is electrically connected to the m data terminals respectively, and one end of the n signal lines is electrically connected to the n signal terminals respectively, wherein m and n are both positive integers greater than or equal to 3; and at least one data terminal is arranged between any two adjacent signal terminals.

[0011] According to some exemplary embodiments, the m data lines are located in the second conductive layer; and in the second conductive layer, at least one data line is provided between any two adjacent second sub-signal traces.

[0012] According to some exemplary embodiments, at least one of the terminals includes a first sub-terminal located in the second conductive layer and a second sub-terminal located in the third conductive layer, and the first sub-terminal and the second sub-terminal are electrically connected through a fourth via.

[0013] According to some exemplary embodiments, in the second conductive layer, the second sub-signal trace includes a cutoff side surface facing the first sub-terminal, the first sub-terminal includes a first surface facing the cutoff side surface, and the cutoff side surface and the first surface are separated by a specified distance in the second direction.

[0014] According to some exemplary embodiments, in the second direction, the cutoff side surface of the second sub-signal trace is closer to the terminal than the first sub-signal trace electrically connected to the second sub-signal trace.

[0015] According to some exemplary embodiments, in the second direction, the cutoff side surface of the second sub-signal trace is closer to the terminal than each of the first via, the second via, and the third via electrically connected to the second sub-signal trace.

[0016] According to some exemplary embodiments, in the second sub-side region, an orthographic projection of the third sub-signal trace on the substrate covers an orthographic projection of a second sub-signal trace transmitting the same signal as the third sub-signal trace on the substrate.

[0017] According to some exemplary embodiments, in the second sub-side region, the width of the orthographic projection of the third sub-signal trace on the substrate along the first direction is greater than the width of the orthographic projection of the second sub-signal trace that transmits the same signal as the third sub-signal trace on the substrate along the first direction.

[0018] According to some exemplary embodiments, the n signal lines include at least two of the following signal lines: a first voltage signal line for transmitting a first voltage signal; a second voltage signal line for transmitting a second voltage signal; a third voltage signal line for transmitting a third voltage signal; an initialization signal line for transmitting an initialization signal; and a pulse voltage signal line for transmitting a pulse voltage signal.

[0019] According to some exemplary embodiments, the cutoff side surfaces of the second sub-signal routes of the n signal routes are respectively opposite to and spaced apart from the first surfaces of the n signal terminals in the second direction; the n spacing distances between the cutoff side surfaces of the second sub-signal routes of the n signal routes and the first surfaces of the n signal terminals in the second direction are approximately equal to each other.

[0020] According to some exemplary embodiments, in the second conductive layer, one data line is provided between any two adjacent second sub-signal traces; or, in the second conductive layer, more than two data lines are provided between any two adjacent second sub-signal traces; or, in the second conductive layer, one data line is provided between some adjacent second sub-signal traces, and more than two data lines are provided between other adjacent second sub-signal traces.

[0021] According to some exemplary embodiments, the first sub-signal routes of the n signal routes include at least two of the following first sub-signal routes: a first sub-signal route of a first voltage signal route for transmitting a first voltage signal; a first sub-signal route of a second voltage signal route for transmitting a second voltage signal; a first sub-signal route of a third voltage signal route for transmitting a third voltage signal; a first sub-signal route of an initialization signal route for transmitting an initialization signal; and a first sub-signal route of a pulse voltage signal route for transmitting a pulse voltage signal, wherein, in the second sub-side area, the first sub-signal routes of at least two signal routes are spaced apart in the second direction.

[0022] According to some exemplary embodiments, in the second sub-side region, the first sub-signal route of the pulse voltage signal route, the first sub-signal route of the third voltage signal route, the first sub-signal route of the second voltage signal route, the first sub-signal route of the first voltage signal route, and the first sub-signal route of the initialization signal route are spaced apart in the second direction in a manner that sequentially moves away from the plurality of terminals. According to some exemplary embodiments, in the second sub-side region, first vias for electrically connecting the first sub-signal route and the second sub-signal route of the at least two signal routes are spaced apart in both the first direction and the second direction.

[0023] According to some exemplary embodiments, in the second sub-side region, the third sub-signal traces for electrically connecting at least two signal traces and the second vias of the conductive transfer portion are spaced apart in the first direction and aligned in the second direction.

[0024] According to some exemplary embodiments, in the second sub-side region, the width of the orthographic projection of the third sub-signal line on the substrate along the first direction is greater than the width of the orthographic projection of the second sub-signal line transmitting the same signal as the third sub-signal line on the substrate along the first direction; and / or, in the second sub-side region, the width of the orthographic projection of the second sub-signal line on the substrate along the first direction is greater than the width of the orthographic projection of the data line on the substrate along the first direction.

[0025] In yet another aspect, a display device is provided, wherein the display device includes the display panel as described above.

[0026] According to some exemplary embodiments, the display device includes a plurality of spliced ​​display panels. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Other objects and advantages of the present disclosure will become apparent from the following description of the present disclosure with reference to the accompanying drawings, which will help to provide a comprehensive understanding of the present disclosure.

[0028] FIG1 is a schematic plan view of a display panel according to some embodiments of the present disclosure;

[0029] FIG2 is a schematic diagram of a pixel driving circuit of a display panel according to some embodiments of the present disclosure;

[0030] FIG3 is a partial schematic plan view of a display panel according to some embodiments of the present disclosure;

[0031] FIG4 is a partial cross-sectional schematic diagram of a display panel according to some embodiments of the present disclosure;

[0032] FIG5 is a partial schematic plan view of a display panel according to some embodiments of the present disclosure;

[0033] 6A and 6B are circuit equivalent schematic diagrams of a local area of ​​a display panel according to some embodiments of the present disclosure;

[0034] FIG7 is a partial plan view of a third conductive layer of a display panel according to some embodiments of the present disclosure;

[0035] FIG8 is a partial plan view of a second conductive layer of a display panel according to some embodiments of the present disclosure;

[0036] FIG9 is a partial plan view of a combined film layer of the second conductive layer and the first conductive layer of a display panel according to some embodiments of the present disclosure;

[0037] FIG10 is a plan view schematically enlarged from the A1 area in FIG9 , showing a first via hole;

[0038] FIG11 is a connection via hole between a third conductive layer and a second conductive layer of a display panel according to some embodiments of the present disclosure;

[0039] FIG12 is a partial schematic plan view of a display panel according to some embodiments of the present disclosure;

[0040] 13A-13C are partial plan views of display panels according to some embodiments of the present disclosure;

[0041] FIG14 is a schematic structural diagram of a display device according to some embodiments of the present disclosure;

[0042] FIG15 is a schematic structural diagram of a display device according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0043] In the following description, for the purpose of explanation, many specific details are set forth to provide a comprehensive understanding of the various exemplary embodiments. However, it is apparent that the various exemplary embodiments can be implemented without these specific details or with one or more equivalent arrangements. In other cases, well-known structures and devices are shown in block diagram form to avoid unnecessarily obscuring the various exemplary embodiments. In addition, the various exemplary embodiments can be different, but not necessarily exclusive. For example, the specific shape, configuration, and characteristics of the exemplary embodiment can be used or implemented in another exemplary embodiment without departing from the inventive concept.

[0044] In the accompanying drawings, the sizes and relative sizes of the elements may be exaggerated for clarity and / or descriptive purposes. Thus, the sizes and relative sizes of the individual elements are not necessarily limited to those shown in the drawings. When the exemplary embodiments can be implemented differently, the specific process sequence can be performed differently from the described sequence. For example, two processes described in succession can be performed substantially simultaneously or in an order opposite to the described sequence. In addition, the same reference numerals represent the same elements.

[0045] When an element is described as being “on”, “connected to” or “coupled to” another element, the element may be directly on, directly connected to or directly coupled to the other element, or there may be intervening elements. However, when an element is described as being “directly on”, “directly connected to” or “directly coupled to” another element, there are no intervening elements. Other terms and / or expressions used to describe the relationship between elements should be interpreted in a similar manner, for example, “between” versus “directly between,” “adjacent” versus “directly adjacent,” or “on” versus “directly on,” etc. Additionally, the term “connected” may refer to a physical connection, an electrical connection, a communication connection, and / or a fluid connection.

[0046] It should be noted that, in this article, the term "the same layer" refers to a layer structure formed by using the same film-forming process to form a film layer used to form a specific pattern, and then patterning the film layer using the same mask through a single patterning process. Depending on the specific pattern, a single patterning process may include multiple exposure, development, or etching processes, and the specific pattern in the resulting layer structure may be continuous or discontinuous. In other words, multiple elements, components, structures, and / or parts located in the "same layer" are composed of the same material and are formed through the same patterning process. Typically, multiple elements, components, structures, and / or parts located in the "same layer" have approximately the same thickness.

[0047] In this document, the term "transistor" may refer to a triode, a thin-film transistor, a field-effect transistor, or other device with similar characteristics. In the embodiments of the present disclosure, to distinguish the two electrodes of a transistor other than the control electrode, one electrode is referred to as the first electrode, and the other electrode is referred to as the second electrode. In actual operation, when the transistor is a thin-film transistor or a field-effect transistor, the first electrode may be the drain electrode, and the second electrode may be the source electrode; alternatively, the first electrode may be the source electrode, and the second electrode may be the drain electrode.

[0048] It should be understood that although the terms first, second, etc. may be used herein to describe different elements, these elements should not be limited by these terms. These terms are merely used to distinguish one element from another. For example, a first element may be named a second element, and similarly, a second element may be named a first element without departing from the scope of the exemplary embodiments.

[0049] In some embodiments of the present disclosure, a display panel is provided, wherein the display panel comprises: a substrate, the substrate comprising at least one side region and a display region, the at least one side region being closer to the side edge of the substrate than the display region, the at least one side region comprising a first sub-side region and a second sub-side region, the first sub-side region being closer to the side edge of the substrate than the second sub-side region; a plurality of pixel units arranged in the display region, the plurality of pixel units being distributed in an array on the substrate along a first direction and a second direction, at least one of the pixel units comprising a light-emitting diode and a pixel driving circuit for driving the light-emitting diode, wherein the first direction and the second direction intersect; a plurality of terminals arranged on the substrate and located in the first sub-side region; and at least one signal trace arranged on the substrate, at least a portion of the at least one signal trace extending from the first sub-side region through the second sub-side region to the display region, one end of the at least one signal trace being electrically connected to the terminal, and the other end being electrically connected to the pixel driving circuit; wherein the The display panel also includes: a first conductive layer arranged on the base substrate; a second conductive layer arranged on a side of the first conductive layer away from the base substrate; and a third conductive layer arranged on a side of the second conductive layer away from the base substrate, wherein the at least one signal trace includes a first sub-signal trace, a second sub-signal trace and a third sub-signal trace electrically connected to each other; the first sub-signal trace is located in the first conductive layer and extends along the first direction; the second sub-signal trace is located in the second conductive layer and extends along the second direction; the third sub-signal trace is located in the third conductive layer and extends along the second direction; the orthographic projection of at least one of the second sub-signal trace and the third sub-signal trace on the base substrate overlaps with the orthographic projection of the first sub-signal trace on the base substrate; and the orthographic projection of the second sub-signal trace on the base substrate is closer to the display area than the orthographic projection of one end of the third sub-signal trace connected to at least one of the terminals on the base substrate, and the orthographic projection of the second sub-signal trace on the base substrate is spaced apart from the orthographic projection of the terminal on the base substrate in the second direction. By redesigning the pixels at the output end, the probability of short circuits in the side segments can be reduced and the yield of display products can be improved.

[0050] FIG. 1 is a schematic plan view of a display panel according to some embodiments of the present disclosure.

[0051] In some embodiments of the present disclosure, referring to FIG1 , a display panel 1000 includes: a substrate 1, the substrate 1 including a display area AA and a non-display area NA, the non-display area NA including at least one side area SA, the at least one side area SA being closer to a side edge 11 of the substrate 1 than the display area AA, the at least one side area SA including a first sub-side area SA1 and a second sub-side area SA2, the first sub-side area SA1 being closer to the side edge 11 of the substrate than the second sub-side area SA2; a plurality of pixel units PX arranged in the display area, the plurality of pixel units PX being distributed in an array on the substrate 1 along a first direction D1 and a second direction D2, at least one of the pixel units PX including a light emitting diode 201 and a pixel driving circuit 100 for driving the light emitting diode, wherein the first direction and the second direction intersect.

[0052] Exemplarily, each pixel PX may include a plurality of sub-pixels, for example, a red sub-pixel, a green sub-pixel, and a blue sub-pixel, or may include a white sub-pixel, a red sub-pixel, a green sub-pixel, and a blue sub-pixel.

[0053] In some exemplary embodiments, the light-emitting diode 201 may be an inorganic light-emitting diode. For example, an inorganic light-emitting diode refers to a light-emitting element made of inorganic materials, wherein LED represents an inorganic light-emitting element different from OLED. Specifically, the inorganic light-emitting element may include a sub-millimeter light-emitting diode (Mini Light Emitting Diode, abbreviated as Mini LED in English) and a micro light-emitting diode (Micro Light Emitting Diode, abbreviated as Micro LED in English). Among them, a micro light-emitting diode (i.e., Micro LED) refers to an ultra-small light-emitting diode with a grain size of less than 100 microns, and a sub-millimeter light-emitting diode (i.e., Mini LED) refers to a small light-emitting diode with a grain size between Micro LED and traditional LED. For example, the grain size of Mini LED can be between 50 and 400 microns.

[0054] FIG. 2 is a schematic diagram of a pixel driving circuit of a display panel according to some embodiments of the present disclosure.

[0055] For example, in some embodiments of the present disclosure, a pixel driving circuit 100 is provided. Referring to FIG. 2 , the pixel driving circuit 100 includes a current control subcircuit 110 and a gating subcircuit 120 .

[0056] The current control sub-circuit 110 is coupled to the scan signal line GATE, the grayscale data line DATA1, the first voltage signal line VDD, and the enable signal line EM. The current control sub-circuit is configured to output a grayscale current signal to the light-emitting diode 201 based on the grayscale data signal Data1 from the grayscale data line DATA1, under the control of the scan signal Gate from the scan signal line GATE and the enable signal Em from the enable signal line EM.

[0057] The gating sub-circuit 120 is coupled to the scan signal line GATE, the reset signal line RESET, the gated data line DATA2, and the pulse voltage signal line HF. The gating sub-circuit 120 is configured to drive the light-emitting diode 201 to emit light continuously under the control of the scan signal Gate from the scan signal line GATE and the gated data signal Data2 from the gated data line DATA2; and to drive the light-emitting diode 201 to emit light intermittently under the control of the reset signal Reset from the reset signal line RESET, the gated data signal Data2 from the gated data line DATA2, and the pulse voltage signal Hf from the pulse voltage signal line HF.

[0058] The magnitude of the grayscale current signal is related to the first voltage signal Vdd provided by the first voltage signal line VDD and the grayscale data signal Data1 provided by the grayscale data line DATA1, and the total duration of the intermittent lighting of the light-emitting diode 201 is related to the pulse voltage signal Hf provided by the pulse voltage signal line HF.

[0059] Thus, when the gating sub-circuit 120 drives the light-emitting diode 201 to continuously emit light, the current control sub-circuit 110 can control the luminous intensity of the light-emitting diode 201 by controlling the magnitude of the grayscale data signal Data1, thereby achieving high grayscale display. When the gating sub-circuit 120 drives the light-emitting diode 201 to intermittently emit light, the luminous intensity of the light-emitting diode 201 can be controlled by controlling the magnitude of the grayscale data signal Data1, and the light-emitting duration of the light-emitting diode 201 can be shortened by using the pulse voltage signal Hf, thereby achieving low grayscale display.

[0060] That is to say, by using the above-mentioned pixel driving circuit 100, when achieving a higher grayscale display, the light-emitting brightness of the light-emitting diode 201 within one frame can be changed by controlling the size of the grayscale data signal Data1; when achieving a lower grayscale display, the light-emitting brightness of the light-emitting diode 201 within one frame can be changed under a high current density by shortening the light-emitting time of the light-emitting diode 201.

[0061] As can be seen from the above, by utilizing the above pixel driving circuit 100 , the light emitting diode 201 can achieve full grayscale display at high current density, with high luminous efficiency, low energy consumption, and cost savings.

[0062] If the frequency of the pulse voltage signal is too low, the human eye will easily perceive flickering, affecting the visual experience. If the frequency of the pulse voltage signal is too high, hardware such as an integrated circuit will be difficult to implement. Based on this, in some embodiments, the frequency range of the pulse voltage signal is 3000-60000Hz. The flickering of the light-emitting diode will not be perceived by the human eye and is easy to implement. For example, the frequency of the pulse voltage signal Hf can be 3000Hz, 20000Hz, 60000Hz, etc.

[0063] Exemplarily, for all circuits included in the display panel, the frequency of the pulse voltage signal is the same and always maintains a preset frequency, or fluctuates within a small range around the preset frequency.

[0064] In some embodiments, the above-mentioned light-emitting diode 201 serves as a light-emitting unit and can be an inorganic light-emitting diode, such as a Mini LED or a Micro LED. The current control subcircuit 110 controls the size of the grayscale data signal Data1, thereby controlling the size of the grayscale current signal transmitted to the light-emitting unit, thereby directly controlling the luminous intensity of the light-emitting diode; the selection subcircuit 120 shortens the duration of the grayscale current signal being transmitted to the light-emitting unit, thereby shortening the working time of the light-emitting unit, thereby indirectly reducing the luminous efficiency of the light-emitting diode within one frame.

[0065] By regulating signal parameters such as the data signal, the first voltage signal, the second voltage signal, the initialization voltage signal, and the pulse voltage signal, the grayscale of the light-emitting unit can be regulated, thereby improving the display effect of the display product.

[0066] FIG. 3 is a partial schematic plan view of a display panel according to some embodiments of the present disclosure.

[0067] In some embodiments of the present disclosure, with reference to FIG1 and FIG3 , a display panel includes a plurality of terminals 2 disposed on a base substrate 1 and located in the first sub-side region SA1; and at least one signal trace 3 disposed on the base substrate, at least a portion of which extends from the first sub-side region SA1 through the second sub-side region SA2 to the display area AA. One end of the at least one signal trace 3 is electrically connected to the terminal 2, and the other end is electrically connected to the pixel driver circuit 100. In other words, at least one pixel driver circuit 100 is electrically connected to at least one terminal 2 via the at least one signal trace 3. The terminal can be electrically connected to an external driver circuit or driver chip to write a drive signal to the pixel driver circuit 100. By redesigning the outgoing pixel connection traces, for example, by redesigning the signal trace and terminal layout, the probability of short circuits in the signal traces in side segments, such as the side region SA, can be reduced, thereby improving the yield of the display product.

[0068] FIG. 4 is a partial cross-sectional schematic diagram of a display panel according to some embodiments of the present disclosure.

[0069] For example, in some embodiments of the present disclosure, referring to FIG4 , the display panel includes: a first conductive layer 4 disposed on the base substrate 1; a second conductive layer 5 disposed on the side of the first conductive layer 4 away from the base substrate 1; and a third conductive layer 6 disposed on the side of the second conductive layer 5 away from the base substrate. An insulating layer, such as an isolation layer ILD layer, a passivation layer PVX, or other functional layer, is disposed between adjacent conductive layers. The insulating layer may be a single layer or multiple layers. Adjacent conductive layers may be electrically connected through vias. For example, the first conductive layer 4 may be electrically connected to the second conductive layer 5 through a first via VH1, and / or the first conductive layer 4 may be electrically connected to the second conductive layer 5 through a third via VH3, and / or the second conductive layer 5 may be electrically connected to the third conductive layer 6 through a second via VH2. The design of multiple vias allows electrical connection between film layers located in different conductive layers, where the different conductive layers may be adjacent or non-adjacent.

[0070] 3 and 4 , the at least one signal trace 3 includes a first sub-signal trace 31, a second sub-signal trace 32, and a third sub-signal trace 33 electrically connected to each other; the first sub-signal trace 31 is located in the first conductive layer 4 and extends along the first direction D1; the second sub-signal trace 32 is located in the second conductive layer 5 and extends along the second direction D2; the third sub-signal trace 33 is located in the third conductive layer 6 and extends along the second direction D2; the orthographic projection of at least one of the second sub-signal trace 32 and the third sub-signal trace 33 on the base substrate 1 at least partially overlaps with the orthographic projection of the first sub-signal trace 31 on the base substrate; and the orthographic projection of the second sub-signal trace 32 on the base substrate does not fall into the first sub-side area SA1, and the orthographic projection of the second sub-signal trace 32 on the base substrate 1 is spaced apart from the orthographic projection of the terminal 2 on the base substrate 1 in the second direction D2.

[0071] Continuing with Figure 3 , a portion of the third sub-signal trace 33 has its orthographic projection on the substrate 1 falling within the first sub-side area SA1. One end 331 of the third sub-signal trace 33 is connected to at least one of the terminals 2. Furthermore, the second sub-signal trace 32 is electrically connected to the third sub-signal trace 33 via the first sub-signal trace 31. The terminal 2 can be electrically connected to an external driver circuit or driver chip, thereby enabling signals to be sequentially written into the third sub-signal trace 33, the first sub-signal trace 31, and the second sub-signal trace 32 via the terminal 2. Furthermore, signals are written into the pixel driver circuit 100, thereby controlling the pixel unit.

[0072] Exemplarily, referring to FIG. 3 and FIG. 9 , the second sub-signal trace 32 is electrically connected to the first sub-signal trace 31 through at least one first via VH1 .

[0073] For example, in some embodiments of the present disclosure, in combination with FIG. 3 and FIG. 4 , the display panel further includes a conductive transition portion 51 located in the second conductive layer 5 ; the third sub-signal trace 33 is electrically connected to one end 511 of the conductive transition portion 51 through a second via VH2 .

[0074] Exemplarily, the other end 512 of the conductive transition portion 51 is electrically connected to the first sub-signal trace 31 through a third via hole VH3 .

[0075] The first, second, and third sub-signal traces 31, 32, and 33, located on different conductive layers, are electrically connected through the first, second, and third vias VH1, VH2, and VH3, as well as the conductive transition portion 51. This allows the second sub-signal trace to be electrically connected to terminal 2 via the first and third sub-signal traces, rather than passing through the first sub-side area SA1. Furthermore, terminal 2 can be electrically connected to an external driver circuit or driver chip, allowing signals to be written to the second sub-signal trace 32 through terminal 2.

[0076] 3 , 7 , and 8 , the orthographic projection of the second sub-signal trace 32 on the substrate substrate is closer to the display area AA than the orthographic projection of the end of the third sub-signal trace 33 connected to at least one terminal 2 on the substrate substrate. Specifically, the second sub-signal trace 32 includes a cutoff side surface 320 facing the terminal 2, and the third sub-signal trace 33 extends directly onto the terminal 2 to make direct electrical contact with the terminal 2. In other words, the cutoff side surface 320 of the second sub-signal trace 32 facing the terminal 2 is spaced a certain distance from the terminal 2 or the end of the third sub-signal trace 33 in contact with the terminal 2, so that the cutoff side surface 320 of the second sub-signal trace 32 facing the terminal 2 is contracted toward the display area AA relative to the end of the third sub-signal trace 33 in contact with the terminal 2, that is, the second sub-signal trace 32 forms an inward-contracted design relative to the third sub-signal trace 33.

[0077] By shrinking the second sub-signal trace 32 and adopting an in-plane via connection design to replace the traditional design of leading two metal traces out to the terminal together, the number of signal traces at the side outlet ends can be reduced, thereby reducing the probability of damage to the outlet traces in subsequent processing processes such as back etching, reducing the probability of short circuits in the side sections, and thus improving the yield of display products.

[0078] Exemplarily, continuing to refer to FIG3 , the display panel may further include at least one data line DL for transmitting data signals, and at least one data line DL may be used to write data signals required to drive the light-emitting units. For example, the data line DL may include a data line DB for writing data signals to drive blue light-emitting units; and / or, the data line DL may include a data line DR for writing data signals to drive red light-emitting units; and / or, the data line DL may include a data line DG for writing data signals to drive green light-emitting units. The data line DL for driving light-emitting units of different colors may be led out through the second sub-side area SA2 and the first sub-side area SA1 and electrically connected to the terminal 2. Further, the terminal may be electrically connected to an external driving circuit or a driving chip, thereby realizing writing the signal into the data line DL through the terminal 2.

[0079] It should be noted that the number of data lines driving light-emitting units of different colors may be the same or different, and the embodiments of the present disclosure do not impose any limitation on this.

[0080] FIG5 is a partial schematic plan view of a display panel according to some embodiments of the present disclosure.

[0081] For example, in some embodiments of the present disclosure, referring to FIG5 , the display panel may include m data lines DL, such as data line DL-1, data line DL-2, data line DL-3, ..., data line DL-m; the display panel may further include n signal lines 3, such as signal line 3-1, signal line 3-2, signal line 3, ..., signal line 3-n; the plurality of terminals 2 include m data terminals 21 and n signal terminals 22, one end of the m data lines DL is electrically connected to the m data terminals 21, respectively, and one end of the n signal lines 3 is electrically connected to the n signal terminals 22, respectively, wherein m and n are both positive integers greater than or equal to 3;

[0082] Exemplarily, at least one data terminal 21 is provided between any two adjacent signal terminals 22. For example, referring to FIG5 , a data terminal 21-1 is provided between a signal terminal 22-1 and a signal terminal 22-2.

[0083] By using data lines to separate the shared mesh signal lines, if a short circuit or other defect occurs during subsequent product testing, the defective area can be accurately located, allowing targeted repairs to be performed on the defective area. For example, referring to Figure 5, if a short circuit occurs during the flying probe process, since the shared signals in the entire surface signal lines, such as the first voltage signal line VDD and the second voltage signal line VSSR, are separated by data lines, the two short-circuit signals can be accurately found in the flying probe test data. For example, taking data line DL-1 and signal line 3-2 as an example, signal line 3-2 can be the second voltage signal line VSSR used to provide the second voltage signal. Assuming that the data of data line DL-1 and signal line 3-2 are abnormal, the specific locations of these two signals can be located relatively accurately within the surface, and targeted repairs can be performed on the specific locations, avoiding over-etching caused by laser etching of other already-etched lines, improving repair efficiency, and improving the overall process yield.

[0084] 6A and 6B are circuit equivalent schematic diagrams of a local area of ​​a display panel according to some embodiments of the present disclosure.

[0085] For example, in some embodiments of the present disclosure, since the signal lines provide DC signals and are spaced apart from the data lines, the signal lines after being energized can not only provide signals for the display panel but also act as capacitors in the energized circuit to stabilize the data signals in the data lines, thereby reducing the crosstalk of the data signals Data caused by coupling with other pulse signals. 6A and 6B , when there are no signal traces on either side of the data line providing a DC signal, its equivalent circuit diagram is shown in FIG6A . Assuming that the other signal Pulse signal changes by ΔV, the data signal Data also changes by ΔV due to the adjacent design being susceptible to coupling crosstalk from other signals. After using the data signal and signal trace spacing design, its equivalent circuit diagram is shown in FIG6B . Assuming that there is a DC signal on each side of the data signal Data in the data line, the DC signals on both sides can be regarded as two capacitors C1 and C2. When the other signal Pulse changes by ΔV, due to the presence of the DC signals C1 and C2, the change of the data signal Data depends on the size of C1 and C2, which is C1 / (C1+C2)·ΔV, thereby stabilizing the data signal Data and reducing the crosstalk from other signals to the data signal Data.

[0086] Figure 7 is a partial planar schematic diagram of the third conductive layer of the display panel according to some embodiments of the present disclosure; Figure 8 is a partial planar schematic diagram of the second conductive layer of the display panel according to some embodiments of the present disclosure; Figure 9 is a partial planar schematic diagram of the combined film layer of the second conductive layer and the first conductive layer of the display panel according to some embodiments of the present disclosure; Figure 10 is an enlarged planar schematic diagram of the A1 area in Figure 9, showing the first via; Figure 11 is a connecting via between the third conductive layer and the second conductive layer of the display panel according to some embodiments of the present disclosure.

[0087] In some embodiments of the present disclosure, with reference to Figures 3, 5 and 8, the m data lines DL are located in the second conductive layer 5; in the second conductive layer 5, at least one data line DL is provided between any two adjacent second sub-signal traces 32.

[0088] 7 , 8 and 11 , at least one of the terminals 2 includes a first sub-terminal 25 in the second conductive layer and a second sub-terminal 26 in the third conductive layer, and the first sub-terminal 25 and the second sub-terminal 26 are electrically connected through a fourth via VH4 .

[0089] For example, referring to Figure 8, in the second conductive layer 5, the second sub-signal trace 32 includes a cutoff side surface 320 facing the first sub-terminal 25, and the first sub-terminal 25 includes a first surface 250 facing the cutoff side surface 320, and the cutoff side surface 320 and the first surface 250 are separated by a specified distance D21 in the second direction D2.

[0090] 8 and 9 , in the second direction D2 , the cutoff side surface 320 of the second sub-signal trace 32 is closer to the terminal 2 than the first sub-signal trace 31 electrically connected to the second sub-signal trace 32 .

[0091] 3 and 9 , in the second direction D2 , the cutoff side surface 320 of the second sub-signal trace 32 is closer to the terminal 2 than each of the first via VH1 , the second via VH2 , and the third via VH3 electrically connected to the second sub-signal trace 32 .

[0092] By shrinking the second sub-signal line inward and adopting an in-plane via connection design to replace the traditional design of leading two metal lines out to the terminal together, the number of side terminal lines can be reduced, thereby reducing the probability of damage to the terminal lines during subsequent processing such as back etching, reducing the probability of short circuits in the side sections, and thus improving the yield of display products.

[0093] For example, in some embodiments of the present disclosure, referring to FIG3 , in the second sub-side area SA2 , the orthographic projection of the third sub-signal line 33 on the substrate covers the orthographic projection of the second sub-signal line 32 on the substrate that transmits the same signal as the third sub-signal line 33 .

[0094] For example, with reference to Figures 3, 7 and 8, in the second sub-side area SA2, the width D13 of the orthographic projection of the third sub-signal trace 33 on the substrate along the first direction D1 is greater than the width D12 of the orthographic projection of the second sub-signal trace 32 that transmits the same signal as the third sub-signal trace 33 on the substrate along the first direction.

[0095] By designing the width D13 of the third sub-signal line to be larger than the width D12 of the second sub-signal line that transmits the same signal as the third sub-signal line, and the orthographic projection of the third sub-signal line on the substrate covers the orthographic projection of the second sub-signal line that transmits the same signal as the third sub-signal line on the substrate, the in-plane wiring layout can be facilitated, the probability of short circuits in the in-plane processing process can be reduced, and the yield of display products can be improved.

[0096] FIG. 12 is a partial schematic plan view of a display panel according to some embodiments of the present disclosure.

[0097] For example, in some embodiments of the present disclosure, referring to FIG. 12 , the n signal traces include at least two of the following signal traces: a first voltage signal trace VDD for transmitting a first voltage signal; a second voltage signal trace VSSR for transmitting a second voltage signal; a third voltage signal trace VSSGB for transmitting a third voltage signal; an initialization signal trace Vinit for transmitting an initialization signal; and a pulse voltage signal trace HF for transmitting a pulse voltage signal. For example, the second voltage signal trace VSSR can provide a second voltage signal to a driving circuit of a red light-emitting unit, the third voltage signal trace VSSGB can provide a third voltage signal to a driving circuit of a green or blue light-emitting unit, the first voltage signal trace VDD can provide a first voltage signal to the driving circuit of the light-emitting unit, the initialization signal trace Vinit can provide an initialization signal to the driving circuit of the light-emitting unit, and the pulse voltage signal trace HF can provide a pulse voltage signal to the driving circuit of the light-emitting unit. For example, the light-emitting unit can be one of a red light-emitting unit, a green light-emitting unit, or a blue light-emitting unit. By adjusting the first voltage signal provided by the first voltage signal line VDD or the pulse voltage signal provided by the pulse voltage signal line HF, the brightness of the light-emitting unit can be regulated, thereby achieving grayscale regulation of the display product and improving the display effect of the display product.

[0098] For example, in some embodiments of the present disclosure, with reference to FIG3 and FIG5 , the cutoff side surfaces 320 of the second sub-signal traces 32 of the n signal traces are respectively opposite to and spaced apart from the first surfaces 220 of the n signal terminals 22 in the second direction D2;

[0099] The n spacing distances D22 between the cut-off side surfaces 320 of the second sub-signal traces 32 of the n signal traces and the first surfaces 220 of the n signal terminals 22 in the second direction D2 are substantially equal to each other.

[0100] By shrinking the second sub-signal trace 32 and adopting an in-plane via connection design to replace the traditional design of leading two metal traces out to the terminal together, the number of signal traces at the side outlet ends can be reduced, thereby reducing the probability of damage to the outlet traces in subsequent processing processes such as back etching, reducing the probability of short circuits in the side sections, and thus improving the yield of display products.

[0101] 13A-13C are partial schematic plan views of a display panel according to some embodiments of the present disclosure.

[0102] For example, in some embodiments of the present disclosure, the number of data lines set between adjacent second sub-signal traces can be one or more. For example, with reference to Figures 13A to 13C, in the second conductive layer, one data line is set between any two adjacent second sub-signal traces; or, in the second conductive layer, two or more data lines are set between any two adjacent second sub-signal traces; or, in the second conductive layer, one data line is set between some adjacent second sub-signal traces, and two or more data lines are set between other adjacent second sub-signal traces. The present disclosure does not specifically limit the number of data lines set between second sub-signal traces.

[0103] Exemplarily, in some embodiments of the present disclosure, referring to Figure 13A, the two adjacent second sub-signal lines 32 can be any two of the second sub-signal line 321 of the first voltage signal line VDD for transmitting the first voltage signal, the second sub-signal line 322 of the second voltage signal line VSSR for transmitting the second voltage signal, the second sub-signal line 323 of the third voltage signal line VSSGB for transmitting the third voltage signal, the second sub-signal line 324 of the initialization signal line Vinit for transmitting the initialization signal, and the second sub-signal line 325 of the pulse voltage signal line HF for transmitting the pulse voltage signal.

[0104] For example, the adjacent second sub-signal lines can be the second sub-signal line 321 of the first voltage signal line VDD for transmitting the first voltage signal and the second sub-signal line 322 of the second voltage signal line VSSR for transmitting the second voltage signal; and / or, the adjacent second sub-signal lines can also be the second sub-signal line 321 of the first voltage signal line VDD for transmitting the first voltage signal and the second sub-signal line 323 of the third voltage signal line VSSGB for transmitting the third voltage signal; and / or, the adjacent second sub-signal lines can also be the second sub-signal line 321 of the first voltage signal line VDD for transmitting the first voltage signal and the second sub-signal line 324 of the initialization signal line Vinit for transmitting the initialization signal; and / or, the adjacent second sub-signal lines can also be the second sub-signal line 321 of the first voltage signal line VDD for transmitting the first voltage signal and the second sub-signal line 325 of the pulse voltage signal line HF for transmitting the pulse voltage signal.

[0105] It should be noted that the signals transmitted by adjacent signal lines can be specifically set according to actual needs, and this disclosure does not limit this.

[0106] By using data lines to separate the shared mesh signal lines, when the product is subsequently tested, if a short circuit or other defect occurs in the product, the defective area can be accurately located, and then the defective area can be repaired in a targeted manner. For example, once a short circuit occurs during the flying probe process, since the shared signals in the entire signal line, such as the first voltage signal line VDD and the second voltage signal line VSSR, are separated by data lines, the two short-circuit signals can be accurately found in the flying probe test data. Targeted repairs are carried out at specific locations to avoid over-engraving caused by laser etching of other already engraved lines, thereby improving repair efficiency and overall process yield. Moreover, since the signal lines provide DC signals and the signal lines are spaced apart from the data lines, the signal lines after power-on can not only provide signals to the display panel, but also act as capacitors in the powered circuit, stabilizing the data signals in the data lines, thereby reducing the crosstalk of the data signals Data coupled with other pulse signals.

[0107] For example, in some embodiments of the present disclosure, first sub-signal lines of a plurality of signal lines may extend along the first direction D1 and be spaced apart in the second direction D2. Referring to FIG3 and FIG9 , the first sub-signal lines of the n signal lines include at least two of the following first sub-signal lines: a first sub-signal line 311 of a first voltage signal line for transmitting a first voltage signal; a first sub-signal line 312 of a second voltage signal line for transmitting a second voltage signal; a first sub-signal line 313 of a third voltage signal line for transmitting a third voltage signal; a first sub-signal line 314 of an initialization signal line for transmitting an initialization signal; and a first sub-signal line 315 of a pulse voltage signal line for transmitting a pulse voltage signal, wherein, in the second sub-side area SA2, the first sub-signal lines 31 of at least two types of signal lines are spaced apart in the second direction D2.

[0108] For example, in some embodiments of the present disclosure, continuing with reference to Figures 3 and 9, in the second sub-side area SA2, the first sub-signal line 315 of the pulse voltage signal line, the first sub-signal line 313 of the third voltage signal line, the first sub-signal line 312 of the second voltage signal line, the first sub-signal line 311 of the first voltage signal line and the first sub-signal line 314 of the initialization signal line are spaced apart in the second direction D2 in a manner that they are sequentially away from the multiple terminals 2.

[0109] By setting the first sub-signal line of the signal line, the second sub-signal line of the signal line and the third sub-signal line of the signal line located in different areas can be electrically connected within the surface, thereby reducing the number of side outlet end lines, thereby reducing the probability of damage to the outlet end lines in subsequent processing processes such as back etching, reducing the probability of short circuit in the side section, and thus improving the yield of the display product.

[0110] For example, in some embodiments of the present disclosure, with reference to FIG3 and FIG9 , in the second sub-side area SA2, first vias VH1 for electrically connecting the first sub-signal trace 31 and the second sub-signal trace 32 of at least two signal traces are spaced apart in both the first direction and the second direction. For example, first vias VH12 for electrically connecting the first sub-signal trace 312 and the second sub-signal trace 322 of the second voltage signal trace VSSR and first vias VH13 for electrically connecting the first sub-signal trace 313 and the second sub-signal trace 323 of the third voltage signal trace VSSGB are spaced apart in both the first direction D1 and the second direction D2.

[0111] For example, in some embodiments of the present disclosure, with reference to FIG3 , FIG9 , and FIG11 , in the second sub-side area SA2 , the third sub-signal trace 33 for electrically connecting at least two signal traces and the second vias VH2 of the conductive transition portion 51 are spaced apart in the first direction D1 and aligned in the second direction D2 . For example, the second via VH21 for electrically connecting the third sub-signal trace 33 for electrically connecting the first voltage signal trace VDD and the conductive transition portion and the second via VH22 for electrically connecting the third sub-signal trace VSSR and the conductive transition portion are spaced apart in the first direction D1 and aligned in the second direction D2 .

[0112] For example, in some embodiments of the present disclosure, in combination with Figures 3, 7 and 8, in the second sub-side area SA2, the width D13 of the orthographic projection of the third sub-signal line 33 on the substrate along the first direction is greater than the width D12 of the orthographic projection of the second sub-signal line that transmits the same signal as the third sub-signal line on the substrate along the first direction; and / or, in the second sub-side area, the width D12 of the orthographic projection of the second sub-signal line on the substrate along the first direction is greater than the width D14 of the orthographic projection of the data line on the substrate along the first direction.

[0113] By designing the width D13 of the third sub-signal line to be larger than the width D12 of the second sub-signal line that transmits the same signal as the third sub-signal line, and the orthographic projection of the third sub-signal line on the substrate covers the orthographic projection of the second sub-signal line that transmits the same signal as the third sub-signal line on the substrate, the in-plane wiring layout can be facilitated, the probability of short circuits in the in-plane processing process can be reduced, and the yield of display products can be improved.

[0114] The width of the orthographic projection of the second sub-signal line 32 and the third sub-signal line 33 of the signal line on the substrate is designed to be larger than the width of the orthographic projection of the data line on the substrate, which can increase the shielding effect of the signal line. The signal line can act as a capacitor in the power-on circuit to stabilize the data signal in the data line, thereby reducing the crosstalk of the data signal Data caused by coupling with other pulse signals.

[0115] FIG14 is a schematic structural diagram of a display device according to some embodiments of the present disclosure.

[0116] Some exemplary embodiments of the present disclosure further provide a display device 2000. Referring to Fig. 14 , the display device 2000 includes any of the display panels 1000 described above.

[0117] FIG15 is a schematic structural diagram of a display device according to some embodiments of the present disclosure.

[0118] For example, in some embodiments of the present disclosure, referring to FIG. 15 , a display device 2000 may further include multiple display panels 1000 , which may be spliced ​​together to achieve a spliced ​​display. In the spliced ​​display panels, the lead-out wiring design may also adopt the lead-out wiring design of any of the display panels 1000 described above, thereby reducing the probability of lead-out short circuits and improving the yield of the overall display device.

[0119] Those skilled in the art will appreciate that the features described in the various embodiments and / or claims of this disclosure may be combined and / or coupled in various ways, even if such combinations and / or couplings are not explicitly described in this disclosure. In particular, the features described in the various embodiments and / or claims of this disclosure may be combined and / or coupled in various ways without departing from the spirit and teachings of this disclosure. All such combinations and / or couplings are intended to fall within the scope of this disclosure.

[0120] Although the present disclosure has been shown and described with reference to certain exemplary embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made to the present disclosure without departing from the spirit and scope of the present disclosure as defined by the appended claims and their equivalents. Therefore, the scope of the present disclosure should not be limited to the above-described embodiments, but should be determined not only by the appended claims but also by the equivalents of the appended claims.

Claims

1. A display panel, wherein: The display panel comprises: A substrate, the substrate comprising at least one side region and a display region, the at least one side region being closer to a side edge of the substrate than the display region, the at least one side region comprising a first sub-side region and a second sub-side region, the first sub-side region being closer to the side edge of the substrate than the second sub-side region; A plurality of pixel units are arranged in the display area, the plurality of pixel units are distributed in an array on the substrate along a first direction and a second direction, at least one of the pixel units comprises a light emitting diode and a pixel driving circuit for driving the light emitting diode, wherein the first direction and the second direction intersect; A plurality of terminals disposed on the base substrate and located in the first sub-side region; and At least one signal line is provided on the substrate, at least a portion of the at least one signal line extends from the first sub-side region to the display region via the second sub-side region, one end of the at least one signal line is electrically connected to the terminal, and the other end is electrically connected to the pixel driving circuit; Wherein, the display panel further includes: A first conductive layer disposed on the base substrate; A second conductive layer disposed on a side of the first conductive layer away from the base substrate; and A third conductive layer is disposed on a side of the second conductive layer away from the base substrate, Wherein, the at least one signal routing line comprises a first sub-signal routing line, a second sub-signal routing line and a third sub-signal routing line which are electrically connected to each other; The first signal sub-wire is located in the first conductive layer and extends along a first direction; The second sub-signal wiring is located in the second conductive layer and extends along a second direction; The third signal sub-wire is located in the third conductive layer and extends along the second direction; The orthographic projection of at least one of the second sub-signal routing and the third sub-signal routing on the substrate at least partially overlaps with the orthographic projection of the first sub-signal routing on the substrate; and One end of the third sub-signal routing is connected to at least one of the terminals, and the orthographic projection of the second sub-signal routing on the substrate is closer to the display area than the orthographic projection of one end of the third sub-signal routing connected to at least one of the terminals on the substrate, and the orthographic projection of the second sub-signal routing on the substrate is spaced apart from the orthographic projection of the terminal on the substrate in the second direction.

2. The display panel according to claim 1, wherein: The orthographic projection of a portion of the third sub-signal routing line on the substrate falls into the first sub-side region; as well as The second sub-signal routing line is electrically connected to the third sub-signal routing line through the first sub-signal routing line.

3. The display panel according to claim 1 or 2, wherein: The second sub-signal routing line is electrically connected to the first sub-signal routing line through at least one first via hole.

4. The display panel according to claim 3, wherein: The display panel further includes a conductive transition portion located in the second conductive layer; The third signal sub-wire is electrically connected to one end of the conductive transition portion through a second via.

5. The display panel according to claim 4, wherein: The other end of the conductive transition portion is electrically connected to the first sub-signal trace through a third via hole.

6. The display panel according to any one of claims 1 to 5, wherein: The display panel further includes m data lines and n signal lines, the plurality of terminals include m data terminals and n signal terminals, one end of the m data lines is electrically connected to the m data terminals respectively, and one end of the n signal lines is electrically connected to the n signal terminals respectively, wherein m and n are positive integers greater than or equal to 3; At least one data terminal is arranged between any two adjacent signal terminals.

7. The display panel according to claim 6, wherein: The m data lines are located in the second conductive layer; In the second conductive layer, at least one data line is arranged between any two adjacent second signal sub-lines.

8. The display panel according to any one of claims 1 to 7, wherein: At least one of the terminals includes a first sub-terminal located in the second conductive layer and a second sub-terminal located in the third conductive layer, and the first sub-terminal and the second sub-terminal are electrically connected through a fourth via.

9. The display panel according to claim 8, wherein: In the second conductive layer, the second sub-signal trace includes a cutoff side surface facing the first sub-terminal, the first sub-terminal includes a first surface facing the cutoff side surface, and the cutoff side surface and the first surface are spaced a specified distance apart in the second direction.

10. The display panel according to claim 9, wherein: In the second direction, the cutoff side surface of the second sub-signal routing line is closer to the terminal than the first sub-signal routing line electrically connected to the second sub-signal routing line.

11. The display panel according to claim 10, wherein: In the second direction, the cutoff side surface of the second signal sub-line is closer to the terminal than each of the first via, the second via, and the third via electrically connected to the second signal sub-line.

12. The display panel according to any one of claims 1 to 11, wherein: In the second sub-side region, the orthographic projection of the third sub-signal routing line on the substrate covers the orthographic projection of the second sub-signal routing line that transmits the same signal as the third sub-signal routing line on the substrate.

13. The display panel according to claim 12, wherein: In the second sub-side region, the width of the orthographic projection of the third sub-signal line on the substrate along the first direction is greater than the width of the orthographic projection of the second sub-signal line transmitting the same signal as the third sub-signal line on the substrate along the first direction.

14. The display panel according to any one of claims 1 to 13, wherein: The n signal traces include at least two of the following signal traces: A first voltage signal wiring for transmitting a first voltage signal; A second voltage signal wiring for transmitting a second voltage signal; A third voltage signal wiring for transmitting a third voltage signal; An initialization signal routing line for transmitting an initialization signal; and Pulse voltage signal routing used to transmit pulse voltage signals.

15. The display panel according to claim 14, wherein: The cut-off side surfaces of the second sub-signal routings of the n signal routings are respectively opposite to the first surfaces of the n signal terminals in the second direction and are spaced apart from each other; The n spacing distances between the cut-off side surfaces of the second sub-signal routing lines of the n signal routing lines and the first surfaces of the n signal terminals in the second direction are substantially equal to each other.

16. The display panel according to claim 6, wherein: In the second conductive layer, one data line is arranged between any two adjacent second signal sub-lines; or, In the second conductive layer, between any two adjacent second signal sub-lines, two or more data lines are arranged; or, In the second conductive layer, one data line is arranged between some adjacent two of the second signal sub-lines, and more than two data lines are arranged between other adjacent two of the second signal sub-lines.

17. The display panel according to claim 16, wherein: The first sub-signal routings of the n signal routings include at least two of the following first sub-signal routings: a first sub-signal line of a first voltage signal line for transmitting a first voltage signal; A first sub-signal routing of a second voltage signal routing for transmitting a second voltage signal; a first sub-signal routing of a third voltage signal routing for transmitting a third voltage signal; A first sub-signal routing of an initialization signal routing for transmitting an initialization signal; and A first sub-signal wiring of a pulse voltage signal wiring for transmitting a pulse voltage signal, Wherein, in the second sub-side region, first sub-signal routing lines of at least two types of signal routing lines are arranged at intervals in the second direction.

18. The display panel according to claim 17, wherein: In the second sub-side area, the first sub-signal route of the pulse voltage signal route, the first sub-signal route of the third voltage signal route, the first sub-signal route of the second voltage signal route, the first sub-signal route of the first voltage signal route and the first sub-signal route of the initialization signal route are spaced apart in a manner that is sequentially away from the multiple terminals in the second direction.

19. The display panel according to any one of claims 3 to 5, wherein: In the second sub-side region, first vias for electrically connecting first sub-signal routings and second sub-signal routings of at least two types of signal routings are arranged at intervals in the first direction and the second direction.

20. The display panel according to claim 4 or 5, wherein: In the second sub-side region, the third sub-signal routing lines for electrically connecting at least two signal routing lines and the second via holes of the conductive transfer portion are arranged at intervals in the first direction and aligned in the second direction.

21. The display panel according to any one of claims 1 to 20, wherein: In the second sub-side region, the width of the orthographic projection of the third sub-signal line on the substrate along the first direction is greater than the width of the orthographic projection of the second sub-signal line transmitting the same signal as the third sub-signal line on the substrate along the first direction; and / or, In the second sub-side region, a width of an orthographic projection of the second sub-signal wiring on the base substrate along the first direction is greater than a width of an orthographic projection of the data line on the base substrate along the first direction.

22. A display device, wherein: The display device includes the display panel according to any one of claims 1 to 21.

23. The display device according to claim 22, wherein: The display device includes a plurality of spliced ​​display panels.

Images