Display substrate and display device

Abstract

The invention provides a display substrate and a display device. The display substrate comprises: a substrate; the pixel units comprise a plurality of sub-pixels which are distributed in an array mode in the first direction and the second direction, and the sub-pixels comprise the first sub-pixels and the second sub-pixels which are located in the same column and two adjacent rows; the sensing transistor is used for driving the sub-pixel and comprises a third grid electrode and a third active layer; and a scanning signal line including a main body portion extending in a first direction and a plurality of protruding portions extending in a second direction. The plurality of protruding parts comprise first protruding parts and second protruding parts, and the orthographic projections of the first protruding parts and the second protruding parts on the substrate are at least partially overlapped with the third active layers of the sensing transistors of the first sub-pixels and the second sub-pixels respectively; the overlapped parts are third grid electrodes of the sensing transistors of the first sub-pixel and the second sub-pixel respectively; the third gates of the sensing transistors of the first sub-pixel and the second sub-pixel are located on both sides of the main body portion of the same scanning signal line in the second direction.

Description

Display substrate and display device Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display substrate and a display device. Background Art

[0002] Organic Light-Emitting Diode (OLED) devices have attracted much attention due to their advantages such as self-luminescence, rich colors, fast response speed, wide viewing angle, light weight, thin thickness, low power consumption, and flexible display. They are now widely used in mobile phones, televisions, wearable devices, etc. With the continuous development of display technology, people's requirements for the image quality of OLED display panels are also getting higher and higher. High pixel density (Pixels Per Inch, PPI) display panels have high image density and better image quality. However, the higher the PPI of the display panel, the smaller the pixel size and the less wiring space.

[0003] How to rationally layout devices and signal lines in a limited space while taking into account the pixel aperture ratio, improve the space utilization of display products, increase the aperture ratio, and increase the life of the display panel is one of the important topics studied by R&D personnel.

[0004] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art.

[0005] Summary of the Invention

[0006] In one aspect, a display substrate is provided, comprising: a base substrate; a plurality of pixel units located on the base substrate, at least one pixel unit including a plurality of sub-pixels, at least one sub-pixel including a light-emitting element and a pixel driving circuit for driving the light-emitting element, wherein the plurality of sub-pixels of the plurality of pixel units are distributed in an array along a first direction and a second direction on the base substrate, and the first direction and the second direction intersect; a scanning signal line located on the base substrate, the scanning signal line including a main body extending along the first direction and a plurality of protrusions extending along the second direction, wherein the pixel driving circuit includes a sensing transistor, the sensing transistor including a third gate and a third active layer; the plurality of sub-pixels of at least one pixel unit including a first sub-pixel and a second sub-pixel, the first sub-pixel being located in the i-th row and j-th column, and the second sub-pixel being located in the i+1-th row and j-th column, wherein , i and j are both positive integers greater than or equal to 1; the multiple protrusions include a first protrusion and a second protrusion, the orthographic projection of the first protrusion on the base substrate at least partially overlaps with the third active layer of the sensing transistor of the first sub-pixel, and the portion where the first protrusion overlaps with the third active layer of the sensing transistor of the first sub-pixel is the third gate of the sensing transistor of the first sub-pixel; the orthographic projection of the second protrusion on the base substrate at least partially overlaps with the third active layer of the sensing transistor of the second sub-pixel, and the portion where the second protrusion overlaps with the third active layer of the sensing transistor of the second sub-pixel is the third gate of the sensing transistor of the second sub-pixel; and the third gate of the sensing transistor of the first sub-pixel and the third gate of the sensing transistor of the second sub-pixel are respectively located on both sides of the main body of the same scanning signal line in the second direction.

[0007] According to some exemplary embodiments, the multiple sub-pixels of at least one pixel unit further include a third sub-pixel and a fourth sub-pixel, the third sub-pixel being located at the i-th row and the j+1-th column, and the fourth sub-pixel being located at the i+1-th row and the j+1-th column; the multiple protrusions further include a third protrusion and a fourth protrusion, the orthographic projection of the third protrusion on the substrate at least partially overlapping with the third active layer of the sensing transistor of the third sub-pixel, and the portion where the third protrusion overlaps with the third active layer of the sensing transistor of the third sub-pixel is the third gate of the sensing transistor of the third sub-pixel; the orthographic projection of the fourth protrusion on the substrate at least partially overlapping with the third active layer of the sensing transistor of the fourth sub-pixel, and the portion where the fourth protrusion overlaps with the third active layer of the sensing transistor of the fourth sub-pixel is the third gate of the sensing transistor of the fourth sub-pixel; and the third gate of the sensing transistor of the third sub-pixel and the third gate of the sensing transistor of the fourth sub-pixel are respectively located on both sides of the main body of the same scanning signal line in the second direction.

[0008] According to some exemplary embodiments, the display substrate further includes a sensing signal line extending along the second direction, the sensing signal line being used to provide a sensing signal to the pixel driving circuit; and the third gate of the sensing transistor of the first sub-pixel and the third gate of the sensing transistor of the third sub-pixel are respectively located on both sides of the same sensing signal line in the first direction; and / or the third gate of the sensing transistor of the second sub-pixel and the third gate of the sensing transistor of the fourth sub-pixel are respectively located on both sides of the same sensing signal line in the first direction.

[0009] According to some exemplary embodiments, the third active layer of the sensing transistor further includes a channel region, a first pole region and a second pole region; the orthographic projection of the channel region of the third active layer on the substrate at least partially overlaps with the orthographic projection of the third gate on the substrate, and the first pole region and the second pole region are respectively located on both sides of the channel region of the third active layer in the first direction; at least a portion of the third active layer located between the channel region of the sensing transistor of the first sub-pixel and the channel region of the sensing transistor of the third sub-pixel is simultaneously used as the first pole region of the sensing transistor of the first sub-pixel and the second pole region of the sensing transistor of the third sub-pixel; and / or, at least a portion of the third active layer located between the channel region of the sensing transistor of the second sub-pixel and the channel region of the sensing transistor of the fourth sub-pixel is simultaneously used as the first pole region of the sensing transistor of the second sub-pixel and the second pole region of the sensing transistor of the fourth sub-pixel.

[0010] According to some exemplary embodiments, the third gate of the sensing transistor of the first sub-pixel and the third gate of the sensing transistor of the third sub-pixel are symmetrical with respect to a first center line, wherein the first center line is an imaginary straight line passing through the center of the sensing line and extending along the second direction; and / or the third gate of the sensing transistor of the second sub-pixel and the third gate of the sensing transistor of the fourth sub-pixel are symmetrical with respect to the first center line.

[0011] According to some exemplary embodiments, the third active layer of the sensing transistor of the first sub-pixel and the third active layer of the sensing transistor of the third sub-pixel are connected to each other and extend along a first direction.

[0012] According to some exemplary embodiments, the first protrusion and the second protrusion respectively protrude from the main body of the same scanning signal line in opposite directions in the second direction, and the first protrusion and the second protrusion are offset by a first predetermined distance in the first direction; and / or, the third protrusion and the fourth protrusion respectively protrude from the main body of the same scanning signal line in opposite directions in the second direction, and the third protrusion and the fourth protrusion are offset by a second predetermined distance in the first direction.

[0013] According to some exemplary embodiments, the pixel driving circuit further includes a switching transistor, which includes a second gate and a second active layer; the multiple protrusions include a fifth protrusion and a sixth protrusion, the orthographic projection of the fifth protrusion on the base substrate at least partially overlaps with the second active layer of the switching transistor of the first sub-pixel, and the portion where the fifth protrusion overlaps with the second active layer of the switching transistor of the first sub-pixel is the second gate of the switching transistor of the first sub-pixel; the orthographic projection of the sixth protrusion on the base substrate at least partially overlaps with the second active layer of the switching transistor of the second sub-pixel, and the portion where the sixth protrusion overlaps with the second active layer of the switching transistor of the second sub-pixel is the second gate of the switching transistor of the second sub-pixel; and the second gate of the switching transistor of the first sub-pixel and the second gate of the switching transistor of the second sub-pixel are respectively located on both sides of the main body of the same scanning signal line in the second direction.

[0014] According to some exemplary embodiments, the fifth protrusion and the sixth protrusion respectively protrude from the main portion of the same scan signal line in opposite directions in the second direction, and the fifth protrusion and the sixth protrusion are offset by a third predetermined distance in the first direction.

[0015] According to some exemplary embodiments, any two of the first predetermined distance, the second predetermined distance, and the third predetermined distance are substantially equal.

[0016] According to some exemplary embodiments, the sensing signal line includes a line main body and a first line protrusion, the first line protrusion protruding from the line main body toward the first sub-pixel; the display substrate also includes a first conductive connection portion, the first conductive connection portion, the first protrusion and the third protrusion are located in the same layer, and the first conductive connection portion is located between the first protrusion and the third protrusion in the first direction; and the orthographic projection of the first line protrusion on the base substrate at least partially overlaps with the orthographic projection of the first conductive connection portion on the base substrate, and the first line protrusion is electrically connected to the first conductive connection portion through a first via.

[0017] According to some exemplary embodiments, the orthographic projection of any one of the first conductive connection portion and the first via on the substrate at least partially overlaps with the orthographic projection of a portion of the third active layer serving as the first electrode region of the sensing transistor of the first sub-pixel and the second electrode region of the sensing transistor of the third sub-pixel on the substrate.

[0018] According to some exemplary embodiments, the display substrate further includes a second conductive connection portion, the second conductive connection portion, the first protrusion and the fifth protrusion are located on the same layer, and the second conductive connection portion is located between the first protrusion and the fifth protrusion in the first direction; the display substrate further includes a light-shielding portion located on the base substrate, the light-shielding portion, the second electrode region of the sensing transistor of the first sub-pixel and the second conductive connection portion have their orthographic projections on the base substrate at least partially overlap, and the second electrode region of the sensing transistor of the first sub-pixel is electrically connected to the light-shielding portion through the second conductive connection portion and the second via.

[0019] According to some exemplary embodiments, the orthographic projection of the second active layer on the base substrate at least partially overlaps with the orthographic projection of the light-shielding portion on the base substrate; the pixel driving circuit also includes a storage capacitor, the storage capacitor includes a first plate and a second plate, at least a portion of the second active layer is used as the first plate, and at least a portion of the light-shielding portion is used as the second plate.

[0020] According to some exemplary embodiments, the sensing signal line further includes a first widening portion, the width of the first widening portion in the first direction is greater than the width of the line main body portion in the first direction, and the orthographic projection of the first widening portion on the substrate is located in the first direction between the orthographic projection of the first plate of the storage capacitor of the first sub-pixel on the substrate and the orthographic projection of the first plate of the storage capacitor of the third sub-pixel on the substrate; and / or, the sensing signal line further includes a second widening portion, the width of the second widening portion in the first direction is greater than the width of the line main body portion in the first direction, and the orthographic projection of the second widening portion on the substrate is located in the first direction between the orthographic projection of the first plate of the storage capacitor of the second sub-pixel on the substrate and the orthographic projection of the first plate of the storage capacitor of the fourth sub-pixel on the substrate.

[0021] According to some exemplary embodiments, the orthographic projection of the first widening portion on the substrate and the orthographic projection of the first plate of the storage capacitor of the first sub-pixel on the substrate are spaced apart by a first spacing distance in the first direction; the orthographic projection of the first widening portion on the substrate and the orthographic projection of the first plate of the storage capacitor of the third sub-pixel on the substrate are spaced apart by a second spacing distance in the first direction; the first spacing distance is substantially equal to the second spacing distance; and / or, the orthographic projection of the second widening portion on the substrate and the orthographic projection of the first plate of the storage capacitor of the second sub-pixel on the substrate are spaced apart by a third spacing distance in the first direction; the orthographic projection of the second widening portion on the substrate and the orthographic projection of the first plate of the storage capacitor of the fourth sub-pixel on the substrate are spaced apart by a fourth spacing distance in the first direction; the third spacing distance is substantially equal to the fourth spacing distance.

[0022] According to some exemplary embodiments, the display substrate further includes a first conductive connection portion, the first conductive connection portion, the first protrusion portion and the second protrusion portion are located on the same layer; and the orthographic projection of the first widening portion on the base substrate at least partially overlaps with the orthographic projection of the first conductive connection portion on the base substrate, and the first widening portion is electrically connected to the first conductive connection portion through a first via.

[0023] According to some exemplary embodiments, the third active layer further includes an active extension portion, which extends from a portion of the third active layer serving as both the first electrode region of the sensing transistor of the first sub-pixel and the second electrode region of the sensing transistor of the third sub-pixel in a direction parallel to an extension direction of the sensing signal line; an orthographic projection of the active extension portion on the substrate at least partially overlaps with an orthographic projection of the sensing signal line on the substrate; and the active extension portion is electrically connected to the first conductive connection portion.

[0024] According to some exemplary embodiments, the second active layer includes a first portion extending along a first direction, a second portion extending along a second direction, and a third portion serving as the first electrode plate, a portion where the first portion overlaps with the fifth protrusion is a channel region of the switching transistor, the second portion connects the first portion and the third portion; and a width of the second portion in the first direction is greater than a width of the first portion in the second direction.

[0025] According to some exemplary embodiments, the pixel driving circuit also includes a driving transistor, which includes a first active layer; the display substrate also includes a fifth conductive connection portion and a first power signal line for transmitting a first power signal, the fifth conductive connection portion and the scanning signal line are located on the same layer, and the first power signal line and the sensing signal line are located on the same layer; one end of the fifth conductive connection portion is electrically connected to the first active layer through a fifth via, and the other end of the fifth conductive connection portion is electrically connected to the first power signal line through a sixth via; and two sub-pixels located in two adjacent rows of pixel units and in the same column share the fifth conductive connection portion.

[0026] According to some exemplary embodiments, the display substrate includes: a semiconductor layer located on the base substrate; a first conductive layer located on a side of the semiconductor layer away from the base substrate; a second conductive layer located on a side of the first conductive layer away from the base substrate; and a light-shielding layer located on a side of the semiconductor layer close to the base substrate, wherein the light-shielding portion is located in the light-shielding layer, the first active layer, the second active layer and the third active layer are located in the semiconductor layer, the scanning signal line, the first conductive connection portion and the second conductive connection portion are located in the first conductive layer, and the sensing signal line and the first power supply line are located in the second conductive layer.

[0027] According to some exemplary embodiments, the display substrate further includes: a pixel defining layer located on a side of the second conductive layer away from the base substrate, the pixel defining layer being used to define a plurality of pixel openings; and a reflective electrode layer located on a side of the pixel defining layer away from the base substrate; and the pixel defining layer is further used to define a plurality of grooves, the plurality of grooves being respectively located between any two adjacent pixel openings, and at least a portion of the reflective electrode layer being located in the plurality of grooves.

[0028] According to some exemplary embodiments, the display substrate further includes a first conductive portion located on a side of the light-shielding layer close to the base substrate; and a second conductive portion located in the semiconductor layer; the orthographic projection of the first conductive portion on the base substrate at least partially overlaps with the orthographic projection of the pixel opening on the base substrate, and the orthographic projection of the second conductive portion on the base substrate at least partially overlaps with the orthographic projection of the pixel opening on the base substrate; and the first electrode further includes the second conductive portion, the second electrode further includes the first conductive portion, the first conductive portion is electrically connected to the light-shielding portion, and the first conductive portion includes a transparent conductive material.

[0029] According to some exemplary embodiments, the display substrate further includes a plurality of data lines located in the second conductive layer, the plurality of data lines including a first data line, a second data line, a third data line and a fourth data line, the first data line being electrically connected to the first electrode of the switching transistor of the first sub-pixel, the second data line being electrically connected to the first electrode of the switching transistor of the second sub-pixel, the third data line being electrically connected to the first electrode of the switching transistor of the third sub-pixel, and the fourth data line being electrically connected to the first electrode of the switching transistor of the fourth sub-pixel; and the first data line and the second data line being located on one side of the pixel driving circuit of the pixel unit in the first direction, the third data line and the fourth data line being located on the other side of the pixel driving circuit of the pixel unit in the first direction, the first data line and the second data line being spaced apart in the first direction, the first data line being located on the side of the second data line away from the pixel driving circuit of the pixel unit, and the fourth data line being located on the side of the third data line away from the pixel driving circuit of the pixel unit.

[0030] In another aspect, a display device is provided, comprising the display substrate as described in any one of the above items. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The above contents and other objects, features and advantages of the present disclosure will become more apparent through the following description of the embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0032] FIG1 is a schematic plan view of a display substrate according to an embodiment of the present disclosure;

[0033] 2A is an equivalent circuit diagram of a pixel driving circuit of a plurality of sub-pixels of the display substrate in FIG. 1 , and FIG. 2B is an equivalent circuit diagram of a pixel circuit of a single sub-pixel of the display substrate in FIG. 1 ;

[0034] 3 is a partial plan view of a display substrate according to some embodiments of the present disclosure, schematically showing a plan view of a pixel driving circuit and a first electrode of a light-emitting element included in the display substrate;

[0035] 4A to 4I are plan views of the multiple film layers shown in FIG3 , wherein FIG4A shows a light shielding layer 30, which includes a plurality of light shielding portions 31; FIG4B shows a second conductive layer 20; FIG4C shows an active layer 40; FIG4D shows a plurality of GI vias; FIG4E shows a first conductive layer 10; FIG4F shows a plurality of passivation layer PVX vias; FIG4G shows a plurality of light emitting element first electrode vias; FIG4H shows a light emitting element first electrode; FIG4I shows a pixel defining layer; and FIG4J shows a schematic diagram of a combined film layer of the second conductive layer 20 and the first conductive layer 10.

[0036] FIG5 is a partial enlarged view of the vicinity of the dotted rectangular area in FIG3 ;

[0037] 6A is a cross-sectional view taken along dotted line 1 in FIG. 5 , and FIG. 6B is a cross-sectional view taken along dotted line 2 in FIG. 5 , wherein the orthographic projections of dotted line 1 and dotted line 2 on the base substrate partially overlap with the second via hole VH2 ;

[0038] FIG7 is a plan view schematically showing a stack of a local light shielding layer 30 and an active layer 40 according to some exemplary embodiments of the present disclosure;

[0039] FIG8 is a partial plan view of a display substrate according to other embodiments of the present disclosure, showing a widened portion of a sensing signal line;

[0040] FIG9 is a partial enlarged view of the area near the upper dotted box in FIG8 ;

[0041] FIG10 is a partial schematic plan view of a display substrate according to some other embodiments of the present disclosure, showing an active extension portion of a third active layer;

[0042] FIG11 is a partial enlarged view of the area near the middle scanning signal line in FIG10;

[0043] FIG12 is a partial schematic plan view of a display substrate according to other embodiments of the present disclosure;

[0044] FIG. 13 is a partial cross-sectional schematic diagram of a display substrate according to other embodiments of the present disclosure.

[0045] It should be noted that, for the sake of clarity, in the drawings used to describe the embodiments of the present invention, the sizes of layers, structures or regions may be enlarged or reduced, that is, these drawings are not drawn according to the actual scale. DETAILED DESCRIPTION

[0046] To make the purpose, technical solutions, and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0047] It should be noted that in the drawings, the sizes and relative sizes of elements may be exaggerated for clarity and / or descriptive purposes. Thus, the sizes and relative sizes of the individual elements are not necessarily limited to those shown in the drawings. In the specification and drawings, the same or similar reference numerals indicate the same or similar parts.

[0048] Unless otherwise defined, technical or scientific terms used in this disclosure should have the ordinary meanings understood by those of ordinary skill in the art. The terms "first," "second," and similar terms used in this disclosure do not denote any order, quantity, or importance, but are simply used to distinguish different components. The terms "include," "comprising," and similar words mean that the element or object preceding the word encompasses the elements or objects listed after the word, and their equivalents, without excluding other elements or objects.

[0049] Unless otherwise specified, directional terms such as "upper," "lower," "left," "right," "inner," and "outer" are used herein to indicate positions or relationships based on the figures shown. These terms are intended solely to facilitate the description of the present disclosure and are not intended to indicate or imply that the devices, components, or parts referred to must have, be constructed, or operate in a specific orientation. It should be understood that when the absolute positions of the objects being described change, the relative positions they represent may also change accordingly. Therefore, these directional terms should not be construed as limiting the present disclosure.

[0050] It should be noted that, in this article, the term "the same layer" refers to a layer structure formed by using the same film-forming process to form a film layer used to form a specific pattern, and then patterning the film layer using the same mask through a single patterning process. Depending on the specific pattern, a single patterning process may include multiple exposure, development, or etching processes, and the specific pattern in the resulting layer structure may be continuous or discontinuous. In other words, multiple elements, components, structures, and / or parts located in the "same layer" are composed of the same material and are formed through the same patterning process. Typically, multiple elements, components, structures, and / or parts located in the "same layer" have approximately the same thickness.

[0051] Those skilled in the art should understand that, in this article, unless otherwise specified, the expression "height" or "thickness" refers to the dimension of the surface of each film layer arranged perpendicular to the display substrate, that is, the dimension along the light emitting direction of the display substrate, or the dimension along the normal direction of the display device.

[0052] In this document, the directional expressions "first direction" and "second direction" are used to describe different directions along a pixel unit, such as the longitudinal and transverse directions of a pixel unit, or the row and column directions of a sub-pixel arrangement. It should be understood that such expressions are merely exemplary descriptions and are not intended to limit the present disclosure.

[0053] In this document, the term "transistor" may refer to a triode, a thin-film transistor, a field-effect transistor, or other device with similar characteristics. In the embodiments of the present disclosure, to distinguish the two electrodes of a transistor other than the control electrode, one electrode is referred to as the first electrode, and the other electrode is referred to as the second electrode. In actual operation, when the transistor is a thin-film transistor or a field-effect transistor, the first electrode may be the drain electrode, and the second electrode may be the source electrode; alternatively, the first electrode may be the source electrode, and the second electrode may be the drain electrode.

[0054] Some exemplary embodiments of the present disclosure provide a display substrate, comprising: a base substrate; a plurality of pixel units located on the base substrate, at least one pixel unit including a plurality of sub-pixels, at least one sub-pixel including a light-emitting element and a pixel driving circuit for driving the light-emitting element, wherein the plurality of sub-pixels of the plurality of pixel units are distributed in an array along a first direction and a second direction on the base substrate, and the first direction and the second direction intersect; a scanning signal line located on the base substrate, the scanning signal line including a main body extending along the first direction and a plurality of protrusions extending along the second direction, wherein the pixel driving circuit includes a sensing transistor, the sensing transistor including a third gate and a third active layer; the plurality of sub-pixels of at least one pixel unit including a first sub-pixel and a second sub-pixel, the first sub-pixel being located at the i-th row and j-th column, and the second sub-pixel being located at the i+1-th row and j-th column. , wherein i and j are positive integers greater than or equal to 1; the multiple protrusions include a first protrusion and a second protrusion, the orthographic projection of the first protrusion on the substrate at least partially overlaps with the third active layer of the sensing transistor of the first sub-pixel, and the portion where the first protrusion overlaps with the third active layer of the sensing transistor of the first sub-pixel serves as the third gate of the sensing transistor of the first sub-pixel; the orthographic projection of the second protrusion on the substrate at least partially overlaps with the third active layer of the sensing transistor of the second sub-pixel, and the portion where the second protrusion overlaps with the third active layer of the sensing transistor of the second sub-pixel serves as the third gate of the sensing transistor of the second sub-pixel; and the third gate of the sensing transistor of the first sub-pixel and the third gate of the sensing transistor of the second sub-pixel are respectively located on opposite sides of the main body of the same scanning signal line in the second direction. In this way, the sensing transistors of the sub-pixels can be evenly distributed on the upper and lower sides of the gate line, greatly improving space utilization, increasing the aperture ratio of the display panel, and increasing the life of the display panel.

[0055] FIG. 1 is a schematic plan view of a display substrate according to an embodiment of the present disclosure.

[0056] 1 , a display substrate according to an embodiment of the present disclosure may include a base substrate 100, a pixel unit PX disposed on the base substrate 100, a driving unit DRU disposed on the base substrate 100, and a trace PL electrically connecting the pixel unit PX to the driving unit DRU, wherein the driving unit DRU is used to drive the pixel unit PX.

[0057] The display substrate may include a display area AA and a non-display area NA. The display area AA may be an area where a pixel unit PX displaying an image is provided. Each pixel unit PX will be described later. The non-display area NA is an area where no pixel unit PX is provided, that is, it may be an area where no image is displayed. A driving unit DRU for driving the pixel unit PX and some traces PL connecting the pixel unit PX to the driving unit DRU may be provided in the non-display area NA. The non-display area NA corresponds to a border in the final display device, and the width of the border may be determined based on the width of the non-display area NA.

[0058] The display area AA can have various shapes. For example, the display area AA can be provided in various shapes, such as a closed polygon (e.g., a rectangle) with straight sides, a circle or an ellipse with curved sides, or a semicircle or a semiellipse with both straight and curved sides. In the embodiment of the present disclosure, the display area AA is provided as a quadrilateral with straight sides. It should be understood that this is merely an exemplary embodiment of the present disclosure and is not intended to limit the present disclosure.

[0059] The non-display area NA may be provided on at least one side of the display area AA. In an embodiment of the present disclosure, the non-display area NA may surround the periphery of the display area AA. In an embodiment of the present disclosure, the non-display area NA may include a transverse portion extending in a first direction X and a longitudinal portion extending in a second direction Y.

[0060] The pixel unit PX is provided in the display area AA. The pixel unit PX is the smallest unit for displaying an image and may be provided in plurality. For example, the pixel unit PX may include a light emitting device that emits white light and / or colored light.

[0061] The pixel units PX may be provided in a plurality and arranged in a matrix along rows extending in the first direction X and columns extending in the first direction Y. However, the embodiments of the present disclosure do not specifically limit the arrangement of the pixel units PX, and the pixel units PX may be arranged in various forms. For example, the pixel units PX may be arranged such that a direction inclined relative to the first direction X and the first direction Y becomes a column direction, and a direction intersecting the column direction becomes a row direction.

[0062] A pixel unit PX may include multiple sub-pixels. For example, a pixel unit PX may include three sub-pixels, namely, a first sub-pixel SP1, a second sub-pixel SP2, and a third sub-pixel SP3. For another example, a pixel unit PX may include four sub-pixels, namely, a first sub-pixel SP1, a second sub-pixel SP2, a third sub-pixel SP3, and a fourth sub-pixel. For example, the first sub-pixel SP1 may be a red sub-pixel, the second sub-pixel SP2 may be a green sub-pixel, the third sub-pixel SP3 may be a blue sub-pixel, and the fourth sub-pixel may be a white sub-pixel.

[0063] Each sub-pixel may include a light-emitting element and a pixel driving circuit for driving the light-emitting element. For example, a first sub-pixel SP1 may include a first light-emitting element located in a first light-emitting area SPA1 and a first pixel driving circuit SPC1 for driving the first light-emitting element. The first light-emitting element may emit red light. A second sub-pixel SP2 may include a second light-emitting element located in a second light-emitting area SPA2 and a second pixel driving circuit SPC2 for driving the second light-emitting element. The second light-emitting element may emit green light. A third sub-pixel SP3 may include a third light-emitting element located in a third light-emitting area SPA3 and a third pixel driving circuit SPC3 for driving the third light-emitting element. The third light-emitting element may emit blue light.

[0064] The light-emitting region of a sub-pixel may be the region where the light-emitting element of the sub-pixel is located. For example, in an OLED display panel, the light-emitting element of a sub-pixel may include a first electrode (e.g., an anode), a light-emitting material layer, and a second electrode (e.g., a cathode) in a stacked arrangement. Thus, the light-emitting region of a sub-pixel may be the region corresponding to the portion of the light-emitting material layer sandwiched between the anode and cathode.

[0065] The sub-pixel also includes a non-emissive area. For example, the pixel driver circuit of the sub-pixel is located in the non-emissive area of ​​the sub-pixel. The ratio of the area of ​​the emissive area of ​​each sub-pixel to the overall area of ​​the sub-pixel (the sum of the areas of the emissive and non-emissive areas) determines the aperture ratio of the sub-pixel.

[0066] The light-emitting device of the OLED (e.g., the light-emitting layer, referred to as the EL layer) may not have good enough consistency during production. For example, when the EL layer is produced by an evaporation process, the limitations of the evaporation process lead to inconsistencies in the EL layers of the produced sub-pixels, resulting in uneven brightness or chromaticity between different sub-pixels. Moreover, as the use time increases, the EL layer will age to varying degrees, which will also lead to inconsistencies in the EL layers of the sub-pixels, resulting in uneven brightness or chromaticity between different sub-pixels. In an embodiment of the present disclosure, the display substrate may further include a photosensitive circuit OSC, which can sense the light actually emitted by the pixel unit. Thus, in an embodiment of the present disclosure, the display substrate can perform optical compensation on the sub-pixels within each pixel unit based on the light actually emitted by the pixel unit sensed by the photosensitive circuit OSC, so as to improve the light uniformity of the display substrate.

[0067] For example, in some exemplary embodiments of the present disclosure, a light measuring circuit OSC is provided in each pixel unit PX, and each light measuring circuit OSC senses the light actually emitted by the pixel unit PX where it is located.

[0068] For example, in an embodiment of the present disclosure, at least two pixel units PX can share a photosensitive circuit OSC. Referring to Figure 1, among the pixel units in the same column, two pixel units PX located in two adjacent rows can share a photosensitive circuit OSC. In this way, there is no need to set a photosensitive circuit for each pixel unit PX, which can reduce the number of photosensitive circuits and thus improve the aperture ratio. When the display substrate is in a display state, the photosensitive circuit OSC can sense the light actually emitted by the two pixel units adjacent to it. For example, the photosensitive circuit OSC can include at least a photoelectric conversion element. In this way, the photosensitive circuit OSC can be configured to: sense the light actually emitted by the two pixel units adjacent to it; and send a sensing electrical signal based on the sensed light.

[0069] For another example, referring to FIG1 , the light sensing circuit OSC can transmit a sensing electrical signal to an external circuit, such as a control IC of a display device. The control IC can control the control signal sent to the pixel unit PX based on the sensing electrical signal. For example, the control IC can control the data signal (i.e., data signal) sent to the pixel driving circuit of each sub-pixel. Under the control of the data signal, each sub-pixel emits light accordingly.

[0070] In the embodiment shown in FIG. 1 , the sub-pixels SP1 , SP2 , and SP3 are arranged side by side, and each sub-pixel SP1 , SP2 , and SP3 has its own data line DL.

[0071] Figure 2A is an equivalent circuit diagram of a pixel driving circuit for multiple sub-pixels of the display substrate in Figure 1 , and Figure 2B is an equivalent circuit diagram of a pixel circuit for a single sub-pixel of the display substrate in Figure 1 . The pixel driving circuit shown in Figure 2B can be any of the aforementioned pixel driving circuits SPC1, SPC2, and SPC3. Referring to Figures 2A and 2B , the pixel driving circuit can include multiple components, such as a driving transistor T1, a switching transistor T2, a sensing transistor T3, and a storage capacitor Cst. This pixel driving circuit can be referred to as a 3T1C structure.

[0072] It should be noted that the pixel driving circuit included in the display substrate according to the embodiment of the present disclosure is described here using the 3T1C structure as an example, but the pixel driving circuit included in the display substrate according to the embodiment of the present disclosure is not limited to the 3T1C structure.

[0073] 2B , the gate of the switching transistor T2 is connected to the scanning signal line GL, the first electrode of the switching transistor T2 is connected to the data line DL, and the second electrode of the switching transistor T2 is connected to the gate of the driving transistor T1. For example, the second electrode of the switching transistor T2 and the gate of the driving transistor T1 may both be electrically connected to the node G. The switching transistor T2 is used to control the writing of the voltage signal from the data line DL into the pixel driving circuit.

[0074] It should be noted that each transistor may include an active layer, a gate, a first electrode (e.g., a source electrode), and a second electrode (e.g., a drain electrode). For example, the driving transistor T1 includes a first gate G1 and a first active layer ACT1; the switching transistor T2 includes a second gate G2 and a second active layer ACT2; and the sensing transistor T3 includes a third gate G3 and a third active layer ACT3. In embodiments of the present disclosure, the active layer of the transistor may be located in a semiconductor layer, and the gate may be located in a different conductive layer.

[0075] It should be noted that, in this document, the first electrode of the transistor may refer to one of the source and the drain of the transistor, and the second electrode of the transistor may refer to the other of the source and the drain of the transistor.

[0076] The gate of the driving transistor T1 is electrically connected to the node G. The first electrode of the driving transistor T1 is connected to a first power supply signal (e.g., a high voltage level signal VDD). The second electrode of the driving transistor T1 can be connected to the anode of the light-emitting element, thereby generating a driving current according to the voltage signal to drive the light-emitting element D1 to emit light. For example, the light-emitting element D1 can be an organic light-emitting diode (OLED).

[0077] The two ends of the storage capacitor Cst are respectively connected to the gate and source of the driving transistor T1, and are used to store the voltage signal input from the data line. For example, one end of the storage capacitor Cst is electrically connected to the node G, and the other end of the storage capacitor Cst is electrically connected to the node S. In other words, one end of the storage capacitor Cst, the second electrode of the switching transistor T2, and the gate of the driving transistor T1 are all electrically connected to the node G, and the other end of the storage capacitor Cst, the second electrode of the driving transistor T1, and the anode of the light-emitting element D1 are all electrically connected to the node S.

[0078] A gate electrode of the sensing transistor T3 is connected to the scan signal line GL, a first electrode of the sensing transistor T3 is connected to the sensing signal line SL, and a second electrode of the sensing transistor T3 is electrically connected to the node S.

[0079] The anode of the light emitting element D1 is electrically connected to the node S, and the cathode of the light emitting element D1 is electrically connected to the low voltage level signal VSS. The level signals VDD and VSS are both DC voltage signals for providing the necessary voltage to drive the light emitting element D1 to emit light.

[0080] Figure 3 is a partial plan view of a display substrate according to some embodiments of the present disclosure, which schematically shows a plan view of a pixel driving circuit and a first electrode of a light-emitting element included in the display substrate. Figures 4A to 4I are plan views of the multiple film layers shown in Figure 3, wherein Figure 4A shows a light-shielding layer 30, which includes multiple light-shielding portions 31; Figure 4B shows a second conductive layer 20; Figure 4C shows an active layer 40; Figure 4D shows multiple GI vias VHG; Figure 4E shows a first conductive layer 10; Figure 4F shows multiple passivation layer PVX vias VHP; Figure 4G shows multiple light-emitting element first electrode vias VHR; Figure 4H shows a light-emitting element first electrode; Figure 4I shows a pixel defining layer; and Figure 4J shows a schematic diagram of the combined film layer of the second conductive layer 20 and the first conductive layer 10.

[0081] With reference to Figures 1 and 3 , the display substrate includes a base substrate 100; a plurality of pixel units located on the base substrate 100, at least one of which includes a plurality of sub-pixels. The sub-pixels include a light-emitting element and a pixel driving circuit for driving the light-emitting element. For example, the driving circuit may include a driving transistor T1, a switching transistor T2, and a sensing transistor T3. The sub-pixels of the plurality of pixel units are arranged in an array along a first direction D1 and a second direction D2 on the base substrate 100, where the first direction D1 and the second direction D2 intersect. With reference to Figures 3 , 4C , and 4E , the display substrate further includes a scan signal line GL located on the base substrate 100. The scan signal line includes a main portion 110 extending along the first direction D1 and a plurality of protrusions extending along the second direction D2. The pixel driving circuit includes a sensing transistor T3, which includes a third gate G3 and a third active layer ACT3. The multiple sub-pixels of the at least one pixel unit include a first sub-pixel SP1 and a second sub-pixel SP2. The first sub-pixel SP1 is located in the i-th row and j-th column, and the second sub-pixel SP2 is located in the i+1-th row and j-th column, where i and j are both positive integers greater than or equal to 1. The multiple protrusions include a first protrusion 111 and a second protrusion 112. The orthographic projection of the first protrusion 111 on the base substrate 100 at least partially overlaps with the third active layer ACT313 of the sensing transistor T31 of the first sub-pixel SP1. The portion where the first protrusion 111 overlaps with the third active layer ACT313 of the sensing transistor T31 of the first sub-pixel SP1 serves as the third gate G31 of the sensing transistor T31 of the first sub-pixel SP1. The orthographic projection of the second protrusion 112 on the base substrate 100 at least partially overlaps with the third active layer ACT324 of the sensing transistor T32 of the second sub-pixel SP2. The portion where the second protrusion 112 overlaps with the third active layer ACT324 of the sensing transistor T32 of the second sub-pixel SP2 is the third gate G32 of the sensing transistor T32 of the second sub-pixel SP2. The third gate G31 of the sensing transistor T31 of the first sub-pixel SP1 and the third gate G32 of the sensing transistor T32 of the second sub-pixel SP2 are located on opposite sides of the main body 110 of the same scanning signal line GL in the second direction.

[0082] In some exemplary embodiments of the present disclosure, with continued reference to FIG3 , FIG4C , and FIG4E , the plurality of sub-pixels of at least one pixel unit further include a third sub-pixel SP3 and a fourth sub-pixel SP4, with the third sub-pixel SP3 located in the i-th row and j+1 column, and the fourth sub-pixel SP4 located in the i+1-th row and j+1 column. The plurality of protrusions further include a third protrusion 113 and a fourth protrusion 114. The orthographic projection of the third protrusion 113 on the base substrate 100 at least partially overlaps with the third active layer ACT313 of the sensing transistor T33 of the third sub-pixel SP3. The portion where the third protrusion 113 overlaps with the third active layer ACT313 of the sensing transistor T33 of the third sub-pixel SP3 serves as the third gate G33 of the sensing transistor T33 of the third sub-pixel SP3. The orthographic projection of the fourth protrusion 114 on the base substrate 100 at least partially overlaps with the third active layer ACT324 of the sensing transistor T34 of the fourth sub-pixel SP4. The portion where the fourth protrusion 114 overlaps with the third active layer ACT324 of the sensing transistor T34 of the fourth sub-pixel SP4 is the third gate G34 of the sensing transistor T34 of the fourth sub-pixel SP4. The third gate G33 of the sensing transistor T33 of the third sub-pixel SP3 and the third gate G34 of the sensing transistor T34 of the fourth sub-pixel SP4 are located on opposite sides of the main body 110 of the same scan signal line GL in the second direction.

[0083] By evenly distributing the sub-pixel sensing transistors on the upper and lower sides of the scan signal line, space utilization can be improved, the aperture ratio can be increased, and it is conducive to realizing the design of a high PPI display panel.

[0084] In some exemplary embodiments of the present disclosure, referring to FIG. 3 , the display substrate further includes a sensing signal line SL extending along a second direction D2. The sensing signal line SL is used to provide a sensing signal to the driving circuit. The third gate G31 of the sensing transistor T31 of the first subpixel SP1 and the third gate G33 of the sensing transistor T33 of the third subpixel SP3 are located on opposite sides of the same sensing signal line SL in the first direction D1. Furthermore, the third gate G32 of the sensing transistor T32 of the second subpixel SP2 and the third gate G34 of the sensing transistor T34 of the fourth subpixel SP4 are located on opposite sides of the same sensing signal line SL in the first direction D1.

[0085] In some exemplary embodiments of the present disclosure, referring to FIG3 and FIG4C , the third active layer ACT3 of the sensing transistor T3 further includes a channel region A0, a first polar region A1, and a second polar region A2. The orthographic projection of the channel region A0 of the third active layer ACT3 on the base substrate 100 at least partially overlaps with the orthographic projection of the third gate G3 on the base substrate 100. The first polar region A1 and the second polar region A2 are respectively located on either side of the channel region A0 of the third active layer ACT3 in the first direction D1. At least a portion of the third active layer ACT3 located between the channel region A013 of the sensing transistor T31 of the first sub-pixel SP1 and the channel region A013 of the sensing transistor T33 of the third sub-pixel SP3 is simultaneously used as the first pole region A113 of the sensing transistor T31 of the first sub-pixel SP1 and the second pole region A213 of the sensing transistor of the third sub-pixel SP3; and / or, at least a portion of the third active layer ACT3 located between the channel region A024 of the sensing transistor T32 of the second sub-pixel SP2 and the channel region A024 of the sensing transistor T34 of the fourth sub-pixel SP4 is simultaneously used as the first pole region A124 of the sensing transistor T32 of the second sub-pixel SP2 and the second pole region A224 of the sensing transistor T34 of the fourth sub-pixel SP4.

[0086] In some exemplary embodiments of the present disclosure, referring to Figure 3, the third gate G31 of the sensing transistor T31 of the first sub-pixel SP1 and the third gate G33 of the sensing transistor T33 of the third sub-pixel SP3 are symmetrical with respect to a first center line, wherein the first center line is an imaginary straight line M1 passing through the center of the sensing line SL and extending along the second direction D2; and / or, the third gate G32 of the sensing transistor T32 of the second sub-pixel SP2 and the third gate G34 of the sensing transistor T34 of the fourth sub-pixel SP4 are symmetrical with respect to the first center line M1.

[0087] By designing the sensing transistors T3 of multiple sub-pixels to be bilaterally symmetrical about the sensing line SL, the cross-line length of the signal scanning line in the first direction D1 can be reduced, greatly saving wiring space, reducing process defect rate, and improving the display quality of the display panel.

[0088] In some exemplary embodiments of the present disclosure, with reference to FIG3 and FIG4C , the third active layer ACT313 of the sensing transistor T31 of the first subpixel SP1 and the third active layer ACT313 of the sensing transistor T33 of the third subpixel SP3 are connected to each other and extend along a first direction D1. In other words, the sensing transistor T31 of the first subpixel SP1 and the sensing transistor T33 of the third subpixel SP3 can share a source and drain. By designing the two sensing transistors of two adjacent subpixels in the same row to share a source and drain, two connection holes can be reduced, further saving wiring space, increasing the aperture ratio of the display substrate, and improving the display quality of the display panel.

[0089] In some exemplary embodiments of the present disclosure, referring to Figure 4E, the first protrusion 111 and the second protrusion 112 respectively protrude from the main body 110 of the same scanning signal line in opposite directions in the second direction D2, and the first protrusion 111 and the second protrusion 112 are offset by a first predetermined distance D12 in the first direction D1; and / or, the third protrusion 113 and the fourth protrusion 114 respectively protrude from the main body 110 of the same scanning signal line in opposite directions in the second direction D2, and the third protrusion 113 and the fourth protrusion 114 are offset by a second predetermined distance D34 in the first direction D1.

[0090] In some exemplary embodiments of the present disclosure, with reference to FIG3 , FIG4C , and FIG4E , the pixel driving circuit further includes a switching transistor T2, which includes a second gate G2 and a second active layer ACT2. For example, the driving circuit of the first sub-pixel SP1 includes a switching transistor T21, which includes a second gate G21 and a second active layer ACT21. The plurality of protrusions include a fifth protrusion 115 and a sixth protrusion 116. The orthographic projection of the fifth protrusion 115 on the base substrate 100 at least partially overlaps with the second active layer ACT21 of the switching transistor T21 of the first sub-pixel SP1. The portion where the fifth protrusion 115 overlaps with the second active layer ACT21 of the switching transistor T21 of the first sub-pixel SP1 is the second gate G21 of the switching transistor T21 of the first sub-pixel SP1. The orthographic projection of the sixth protrusion 116 on the base substrate 100 at least partially overlaps with the second active layer ACT22 of the switching transistor T22 of the second sub-pixel SP2. The portion where the sixth protrusion 116 overlaps with the second active layer ACT22 of the switching transistor T22 of the second sub-pixel SP2 is the second gate G22 of the switching transistor T22 of the second sub-pixel SP2. The second gate G21 of the switching transistor T21 of the first sub-pixel SP1 and the second gate G22 of the switching transistor T22 of the second sub-pixel SP2 are located on opposite sides of the main body 110 of the same scanning signal line GL in the second direction D2.

[0091] By designing the switching transistors T2 of multiple sub-pixels on the upper and lower sides of the signal scanning line, wiring space can be greatly saved, process defect rate can be reduced, and the display quality of the display panel can be improved.

[0092] In some exemplary embodiments of the present disclosure, referring to Figure 4E, the fifth protrusion 115 and the sixth protrusion 116 respectively protrude from the main body 110 of the same scan signal line GL in opposite directions in the second direction D2, and the fifth protrusion 115 and the sixth protrusion 116 are offset by a third predetermined distance D56 in the first direction D1.

[0093] In some exemplary embodiments of the present disclosure, with continued reference to FIG. 4E , any two of the first predetermined distance D12 , the second predetermined distance D34 , and the third predetermined distance D56 are substantially equal.

[0094] 4J , the display substrate further includes first, second, third, and fourth data lines DL1 , DL2 , DL3 , and DL4 , which are located in the second conductive layer 20 .

[0095] Referring to Figure 3 and Figure 4J, the first data line DL1 is electrically connected to the switching transistor T21 of the first sub-pixel SP1, and is used to write a data signal to the first sub-pixel SP1; the second data line DL2 is electrically connected to the switching transistor T22 of the second sub-pixel SP2, and is used to write a data signal to the second sub-pixel SP2; similarly, the third data line DL3 is electrically connected to the switching transistor of the third sub-pixel SP3, and is used to write a data signal to the third sub-pixel SP3; the fourth data line DL4 is electrically connected to the switching transistor of the third sub-pixel SP4, and is used to write a data signal to the fourth sub-pixel SP4.

[0096] Due to limitations in the spatial layout of the data lines, the first data line DL1 and the second data line DL2 are offset in the first direction D1 by a fourth predetermined distance D012, and the third data line DL3 and the fourth data line DL4 are offset in the first direction D1 by a fifth predetermined distance D034. It should be noted that the offset distance between data lines herein may refer to the minimum spacing distance or the average spacing distance between two adjacent data lines.

[0097] In the embodiment of the present disclosure, the first electrode (source or drain) of the switching transistor T21 of the first sub-pixel SP1 is electrically connected to the first data line DL1 through the third conductive connection portion 123 and the third via hole VH3. Similarly, the first electrode (source or drain) of the switching transistor T22 of the second sub-pixel SP2 is electrically connected to the second data line DL2, the first electrode (source or drain) of the switching transistor T23 of the third sub-pixel SP3 is electrically connected to the third data line DL3, and the first electrode (source or drain) of the switching transistor T24 of the fourth sub-pixel SP4 is electrically connected to the fourth data line DL4. That is to say, for the first sub-pixel SP1 and the third sub-pixel SP3 located in the same row, the first electrode of the switching transistor of the first sub-pixel SP1 is electrically connected to the first data line DL1 located on the outside, and the first electrode of the switching transistor of the third sub-pixel SP3 is electrically connected to the third data line DL3 located on the inside; for the second sub-pixel SP2 and the fourth sub-pixel SP4 located in the same row, the first electrode of the switching transistor of the second sub-pixel SP2 is electrically connected to the second data line DL2 located on the inside, and the first electrode of the switching transistor of the fourth sub-pixel SP4 is electrically connected to the fourth data line DL4 located on the outside.

[0098] In order to ensure that the distance from the data signal passing through the data writing transistor to the driving transistor does not deviate too far, for example, to ensure that the distance from the data signal passing through the switching transistor T21 of the first sub-pixel SP1 to the driving transistor T11 of the first sub-pixel SP1 deviates less, multiple protrusions are designed to be offset. For example, the first protrusion 111 and the second protrusion 112 are offset by a first predetermined distance D12 in the first direction D1, the third protrusion 113 and the fourth protrusion 114 are offset by a second predetermined distance D34 in the first direction D1, and the fifth protrusion 115 and the sixth protrusion 116 are offset by a third predetermined distance D56 in the first direction D1.

[0099] For example, in some embodiments, any two of the first offset distance D12, the third predetermined distance D56, and the fourth predetermined distance D012 may be substantially equal. For example, in other embodiments, the third predetermined distance D56 is greater than the first offset distance D12; and / or the third predetermined distance D56 is greater than the fourth predetermined distance D012; and / or the fourth predetermined distance D012 is greater than the first offset distance D12.

[0100] By disposing the third gate G3 of the sensing transistor T3 and the second gate G2 of the switching transistor T2 of multiple sub-pixels on opposite sides of the main portion 110 of the same scan signal line, and regularly offsetting the third gate G3 of the sensing transistor T3 and the second gate G2 of the switching transistor T2 of the multiple sub-pixels by a certain distance in the first direction D1, the space on both sides of the main portion 110 of the scan signal line can be fully utilized, thereby reducing the crossover length of the horizontal scan signal line, further saving wiring space, and improving the aperture ratio, thereby achieving a high PPI design for the display panel. In some exemplary embodiments of the present disclosure, with reference to Figures 3 and 4B, the sensing signal line SL includes a main portion 210 and a first protrusion 211 and a second protrusion 212. The first protrusion 211 protrudes from the main portion 210 toward the first sub-pixel SP1, and the second protrusion 212 protrudes from the main portion 210 toward the fourth sub-pixel SP4.

[0101] 4E , the display substrate further includes a first conductive connection portion 121 and a sixth conductive connection portion 126. The first conductive connection portion 121, the sixth conductive connection portion 126, the first protrusion 111, the second protrusion 112, the third protrusion 113 and the fourth protrusion 114 are located on the same layer. The first conductive connection portion 121 is located between the first protrusion 111 and the third protrusion 113 in the first direction D1, and the sixth conductive connection portion 126 is located between the second protrusion 112 and the fourth protrusion 114 in the first direction D1.

[0102] 3 , 4B , and 4E , the orthographic projection of the first linear protrusion 211 on the base substrate 100 at least partially overlaps with the orthographic projection of the first conductive connection portion 121 on the base substrate 100, and the first linear protrusion 211 is electrically connected to the first conductive connection portion 121 via the first via VH1. The orthographic projection of the second linear protrusion 212 on the base substrate 100 at least partially overlaps with the orthographic projection of the sixth conductive connection portion 126 on the base substrate 100, and the second linear protrusion 212 is electrically connected to the sixth conductive connection portion 126 via the seventh via VH7.

[0103] Referring to FIG4B , the display substrate further includes a first conductive transition portion 221 and a second conductive transition portion 222. The first conductive transition portion 221 and the second conductive transition portion 222 are located on the same layer as the first and second linear protrusions 211 and 212. With reference to FIG3 , FIG4B , and FIG4E , the orthographic projection of the first conductive transition portion 221 on the base substrate 100 at least partially overlaps with the orthographic projection of the second conductive connection portion 122 on the base substrate 100. The first conductive transition portion 221 is electrically connected to the second conductive connection portion 122 via a second via VH2. The orthographic projection of the second conductive transition portion 222 on the base substrate 100 at least partially overlaps with the orthographic projection of the fourth conductive connection portion 124 on the base substrate 100. The second conductive transition portion 222 is electrically connected to the fourth conductive connection portion 124 via an eighth via VH8. In some exemplary embodiments of the present disclosure, in combination with Figures 3, 4C and 4E, the orthographic projection of either the first conductive connection portion 121 and the first via hole VH1 on the base substrate 100 at least partially overlaps with the orthographic projection of a portion of the third active layer ACT3 that simultaneously serves as the first electrode region A113 of the sensing transistor T31 of the first sub-pixel SP1 and the second electrode region A213 of the sensing transistor T33 of the third sub-pixel SP3 on the base substrate 100.

[0104] Figure 5 is a partial enlarged view near the dotted rectangular area in Figure 3 . Figure 6A is a cross-sectional view taken along dotted line 1 in Figure 5 , and Figure 6B is a cross-sectional view taken along dotted line 2 in Figure 5 . The orthographic projections of dotted lines 1 and 2 on the substrate partially overlap with the first via hole VH2 . Referring to Figures 3 , 4C , and 6A , the third active layer ACT313 of the first subpixel SP1 in the substrate is electrically connected to the first conductive layer 10 through the first via hole VH1 and the second via hole VH2 , respectively, forming the source and drain of the sensing transistor T31 of the first subpixel SP1.

[0105] In some exemplary embodiments of the present disclosure, referring to Figure 4E, the display substrate further includes a second conductive connection portion 122, the second conductive connection portion 122, the first protrusion 111 and the fifth protrusion 115 are located on the same layer, and the second conductive connection portion 122 is located between the first protrusion 111 and the fifth protrusion 115 in the first direction D1.

[0106] 3 , 4A , 4C and 4E , the display substrate further includes a light shielding portion 31 on the base substrate 100 , and the orthographic projections of any two of the light shielding portion 31 and the second electrode region A213 and the second conductive connection portion 122 of the sensing transistor T31 of the first sub-pixel SP1 on the base substrate 100 at least partially overlap, and the second electrode region A213 of the sensing transistor T31 of the first sub-pixel SP1 is electrically connected to the light shielding portion 31 through the second conductive connection portion 122 and the second via hole VH2.

[0107] 3 , 4A , 4G , and 4H , the display substrate further includes a light-emitting element first electrode 91 and a light-emitting element first electrode via hole VHR located on the base substrate 100. For example, the light-emitting element first electrode 91 includes the light-emitting element first electrode 913 of the third sub-pixel SP3, the light-emitting element first electrode via hole VHR includes the light-emitting element first electrode via hole VHR3 of the third sub-pixel SP3, and the light-shielding portion 31 includes the light-shielding portion 313 of the third sub-pixel SP3. The light-emitting element first electrode 913 of the third sub-pixel SP3 is electrically connected to the light-shielding portion 313 of the third sub-pixel SP3 via the light-emitting element first electrode via hole VHR3 of the third sub-pixel SP3.

[0108] FIG. 7 is a plan view schematically illustrating a stack of a partial light-shielding layer 30 and an active layer 40 according to some exemplary embodiments of the present disclosure.

[0109] In some exemplary embodiments of the present disclosure, referring to FIG7 , the orthographic projection of the second active layer ACT2 on the base substrate 100 at least partially overlaps with the orthographic projection of the light shielding portion 31 on the base substrate. The pixel driving circuit further includes a storage capacitor Cst, which includes a first plate S1 and a second plate S2. At least a portion of the second active layer ACT2 serves as the first plate S1, and at least a portion of the light shielding portion 31 serves as the second plate S2. By designing the driving circuit, for example, the sensing transistors T3 are evenly distributed on the upper and lower sides of the main body 110 of the scanning signal line, with bilateral symmetry, which can save wiring space and save more space for the storage capacitor, thereby facilitating an increase in the capacitance value of the storage capacitor.

[0110] FIG8 is a partial plan view of a display substrate according to some other embodiments of the present disclosure, showing a widened portion of a sensing signal line; FIG9 is a partial enlarged view of an area near the upper dotted box in FIG8 .

[0111] In other exemplary embodiments of the present disclosure, in combination with Figures 8 and 9, the sensing signal line SL further includes a first widening portion 213, a width d of the first widening portion 213 in the first direction D1 is greater than a width c of the line main body portion 210 in the first direction D1, and an orthographic projection of the first widening portion 213 on the substrate is located in the first direction D1 between an orthographic projection of the first plate S11 of the storage capacitor of the first sub-pixel SP1 and an orthographic projection of the first plate S13 of the storage capacitor of the third sub-pixel SP3 on the substrate; and / or, continuing to refer to Figure 8, the sensing signal line SL further includes a second widening portion 214, a width e of the second widening portion 214 in the first direction D1 is greater than a width c of the line main body portion 210 in the first direction D1, and an orthographic projection of the second widening portion 214 on the substrate is located in the first direction between an orthographic projection of the first plate S12 of the storage capacitor of the second sub-pixel SP2 and an orthographic projection of the first plate S14 of the storage capacitor of the fourth sub-pixel SP4 on the substrate.

[0112] Continuing with reference to FIG7 , FIG8 , and FIG9 , the orthographic projection of the first widened portion 213 on the substrate is spaced apart from the orthographic projection of the first plate S11 of the storage capacitor of the first sub-pixel SP1 on the substrate by a first spacing distance a in the first direction D1, wherein the first plate S11 of the storage capacitor of the first sub-pixel SP1 is a region of the second active layer ACT21 of the first sub-pixel SP1 that overlaps with the light shielding portion 31. The orthographic projection of the first widened portion 213 on the substrate is spaced apart from the orthographic projection of the first plate S13 of the storage capacitor of the third sub-pixel SP3 on the substrate by a second spacing distance a in the first direction D1, wherein the first plate S13 of the storage capacitor of the third sub-pixel SP3 is a region of the second active layer ACT23 of the third sub-pixel SP3 that overlaps with the light shielding portion 31. In other words, the first spacing distance is substantially equal to the second spacing distance. And / or, the orthographic projection of the second widening portion 214 on the substrate and the orthographic projection of the first plate S12 of the storage capacitor of the second sub-pixel SP2 on the substrate are spaced apart by a third spacing distance b in the first direction D1, wherein the first plate S12 of the storage capacitor of the second sub-pixel SP2 is the area in the second active layer ACT22 of the second sub-pixel SP2 that overlaps with the shading portion 31; the orthographic projection of the second widening portion 214 on the substrate and the orthographic projection of the first plate S14 of the storage capacitor of the fourth sub-pixel SP4 on the substrate are spaced apart by a fourth spacing distance b in the first direction D1, wherein the first plate S14 of the storage capacitor of the fourth sub-pixel SP4 is the area in the second active layer ACT24 of the fourth sub-pixel SP4 that overlaps with the shading portion 31, that is, the third spacing distance is substantially equal to the fourth spacing distance.

[0113] 3 and 4C , the driving transistor T11 of the first sub-pixel SP1 is electrically connected to the storage capacitor of the first sub-pixel SP1 through the fourth via hole VH4 , and the storage capacitor of the first sub-pixel SP1 can be used to store the driving voltage to ensure the stability of the pixel driving.

[0114] In an exemplary embodiment, the spacing distance a and the spacing distance b may be substantially equal, that is, any two of the first spacing distance, the second spacing distance, the third spacing distance, and the fourth spacing distance may be substantially equal.

[0115] It should be noted that, in this article, unless otherwise specified, the expression "substantially equal" may include various situations where the ratio of two compared values ​​ranges from 0.8 to 1.2, for example, the two compared values ​​are equal, and the ratio of the two compared values ​​is 0.8, 0.9, 1.1, 1.2, etc.

[0116] By horizontally placing the sensing transistors of multiple sub-pixels and evenly distributing them above and below the scanning signal line, the sensing transistors T3 of two sub-pixels share a common source and drain, meaning that the sensing transistors T3 of the multiple sub-pixels are symmetrical about the sensing signal line SL. At the same time, the sensing signal line SL is widened in the left and right sub-pixel opening regions to ensure that the distance from the sensing signal line SL to the first gate G1 of the drive transistor T1 of each sub-pixel is the same, thereby uniformly affecting the potential of the first gate G1 of the drive transistor T1 of each sub-pixel. Furthermore, the widened sensing signal line SL in the left and right sub-pixel opening regions also helps reduce the resistance of the sensing signal line SL, lowering voltage drop and improving the brightness uniformity of each sub-pixel, thereby enhancing the display quality of the display panel.

[0117] In other exemplary embodiments of the present disclosure, with reference to FIG4E and FIG8 , the display substrate further includes a first conductive connection portion 121. The first conductive connection portion 121, the first protrusion 111, and the second protrusion 112 are located on the same layer. The orthographic projection of the first widening portion 213 on the base substrate at least partially overlaps with the orthographic projection of the first conductive connection portion 121 on the base substrate. The first widening portion 213 is electrically connected to the first conductive connection portion through a first via hole VH1.

[0118] FIG10 is a partial plan view of a display substrate according to some other embodiments of the present disclosure, showing an active extension portion of a third active layer; FIG11 is a partial enlarged view of an area near a middle scanning signal line in FIG10 .

[0119] In other exemplary embodiments of the present disclosure, with reference to FIG10 and FIG11 , the third active layer ACT3 further includes an active extension portion ACT301. The active extension portion ACT301 extends from a portion of the third active layer ACT3 that functions as both the first electrode region A113 of the sensing transistor T31 of the first sub-pixel SP1 and the second electrode region A213 of the sensing transistor T33 of the third sub-pixel SP3, in a direction parallel to the extending direction of the sensing signal line SL. The orthographic projection of the active extension portion ACT301 on the base substrate at least partially overlaps with the orthographic projection of the sensing signal line SL on the base substrate. The active extension portion ACT301 is electrically connected to the first conductive connection portion 121.

[0120] Continuing with reference to Figures 10 and 11, the second active layer ACT2 includes a first portion ACT201 extending along the first direction D1, a second portion ACT202 extending along the second direction D2, and a third portion ACT203 serving as a first electrode S1. The portion where the first portion ACT201 overlaps with the fifth protrusion 115 is a channel region of the switching transistor, and the second portion ACT202 connects the first portion ACT201 and the third portion ACT203; the width f of the second portion ACT202 in the first direction D1 is greater than the width g of the first portion ACT201 in the second direction.

[0121] By horizontally placing the sensing transistors of multiple sub-pixels and evenly distributing them above and below the scanning signal line, the sensing transistors T3 of each sub-pixel share a common source and drain, meaning that the sensing transistors T3 of the multiple sub-pixels are symmetrical about the sensing signal line SL. Furthermore, the sensing signal line SL is widened in the left and right sub-pixel opening regions, ensuring that the distance from the sensing signal line SL to the third gate G3 of the sensing transistor T3 of each sub-pixel is the same, thereby uniformly affecting the potential of the third gate G3 of the sensing transistor T3 of each sub-pixel. Furthermore, connecting the common source and drain terminal to the sensing signal line SL through a first via VH1, where the first via VH1 is located on the sensing signal line SL, saves wiring space in the first direction D1 and facilitates widening the width of the high-impedance second active layer ACT2, such as the width of the second portion ACT202 of the second active layer ACT2. This facilitates potential input to the scanning signal line and further improves the aperture ratio. Furthermore, the double-layer design reduces the resistance of the sensing signal line SL, lowering voltage drop and improving brightness uniformity across sub-pixels, thereby enhancing the display quality of the display panel.

[0122] FIG. 12 is a partial schematic plan view of a display substrate according to other embodiments of the present disclosure.

[0123] In other exemplary embodiments of the present disclosure, referring to FIG4E and FIG12 , the pixel driving circuit further includes a driving transistor T1, which includes a first active layer ACT1. The display substrate further includes a fifth conductive connection portion 125 and a first power signal line VDD for transmitting a first power signal. The fifth conductive connection portion 125 and the scan signal line GL are located on the same layer, and the first power signal line VDD and the sense signal line SL are located on the same layer. One end of the fifth conductive connection portion 125 is electrically connected to the first active layer ACT1 via a fifth via hole VH5, and the other end of the fifth conductive layer connection portion is electrically connected to the first power signal line VDD via a sixth via hole VH6. Two sub-pixels located in two adjacent rows of pixel units and in the same column share the fifth conductive connection portion. For example, the second sub-pixel SP2 and the fifth sub-pixel SP5 are two sub-pixels located in two adjacent rows of pixel units and in the same column. The second sub-pixel SP2 and the fifth sub-pixel SP5 can share the fifth conductive connection portion 125. This design saves wiring space, further increases the aperture ratio, and thus improves the display quality of the display panel.

[0124] FIG. 13 is a partial cross-sectional schematic diagram of a display substrate according to other embodiments of the present disclosure.

[0125] For example, referring to FIG13 , the display substrate includes: a semiconductor layer 40 located on a base substrate; a first conductive layer 10 located on a side of the semiconductor layer 40 away from the base substrate; a second conductive layer 20 located on a side of the first conductive layer 10 away from the base substrate; and a light shielding layer 30 located on a side of the semiconductor layer 40 closer to the base substrate. Referring to FIG4A , FIG4B , FIG4C , and FIG4E , a light shielding portion 31 is located on the light shielding layer 30, a first active layer ACT1 , a second active layer ACT2 , and a third active layer ACT3 are located on the semiconductor layer 40, a scan signal line GL, a first conductive connection portion 121 , and a second conductive connection portion 122 are located on the first conductive layer 10, and a sensing signal line SL and a first power line VDD are located on the second conductive layer 20.

[0126] Exemplarily, continuing to refer to Figure 13, the display substrate also includes a pixel defining layer 50 located on the side of the second conductive layer 20 away from the base substrate, and the pixel defining layer 50 is used to define multiple pixel openings; the display substrate also includes a reflective electrode layer 93 located on the side of the pixel defining layer 50 away from the base substrate.

[0127] 3 , 4I and 13 , the pixel defining layer 50 is further configured to define a plurality of grooves 52 , each of which is located between any adjacent pixel openings. At least a portion of the reflective electrode layer 93 is located in the plurality of grooves 52 , thereby avoiding crosstalk between adjacent pixels and improving the stability of the display panel.

[0128] For example, in some embodiments of the present disclosure, with reference to FIG7 and FIG13 , the display substrate further includes a first conductive portion 90 located on the side of the light shielding layer 30 close to the base substrate; a second conductive portion 41 located on the semiconductor layer 40; the orthographic projection of the first conductive portion 90 on the base substrate at least partially overlaps with the orthographic projection of the pixel opening PO on the base substrate, and the orthographic projection of the second conductive portion 41 on the base substrate at least partially overlaps with the orthographic projection of the pixel opening PO on the base substrate. The first electrode S1 further includes the second conductive portion 41, and the second electrode S2 further includes the first conductive portion 90. The first conductive portion 90 is electrically connected to the light shielding portion 30 and comprises a transparent conductive material, such as ITO, IZO, or other transparent conductive materials.

[0129] Optionally, embodiments of the present disclosure further provide a display device that may include the aforementioned display substrate. The display device may include, but is not limited to, electronic paper, mobile phones, tablet computers, monitors, laptop computers, digital photo frames, navigation systems, and any other product or component with a display function. It should be understood that this display device has the same beneficial effects as the display substrate provided in the aforementioned embodiments.

[0130] Although some embodiments of the present general inventive concept have been shown and described, it will be appreciated by those skilled in the art that changes may be made to these embodiments without departing from the principles and spirit of the present general inventive concept, the scope of which is defined in the claims and their equivalents.

Claims

1. A display substrate, characterized in that: The display substrate comprises: substrate substrate; A plurality of pixel units located on the substrate, at least one pixel unit includes a plurality of sub-pixels, at least one sub-pixel includes a light-emitting element and a pixel driving circuit for driving the light-emitting element, wherein the plurality of sub-pixels of the plurality of pixel units are distributed in an array along a first direction and a second direction on the substrate, and the first direction and the second direction intersect; A scanning signal line located on the base substrate, the scanning signal line comprising a main body extending along a first direction and a plurality of protrusions extending along a second direction, Wherein, the pixel driving circuit includes a sensing transistor, and the sensing transistor includes a third gate and a third active layer; The plurality of sub-pixels of at least one pixel unit include a first sub-pixel and a second sub-pixel, wherein the first sub-pixel is located at the i-th row and the j-th column, and the second sub-pixel is located at the i+1-th row and the j-th column, wherein i and j are positive integers greater than or equal to 1; The plurality of protrusions include a first protrusion and a second protrusion, wherein an orthographic projection of the first protrusion on the substrate at least partially overlaps with a third active layer of the sensing transistor of the first sub-pixel, and a portion where the first protrusion overlaps with the third active layer of the sensing transistor of the first sub-pixel is a third gate of the sensing transistor of the first sub-pixel; an orthographic projection of the second protrusion on the substrate at least partially overlaps with the third active layer of the sensing transistor of the second sub-pixel, and a portion where the second protrusion overlaps with the third active layer of the sensing transistor of the second sub-pixel is a third gate of the sensing transistor of the second sub-pixel; and The third gate of the sensing transistor of the first sub-pixel and the third gate of the sensing transistor of the second sub-pixel are respectively located at two sides of the main body of the same scanning signal line in the second direction.

2. The display substrate according to claim 1, wherein: The multiple sub-pixels of at least one pixel unit further include a third sub-pixel and a fourth sub-pixel, the third sub-pixel is located at the i-th row and the j+1-th column, and the fourth sub-pixel is located at the i+1-th row and the j+1-th column; The plurality of protrusions further include a third protrusion and a fourth protrusion, wherein the orthographic projection of the third protrusion on the substrate at least partially overlaps with the third active layer of the sensing transistor of the third sub-pixel, and the portion where the third protrusion overlaps with the third active layer of the sensing transistor of the third sub-pixel is the third sub-pixel. a third gate of the sensing transistor; The orthographic projection of the fourth protrusion on the substrate at least partially overlaps with the third active layer of the sensing transistor of the fourth sub-pixel, and the portion where the fourth protrusion overlaps with the third active layer of the sensing transistor of the fourth sub-pixel is the third gate of the sensing transistor of the fourth sub-pixel; as well as The third gate of the sensing transistor of the third sub-pixel and the third gate of the sensing transistor of the fourth sub-pixel are respectively located at two sides of the main body of the same scanning signal line in the second direction.

3. The display substrate according to claim 2, wherein: The display substrate further comprises a sensing signal line extending along a second direction, wherein the sensing signal line is used to provide a sensing signal to the pixel driving circuit; as well as The third gate of the sensing transistor of the first sub-pixel and the third gate of the sensing transistor of the third sub-pixel are respectively located on both sides of the same sensing signal line in the first direction; and / or the third gate of the sensing transistor of the second sub-pixel and the third gate of the sensing transistor of the fourth sub-pixel are respectively located on both sides of the same sensing signal line in the first direction.

4. The display substrate according to claim 2 or 3, wherein: The third active layer of the sensing transistor further includes a channel region, a first polar region, and a second polar region; The orthographic projection of the channel region of the third active layer on the substrate at least partially overlaps with the orthographic projection of the third gate on the substrate, and the first polar region and the second polar region are respectively located on two sides of the channel region of the third active layer in the first direction; At least a portion of the third active layer located between the channel region of the sensing transistor of the first sub-pixel and the channel region of the sensing transistor of the third sub-pixel is simultaneously used as a first pole region of the sensing transistor of the first sub-pixel and a second pole region of the sensing transistor of the third sub-pixel; and / or, at least a portion of the third active layer located between the channel region of the sensing transistor of the second sub-pixel and the channel region of the sensing transistor of the fourth sub-pixel is simultaneously used as a first pole region of the sensing transistor of the second sub-pixel and a second pole region of the sensing transistor of the fourth sub-pixel.

5. The display substrate according to any one of claims 2 to 4, wherein: The third gate of the sensing transistor of the first sub-pixel and the third gate of the sensing transistor of the third sub-pixel are symmetrical with respect to a first center line, wherein the first center line is an imaginary straight line passing through the center of the sensing line and extending along the second direction; and / or The third gate of the sensing transistor of the second sub-pixel and the third gate of the sensing transistor of the fourth sub-pixel are symmetrical with respect to the first center line.

6. The display substrate according to any one of claims 2 to 5, wherein: The third active layer of the sensing transistor of the first sub-pixel and the third active layer of the sensing transistor of the third sub-pixel are connected to each other and extend along a first direction.

7. The display substrate according to any one of claims 2 to 6, wherein: The first protrusion and the second protrusion respectively protrude from the main body of the same scanning signal line in opposite directions in the second direction, and the first protrusion and the second protrusion are offset by a first predetermined distance in the first direction; and / or, The third protrusion and the fourth protrusion respectively protrude from the main body of the same scanning signal line in opposite directions in the second direction, and the third protrusion and the fourth protrusion are offset by a second predetermined distance in the first direction.

8. The display substrate according to any one of claims 2 to 7, wherein: The pixel driving circuit further includes a switch transistor, wherein the switch transistor includes a second gate and a second active layer; The plurality of protrusions include a fifth protrusion and a sixth protrusion, the orthographic projection of the fifth protrusion on the base substrate at least partially overlaps with the second active layer of the switch transistor of the first sub-pixel, and the portion where the fifth protrusion overlaps with the second active layer of the switch transistor of the first sub-pixel is the second gate of the switch transistor of the first sub-pixel; the orthographic projection of the sixth protrusion on the base substrate at least partially overlaps with the second active layer of the switch transistor of the second sub-pixel, and the portion where the sixth protrusion overlaps with the second active layer of the switch transistor of the second sub-pixel is the second gate of the switch transistor of the second sub-pixel; and The second gate of the switch transistor of the first sub-pixel and the second gate of the switch transistor of the second sub-pixel are respectively located at two sides of the main body of the same scan signal line in the second direction.

9. The display substrate according to claim 8, wherein: The fifth protrusion and the sixth protrusion respectively protrude from the main body of the same scanning signal line in opposite directions in the second direction, and the fifth protrusion and the sixth protrusion are offset by a third predetermined distance in the first direction.

10. The display substrate according to claim 9, wherein: Any two of the first predetermined distance, the second predetermined distance, and the third predetermined distance are substantially equal.

11. The display substrate according to any one of claims 2 to 10, wherein: The sensing signal line includes a line main body and a first line protrusion, and the first line protrusion protrudes from the line main body toward the first sub-pixel; The display substrate further includes a first conductive connection portion, wherein the first conductive connection portion, the first protrusion portion, and the third protrusion portion are located in the same layer, and the first conductive connection portion is located between the first protrusion portion and the third protrusion portion in a first direction; as well as An orthographic projection of the first linear protrusion on the base substrate at least partially overlaps with an orthographic projection of the first conductive connection portion on the base substrate, and the first linear protrusion is electrically connected to the first conductive connection portion through a first via hole.

12. The display substrate according to claim 11, wherein: An orthographic projection of any one of the first conductive connection portion and the first via on the substrate at least partially overlaps with an orthographic projection of a portion of the third active layer that simultaneously serves as a first electrode region of the sensing transistor of the first sub-pixel and a second electrode region of the sensing transistor of the third sub-pixel on the substrate.

13. The display substrate according to claim 12, wherein: The display substrate further includes a second conductive connection portion, wherein the second conductive connection portion, the first protrusion portion, and the fifth protrusion portion are located in the same layer, and the second conductive connection portion is located between the first protrusion portion and the fifth protrusion portion in the first direction; The display substrate also includes a light-shielding portion located on the base substrate, and the orthographic projections of any two of the light-shielding portion, the second polar region of the sensing transistor of the first sub-pixel, and the second conductive connection portion on the base substrate at least partially overlap, and the second polar region of the sensing transistor of the first sub-pixel is electrically connected to the light-shielding portion through the second conductive connection portion and the second via.

14. The display substrate according to claim 13, wherein: The orthographic projection of the second active layer on the base substrate at least partially overlaps with the orthographic projection of the light shielding portion on the base substrate; The pixel driving circuit further includes a storage capacitor including a first electrode plate and a second electrode plate, at least a portion of the second active layer is used as the first electrode plate, and at least a portion of the light shielding portion is used as the second electrode plate.

15. The display substrate according to claim 14, wherein: The sensing signal line further includes a first widened portion, the width of the first widened portion in the first direction is greater than the width of the line main body portion in the first direction, and the orthographic projection of the first widened portion on the base substrate is located in the first direction between the orthographic projection of the first electrode plate of the storage capacitor of the first sub-pixel on the base substrate and the orthographic projection of the first electrode plate of the storage capacitor of the third sub-pixel on the base substrate; and / or, The sensing signal line also includes a second widened portion, the width of the second widened portion in the first direction is greater than the width of the line main body portion in the first direction, and the orthographic projection of the second widened portion on the base substrate is located in the first direction between the orthographic projection of the first plate of the storage capacitor of the second sub-pixel on the base substrate and the orthographic projection of the first plate of the storage capacitor of the fourth sub-pixel on the base substrate.

16. The display substrate according to claim 15, wherein: An orthographic projection of the first widened portion on the base substrate and an orthographic projection of the first plate of the storage capacitor of the first sub-pixel on the base substrate are spaced apart by a first spacing distance in a first direction; The orthographic projection of the first widened portion on the base substrate and the orthographic projection of the first electrode plate of the storage capacitor of the third sub-pixel on the base substrate are spaced apart by a second spacing distance in the first direction; the first spacing distance is substantially equal to the second spacing distance; and / or, An orthographic projection of the second widened portion on the base substrate and an orthographic projection of the first electrode plate of the storage capacitor of the second sub-pixel on the base substrate are spaced apart by a third spacing distance in the first direction; The orthographic projection of the second widened portion on the substrate and the orthographic projection of the first plate of the storage capacitor of the fourth sub-pixel on the substrate are spaced apart by a fourth spacing distance in the first direction; the third spacing distance is substantially equal to the fourth spacing distance.

17. The display substrate according to claim 15 or 16, wherein: The display substrate further includes a first conductive connection portion, wherein the first conductive connection portion, the first protrusion portion and the second protrusion portion are located in the same layer; as well as The orthographic projection of the first widened portion on the base substrate at least partially overlaps with the orthographic projection of the first conductive connection portion on the base substrate, and the first widened portion is electrically connected to the first conductive connection portion through a first via hole.

18. The display substrate according to claim 17, wherein: The third active layer further includes an active extension portion, the active extension portion extending from a portion of the third active layer simultaneously serving as a first polar region of the sensing transistor of the first sub-pixel and a second polar region of the sensing transistor of the third sub-pixel in a direction parallel to an extension direction of the sensing signal line; The orthographic projection of the active extension on the substrate is parallel to the orthographic projection of the sensing signal line on the substrate. The orthographic projections of at least partially overlap; as well as The active extension portion is electrically connected to the first conductive connection portion.

19. The display substrate according to claim 18, wherein: The second active layer includes a first portion extending along a first direction, a second portion extending along a second direction, and a third portion serving as the first electrode plate, a portion where the first portion overlaps with the fifth protrusion is a channel region of the switch transistor, and the second portion connects the first portion and the third portion; as well as The width of the second portion in the first direction is greater than the width of the first portion in the second direction.

20. The display substrate according to any one of claims 1 to 19, wherein: The pixel driving circuit further comprises a driving transistor, wherein the driving transistor comprises a first active layer; The display substrate further includes a fifth conductive connection portion and a first power signal line for transmitting a first power signal, the fifth conductive connection portion and the scanning signal line are located on the same layer, and the first power signal line and the sensing signal line are located on the same layer; One end of the fifth conductive connection portion is electrically connected to the first active layer through a fifth via hole, and the other end of the fifth conductive connection portion is electrically connected to the first power signal line through a sixth via hole; and Two sub-pixels located in two adjacent rows of pixel units and in the same column share the fifth conductive connection portion.

21. The display substrate according to any one of claims 13 to 19, wherein: The display substrate comprises: A semiconductor layer located on the substrate; A first conductive layer located on a side of the semiconductor layer away from the substrate; A second conductive layer located on a side of the first conductive layer away from the base substrate; and a light shielding layer located on a side of the semiconductor layer close to the substrate, Among them, the light-shielding portion is located in the light-shielding layer, the first active layer, the second active layer and the third active layer are located in the semiconductor layer, the scanning signal line, the first conductive connection portion and the second conductive connection portion are located in the first conductive layer, and the sensing signal line and the first power supply line are located in the second conductive layer.

22. The display substrate according to claim 21, wherein: The display substrate further comprises: a pixel defining layer located on a side of the second conductive layer away from the base substrate, the pixel defining layer being used to define a plurality of pixel openings; and a reflective electrode layer located on a side of the pixel defining layer away from the base substrate; and The pixel defining layer is further used to define a plurality of grooves, wherein the plurality of grooves are respectively located between any two adjacent pixel openings, and at least a portion of the reflective electrode layer is located in the plurality of grooves.

23. The display substrate according to claim 22, wherein: The display substrate further comprises a first conductive portion located on a side of the light shielding layer close to the base substrate; and a second conductive portion located on the semiconductor layer; The orthographic projection of the first conductive portion on the base substrate at least partially overlaps with the orthographic projection of the pixel opening on the base substrate, and the orthographic projection of the second conductive portion on the base substrate at least partially overlaps with the orthographic projection of the pixel opening on the base substrate; as well as The first electrode plate further includes the second conductive portion, and the second electrode plate further includes the first conductive portion. The first conductive portion is electrically connected to the light shielding portion, and the first conductive portion includes a transparent conductive material.

24. The display substrate according to any one of claims 8 to 10, wherein: The display substrate further includes a plurality of data lines located in the second conductive layer, the plurality of data lines including a first data line, a second data line, a third data line and a fourth data line, the first data line being electrically connected to a first electrode of a switch transistor of the first sub-pixel, the second data line being electrically connected to a first electrode of a switch transistor of the second sub-pixel, the third data line being electrically connected to a first electrode of a switch transistor of the third sub-pixel, and the fourth data line being electrically connected to a first electrode of a switch transistor of the fourth sub-pixel; and The first data line and the second data line are located on one side of the pixel driving circuit of the pixel unit in the first direction, the third data line and the fourth data line are located on the other side of the pixel driving circuit of the pixel unit in the first direction, the first data line and the second data line are spaced apart in the first direction, the first data line is located on a side of the second data line away from the pixel driving circuit of the pixel unit, and the fourth data line is located on a side of the third data line away from the pixel driving circuit of the pixel unit.

25. A display device, characterized in that: The display device includes the display substrate according to any one of claims 1 to 24.

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