Optical coherence tomography system and method

Abstract

The invention provides an optical coherence tomography system and method.The FPGA is used for collecting a current frame fundus image of a to-be-detected eye pixel by pixel, conducting analog-digital conversion on pixel data of each collected pixel point, and storing each obtained converted data in a preset storage unit; the processor is used for acquiring to-be-transmitted data from the preset storage unit in an asynchronous mode in the process that the FPGA collects the current frame of fundus image of the to-be-detected eye pixel by pixel, and sending the to-be-transmitted data to the upper computer through the gigabit Ethernet. In the system, when the FPGA acquires the current frame of fundus image of the eye to be detected pixel by pixel, the processor can acquire the data to be transmitted from the preset storage unit in an asynchronous mode and send the data to be transmitted to the upper computer through the gigabit Ethernet without waiting for the FPGA to completely acquire the current frame of fundus image, so that the image transmission time can be remarkably shortened, and the image transmission efficiency is improved. And the high-efficiency flow of the data is ensured.

Description

Technical Field

[0001] The present invention relates to the technical field of data processing, and in particular to an optical coherence tomography system and method. Background Art

[0002] Optical Coherence Tomography (OCT) technology is a three-dimensional tomography technology. Generally, it is based on fundus images to locate and track the movement state of the human eye, so as to guide OCT to perform tracking scans on the human eye to obtain OCT images. At the same time, in the OCT system, the acquisition and transmission of fundus images are key technologies for real-time tracking of eye movement or blinking in ophthalmic applications. Since the OCT scanning speed is as high as 400,000 times per second, a high-speed acquisition card (PCIE3.0*8, with a maximum speed of 8GB / s) is usually used to transmit OCT data. In order to maintain the efficiency and real-time performance of the system, the transmission speed of the fundus image must also be high enough (completed within 2ms from acquisition to transmission) to synchronize with the OCT data in time. In the OCT system, the real-time acquisition and fast transmission of fundus images are crucial for improving the imaging accuracy, avoiding the accumulation of invalid data, and reducing the rescan time. Usually, the fundus image is transmitted through a high-speed interface (such as USB 3.2). USB3.2 has a bandwidth of up to 10Gbps and can achieve the high-speed transmission of the entire frame of the fundus image. However, due to the requirements of transmission distance, system compatibility, and application scenarios, gigabit Ethernet needs to be used as the transmission means. However, the bandwidth of gigabit Ethernet is limited to about 1Gbps, and in the high-speed image acquisition scenario, the transmission speed of the fundus image is slow, increasing the image transmission time. Summary of the Invention

[0003] The purpose of the present invention is to provide an optical coherence tomography system and method to reduce the image transmission time.

[0004] An optical coherence tomography system provided by the present invention includes an OCT imaging unit, a fundus image imaging unit, and a host computer. The fundus image imaging unit includes: an FPGA and a processor. The FPGA is used to collect the current frame of the fundus image of the eye to be measured pixel by pixel, perform analog-to-digital conversion on the pixel data of each collected pixel point to obtain the converted data corresponding to each pixel point respectively, and save each converted data to a preset storage unit. The processor is used to, during the process of the FPGA collecting the current frame of the fundus image of the eye to be measured pixel by pixel, in an asynchronous manner, obtain the data to be transmitted from the preset storage unit, send the data to be transmitted to the host computer through gigabit Ethernet, and is used to detect eye movement.

[0005] Further, the processor is also configured to: packetize the acquired data to be transmitted to obtain packetized data; and send the packetized data to the host computer via Gigabit Ethernet.

[0006] Further, the processor is also configured to: after sending the packetized data to the host computer, determine whether there is new data to be transmitted in the preset storage unit; if there is new data to be transmitted, acquire the new data to be transmitted, packetize the new data to be transmitted to obtain new packetized data; and send the new packetized data to the host computer.

[0007] Further, the FPGA is also configured to: after completing the acquisition of the current frame fundus image, trigger an interrupt to generate an interrupt instruction; and send the interrupt instruction to the processor so that the processor adds marking information to the current frame fundus image.

[0008] Further, the marking information includes: timestamp information; the host computer is also configured to: after receiving the complete current frame fundus image, compare the complete current frame fundus image with a preset standard fundus image to obtain a comparison result; if the comparison result indicates a difference between the current frame fundus image and the standard fundus image, determine that there is an abnormal movement in the eye to be measured; according to the moment corresponding to the timestamp information, locate the abnormal position with the abnormal movement in the OCT image corresponding to the eye to be measured; wherein, the OCT image is acquired by the OCT imaging unit at the moment corresponding to the timestamp information; and start re-scanning the eye to be measured from the abnormal position through the OCT imaging unit to obtain the target OCT image of the eye to be measured.

[0009] Further, the abnormal movement includes: eye movement and / or blinking.

[0010] Further, the host computer is also configured to: send an acquisition instruction to the FPGA so that the FPGA acquires the current frame fundus image of the eye to be measured pixel by pixel according to the acquisition instruction; and send a transmission instruction to the processor so that the processor, in the process of the FPGA acquiring the current frame fundus image of the eye to be measured pixel by pixel, asynchronously acquires the data to be transmitted from the preset storage unit according to the transmission instruction.

[0011] Further, the system further includes a register; the register is used to store the data volume of all the converted data stored in the preset storage unit.

[0012] Further, the register is also configured to: update the data volume when the converted data stored in the preset storage unit is updated.

[0013] An optical coherence tomography method provided by the present invention includes: the FPGA acquires the current frame fundus image of the eye to be measured pixel by pixel, performs analog-to-digital conversion on the pixel data of each acquired pixel point to obtain the converted data corresponding to each pixel point respectively; saves each converted data to a preset storage unit; during the process of the FPGA acquiring the current frame fundus image of the eye to be measured pixel by pixel, the processor, in an asynchronous manner, obtains the data to be transmitted from the preset storage unit, sends the data to be transmitted to the host computer through Gigabit Ethernet, and is used to detect eye movement.

[0014] For the optical coherence tomography system and method provided by the present invention, the FPGA is used to acquire the current frame fundus image of the eye to be measured pixel by pixel, perform analog-to-digital conversion on the pixel data of each acquired pixel point, and save each obtained converted data to a preset storage unit; the processor is used to, during the process of the FPGA acquiring the current frame fundus image of the eye to be measured pixel by pixel, in an asynchronous manner, obtain the data to be transmitted from the preset storage unit, and send the data to be transmitted to the host computer through Gigabit Ethernet. In this system, while the FPGA acquires the current frame fundus image of the eye to be measured pixel by pixel, the processor can, in an asynchronous manner, obtain the data to be transmitted from the preset storage unit and send it to the host computer through Gigabit Ethernet, without waiting for the FPGA to complete the acquisition of the entire current frame fundus image, thereby significantly reducing the image transmission time and ensuring the efficient flow of data. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following will briefly introduce the drawings required for use in the description of the specific embodiments or the prior art. Obviously, the following drawings are some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0016] Figure 1 It is a schematic diagram of an optical coherence tomography system provided by an embodiment of the present invention; Figure 2 It is a flowchart of an optical coherence tomography method provided by an embodiment of the present invention; Figure 3 It is a flowchart of another optical coherence tomography method provided by an embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0017] The technical solution of the present invention will be clearly and completely described below in conjunction with the embodiments. Obviously, the described embodiments are some, but not all, of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0018] In the related art, gigabit Ethernet is required as the transmission means for fundus images. However, the bandwidth of gigabit Ethernet is limited to about 1 Gbps, and in high-speed image acquisition scenarios, the transmission speed of fundus images is slow, increasing the image transmission time. Based on this, the embodiments of the present invention provide an optical coherence tomography system and method, and this technology can be applied to scenarios where the transmission speed of fundus images needs to be improved.

[0019] For ease of understanding of this embodiment, first, an optical coherence tomography system disclosed in the embodiments of the present invention will be introduced, as Figure 1As shown, it includes an OCT imaging unit, a fundus image imaging unit, and a host computer. The fundus image imaging unit includes: FPGA 10 and processor 11; FPGA 10 is a programmable logic chip that can perform general functions, that is, it can be programmed to implement the required logic processing functions. FPGA 10 corresponds to the PL (Programmable Logic) terminal; processor 11 can also be called an ARM processor and corresponds to the PS (Processing System) terminal; FPGA 10 is used to collect the current frame fundus image of the eye to be measured pixel by pixel, perform analog-to-digital conversion on the pixel data of each pixel point collected, and obtain the converted data corresponding to each pixel point respectively; save each converted data to a preset storage unit; the above-mentioned fundus image refers to an image of the posterior structure of the eyeball taken by a special photography technique (such as a fundus camera), mainly showing structures such as the retina, optic disc, macula, retinal blood vessels, and choroid; the above-mentioned pixel data can include: brightness information, color information, etc. According to these pixel data, the light reflection intensity and structural tissue characteristics of different structures can be reflected; the above-mentioned preset storage unit can be DDR (Double Data Rate, that is, double-speed synchronous dynamic random access memory), etc.; in actual implementation, the collection of the fundus image can be controlled by FPGA 10, adopting a pixel-by-pixel collection mode. Through precise control of the galvanometer scanning and light source irradiation, FPGA 10 cooperates with the galvanometer and the light source to control, and realizes the point-by-point collection of the current frame fundus image of the eye to be measured. During the collection process, FPGA 10 captures each pixel point of the fundus image in sequence. The pixel data of each pixel point collected is usually analog data. An ADC (Analog-to-Digital Converter) can be used to perform analog-to-digital conversion on the pixel data of each pixel point to obtain the converted data corresponding to each pixel point respectively. The converted data is a digital signal, and the converted data corresponding to each pixel point can be stored in the preset storage unit in digital quantity form, laying a foundation for subsequent network transmission and waiting for the processor to read. The above-mentioned collection process can be swept at a frequency of 400 kHz, so that even under the requirements of high-speed imaging, data conversion remains accurate and efficient.

[0020] The processor 11 is used to obtain the data to be transmitted from a preset storage unit in an asynchronous manner during the process of the FPGA 10 collecting the current frame fundus image of the eye to be measured pixel by pixel, send the data to be transmitted to the host computer through Gigabit Ethernet, and is used to detect eye movement; the above asynchronous manner can be understood as that the data collection process of the FPGA 10 and the transmission process of the processor are completely independent, and the clock domains, control logics, and data streams of the FPGA 10 and the processor do not need to be strictly synchronized, but are synchronized and coordinated through the interaction notification of interrupts and registers. This asynchronous mode ensures that data collection and network transmission do not block each other, and the transmission process of the processor does not affect the continuous collection of the FPGA 10, enabling the entire transmission system to effectively support high-speed data collection; the above Gigabit Ethernet is a high-speed local area network technology with a theoretical transmission rate of up to 1 gigabit per second, mainly used to improve the data transmission efficiency between network devices; in actual implementation, the data collection of the FPGA 10 and the data transmission of the processor are completely independent and operate in an asynchronous manner. The FPGA 10 continuously performs data collection. Even during the process of the processor transmitting data, the FPGA 10 can still continuously write the newly collected and converted data into the preset storage unit; specifically, during the process of the FPGA 10 collecting the current frame fundus image of the eye pixel by pixel, the processor can obtain the data to be transmitted from the preset storage unit and send it to the host computer through Gigabit Ethernet, and the host computer can also detect whether there is eye movement in the eye to be measured according to the received data.

[0021] In the above optical coherence tomography system and method, the FPGA is used to collect the current frame fundus image of the eye to be measured pixel by pixel, perform analog-to-digital conversion on the pixel data of each collected pixel point, and save each obtained converted data to a preset storage unit; the processor is used to obtain the data to be transmitted from the preset storage unit in an asynchronous manner during the process of the FPGA collecting the current frame fundus image of the eye to be measured pixel by pixel, send the data to be transmitted to the host computer through Gigabit Ethernet, and is used to detect eye movement. In this system, while the FPGA is collecting the current frame fundus image of the eye to be measured pixel by pixel, the processor can obtain the data to be transmitted from the preset storage unit in an asynchronous manner and send it to the host computer through Gigabit Ethernet without waiting for the FPGA to complete the collection of the entire current frame fundus image, thereby significantly reducing the image transmission time and ensuring the efficient flow of data.

[0022] Further, the processor is also used for: performing packetization processing on the acquired data to be transmitted to obtain packetized data; and sending the packetized data to the host computer through Gigabit Ethernet. In actual implementation, after the processor acquires the data to be transmitted, it can start the packetization process and perform packetization processing on the acquired data to be transmitted. Specifically, the data to be transmitted can be segmented and encapsulated into multiple independent data units according to a preset specific rule, which is the above-mentioned packetized data, and then the packetized data is sent to the host computer through Gigabit Ethernet. Through packetization processing, the transmission efficiency can be improved, data integrity can be ensured, and flexible management of network protocols can be supported.

[0023] Further, the processor is also used for: after sending the packetized data to the host computer, determining whether there is new data to be transmitted in the preset storage unit; if there is new data to be transmitted, acquiring the new data to be transmitted, performing packetization processing on the new data to be transmitted to obtain new packetized data; and sending the new packetized data to the host computer. In actual implementation, the processor can dynamically query the data volume. Specifically, after the processor sends the packetized data to the host computer each time, it can immediately check whether there is new data to be transmitted in the preset storage unit. If there is new data to be transmitted, it continues with packetization and sending; since network transmission may be affected by jitter and the data volume sent each time is not fixed, the processor dynamically adjusts the transmission data volume to ensure the efficient use of the network channel, thereby realizing "dynamic transmission". The process of performing packetization processing on the data to be transmitted adopts a dynamic mechanism. The processor first queries the data volume in the DDR and dynamically generates an Ethernet data packet of an appropriate size according to the current available data volume. The core of this packetization mechanism lies in flexibly adapting to changes in network bandwidth. The data volume transmitted each time is not fixed, and it can be flexibly adjusted according to the network transmission rate and the current data volume. Such a design not only ensures the maximum utilization of bandwidth but also effectively reduces the delay fluctuation of data transmission when the network is unstable, guaranteeing efficient data transmission.

[0024] Further, the FPGA is also used for: after completing the acquisition of the current frame fundus image, triggering an interruption to generate an interruption instruction; and sending the interruption instruction to the processor so that the processor adds marking information to the current frame fundus image. In actual implementation, after the FPGA completes the acquisition of the current frame fundus image, it can trigger an interruption, generate an interruption instruction, and send the terminal instruction to the processor. The processor can then obtain the acquisition progress of the current frame fundus image (such as 100% completed) according to the interruption instruction and add corresponding marking information to the current frame fundus image. This marking information can be used to indicate that the acquisition of the current frame fundus image has been completed.

[0025] Further, the marking information includes: timestamp information; the host computer is further configured to: after receiving the complete current-frame fundus image, compare the complete current-frame fundus image with a preset standard fundus image to obtain a comparison result; if the comparison result indicates a difference between the current-frame fundus image and the standard fundus image, determine that there is an abnormal movement in the eye to be measured; the above standard fundus image can be a fundus image used as a benchmark of the same patient's eye to be measured collected in advance; the above abnormal movement includes: eye movement and / or blinking; in actual implementation, when the host computer receives the complete current-frame fundus image, it can compare the complete current-frame fundus image with the pre-obtained standard fundus image to determine whether the patient has abnormal movements such as eye movement and / or blinking. If there is a difference between the two images, it can usually be confirmed that there is an abnormal movement of eye movement and / or blinking in the eye to be measured.

[0026] Locate the abnormal position with abnormal movement in the OCT image corresponding to the eye to be measured according to the moment corresponding to the timestamp information; wherein, the OCT image is collected by the OCT imaging unit at the moment corresponding to the timestamp information; start re-scanning the eye to be measured from the abnormal position through the OCT imaging unit to obtain the target OCT image of the eye to be measured. After detecting that there is an abnormal movement of eye movement and / or blinking in the eye to be measured, the host computer can accurately locate the abnormal position with abnormal movement in the OCT image collected by the OCT imaging unit according to the timestamp information, and can notify the OCT imaging unit to start re-scanning the eye to be measured from the abnormal position. Re-scanning means performing an optical coherence tomography operation again on the previously affected fundus partial area (here the fundus part is the tomographic scanning part of OCT) due to eye movement and / or blinking. The light can be projected onto the corresponding fundus area again according to the previously set scanning mode, and the reflected optical signal is received and processed to obtain the OCT image corresponding to this re-scanned fundus area part. Combine this part of the OCT image with the previously obtained qualified fundus area part to re-construct the accurate target OCT image of the eye to be measured. Through this process, it is ensured that the imaging deviation caused by eye movement and / or blinking can be quickly corrected, the accumulation of invalid data is reduced, and at the same time, the additional time required for re-scanning is greatly shortened.

[0027] Further, the host computer is further configured to: send an acquisition instruction to the FPGA, so that the FPGA acquires the current frame fundus image of the eye to be measured pixel by pixel according to the acquisition instruction; send a transmission instruction to the processor, so that the processor, according to the transmission instruction, in the process of the FPGA acquiring the current frame fundus image of the eye to be measured pixel by pixel, asynchronously obtains the data to be transmitted from a preset storage unit. In actual implementation, when it is necessary to acquire a fundus image, the host computer can first send an acquisition instruction to the FPGA and then send a transmission instruction to the processor. After receiving the acquisition instruction, the FPGA can start to execute the acquisition process; after receiving the transmission instruction, the processor can execute the process of obtaining the data to be transmitted from the preset storage unit and sending it to the host computer.

[0028] Further, the system further includes a register; the register is used to store the data volume of all the converted data saved in the preset storage unit. For the convenience of description, in this embodiment, the preset storage unit is taken as DDR. The register and DDR are two key components in the computer storage system. The computer storage system is a hierarchical structure, and the register and DDR are at different levels. Specifically, the register is located inside the CPU and is the storage unit with the fastest speed and the smallest capacity, and can directly participate in operations; DDR is located on the motherboard outside the CPU and belongs to the main memory, with a slower speed but a large capacity, and is used to store programs and data. In actual implementation, after the FPGA saves the data after analog-to-digital conversion to the preset storage unit, the register can display the data volume of the data saved in the preset storage unit. The processor can determine the data volume of the data to be transmitted according to the data volume displayed by the register. Specifically, all the data stored in the preset storage unit can be used as the data to be transmitted and sent to the host computer.

[0029] The register is further configured to: update the data volume when the converted data saved in the preset storage unit is updated. In actual implementation, as the acquisition process of the FPGA progresses, the data it saves to the preset storage unit will also change continuously, and the size of the data volume will also be updated continuously, and the register will also update the size of the data volume it displays. In this embodiment, synchronization and coordination are achieved through an interrupt instruction and register status update: after the FPGA completes the acquisition of a certain amount of data, it updates the register information. For example, the register information is updated every time 10 bytes are acquired; the acquisition time is less than the update time and much less than the transmission time. The processor can query the data volume of the data stored in the DDR in real time and continue to packetize and transmit to ensure the smoothness and non-blocking of the data stream.

[0030] It should be noted that when the FPGA completes the acquisition of a fundus image once, it reports an interrupt instruction, but the acquisition and conversion of the data and storing it in the DDR are executed in real time. For example, it can be simply understood that the FPGA acquires one pixel point every 10 ns and then stores it in the DDR in sequence.

[0031] Secondly, when the processor performs data transmission, it is actually earlier than the time when the interrupt instruction is reported. That is, without interruption, the FPGA acquisition and the processor data transmission are carried out simultaneously. The role of the interrupt instruction is to inform the processor that the FPGA has completed the acquisition of the fundus image, so that the processor can distinguish different fundus images, that is, mark different fundus images.

[0032] The application of register status update means that in this system, during the processes of the FPGA performing operations such as fundus image acquisition and data processing, some key status information or control information will be written into the register. For example, there may be a register bit used to indicate whether the currently acquired data volume has reached a certain threshold, or whether the acquired data has undergone necessary preprocessing, etc. The processor can read the content in the register regularly or as needed. Once it reads that the corresponding flag bit is set (that is, set to a specific value, such as changing from 0 to 1 to indicate that an event has occurred), it can obtain the relevant status of the FPGA, and then make corresponding operation decisions, such as starting data transmission, adjusting transmission parameters, etc. Conversely, the processor can also convey instructions to the FPGA by writing content into the register. For example, notify the FPGA to pause acquisition or change some parameters of the acquisition, so as to achieve the coordinated cooperation between the two different tasks of acquisition and transmission. Usually, as long as the register status is updated, the transmission process can be executed, and it is not necessary to reach a certain threshold.

[0033] For easy understanding, refer to Figure 2 The flowchart of an optical coherence tomography method shown in the figure. It can be seen from the figure that the process includes: fundus image acquisition → per-pixel data conversion → data storage to DDR → interrupt notification and data query → determine whether there is acquired data → PS-side dynamic packetization and transmission → detect eye movement or blink → whether there is eye movement or blink → rescan OCT. In addition, the high bandwidth and long-distance transmission capabilities of Gigabit Ethernet enable the system to have stronger adaptability and reliability in complex medical environments.

[0034] The system can also be flexibly adjusted according to the bandwidth jitter situation to further optimize the utilization rate of network resources, ensuring that even in a low-bandwidth environment, efficient real-time transmission of images can be achieved. The real-time performance, stability, and anti-interference ability of the entire system have been greatly improved, making it suitable for application scenarios of high-speed data acquisition and real-time eye movement tracking.

[0035] In the case of high-speed sweep frequency of 400 kHz, the design goal of this system is to complete the transmission of fundus images with a resolution of 1024x2048 (about 4MB) within 2 ms. For USB 3.2, although it has a bandwidth of 10 Gbps and can theoretically support high-speed transmission, in the OCT system, the limitations of the system structure, transmission medium and environment often need to be considered. Therefore, this system adopts a gigabit network transmission scheme. The bandwidth of the gigabit network is about 1 Gbps, and the measured transmission rate is about 800 Mbps (ZYNQ-7000 series), that is, 100 MB / s, which means that a 4M image takes about 40 ms. In order to achieve the required low-latency effect under this bandwidth limitation, the dynamic asynchronous transmission mechanism designed in this scheme realizes the efficient transmission of 4MB data within 2 ms.

[0036] This scheme realizes the collaborative work of the PL side (FPGA) and the PS side (processor) through the ZYNQ-7000 chip to achieve the asynchronous dynamic transmission of fundus images, aiming to reduce the transmission delay and enhance the real-time response ability of the system. In the system design, core modules such as pixel-by-pixel acquisition, dynamic data packetization, asynchronous transmission and eye movement detection are adopted to realize their respective independent functions and synchronize and coordinate through interrupts and registers.

[0037] The system can realize eye movement detection during the acquisition process. After detecting eye movement, by synchronizing with the OCT system, the system can timely trigger the re-scanning of the area, significantly reducing the OCT image deviation caused by eye movement. For high-speed sweep frequency and large fundus images, asynchronous dynamic transmission ensures that data reaches the host computer quickly, greatly reducing the latency problem.

[0038] The above optical coherence tomography system has its core in using the ZYNQ-7000 series to realize the collaborative work of the PL side (FPGA) and the processor PS side (ARM processor) to complete independent acquisition and transmission tasks. The entire system realizes the collaborative work of acquisition and transmission through the interrupt mechanism and the register notification mechanism. After the acquired data is stored in the DDR, the network communication end dynamically queries the data volume and packetizes and sends it to realize the dynamic asynchronous transmission of data.

[0039] The system realizes efficient transmission in a gigabit network with limited bandwidth to support the fast response and high-precision imaging of the OCT system. This system can enable the dynamic transmission of fundus images during the acquisition process, thereby shortening the image transmission time and achieving fast response, especially in reducing the re-scanning time and the accumulation of invalid data after eye movement detection.

[0040] In summary, this scheme has the following effects and advantages: (1) Real-time dynamic transmission: Through asynchronous and dynamic transmission mechanisms, the system can transmit data while collecting it, without waiting for the image collection to complete, significantly reducing transmission latency and ensuring the efficient flow of data.

[0041] (2) Asynchronous acquisition and transmission: The FPGA acquisition and the processor transmission are completely independent and do not block each other. The acquisition and transmission processes can proceed in parallel, effectively utilizing system resources.

[0042] (3) Dynamically transmitted data volume: The processor dynamically adjusts the transmitted data volume according to the network conditions and the current data volume in the DDR, maximizing the utilization of bandwidth resources. Even when the network status fluctuates, the efficiency of data transmission can be ensured.

[0043] (4) Low-latency transmission: Under the conditions of 400kHz sweep frequency and 4MB data scale, it can be transmitted within 2ms through a gigabit network, ensuring fast response after eye movement detection and the need for OCT rescan, and greatly shortening the time for collecting invalid data.

[0044] The present invention provides another optical coherence tomography method, as Figure 3 shown, the method includes the following steps: Step S302, the FPGA acquires the current frame fundus image of the eye to be measured pixel by pixel, performs analog-to-digital conversion on the pixel data of each acquired pixel point to obtain the converted data corresponding to each pixel point respectively; saves each converted data to a preset storage unit; Step S304, during the process of the FPGA acquiring the current frame fundus image of the eye to be measured pixel by pixel, the processor uses an asynchronous method to obtain the data to be transmitted from the preset storage unit, and sends the data to be transmitted to the host computer through a gigabit Ethernet and is used for eye movement detection.

[0045] In the above optical coherence tomography method, while the FPGA acquires the current frame fundus image of the eye to be measured pixel by pixel, the processor can use an asynchronous method to obtain the data to be transmitted from the preset storage unit and send it to the host computer through a gigabit Ethernet, without waiting for the FPGA to complete the acquisition of the entire current frame fundus image, thereby significantly reducing the image transmission time and ensuring the efficient flow of data.

[0046] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. An optical coherence tomography system, comprising an OCT imaging unit, a fundus imaging unit and a host computer, characterized in that: The fundus image imaging unit comprises: an FPGA and a processor; The FPGA is used to collect the fundus image of the current frame of the eye to be tested pixel by pixel, perform analog-to-digital conversion on the pixel data of each collected pixel point, and obtain converted data corresponding to each pixel point; and save each of the converted data to a preset storage unit; The processor is used to obtain the data to be transmitted from the preset storage unit in an asynchronous manner during the process of the FPGA collecting the fundus image of the current frame of the eye to be tested pixel by pixel, send the data to be transmitted to the host computer via Gigabit Ethernet, and detect eye movement.

2. The system according to claim 1, characterized in that The processor is further configured to: Performing package processing on the acquired data to be transmitted to obtain packaged data; The packaged data is sent to the host computer via Gigabit Ethernet.

3. The system according to claim 2, characterized in that The processor is further configured to: After sending the packaged data to the host computer, determining whether there is new data to be transmitted in the preset storage unit; If there is new data to be transmitted, the new data to be transmitted is obtained, and the new data to be transmitted is packaged to obtain new packaged data; The new package data is sent to the host computer.

4. The system according to claim 1, characterized in that The FPGA is also used for: After the acquisition of the fundus image of the current frame is completed, an interrupt is triggered to generate an interrupt instruction; The interrupt instruction is sent to the processor, so that the processor adds marking information to the fundus image of the current frame.

5. The system according to claim 4, characterized in that The marking information includes: timestamp information; the host computer is also used for: After receiving the complete fundus image of the current frame, comparing the complete fundus image of the current frame with a preset standard fundus image to obtain a comparison result; If the comparison result indicates that there is a difference between the fundus image of the current frame and the standard fundus image, it is determined that there is an abnormal movement of the eye to be tested; According to the time corresponding to the timestamp information, the abnormal position where the abnormal action exists is located in the OCT image corresponding to the eye to be tested; wherein the OCT image is acquired by the OCT imaging unit at the time corresponding to the timestamp information; The eye to be tested is rescanned starting from the abnormal position by the OCT imaging unit to obtain a target OCT image of the eye to be tested.

6. The system according to claim 5, characterized in that The abnormal movements include: eye movements and / or blinking.

7. The system according to claim 1, characterized in that The host computer is also used for: Sending an acquisition instruction to the FPGA, so that the FPGA acquires the fundus image of the current frame of the eye to be tested pixel by pixel according to the acquisition instruction; A transmission instruction is sent to the processor, so that the processor acquires the data to be transmitted from the preset storage unit in an asynchronous manner according to the transmission instruction during the process in which the FPGA acquires the fundus image of the current frame of the eye to be tested pixel by pixel.

8. The system according to claim 1, characterized in that The system also includes a register; The register is used to store the data amount of all converted data stored in the preset storage unit.

9. The system according to claim 8, characterized in that The registers are also used for: When the converted data stored in the preset storage unit is updated, the data amount is updated.

10. An optical coherence tomography method, characterized in that: The method comprises: The FPGA collects the fundus image of the current frame of the eye to be tested pixel by pixel, performs analog-to-digital conversion on the pixel data of each pixel point collected, and obtains the converted data corresponding to each pixel point; and saves each of the converted data to a preset storage unit; During the process of the FPGA collecting the fundus image of the current frame of the eye to be tested pixel by pixel, the processor obtains the data to be transmitted from the preset storage unit in an asynchronous manner, sends the data to be transmitted to the host computer via Gigabit Ethernet, and uses it to detect eye movement.

Images