Method and device for executing unconditional jump instruction

Abstract

The present invention discloses a method and device for executing unconditional jump instructions. The method transmits the branch prediction result obtained in the instruction fetch stage and the instruction type information parsed in the decoding stage to the instruction dispatch stage. Then, in the instruction dispatch stage, it is determined whether to stop dispatching instructions based on the instruction type information and the branch prediction result. If the dispatched instruction is an unconditional jump instruction and the instruction is predicted to not jump, then the dispatch of all instructions following the unconditional jump instruction is stopped, so that instructions on the erroneous path are no longer speculatively executed, reducing damage to the processor state. If the instruction is another type of instruction or an unconditional jump instruction predicted to be a jump, then the instruction dispatch is not affected. The present invention aims to reduce the time it takes to restore the processor state when a branch misprediction occurs in the processor, thereby improving the performance of the processor.

Description

Technical Field

[0001] The present invention relates to processor design technology, and in particular to an execution method and device for an unconditional jump instruction. Background Art

[0002] Processors improve performance through branch prediction and speculative execution. This involves speculating on instructions along the predicted path based on the branch prediction before the actual execution result of the branch instruction is determined. If the branch prediction is correct, the speculatively executed instructions are all expected to be executed, speeding up the processor's execution. If the branch prediction is incorrect, the processor state must be cleared from the effects of all instructions along the incorrect path, restoring the processor to the state at the time of the incorrectly predicted branch. Only then can the processor begin executing instructions along the correct path. Therefore, the shorter the processor state recovery time after a branch misprediction, the better. The time to recover the processor state after a branch misprediction is closely related to the number of instructions that were incorrectly speculated. A greater number of instructions are incorrectly speculated, and the recovery time (for example, the time required to rebuild the register renaming map) is often longer. Among the branch instructions defined by processor architectures are unconditional jump instructions, such as the JAL and JALR instructions in the RISC-V open instruction set architecture and the BL and BLR instructions in the ARM instruction set architecture. These instructions always result in a jump; only target addresses need to be predicted. However, if the current branch prediction structure does not have any record of unconditional jump instructions and cannot provide a predicted target address, the unconditional jump instruction will still be predicted as not jumping, and the processor will fetch and execute instructions sequentially. In this case, all instructions fetched and executed sequentially will be incorrectly speculated and there is no need to continue executing them. However, the existing technology does not classify branch types and only performs speculative execution based on branch prediction results. After the execution result of the branch instruction is generated, subsequent processing is performed based on whether the prediction is correct. In fact, if speculative execution is not stopped when it is clear that the speculative execution is incorrect, it will help reduce the time required to restore the processor state when a branch misprediction occurs, thereby improving processor performance. Summary of the Invention

[0003] The technical problem to be solved by the present invention is as follows: In view of the above-mentioned problems in the prior art, a method and device for executing an unconditional jump instruction are provided. The present invention aims to reduce the time required to restore the processor state when a branch misprediction occurs in the processor, thereby improving the performance of the processor.

[0004] In order to solve the above technical problems, the technical solution adopted by the present invention is:

[0005] A method for executing an unconditional jump instruction comprises the following steps: passing a branch prediction result obtained in an instruction fetch stage and instruction type information parsed in a decoding stage to an instruction dispatch stage; then, in the instruction dispatch stage, determining whether to stop dispatching instructions based on the instruction type information and the branch prediction result; if the dispatched instruction is an unconditional jump instruction and the instruction is predicted to not jump, then stopping dispatching all instructions following the unconditional jump instruction so that instructions on the erroneous path are no longer speculatively executed to reduce damage to the processor state; if the instruction is another type of instruction or an unconditional jump instruction predicted to jump, then instruction dispatch is not affected.

[0006] Optionally, the branch prediction result obtained in the instruction fetch stage and the instruction type information parsed in the decoding stage are passed to the instruction dispatch stage, including: S101, the instruction fetch stage performs instruction fetch and branch prediction, and the prediction result is passed to the subsequent stage of the pipeline along with the instruction encoding; S102, the instruction decoding stage parses the instruction type according to the instruction encoding, and the instruction type information is passed to the subsequent stage of the pipeline.

[0007] Optionally, determining whether to stop dispatching instructions according to instruction type information and branch prediction results during the instruction dispatching stage includes:

[0008] S201, determining whether the dispatched instruction is an unconditional jump instruction;

[0009] S202, when the dispatched instruction is an unconditional jump instruction, determine whether the branch prediction result predicts a jump. If a jump occurs, the instruction is dispatched, and its subsequent instructions are also judged in turn whether they can be dispatched, and enter the instruction execution stage; otherwise, after dispatching the instruction, stop dispatching all subsequent instructions and enter the instruction execution stage.

[0010] Optionally, after entering the instruction execution stage in step S202, the instruction execution stage determines whether the prediction is correct based on the actual execution result and the prediction result of the unconditional jump instruction. If the branch prediction is correct, it will not affect other instructions in the pipeline; otherwise, the instruction dispatch stage is unblocked after clearing the instructions on the wrong path.

[0011] Optionally, step S202 also includes dispatching the instruction when the dispatched instruction is not an unconditional jump instruction, and its subsequent instructions are also judged in turn whether they can be dispatched, and enter the instruction execution stage to operate according to the instruction function.

[0012] In addition, the present invention also provides an electronic device, comprising a microprocessor and a memory connected to each other, wherein the microprocessor is programmed or configured to execute the execution method of the unconditional jump instruction.

[0013] In addition, the present invention also provides a computer-readable storage medium, in which a computer program or instruction is stored. The computer program or instruction is programmed or configured to execute the execution method of the unconditional jump instruction through a processor.

[0014] In addition, the present invention also provides a computer program product, including a computer program or instructions, wherein the computer program or instructions are programmed or configured to execute the execution method of the unconditional jump instruction through a processor.

[0015] Compared with the prior art, the present invention can mainly achieve the following beneficial effects: the present invention can reduce the time required to restore the processor state when a branch is mispredicted. After an unconditional jump instruction is predicted to not jump, the processor will sequentially fetch instructions. These fetched instructions are instructions on the wrong path. After entering the dispatch stage, they will be blocked from dispatch and will not continue to be speculatively executed, reducing damage to the processor state. In addition, after these instructions on the wrong path are blocked in the dispatch stage, other pipeline stages before the dispatch stage in the pipeline will also be blocked in turn, thereby preventing more instructions on the wrong path from being fetched into the pipeline. The present invention can reduce the number of instructions on the wrong path that are speculatively executed, thereby reducing the time required to restore the processor state when a branch is mispredicted. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 Schematic diagram of the basic process of the method of the embodiment of the present invention. DETAILED DESCRIPTION

[0017] In order to enable those skilled in the art to better understand the technical solution of the present invention, the technical solution of the present invention will be further described in detail below with reference to the accompanying drawings in the embodiments of the present invention.

[0018] like Figure 1 As shown, the execution method of the unconditional jump instruction of this embodiment includes the following steps: passing the branch prediction result obtained in the instruction fetch stage and the instruction type information parsed in the decoding stage to the instruction dispatch stage, and then judging whether to stop dispatching instructions according to the instruction type information and the branch prediction result in the instruction dispatch stage; if the dispatched instruction is an unconditional jump instruction and the instruction is predicted to not jump, then stop dispatching all instructions following the unconditional jump instruction, so that the instructions on the wrong path will no longer be speculated and executed to reduce damage to the processor state; if it is another type of instruction or an unconditional jump instruction predicted to jump, then the instruction dispatch is not affected.

[0019] like Figure 1As shown, in this embodiment, the branch prediction result obtained in the instruction fetch stage and the instruction type information parsed in the decoding stage are passed to the instruction dispatch stage, including: S101, the instruction fetch stage performs instruction fetch and branch prediction, and the prediction result is passed to the subsequent stage of the pipeline along with the instruction encoding; S102, the instruction decoding stage parses the instruction type according to the instruction encoding, and the instruction type information is passed to the subsequent stage of the pipeline.

[0020] like Figure 1 As shown, in this embodiment, determining whether to stop dispatching instructions according to instruction type information and branch prediction results during the instruction dispatch stage includes:

[0021] S201, determining whether the dispatched instruction is an unconditional jump instruction;

[0022] S202, when the dispatched instruction is an unconditional jump instruction, determine whether the branch prediction result predicts a jump. If a jump occurs, the instruction is dispatched, and its subsequent instructions are also judged in turn whether they can be dispatched, and enter the instruction execution stage; otherwise, after dispatching the instruction, stop dispatching all subsequent instructions and enter the instruction execution stage.

[0023] like Figure 1 As shown, after entering the instruction execution stage in step S202 of this embodiment, the instruction execution stage determines whether the prediction is correct based on the actual execution result and the prediction result of the unconditional jump instruction. If the branch prediction is correct, it will not affect other instructions in the pipeline; otherwise, the instruction dispatch stage is unblocked after clearing the instructions on the wrong path.

[0024] like Figure 1 As shown, step S202 of this embodiment also includes dispatching the instruction when the dispatched instruction is not an unconditional jump instruction, and its subsequent instructions are also judged in turn whether they can be dispatched, entering the instruction execution stage to operate according to the instruction function.

[0025] The execution method for unconditional jump instructions in this embodiment can be divided into four stages: 1) The instruction fetch stage performs instruction fetching and branch prediction. The branch prediction result includes whether the instruction will jump and the jump target address. The branch prediction result is passed along with the fetched instruction code to the subsequent pipeline stage; 2) The decode stage parses the instruction code to determine the instruction type. The instruction type information is passed to the subsequent pipeline stage; 3) The instruction dispatch stage determines whether to stop instruction dispatch based on the instruction type information and the branch prediction result. If the instruction type indicates that the instruction being dispatched is an unconditional jump instruction, the "jump occurrence" information in the branch prediction result is checked. If a jump occurs, the unconditional jump instruction is dispatched normally and enters the instruction execution stage. All subsequent instructions that have been fetched and decoded are also evaluated for dispatchability. If a jump does not occur, the dispatch of the unconditional jump instruction stops all subsequent instructions from being dispatched. If the instruction type indicates that the instruction being dispatched is not an unconditional jump instruction, the instruction is dispatched normally, and all subsequent instructions that have been fetched and decoded are also evaluated for dispatchability. 4) The instruction execution phase operates according to the instruction type. If the instruction is not an unconditional jump instruction, then the operation is performed according to its function. Since this part does not fall within the scope of the problem to be solved by the present invention, it will not be described in detail. If the instruction is an unconditional jump instruction, then the branch prediction is judged to be correct based on its actual execution result and the predicted result. If the prediction is that the jump will not occur or the predicted target address is different from the actual target address, then the branch prediction is incorrect; if the prediction is that the jump will occur and the predicted target address is the same as the actual target address, then the branch prediction is correct. For unconditional jump instructions with incorrect predictions, after execution, a pipeline clear operation will be triggered, clearing all instructions on the incorrect path that have been fetched after it, then fetching instructions from the correct target address and unblocking the instruction dispatch phase, allowing instructions on the correct path to be dispatched for execution. For unconditional jump instructions with correct predictions, after execution, no changes will be caused to other instructions in the pipeline, because the instructions following it are instructions on the correct path and should be executed. In summary, when an unconditional jump instruction is predicted not to jump, the method of this embodiment stops dispatching all instructions on the subsequent error path that were fetched, preventing these instructions from being speculatively executed and reducing damage to the processor state. Furthermore, after these instructions on the error path are blocked in the dispatch stage, the other pipeline stages before the dispatch stage are also blocked in turn, preventing further instructions on the error path from being fetched and entering the pipeline. This reduces the number of instructions on the error path that are speculatively executed, thereby reducing the time required to restore the processor state in the event of a branch misprediction.

[0026] In addition, this embodiment also provides an electronic device, including a microprocessor and a memory connected to each other, wherein the microprocessor is programmed or configured to execute the execution method of the unconditional jump instruction.

[0027] In addition, this embodiment also provides a computer-readable storage medium, in which a computer program or instruction is stored. The computer program or instruction is programmed or configured to execute the execution method of the unconditional jump instruction through a processor.

[0028] In addition, this embodiment also provides a computer program product, including a computer program or instructions, which are programmed or configured to execute the execution method of the unconditional jump instruction through a processor.

[0029] Those skilled in the art should understand that the technical solution provided by the present invention may be in the form of a method, a system, or a computer program product. Therefore, the present invention may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware aspects. Moreover, the present invention may take the form of a computer program product implemented on one or more computer-readable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code. The present invention is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present invention. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of processes and / or boxes in the flowchart and / or block diagram, may be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the functions described in the process. Figure 1 a process or multiple processes and / or boxes Figure 1 These computer program instructions can also be stored in a computer-readable memory that can guide a computer or other programmable data processing device to work in a specific way, so that the instructions stored in the computer-readable memory produce a product including the instruction device, which implements the function specified in the process. Figure 1 a process or multiple processes and / or boxes Figure 1 These computer program instructions can also be loaded onto a computer or other programmable data processing device, so that a series of operation steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process in the process. Figure 1 a process or multiple processes and / or boxes Figure 1A step that specifies a function in one or more boxes.

[0030] The above description is merely a preferred embodiment of the present invention. The scope of protection of the present invention is not limited to the above embodiment. All technical solutions based on the concept of the present invention are within the scope of protection of the present invention. It should be noted that for those skilled in the art, various improvements and modifications that do not depart from the principles of the present invention should also be considered within the scope of protection of the present invention.

Claims

1. A method for executing an unconditional jump instruction, characterized in that: The method comprises the following steps: passing the branch prediction result obtained in the instruction fetch stage and the instruction type information parsed in the decoding stage to the instruction dispatch stage, and then determining whether to stop dispatching instructions according to the instruction type information and the branch prediction result in the instruction dispatch stage; if the dispatched instruction is an unconditional jump instruction and the instruction is predicted to not jump, then stopping dispatching all instructions following the unconditional jump instruction so that instructions on the wrong path are no longer speculatively executed to reduce damage to the processor state; if the instruction is another type of instruction or an unconditional jump instruction predicted to be a jump, then instruction dispatch is not affected; The step of determining whether to stop dispatching instructions according to instruction type information and branch prediction results during the instruction dispatching phase includes: S201, determining whether the dispatched instruction is an unconditional jump instruction; S202, when the dispatched instruction is an unconditional jump instruction, determine whether the branch prediction result predicts a jump. If a jump occurs, the instruction is dispatched, and its subsequent instructions are also judged in turn whether they can be dispatched, and enter the instruction execution stage; otherwise, after dispatching the instruction, stop dispatching all subsequent instructions and enter the instruction execution stage.

2. The method for executing an unconditional jump instruction according to claim 1, wherein: The branch prediction result obtained in the instruction fetch stage and the instruction type information parsed in the decoding stage are passed to the instruction dispatch stage, including: S101, the instruction fetch stage performs instruction fetch and branch prediction, and the prediction result is passed to the subsequent stage of the pipeline along with the instruction encoding; S102, the instruction decoding stage parses the instruction type according to the instruction encoding, and the instruction type information is passed to the subsequent stage of the pipeline.

3. The method for executing an unconditional jump instruction according to claim 1, wherein: After entering the instruction execution stage in step S202, the instruction execution stage determines whether the prediction is correct based on the actual execution result and the prediction result of the unconditional jump instruction. If the branch prediction is correct, it will not affect other instructions in the pipeline; otherwise, the instruction dispatch stage is unblocked after clearing the instructions on the wrong path.

4. The method for executing an unconditional jump instruction according to claim 1, wherein: Step S202 also includes dispatching the instruction when the dispatched instruction is not an unconditional jump instruction, and its subsequent instructions are also judged in turn whether they can be dispatched, and enter the instruction execution stage to operate according to the instruction function.

5. An electronic device comprising a microprocessor and a memory connected to each other, characterized in that: The microprocessor is programmed or configured to execute the method for executing the unconditional jump instruction according to any one of claims 1 to 4.

6. A computer-readable storage medium having a computer program or instruction stored therein, characterized in that: The computer program or instruction is programmed or configured to execute the execution method of the unconditional jump instruction according to any one of claims 1 to 4 through a processor.

7. A computer program product comprising a computer program or instructions, characterized in that The computer program or instruction is programmed or configured to execute the execution method of the unconditional jump instruction according to any one of claims 1 to 4 through a processor.

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