Phase-locked loop dynamic response analysis method under distortion voltage of island micro-grid

Abstract

The invention discloses a phase-locked loop dynamic response analysis method under distortion voltage of an island micro-grid, which comprises the following steps: a phase-locked loop has a PLL model under distortion voltage, the stability margin, dynamic response and anti-interference capability of the PLL model are analyzed to obtain steady-state performance parameters under distortion voltage, and the steady-state performance parameters under distortion voltage are analyzed; and a theoretical basis is provided for phase locking and frequency locking of the power grid when the island micro-grid breaks down.

Description

Technical Field

[0001] The present invention belongs to the technical field of power grids, and particularly relates to a method for analyzing the dynamic response of a phase-locked loop under distorted voltage in an island microgrid. Background Art

[0002] With the practical problems of power shortage and development obstacles on islands, a new type of island power grid form based on the collaborative control and efficient interaction of sources, energy storage, loads, etc., namely the island microgrid system, has emerged as the times require. The island microgrid is a micro-power system applied to islands, which is based on the available energy on the islands and consists of various forms of power generation and supply systems, energy storage devices, and power electronic devices.

[0003] Due to the diversity on the power supply side and the power consumption side within the system, when the island microgrid uniformly manages and regulates the distribution of electric energy within the system, a large number of power electronic devices and equipment, such as transformers, converters, and inverters, are required. Inevitably, various harmonics will invade the power grid, further causing serious distortion of the grid voltage. In addition, during the switching process of the inverter between grid-connected and off-grid, as well as the uncertainty of green energy and the pulse power characteristics of high-power loads, it will further cause grid frequency jumps, greatly reducing the power quality of the grid and significantly increasing the difficulty of grid-connected control.

[0004] If the island microgrid is connected to the grid, and the voltage frequencies and phases of the island microgrid and the main grid are not synchronized, or the voltage frequencies and phases of the power consumption side and the power supply side of the island microgrid are not synchronized, the island microgrid cannot operate normally in grid connection. At the same time, the voltage non-synchronization will cause a huge voltage drop on both sides of the grid connection, resulting in a huge impact current, burning out the circuit, and damaging the entire power grid system, which needs to be further improved. Summary of the Invention

[0005] The present invention provides a method for analyzing the dynamic response of a phase-locked loop under distorted voltage in an island microgrid, which can analyze the dynamic response of the phase-locked loop under distorted voltage and obtain steady-state performance parameters that can be quickly analyzed under distorted voltage.

[0006] To solve the above problems, the technical solutions provided by the present invention are as follows:

[0007] An embodiment of the present invention provides a method for analyzing the dynamic response of a phase-locked loop under distorted voltage in an island microgrid, including: the phase-locked loop under distorted voltage has a PLL model, and the stability margin, dynamic response, and anti-interference ability of the PLL model are analyzed to obtain steady-state performance parameters under distorted voltage.

[0008] In an alternative embodiment of the present invention, the stability margin analysis of the PLL model includes:

[0009] The open-loop transfer function of the PLL model is designed as

[0010] Among them, ω z is the corner frequency, and ω z = k i / k p ;

[0011] Based on the above formula (1), the PLL phase margin PM is:

[0012] PM = φ z + φ p (2);

[0013] Among them, and the crossover frequency

[0014] For PM with respect to ω c taking the partial derivative and making the result zero, that is:

[0015]

[0016] At the same time, by combining formula (2), we can get:

[0017]

[0018] From formula (4), it can be obtained that when ω p and ω z are fixed values, when , the PM of the PLL is the largest;

[0019] Among them, let ω p = g 2 ω z , g is a constant, and from formula (4), we can get:

[0020]

[0021] From formula (5), it can be obtained that the parameters of the PLL are determined by g and ω c , and by combining formulas (2) and (5), we can get:

[0022]

[0023] When the phase margin of the function curve of the above formula (6) is selected between 45° and 70°, the stability of the PLL is better, and at this time g ∈ (2.4, 5.6); when g = 3.5, PM = 58.11.

[0024] In an optional embodiment of the present invention, the dynamic response analysis of the PLL model includes: when there is a phase mutation or frequency jump, in order to obtain the minimum settling time, relevant parameter design is carried out; by combining formulas (1) and (5), the open-loop transfer function of the PLL can be obtained as:

[0025] From Equation (7), the open-loop transfer function G of the PLL OL (s) is a second-order function and has two poles at the origin. Therefore, the PLL can lock the phase information without error during phase mutation or frequency jump;

[0026] The error transfer function is

[0027] Let g = 2ζ + 1, and the above equation is simplified to:

[0028] During phase mutation (Δθ), the error signal is Laplace-transformed as:

[0029]

[0030] Similarly, during frequency jump (Δω), the error signal is Laplace-transformed as:

[0031]

[0032] In the time domain, the expressions of Equation (10) and Equation (11) are as follows:

[0033]

[0034]

[0035] From Equation (12) and Equation (13), it can be seen that during phase mutation or frequency jump, for any damping coefficient ζ, the dynamic response of the PLL is related to the crossover frequency ωc: ω c The larger it is, the faster the dynamic response speed of the PLL; ω c The larger it is, the anti-interference ability of the PLL will decrease. Therefore, when selecting ω c , it is necessary to balance the dynamic response speed and the anti-interference ability;

[0036] In the dynamic response of the PLL to phase mutation and frequency jump with different ζ, the response of the PLL should be balanced between the response speed and overshoot; when ζ is small, the dynamic response speed of the PLL is fast but the overshoot is large; on the contrary, the dynamic response speed is slow but the overshoot is small; the selection range of the damping coefficient ζ is 0.6 - 1. At this time, the dynamic response speed of the PLL is fast and the overshoot is within a reasonable range, and at the same time, ζ has little influence on the anti-interference ability of the PLL.

[0037] In an optional embodiment of the present invention, the anti-interference ability analysis of the PLL model includes: analyzing the selection of the crossover frequency ω c to make the PLL have better anti-interference ability;

[0038] When using a notch filter, there is an upper bandwidth BW for the open-loop transfer function of the PLLOL , to ensure that the passband of the PLL is not affected by the notch filter, so when selecting ω c , ω c should be far from the notch frequency, generally selected at 1 / 4 to 1 / 5 of the notch frequency, such as 2π·20~2π·25 rad / s;

[0039] The disturbance closed-loop transfer function of the PLL is designed as:

[0040]

[0041] Let ζ = 0.707, g = 3.5, V +1 = 1. At this time, in the Bode diagrams of the disturbance transfer function and the open-loop transfer function of the PLL at different ω c , for the disturbance transfer function of the PLL with ω c being a constant and the open-loop transfer function, at ω c , their amplitude characteristics are the same; when ω > ω c , their attenuation amounts are almost the same; at the required ω c , the open-loop function can be used to replace the disturbance function for relevant calculations.

[0042] In an alternative embodiment of the present invention, the analysis of the disturbance resistance ability of the PLL model includes: G OL (s) amplitude characteristic analysis, ω d is the lowest disturbance frequency, and atten ωd is the attenuation value at the lowest disturbance frequency;

[0043]

[0044] Substitute ω p = gω c to get:

[0045] From this, it can be obtained that:

[0046] From Equation (17), ω c According to the preset suitable atten ωd being fixed, ω d = 6ω = 2π·300 rad / s. Let ω c = 2π·25 rad / s, when g = 3.5, atten ωd = -32.29 dB, which can meet the requirements of the PLL, and ω c can be set to 2π·25 rad / s;

[0047] Substitute the design values of ω c , ζ and g as follows: ω c= 2π·25 rad / s, ζ = 0.707, g = 3.5. From this, the parameters of the PLL can be further designed. Cut-off frequency ω p = gω c = 2π·87.5 rad / s.

[0048] Compared with the prior art, the embodiment of the present invention provides a method for analyzing the dynamic response of a phase-locked loop under distorted voltage in an island microgrid, having the following beneficial effects: A method for analyzing the dynamic response of a phase-locked loop under distorted voltage in an island microgrid includes: The phase-locked loop under distorted voltage has a PLL model. Analyze the stability margin, dynamic response, and anti-interference ability of the PLL model to obtain the steady-state performance parameters under distorted voltage, providing a theoretical basis for the grid to lock the phase and frequency in time when a fault occurs in the island microgrid. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] To more clearly illustrate the technical solutions in the embodiments or the prior art, the following briefly introduces the drawings required for use in the description of the embodiments or the prior art. Obviously, the following drawings are only some embodiments of the invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0050] Figure 1 It is a function curve diagram of PM with respect to g provided by the embodiment of the present application.

[0051] Figure 2 It is a schematic diagram of the PLL dynamic response - phase mutation when ζ is different provided by the embodiment of the present application.

[0052] Figure 3 It is a schematic diagram of the PLL dynamic response - frequency jump when ζ is different provided by the embodiment of the present application.

[0053] Figure 4 It is a schematic diagram of the open-loop transfer function and disturbance closed-loop transfer function curves of the PLL model provided by the embodiment of the present application.

[0054] Figure 5 It is the open-loop transfer function of the PLL model provided by the embodiment of the present application under different ω c Bode diagram

[0055] Figure 6 It is the amplitude characteristic diagram of G OL (s) provided by the embodiment of the present application. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0056] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative efforts belong to the scope of protection of the present application.

[0057] An embodiment of the present invention provides a method for analyzing the dynamic response of a phase-locked loop under distorted voltage in an islanded microgrid, including the following steps: The phase-locked loop has a PLL model under distorted voltage. Analyze the stability margin, dynamic response, and anti-interference ability of the PLL model to obtain the steady-state performance parameters under distorted voltage.

[0058] Embodiment 1

[0059] The stability margin analysis of the PLL model includes:

[0060] The open-loop transfer function of the PLL model is designed as

[0061] where ω z is the corner frequency, and ω z = k i / k p ;

[0062] Based on the above formula (1), the PLL phase margin PM is PM = φ z + φ p (2);

[0063] where and the crossover frequency

[0064] For PM with respect to ω c take the partial derivative and set the result to zero, that is

[0065] At the same time, combining formula (2) gives:

[0066] From formula (4), it can be seen that when ω p and ω z are fixed values, when , the PM of the PLL is the largest;

[0067] where, let ω p = g 2 ω z , g is a constant, and from formula (4) we get:

[0068]

[0069] From formula (5), it can be seen that the parameters of the PLL are determined by g and ωc By combining equations (2) and (5), we can obtain:

[0070] As Figure 1 shown, when the phase margin of the function curve of the above equation (6) is selected between 45° and 70°, the PLL has better stability. At this time, g ∈ (2.4, 5.6); when g = 3.5, PM = 58.11.

[0071] Example 2

[0072] The dynamic response analysis of the PLL model includes: when there is a phase mutation or a frequency jump, in order to obtain the minimum settling time, the relevant parameter design is carried out as follows:

[0073] By combining equations (1) and (5), the open-loop transfer function of the PLL can be obtained as:

[0074]

[0075] From equation (7), the open-loop transfer function G OL (s) of the PLL is a second-order function and has two poles at the origin. Therefore, the PLL can lock the phase information without error when there is a phase mutation or a frequency jump;

[0076] The error transfer function is:

[0077]

[0078] Let g = 2ζ + 1, and the above equation is simplified to:

[0079]

[0080] When there is a phase mutation (Δθ), the error signal is Laplace-transformed as:

[0081]

[0082] Similarly, when there is a frequency jump (Δω), the error signal is Laplace-transformed as:

[0083]

[0084] In the time domain, the expressions of equations (10) and (11) are as follows:

[0085]

[0086] From equations (12) and (13), it can be obtained that when there is a phase mutation or a frequency jump, for any damping coefficient ζ, the dynamic response of the PLL is related to the crossover frequency ω c : ωc The larger it is, the faster the dynamic response speed of the PLL; however, when ω c is larger, the disturbance rejection ability of the PLL will decrease. Therefore, when selecting ω c , it is necessary to balance the dynamic response speed and the disturbance rejection ability.

[0087] As Figure 2 and Figure 3 shown, in the dynamic response phase mutation and frequency jump of the PLL with different ζ, the response of the PLL should be balanced between the response speed and overshoot; when ζ is small, the dynamic response speed of the PLL is fast but the overshoot is large; on the contrary, the dynamic response speed is slow but the overshoot is small; the selection range of the damping coefficient ζ is 0.6-1. At this time, the dynamic response speed of the PLL is fast and the overshoot is within a reasonable range, and at the same time, ζ has little influence on the disturbance rejection ability of the PLL.

[0088] Embodiment 3

[0089] The analysis of the disturbance rejection ability of the PLL model includes: analyzing the selection of the crossover frequency ω c so that the PLL has better disturbance rejection ability;

[0090] When using a notch filter, there is an upper bandwidth BW OL in the open-loop transfer function of the PLL. To make the bandpass of the PLL not affected by the notch filter, therefore, when selecting ω c , ω c should be far from the notch frequency, generally selected at 1 / 4-1 / 5 of the notch frequency, such as 2π·20-2π·25 rad / s;

[0091] The disturbance closed-loop transfer function of the PLL is designed as:

[0092]

[0093] As Figure 4 and Figure 5 shown, let ζ = 0.707, g = 3.5, V +1 = 1. At this time, in the Bode diagrams of the disturbance transfer function and the open-loop transfer function of the PLL at different ω c , for the disturbance transfer function of the PLL with ω c being a constant and the open-loop transfer function, when ω c , the amplitude characteristics of the two are the same; when ω > ω c , the attenuation amounts of the two are almost the same; at the required ω c , the open-loop function can be used to replace the disturbance function for relevant calculations.

[0094] The analysis of the disturbance rejection ability of the PLL model includes: the amplitude characteristic analysis of G OL (s), as Figure 6 shown, in GOL (s) In the amplitude characteristic diagram, ω d is the lowest disturbance frequency, and atten ωd is the attenuation value of the lowest disturbance frequency.

[0095]

[0096] Substitute ω p = gω c and we get:

[0097] From this, we can obtain

[0098] From Equation (3.42), we can get ω c According to the pre-set suitable atten ωd is determined. ω d = 6ω = 2π·300 rad / s. Let ω c = 2π·25 rad / s, when g = 3.5, atten ωd = -32.29 dB, which can meet the PLL requirements, and ω c can be set to 2π·25 rad / s.

[0099] Substitute ω c , the design values of ζ and g are as follows: ω c = 2π·25 rad / s, ζ = 0.707, g = 3.5. From this, the parameters of the PLL can be further designed, the cut-off frequency ω p = gω c = 2π·87.5 rad / s.

[0100] In summary, although the present invention has been disclosed above with preferred embodiments, the above preferred embodiments are not intended to limit the present invention. Those of ordinary skill in the art can make various modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A method for analyzing the dynamic response of a phase-locked loop under distorted voltage of an island microgrid, characterized in that: include: The phase-locked loop has a PLL model under distorted voltage. The stability margin, dynamic response and anti-interference ability of the PLL model are analyzed to obtain the steady-state performance parameters under distorted voltage.

2. The method for analyzing the dynamic response of a phase-locked loop under distorted voltage of an island microgrid according to claim 1 is characterized in that: The stability margin analysis of the PLL model includes: The open-loop transfer function of the PLL model is designed as Among them, ω z is the turning frequency, and ω z =k i / k p ; Based on the above formula (1), the PLL phase margin PM is: PM=φ z +φ p (2); in, And the crossing frequency For PM to ω c When we take the partial derivative and make the result zero, we get: At the same time, combining equation (2) we can get: From formula (4), we can get that when ω p and ω z When is a fixed value, When , the PM of PLL is the largest; Among them, let ω p =g 2 ω z , g is a constant, and from formula (4) we can get: From equation (5), we can get that the parameters of PLL are g and ω c Determine, combine equation (2) and (5) to get: When the phase margin of the function curve of equation (6) is selected between 45° and 70°, the stability of the PLL is better, and at this time g∈(2.4,5.6); when g=3.5, PM=58.

11.

3. The method for analyzing the dynamic response of a phase-locked loop under distorted voltage of an island microgrid according to claim 2 is characterized in that: The dynamic response analysis of the PLL model includes: when the phase changes suddenly or the frequency jumps, in order to obtain the minimum stabilization time, the relevant parameter design is performed; by combining equation (1) and equation (5), the PLL open-loop transfer function is obtained as follows: From equation (7), we can get the PLL open-loop transfer function G OL (s) is a second-order function with two poles at the origin, so the PLL can lock the phase information without error when the phase changes suddenly or the frequency jumps; The error transfer function is Assume g = 2ζ + 1, the above formula is simplified to: When the phase changes suddenly (Δθ), the error signal is transformed by Laplace transform to: Similarly, when the frequency jumps (Δω), the error signal is transformed by Laplace to: In the time domain, equations (10) and (11) are expressed as follows: From equations (12) and (13), it can be obtained that when the phase changes suddenly or the frequency jumps, the dynamic response of the PLL is related to the crossover frequency ωc under any damping coefficient ζ: c The larger the value, the faster the dynamic response speed of the PLL. c When the value is larger, the anti-interference ability of PLL will decrease. c When using the UPS, it is necessary to balance the dynamic response speed and anti-interference ability; In the dynamic response phase mutation and frequency jump of PLL at different ζ, the response of PLL should balance the response speed and overshoot; when ζ is small, the dynamic response speed of PLL is fast but the overshoot is large; conversely, the dynamic response speed is slow but the overshoot is small; the selection range of damping coefficient ζ is 0.6~1, at this time, the dynamic response speed of PLL is fast and the overshoot is within the appropriate range, and ζ has little effect on the anti-interference ability of PLL.

4. The method for analyzing the dynamic response of a phase-locked loop under distorted voltage of an island microgrid according to claim 3 is characterized in that: The PLL model anti-interference ability analysis includes: c The selection is analyzed to make the PLL have better anti-interference ability; When using a notch filter, the open-loop transfer function of the PLL has an upper bandwidth BW OL In order to make the passband of PLL not affected by the notch filter, we select ω c ,ω c It should be far away from the notch frequency, generally selected at 1 / 4 to 1 / 5 of the notch frequency, such as 2π·20 to 2π·25rad / s; The perturbation closed-loop transfer function of the PLL is designed as: Assume ζ = 0.707, g = 3.5, V +1 =1, at this time, PLL at different ω c In the Bode diagram of the disturbance transfer function and the open-loop transfer function, for ω c The perturbation transfer function of the PLL with a constant is the same as the open-loop transfer function at ω c When ω>ω, the amplitude characteristics of the two are the same; when ω>ω c When ω c The open-loop function can be used to replace the disturbance function for relevant calculations.

5. The method for analyzing the dynamic response of a phase-locked loop under distorted voltage of an island microgrid according to claim 4 is characterized in that: PLL model anti-interference ability analysis includes: G OL (s) Amplitude characteristics analysis, ω d is the minimum disturbance frequency, atten ωd is the attenuation value of the lowest disturbance frequency; ω p =gω c Bring in: From this we can get: From formula (17), we can get: c According to the pre-set suitable atten ωd For determination, ω d =6ω=2π·300rad / s, let ω c =2π·25rad / s, g=3.5, atten ωd =-32.29dB, which can meet the PLL requirements, ω c It can be set to 2π·25rad / s; ω c The design values ​​of , ζ and g are as follows: c =2π·25rad / s, ζ=0.707, g=3.5, from which the parameters of PLL can be further designed. Cut-off frequencyω p =gω c =2π·87.5rad / s.

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