Pulse switch parameter updating method, electronic equipment and medium

Abstract

The invention discloses a pulse switch parameter updating method, electronic equipment and a medium. The pulse switch parameter updating method comprises the following steps: setting a switch period reference value; obtaining a current switching period, a first duty ratio of the first PWM signal and a second duty ratio of the second PWM signal; respectively judging a first action and a second action according to a first duty ratio of the first PWM signal and a second duty ratio of the second PWM signal, and setting a first mark position; when the first flag bit is detected, the switching period, the duty ratio of the first PWM signal, the duty ratio of the second PWM signal, the first action corresponding to the first PWM signal and the second action corresponding to the second PWM signal are updated at the next target time point through timing of a cycle timer; wherein the target time point is a time point corresponding to the trough of the triangular carrier of the carrier counter of the PWM wave in the current switching period; and after updating is completed, the first flag bit is set, and the cycle timer is reset.

Description

Technical Field

[0001] This application relates to the field of power electronics control technology, and particularly to a method for updating pulse switch parameters, an electronic device, and a medium. Background Art

[0002] Pulse Width Modulation (PWM) is a technology for controlling analog output by adjusting the pulse width of a digital signal. Its core principle is to use a square wave with a fixed frequency as the carrier wave, and change the average voltage or power of the signal by adjusting the duration of the high-level period (duty cycle) within each cycle. For example, when the duty cycle is 50%, the output average voltage is half of the power supply voltage. Currently, especially in variable-frequency PWM control systems, the pulse width modulation technology has been widely applied. How to reasonably configure and apply the PWM module is crucial for variable-frequency control.

[0003] Chinese Patent CN111146927A discloses a method for updating variable-frequency PWM control switch parameters, a PWM control method, and a PWM controller. This method solves the problem of incorrect pulses in timing by increasing an intermediate value, first updating to the intermediate value of the switch parameters, and then updating from the intermediate value of the switch parameters to the switch parameters to be updated after a sampling calculation period. However, this method can only solve the situation of incorrect pulses caused by deviations in chip execution time, and cannot effectively solve the situation of incorrect pulses caused by other reasons.

[0004] In the prior art, in variable-frequency interleaved PWM applications, there are problems such as Figure 1 shown similar incorrect pulse problems. Chinese Patent CN117938130A discloses a method for updating PWM control switch parameters, as Figure 2 shown. That is, update the first duty cycle of the first PWM signal at the time point corresponding to the peak of the triangular carrier wave of the carrier counter of the PWM wave in the current switching cycle, and update the second duty cycle of the second PWM signal and the switching cycle PRD at the time point corresponding to the valley of the triangular carrier wave of the carrier counter of the PWM wave in the current switching cycle; thus avoiding abnormal pulse widths of the first PWM signal and the second PWM signal output. To achieve that when the related device needs variable frequency, whether the period of the PWM wave is increased or decreased, incorrect pulse widths do not occur.

[0005] However, when adjusting the pulse width by the PWM control switch parameter update method disclosed in Chinese Patent CN117938130A, that is, updating the first duty cycle of the first PWM signal at the time point corresponding to the peak of the triangular carrier wave in the current switching cycle, and updating the second duty cycle of the second PWM signal and the switching cycle PRD at the time point corresponding to the trough of the triangular carrier wave of the carrier counter of the PWM wave in the current switching cycle, it will result in a slow actual switch update speed. Specifically, to update the first duty cycle of the first PWM signal, it is necessary to wait for the carrier counter of the PWM wave to run to the time point corresponding to the peak of the triangular carrier wave in the next cycle before the value can be written into the active register to successfully update.

[0006] At the same time, when adjusting the pulse width by the PWM control switch parameter update method disclosed in Chinese Patent CN117938130A, that is, updating the first duty cycle of the first PWM signal at the time point corresponding to the peak of the triangular carrier wave in the current switching cycle, and updating the second duty cycle of the second PWM signal and the switching cycle PRD at the time point corresponding to the trough of the triangular carrier wave of the carrier counter of the PWM wave in the current switching cycle, if the switching cycle PRD, the first duty cycle of the first PWM signal, and the second duty cycle of the second PWM signal are not fully updated, it is easy to appear as Figure 3 the non-target level shown. Especially when the duty cycle exceeds 50%, due to the random loading of the switching cycle PRD, the first duty cycle of the first PWM signal, the second duty cycle of the second PWM signal, the first action of the first PWM signal, and the second action of the second PWM signal, the effect is even worse, and error pulses are extremely likely to appear. Specifically, the second duty cycle of the second PWM signal is obtained by subtracting the first duty cycle of the first PWM signal from the switching cycle PRD. When the switching cycle PRD, the first duty cycle of the first PWM signal, and the second duty cycle of the second PWM signal change greatly, the second duty cycle of the second PWM signal should become very small. However, due to the problem of the program execution timing, such as executing the instruction to update the switching cycle PRD first at the zero crossing point and not having time to execute the instruction to update the second duty cycle of the second PWM signal, the system still executes the original second duty cycle of the second PWM signal at the zero crossing point. Since the value of the original second duty cycle of the second PWM signal is very large, it is easy to cause a high level with a duty cycle higher than 50%. Therefore, in variable frequency applications, this solution is extremely likely to cause system instability problems, resulting in abnormal operation of power electronic devices. And due to the limitations of the method, corresponding actions cannot be carried out by reasonably planning the action register, and pulses exceeding 50% cannot be controlled. Summary of the Invention

[0007] Aiming at the deficiencies of the prior art, the embodiments of the present invention provide a pulse switch parameter update method, an electronic device, and a medium.

[0008] In a first aspect, an embodiment of the present invention provides a method for updating pulse switch parameters. The method is applied to an enhanced pulse width modulation module, which includes a first channel and a second channel. The first channel generates a first PWM signal, and the second channel generates a second PWM signal; a PWM wave is generated based on the first PWM signal and the second PWM signal; the method specifically includes the following steps: Set the switch period reference value; Obtain the current switch period PRD, the first duty cycle of the first PWM signal, and the second duty cycle of the second PWM signal; determine the first action corresponding to the first PWM signal according to the first duty cycle of the first PWM signal, determine the second action corresponding to the second PWM signal according to the second duty cycle of the second PWM signal, and set the first flag bit. When the first flag bit is detected, use a cyclic timer to time and update the switch period PRD, the duty cycle of the first PWM signal, the duty cycle of the second PWM signal, the first action corresponding to the first PWM signal, and the second action corresponding to the second PWM signal at the next target time point; wherein, the target time point is the time point corresponding to the trough of the triangular carrier wave of the carrier counter of the PWM wave in the current switch period; after the update is completed, set the first flag bit and clear the cyclic timer.

[0009] In a second aspect, an embodiment of the present invention provides a PWM control switch parameter update system. The system is applied to an enhanced pulse width modulation module, which includes a first channel and a second channel. The first channel generates a first PWM signal, and the second channel generates a second PWM signal; a PWM wave is generated based on the first PWM signal and the second PWM signal; the system includes: A setting module for setting the switch period reference value; An obtaining module for obtaining the current switch period PRD, the first duty cycle of the first PWM signal, and the second duty cycle of the second PWM signal; determining the first action corresponding to the first PWM signal according to the first duty cycle of the first PWM signal, determining the second action corresponding to the second PWM signal according to the second duty cycle of the second PWM signal, and setting the first flag bit. An update module for, when the first flag bit is detected, using a cyclic timer to time and update the switch period PRD, the duty cycle of the first PWM signal, the duty cycle of the second PWM signal, the first action corresponding to the first PWM signal, and the second action corresponding to the second PWM signal at the next target time point; wherein, the target time point is the time point corresponding to the trough of the triangular carrier wave of the carrier counter of the PWM wave in the current switch period; after the update is completed, set the first flag bit and clear the cyclic timer.

[0010] In a third aspect, an embodiment of the present invention provides an electronic device, including a memory and a processor, where the memory is coupled to the processor; wherein, the memory is used to store program data, and the processor is used to execute the program data to implement the above-mentioned pulse switch parameter update method.

[0011] In a fourth aspect, an embodiment of the present invention provides a computer-readable storage medium, on which a computer program is stored, and when the program is executed by a processor, the above-mentioned pulse switch parameter update method is implemented.

[0012] In a fifth aspect, an embodiment of the present invention provides a computer program product, including a computer program / instructions, and when the computer program / instructions are executed by a processor, the above-mentioned pulse switch parameter update method is implemented.

[0013] Compared with the prior art, the beneficial effects of the present invention are as follows: The present invention provides a method for updating pulse switch parameters. When a first flag bit is detected, a cyclic timer is used for timing to update the switching period PRD, the duty cycle of the first PWM signal, the duty cycle of the second PWM signal, the first action corresponding to the first PWM signal, and the second action corresponding to the second PWM signal at the next target time point; wherein, the target time point is the time point corresponding to the trough of the triangular carrier wave of the carrier counter of the PWM wave in the current switching period; after the update is completed, the first flag bit is set, and the cyclic timer is cleared; thus avoiding abnormal pulses and solving the problem caused by insufficient update of the duty cycle, and at the same time solving the problem of slow actual switch update speed. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following drawings are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0015] Figure 1 It is a waveform diagram of a PWM wave during the update process of PWM control switch parameters in the related art; Figure 2 It is another waveform diagram of a PWM wave during the update process of PWM control switch parameters in the related art; Figure 3 It is another waveform diagram of a PWM wave during the update process of PWM control switch parameters in the related art; Figure 4 It is a waveform diagram of a PWM wave during the update process of PWM control switch parameters provided by an embodiment of the present invention; Figure 5Flowchart of a method for updating pulse switch parameters provided by an embodiment of the present invention; Figure 6 Schematic structural diagram of an enhanced pulse width modulation module provided by an embodiment of the present invention; Figure 7 Schematic working diagram of an enhanced pulse width modulation module provided by an embodiment of the present invention; Figure 8 Schematic diagram of an electronic device provided by an embodiment of the present invention. Detailed implementation manners

[0016] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0017] It should be noted that, without conflict, the features in the following embodiments and implementation manners can be combined with each other.

[0018] This embodiment provides a PWM control circuit. The PWM control circuit outputs two PWM signals, namely a first PWM signal and a second PWM signal. Among them, the first PWM signal and the second PWM signal are interleaved and modulated, and the rising edge of the first PWM signal leads the rising edge of the second PWM signal by a preset angle, that is, a dynamic phase offset amount is established between the first PWM signal and the second PWM signal. That is, through the phase shift modulation technology, the trigger edge of the first PWM signal is advanced by a set phase angle compared with the second PWM signal. The PWM control circuit has a dynamic phase compensation mechanism, which can adjust the duty cycle phase parameter and the working cycle duration in real time, so that the phase and period of the output PWM signal can be dynamically changed, realizing the online reconstruction of the output waveform.

[0019] Further, the PWM control circuit includes a period register containing PWM period values, a comparator, an action limiter, and a PWM counter. The period register is used to set the periods of the first PWM signal and the second PWM signal. Specifically, the period register uses a shadow register mechanism to store the reference period value T_base of the two PWM signals, automatically loads the pre-stored period parameters when the count value is equal to 0, updates the period accuracy up to ±1.5 ns, and at the same time, this period register supports an asynchronous update mode. The comparator is used to compare the PWM period value with the PWM count value to provide a key comparison result for subsequent operations. The action limiter is used to receive the comparison value output by the comparator, compare the comparison value with the count value, and limit the PWM signal. According to the comparison result, the PWM signal is effectively limited to ensure that the PWM signal fluctuates within a reasonable range. It is particularly noteworthy that when the PWM count value is zero, at this time, it is necessary to update the PWM period value, reset the duty cycles of the first PWM signal and the second PWM signal, and accurately and orderly update the actions corresponding to the first PWM signal and the second PWM signal. Thus, it is ensured that the entire PWM control circuit can operate continuously, stably, and efficiently, accurately output the PWM signal that meets the expectations, and thus achieve precise control of related devices or systems.

[0020] This embodiment provides an enhanced pulse width modulation module. Figure 6 It is a schematic structural diagram of an enhanced pulse width modulation module of this embodiment, as Figure 6 and Figure 7 shown. This enhanced pulse width modulation module includes: a time reference sub-module 01, a comparison function sub-module 02, and an action limiting sub-module 03.

[0021] Among them, the time reference sub-module 01 includes a time reference register, and the time reference register includes a current register and a mapping register. The comparison function sub-module 02 includes a first comparison register and a second comparison register; the first comparison register is a CMPA register (Compare Accumulator A), the second comparison register is a CMPB register (Compare Accumulator B), the CMPA register includes a CMPA current register and a CMPA mapping register, and the CMPB register includes a CMPB current register and a CMPB mapping register. The action limiting sub-module 03 includes a first action limiting register and a second action limiting register; the first action limiting register is an AQA register, and the second action limiting register is an AQB register.

[0022] In the embodiment of the present application, by reasonably planning the switch action value, the modulation of the duty cycle can be made wider, and a pulse width with a duty cycle exceeding 50% can be modulated. As Figure 4The illustrated example is a schematic diagram of pulse width modulation with a duty cycle less than 50% transitioning to a duty cycle greater than 50%.

[0023] Specifically, in this example, when controlling with a duty cycle less than 50%, the A channel (i.e., the first PWM signal) drives to generate a rising edge of the drive at point C, and a falling edge of the drive is generated when the counter counts up to the first duty cycle CMPA_Old point of the old first PWM signal. The B channel (i.e., the second PWM signal) drives to generate a rising edge of the drive at point B, and a falling edge of the drive is generated when the counter counts down to the second duty cycle CMPB_Old point of the old second PWM signal. When controlling with a duty cycle greater than 50%, the A channel drives to generate a rising edge of the drive at point C, and a falling edge of the drive is generated when the counter counts down to the first duty cycle CMPA_New point of the new first PWM signal. The B channel drives to generate a rising edge of the drive at point B, and a falling edge of the drive is generated when the counter counts up to the second duty cycle CMPB_New point of the new second PWM signal.

[0024] In some examples, due to poor planning of the update strategy, when controlling with a duty cycle exceeding 50%, such as when switching from a duty cycle exceeding 50% to a duty cycle less than 50%, the duty cycle should become very small at this time. However, due to issues with the program execution timing, such as executing the instruction to update the switching period PRD at the zero crossing point first, and not having enough time to execute the instruction to update the first duty cycle of the first PWM signal and the first action of the first PWM signal, it is easy to have a high level with a duty cycle higher than 50% for a long time.

[0025] Similarly, if the instruction to update the switching period PRD is executed first at the zero crossing point, and there is not enough time to execute the instruction to update the second duty cycle of the second PWM signal and the second action of the second PWM signal, it is also easy to have a high level with a duty cycle higher than 50%.

[0026] Moreover, when controlling with a duty cycle exceeding 50%, such as when switching from a duty cycle exceeding 50% to a duty cycle less than 50% and the first and second PWM signals need to be updated simultaneously, due to the priority of the action register, they cannot be updated simultaneously, so it is easy for a certain PWM signal to have a high level with a duty cycle higher than 50% for a long time.

[0027] To solve the above problems, based on the action update strategy mentioned above, this example proposes a new method of passing through the switching period PRD, the first duty cycle of the first PWM signal, and the second duty cycle of the second PWM signal, and setting the update flag after determining the first action of the first PWM signal and the second action of the second PWM signal according to the duty cycle, and writing a loop near the zero crossing point, i.e., point C, and fully loading the above parameters in the loop.

[0028] Such as Figure 5As shown, this embodiment provides a method for updating pulse switch parameters. The method is applied to an enhanced pulse width modulation module. By continuously updating the value of the mapped register in the comparison register, and in the existing flyback quasi-resonant control technology, calculate the new switching period PRD, the first duty cycle of the first PWM signal, and the second duty cycle of the second PWM signal. After determining the first action of the first PWM signal and the second action of the second PWM signal according to the duty cycles, set the update flag bit, write in a loop near the zero crossing point, and fully load the above parameters in the loop to ensure that the value in the mapped register is loaded into the current register. Among them, the enhanced pulse width modulation module includes a first channel and a second channel. The first channel generates a first PWM signal, and the second channel generates a second PWM signal. Generate a PWM wave according to the first PWM signal and the second PWM signal. The method for updating pulse switch parameters includes the following steps: Step S1, set the switching period reference value.

[0029] Specifically, the enhanced pulse width modulation module includes a time reference sub-module. Among them, the time reference sub-module includes a time reference period register and a time reference counter. The time reference period register includes a current register and a mapped register. Use the value in the current register as the switching period reference value to complete the initialization.

[0030] Step S2, obtain the current switching period PRD, the first duty cycle of the first PWM signal, and the second duty cycle of the second PWM signal; determine the first action corresponding to the first PWM signal according to the first duty cycle of the first PWM signal, determine the second action corresponding to the second PWM signal according to the second duty cycle of the second PWM signal, and set the first flag bit.

[0031] Step S3, when the first flag bit is detected, use the loop timer to time to update the switching period PRD, the duty cycle of the first PWM signal, the duty cycle of the second PWM signal, the first action corresponding to the first PWM signal, and the second action corresponding to the second PWM signal at the next target time point C; where the target time point C is the time point corresponding to the trough of the triangular carrier wave of the carrier counter of the PWM wave in the current switching period; after the update is completed, set the first flag bit and clear the loop timer.

[0032] Specifically, as Figure 4 shown, in the first coordinate system, the abscissa represents time, and the ordinate represents the value of the carrier counter; as Figure 4 shown in channel A, shows a schematic diagram of the first PWM signal; as Figure 4As shown in Channel B in , a schematic diagram of the second PWM signal is presented. Set the current switching period as the old switching period PRD_Old, set the current duty cycle of the first PWM signal as the first duty cycle CMPA_Old of the old first PWM signal, set the current duty cycle of the second PWM signal as the second duty cycle CMPB_Old of the old second PWM signal, set the current action of the first PWM signal as the corresponding first action AQA_Old of the old first PWM signal, set the current action of the second PWM signal as the corresponding second action AQB_Old of the old second PWM signal, set the new period calculated by the flyback quasi-resonant as the new switching period PRD_New, set the new duty cycle of the first PWM signal as the first duty cycle CMA_New of the new first PWM signal, set the current duty cycle of the second PWM signal as the second duty cycle CMB_New of the new second PWM signal, set the new action of the first PWM signal as the corresponding first action AQA_New of the new first PWM signal, set the current action of the second PWM signal as the corresponding second action AQB_New of the new second PWM signal. When the time base counter equals zero, theoretically, the updated normal operation can update the period value PRD, the duty cycle of the first PWM signal, the duty cycle of the second PWM signal, the action of the first PWM signal, or the action of the second PWM signal at any time point among A, B, and C. Among them, time points A and B are the time points corresponding to the peaks of the triangular carrier wave, and time point C is the time point corresponding to the valley of the triangular carrier wave.

[0033] In this embodiment, through the above steps S1 to S3, the cycle value PRD, the duty cycle of the first PWM signal, the duty cycle of the second PWM signal, the action of the first PWM signal, and the action of the second PWM signal are uniformly and fully updated at the target time point C. By adjusting the update order of the switch parameters, this embodiment ensures that no error pulses are generated during the frequency conversion process and guarantees that there are no abnormalities in the PWM output drive after the update. Specifically, when the flyback quasi-resonant control calculates a new set of updated switch cycle values, for the switch cycle PRD, the first duty cycle of the first PWM signal, and the second duty cycle of the second PWM signal, after determining the first action of the first PWM signal and the second action of the second PWM signal based on the duty cycle, the flag bit is set. When the first flag bit is detected and the switch cycle is updated at the next C time point, the cyclic timer is entered, and at the same time, the switch cycle PRD, the duty cycle of the first PWM signal, and the duty cycle of the second PWM signal are updated. And the actions of the first PWM signal and the second PWM signal are sequentially updated. After the full update is completed, the first flag bit is set, and the cyclic timer is cleared. The C time point is the time point corresponding to the trough of the triangular carrier wave of the PWM wave carrier counter under the current switch cycle. At this time, the second duty cycle of the new second PWM signal should be equal to the switch cycle PRD minus the first duty cycle of the first PWM signal, thus naturally avoiding the problems caused by abnormal pulses and insufficient update of the duty cycle. And when the time point corresponding to the trough of the triangular carrier wave of the PWM wave carrier counter under the current switch cycle, the switch cycle PRD, the first duty cycle of the first PWM signal, and the second duty cycle of the second PWM signal are fully updated simultaneously, avoiding the problem of "to update the first duty cycle of the first PWM signal, it is necessary to wait until the time point corresponding to the peak of the triangular carrier wave of the next cycle of the PWM wave carrier counter to write the value into the active register to successfully update", so the actual switch update speed will be faster. And due to the full update of the AQ register within the loop, the problem of "the high level exceeding the control expected duty cycle and thus exceeding the control expectation due to the sequential update of the AQ register and the failure to update the action register in time" is avoided.

[0034] Certainly, in some of these embodiments, the enhanced pulse width modulation module is a DSP, a CPU, or a microcontroller. The enhanced pulse width modulation module adopts an up-down counting mode to generate a symmetric triangular carrier wave. Further, the triangular carrier wave is an isosceles triangular wave.

[0035] In some of these embodiments, the pulse switch parameter update method further includes: while the duty cycle of the second PWM signal is updated, setting the current switch cycle value to the switch cycle reference value at the second time point. That is, when the value of the PWM wave carrier counter is zero, i.e., at the time point corresponding to the trough of the triangular carrier wave of the PWM wave carrier counter under the current switch cycle, the current switch cycle value is set to the switch cycle reference value to complete the frequency conversion.

[0036] On the other hand, an embodiment of the present invention further provides a PWM control switch parameter update system, which is applied to an enhanced pulse width modulation module. The enhanced pulse width modulation module includes a first channel and a second channel. The first channel generates a first PWM signal, and the second channel generates a second PWM signal; a PWM wave is generated according to the first PWM signal and the second PWM signal; the system includes: A setting module, configured to set a reference value of the switching period; An acquisition module, configured to acquire the current switching period PRD, the first duty cycle of the first PWM signal, and the second duty cycle of the second PWM signal; judge the first action corresponding to the first PWM signal according to the first duty cycle of the first PWM signal, judge the second action corresponding to the second PWM signal according to the second duty cycle of the second PWM signal, and set the first flag bit; An update module, configured to, when the first flag bit is detected, time through a cycle timer to update the switching period PRD, the duty cycle of the first PWM signal, the duty cycle of the second PWM signal, the first action corresponding to the first PWM signal, and the second action corresponding to the second PWM signal at the next target time point; wherein, the target time point is the time point corresponding to the trough of the triangular carrier wave of the carrier counter of the PWM wave in the current switching period; after the update is completed, set the first flag bit and clear the cycle timer.

[0037] Regarding the system in the above embodiment, the specific manners in which each module performs operations have been described in detail in the embodiment related to the method, and will not be elaborated herein.

[0038] For the system embodiment, since it basically corresponds to the method embodiment, the relevant parts can refer to the partial description of the method embodiment. The system embodiments described above are only illustrative. The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place, or may be distributed to multiple network units. Some or all of the modules can be selected according to actual needs to achieve the purpose of the solution of the present application. Those of ordinary skill in the art can understand and implement it without creative work.

[0039] Correspondingly, the present application further provides an electronic device, including: one or more processors; a memory for storing one or more programs; when the one or more programs are executed by the one or more processors, the one or more processors implement the pulse switch parameter update method as described above. As Figure 8As shown in the figure, it is a hardware structure diagram of any device with data processing capabilities where the pulse switch parameter update method provided by the embodiment of the present invention is located. In addition to Figure 8 the processor, memory, and network interface shown, any device with data processing capabilities where the device in the embodiment is located usually includes other hardware according to the actual functions of the device, which will not be elaborated here.

[0040] Correspondingly, the present application also provides a computer-readable storage medium, on which computer instructions are stored. When the instructions are executed by the processor, the pulse switch parameter update method as described above is implemented. The computer-readable storage medium may be an internal storage unit of any device with data processing capabilities described in any of the foregoing embodiments, such as a hard disk or memory. The computer-readable storage medium may also be an external storage device, such as a plug-in hard disk, a Smart Media Card (SMC), an SD card, a Flash Card, etc. equipped on the device. Further, the computer-readable storage medium may also include both the internal storage unit of any device with data processing capabilities and the external storage device. The computer-readable storage medium is used to store the computer program and other programs and data required by any device with data processing capabilities, and may also be used to temporarily store the data that has been output or will be output.

[0041] After considering the specification and practicing the content disclosed herein, those skilled in the art will readily think of other implementation schemes of the present application. The present application is intended to cover any variations, uses, or adaptations of the present application, which follow the general principles of the present application and include the common general knowledge or conventional technical means in the technical field not disclosed in the present application. The specification and the embodiments are only regarded as exemplary.

[0042] It should be understood that the present application is not limited to the exact structure already described and shown in the drawings, and various modifications and changes can be made without departing from its scope.

Claims

1. A pulse switch parameter updating method, characterized in that: The method is applied to an enhanced pulse width modulation module, the enhanced pulse width modulation module includes a first channel and a second channel, the first channel generates a first PWM signal, and the second channel generates a second PWM signal; a PWM wave is generated according to the first PWM signal and the second PWM signal; the method specifically includes the following steps: Set the switching cycle reference value; Obtaining the current switching period PRD, the first duty cycle of the first PWM signal, and the second duty cycle of the second PWM signal; determining a first action corresponding to the first PWM signal according to the first duty cycle of the first PWM signal, determining a second action corresponding to the second PWM signal according to the second duty cycle of the second PWM signal, and setting a first flag; When the first flag is detected, the cyclic timer is used to update the switching period PRD, the duty cycle of the first PWM signal, the duty cycle of the second PWM signal, the first action corresponding to the first PWM signal, and the second action corresponding to the second PWM signal at the next target time point; wherein the target time point is the time point corresponding to the trough of the triangular carrier of the PWM wave carrier counter in the current switching period; after the update is completed, the first flag is set and the cyclic timer is cleared.

2. A pulse switch parameter updating method according to claim 1, characterized in that: The process of setting the switching cycle reference value includes: The enhanced pulse width modulation module includes a time reference submodule; the time reference submodule includes a time reference period register and a time reference counter, and the time reference period register includes a current register and a mapping register; The value in the current register is used as the switching cycle reference value.

3. A pulse switch parameter updating method according to claim 1, characterized in that: The process of obtaining the current switching period PRD, the first duty cycle of the first PWM signal and the second duty cycle of the second PWM signal includes: The current switching period PRD, the first duty cycle of the first PWM signal, and the second duty cycle of the second PWM signal are calculated by the flyback quasi-resonance control method.

4. A pulse switch parameter updating method according to claim 1, characterized in that: The pulse switch parameter updating method further includes: After updating the switching period PRD, the duty cycle of the first PWM signal, the duty cycle of the second PWM signal, the first action corresponding to the first PWM signal, and the second action corresponding to the second PWM signal, the updated duty cycle of the second PWM signal is equal to the difference between the switching period PRD and the duty cycle of the first PWM signal.

5. A pulse switch parameter updating method according to claim 1, characterized in that: The pulse switch parameter updating method further includes: When the duty cycle is controlled to be less than 50%, the first PWM signal generates a rising edge of driving at the target time point, and generates a falling edge of driving when the counter counts up to the first duty cycle CMPA_Old point of the old first PWM signal; the second PWM signal generates a rising edge of driving at the second time point, and generates a falling edge of driving when the counter counts down to the second duty cycle CMPB_Old point of the old second PWM signal, and the second time point is the time point corresponding to the peak of the triangular carrier of the carrier counter of the PWM wave in the current switching cycle.

6. A pulse switch parameter updating method according to claim 1, characterized in that: The pulse switch parameter updating method further includes: When the duty cycle is controlled to be greater than 50%, the first PWM signal generates a rising edge of driving at the target time point, and generates a falling edge of driving when the counter counts down to the first duty cycle CMPA_New point of the new first PWM signal; the second PWM signal generates a rising edge of driving at the second time point, and generates a falling edge of driving when the counter counts up to the second duty cycle CMPB_New point of the new second PWM signal, and the second time point is the time point corresponding to the peak of the triangular carrier of the carrier counter of the PWM wave in the current switching cycle.

7. A PWM control switch parameter update system, characterized in that: The system is applied to an enhanced pulse width modulation module, the enhanced pulse width modulation module comprises a first channel and a second channel, the first channel generates a first PWM signal, and the second channel generates a second PWM signal; Generate a PWM wave according to the first PWM signal and the second PWM signal; the system comprises: A setting module, used to set a reference value of a switching cycle; an acquisition module, used for acquiring a current switching period PRD, a first duty cycle of a first PWM signal, and a second duty cycle of a second PWM signal; determining a first action corresponding to the first PWM signal according to the first duty cycle of the first PWM signal, determining a second action corresponding to the second PWM signal according to the second duty cycle of the second PWM signal, and setting a first flag; An update module is used to, when a first flag is detected, time the cycle timer to update the switching period PRD, the duty cycle of the first PWM signal, the duty cycle of the second PWM signal, the first action corresponding to the first PWM signal, and the second action corresponding to the second PWM signal at the next target time point; wherein the target time point is the time point corresponding to the trough of the triangular carrier of the PWM wave carrier counter in the current switching period; after the update is completed, the first flag is set and the cycle timer is cleared.

8. An electronic device, comprising a memory and a processor, characterized in that: The memory is coupled to the processor; wherein the memory is used to store program data, and the processor is used to execute the program data to implement the pulse switch parameter updating method described in any one of claims 1-6 above.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the program is executed by a processor, the pulse switch parameter updating method as described in any one of claims 1 to 6 is implemented.

10. A computer program product comprising a computer program / instructions, characterized in that When the computer program / instruction is executed by a processor, the pulse switch parameter updating method described in any one of claims 1-6 is implemented.

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