A radio comprehensive detector

Abstract

The present invention relates to the field of radio testing technology, and particularly relates to a radio integrated detector, comprising a main control part, a host computer part, and a radio frequency part; the main control part is collaboratively constituted by an MCU and a FPGA, the MCU communicates with the host computer via a communication interface, the FPGA is connected to the radio frequency part via a parallel bus, and is configured with a PS mode program loading interface; the radio frequency part adopts a zero intermediate frequency software radio architecture, including a receiving channel and a transmitting channel; the host computer part comprises a touch screen, and is connected to a main control board via a communication interface. The present invention can simulate communication and navigation signals of aircraft, ships, towers, and satellites, and complete functional tests of 17 types of radio airborne equipment, such as shortwave / ultra-shortwave radio stations, microwave / instrument landing systems, and radio altimeters, thereby achieving the field maintenance goals of single-person carrying, single-person operation, and single-person flight, and significantly improving the versatility, efficiency, and environmental adaptability of aircraft maintenance.

Description

Technical Field

[0001] The invention relates to the technical field of radio testing, in particular to a radio comprehensive detector. Background Art

[0002] With the rapid evolution of aviation equipment and the increasing intensity of combat-oriented training, maintenance efficiency has become a key factor impacting aircraft mission execution capabilities. Currently, testing of aviation radio equipment primarily relies on traditional ground support equipment, but these devices suffer from significant design limitations: poor versatility necessitates specialized instrumentation for different aircraft models, single-function systems struggle to cover complex testing requirements, complex hardware architectures result in bulky and heavy equipment, and cumbersome operational procedures rely heavily on manual intervention. These issues severely hinder the agility of field maintenance, making rapid deployment and efficient testing difficult, especially in emergency scenarios. Summary of the Invention

[0003] In order to solve the problems of the prior art, the present invention proposes a radio integrated detector, which realizes the field maintenance goals of single-person carrying, single-person operation, and single-person release, and significantly improves the versatility, efficiency and environmental adaptability of aircraft maintenance.

[0004] The present invention is achieved through the following technical solutions:

[0005] A radio integrated detector comprises a main control part, a host computer part and a radio frequency part;

[0006] The main control part is composed of MCU and FPGA. The MCU communicates with the host computer through a communication interface. The FPGA is connected to the radio frequency part through a parallel bus and is configured with a PS mode program loading interface.

[0007] The radio frequency part adopts a zero-IF software radio architecture, including a receiving channel and a transmitting channel;

[0008] The receiving channel includes a limiter, a preselection filter group, a digitally controlled attenuator, a low noise amplifier and a single-pole double-throw switch group in sequence; the preselection filter group is composed of filters in six independent frequency bands, which is used to suppress external interference signals in sections;

[0009] The single-pole double-throw switch group in the receiving channel divides the received signal into frequency band 1 and frequency band 2. Frequency band 1 is up-converted by the point frequency signal generated by phase-locked loop PLL1, and then demodulated by the IQ demodulator and the broadband signal of phase-locked loop PLL2 to generate the baseband IQ signal; frequency band 2 is directly input into the IQ demodulator for demodulation.

[0010] The transmitting channel includes an IQ modulator, a driving amplifier, a digitally controlled attenuator and a preselection filter group in sequence, and the transmitting and receiving channels share a preselection filter group of six independent frequency bands;

[0011] The input end of the IQ modulator in the transmitting channel receives the baseband IQ signal and modulates it with the broadband signal of the phase-locked loop PLL2 to generate an RF signal; the single-pole double-throw switch group divides the modulated RF signal into frequency band 1 and frequency band 2, wherein frequency band 1 is down-converted by the point frequency signal generated by the phase-locked loop PLL1, and frequency band 2 is directly passed to the driver amplifier and output through the pre-selection filter group;

[0012] The host computer part includes a touch screen, which is connected to the main control board through a communication interface.

[0013] Furthermore, the pre-selected filter group of the receiving channel covers the L-band and microwave band, the bandwidth of each independent frequency band filter matches the operating frequency band of the airborne equipment, and the filter switching is dynamically controlled by the MCU according to the test requirements.

[0014] Furthermore, the receiving channel and transmitting channel of the RF part are respectively connected to a dual-channel 14-bit ADC / DAC, the sampling rate of the ADC / DAC is not less than 40MHz, and the FPGA analyzes the phase and frequency information of the baseband signal through an amplitude threshold judgment algorithm.

[0015] Furthermore, the power module of the main control part includes an 8.4V rechargeable lithium battery, a 27V external DC interface, and a 3.3V, 1.5V, 1.1V, ±5V secondary power conversion circuit implemented by a TPS chip. The lithium battery power supply link is configured with an overvoltage / overcurrent protection circuit, and all secondary power supplies are independently powered by lithium batteries.

[0016] Furthermore, the interface module of the detector includes two antenna interfaces and two altimeter interfaces;

[0017] Multi-function multiplexing interface, integrating MCU program download, FPGA configuration loading and battery charging functions;

[0018] Expansion interface, two SPI communication pins and general IO port for external sensors.

[0019] Furthermore, the functional modules of the detector include a monitoring unit that monitors the power supply voltage, battery charge and RF signal power in real time and displays alarm information through a QT interface;

[0020] Test unit, including TACAN test, microwave landing test, heading test, automatic ship identification test, etc.;

[0021] The system setting unit configures the communication protocol encryption parameters, the touch screen response time and the three-level event interrupt priority, and the interrupt priority is implemented through a preemptive scheduling mechanism.

[0022] Furthermore, the phase-locked loops PLL1 and PLL2 of the radio frequency part generate a point-frequency signal and a broadband signal respectively, and the bandwidth of PLL2 covers the full operating frequency band of the IQ demodulator.

[0023] The present invention can simulate the communication and navigation signals of aircraft, ships, towers and satellites, and complete functional tests of 17 types of radio airborne equipment such as shortwave / ultra-shortwave radio stations, microwave / instrument landing systems, and radio altimeters, achieving the field maintenance goals of single-person carrying, single-person operation, and single-person flight, significantly improving the versatility, efficiency, and environmental adaptability of aircraft maintenance.

[0024] Beneficial effects of the present invention:

[0025] (1) The radio integrated detector proposed in the present invention adopts a zero-IF software radio architecture, omitting the traditional multi-stage frequency conversion circuit, and combining MCU+FPGA collaborative control and modular design to greatly simplify the radio frequency link, reducing the device volume by about 50% and the weight to the standard of a single person carrying it, meeting the requirements of rapid field deployment. The six-band independent frequency band division of the pre-selection filter group and the shared design of the transmit and receive channels reduce redundant hardware and further compress the space occupied;

[0026] (2) The present invention proposes a radio integrated detector, in which the receiving channel and the transmitting channel dynamically switch between frequency band 1 and frequency band 2 through a single-pole double-throw switch group. Combined with the coordinated work of the phase-locked loops PLL1 and PLL2, full frequency band compatibility from the L band to the microwave band is achieved. It can adapt to the 2 MHz to 6 GHz frequency band of aviation radio, covering the detection requirements of existing and new airborne equipment. The frequency band bandwidth of the pre-selected filter group is strictly matched with the airborne equipment. The filter switching is dynamically controlled by the MCU to avoid the poor compatibility problem of traditional equipment caused by the fixed frequency band.

[0027] (3) The present invention proposes a radio integrated tester that integrates a QT interface on the touch screen host computer, supports one-touch channel configuration, dynamic azimuth / distance simulation, and identification tone control, increases the automation level of the test process by 80%, reduces the number of manual operation steps to less than 3, and has an automatic signal generation function in continuous mode, replacing the traditional manual item-by-item configuration, significantly shortening the test time;

[0028] (4) The present invention proposes a radio integrated detector that supports comprehensive functions such as power measurement, sensitivity testing, and precision ranging. It uses FPGA to analyze the baseband signal phase and frequency information in real time, with a detection accuracy of ±0.1dB. The dual-channel 14-bit ADC / DAC ensures the fidelity of signal acquisition and generation, meeting the requirements of high dynamic range testing.

[0029] (5) The present invention proposes a radio integrated detector, in which key components (such as ADC / DAC, power management chip) adopt domestic solutions, combined with the multi-stage conversion and overvoltage / overcurrent protection circuit of the TPS series power chip to ensure the stable operation of the equipment in complex field environments. The encrypted communication protocol and the three-level event interrupt preemption mechanism prevent data leakage and system freezes, thereby reducing the failure rate. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0031] Figure 1 This is a system block diagram of a radio integrated detector proposed by the present invention;

[0032] Figure 2 The digital-to-analog / analog-to-digital conversion circuit principle of a radio integrated detector proposed by the present invention Figure 1 ;

[0033] Figure 3 The digital-to-analog / analog-to-digital conversion circuit principle of a radio integrated detector proposed by the present invention Figure 2

[0034] Figure 4 The power supply circuit principle of a radio integrated detector proposed by the present invention Figure 1 ;

[0035] Figure 5 The power supply circuit principle of a radio integrated detector proposed by the present invention Figure 2 ;

[0036] Figure 6 The power supply circuit principle of a radio integrated detector proposed by the present invention Figure 3 ;

[0037] Figure 7 The power supply circuit principle of a radio integrated detector proposed by the present invention Figure 4 ;

[0038] Figure 8 This is a schematic diagram of the MUC control circuit of a radio integrated detector proposed by the present invention;

[0039] Figure 9 The FPGA control circuit principle of a radio integrated detector proposed by the present invention Figure 1 ;

[0040] Figure 10 The FPGA control circuit principle of a radio integrated detector proposed by the present invention Figure 2 ;

[0041] Figure 11 The interface circuit principle of a radio integrated detector proposed by the present invention Figure 1 ;

[0042] Figure 12 The interface circuit principle of a radio integrated detector proposed by the present invention Figure 2 ;

[0043] Figure 13 This is a flow chart of audio decoding of a radio integrated detector proposed by the present invention;

[0044] Figure 14 This is a system block diagram of the radio frequency part of a radio integrated detector proposed by the present invention;

[0045] Figure 15 This is a system framework diagram of a radio integrated detector proposed by the present invention;

[0046] Figure 16 This is an operational response flow chart of a radio integrated detector proposed by the present invention;

[0047] Figure 17 This is an interface synchronization flow chart of a radio integrated detector proposed by the present invention;

[0048] Figure 18 This is a flow chart of event interrupt priority of a radio integrated detector proposed by the present invention. DETAILED DESCRIPTION

[0049] In order to make the objectives, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with examples and drawings. The exemplary embodiments of the present invention and their descriptions are only used to explain the present invention and are not intended to limit the present invention.

[0050] Example 1

[0051] refer to Figure 1 The radio integrated detector proposed in this embodiment includes a main control part, a radio frequency part and a host computer part.

[0052] The main control unit responds to the host computer's operating instructions and transmits necessary data to the host computer for display. It also collaborates with the radio frequency unit to complete signal transmission, reception, encoding and decoding. It mainly consists of wireless communication, digital-to-analog / analog-to-digital conversion, power supply, interface, control core, expansion slots, etc.

[0053] refer to Figure 2-Figure 3The digital-to-analog / analog-to-digital conversion includes two ADCs / DACs, and a dual-channel ADC / DAC is used to maximize the use of space. To ensure the quality and bandwidth of the transmitted and received signals, a 14-bit model with a frequency better than 40M is used. Since the battery power also needs to be collected using ADC, and since the accuracy requirement is not high, this embodiment uses the ADC provided by the MCU or FPGA.

[0054] refer to Figure 4-Figure 7 The power supply uses 8.4V rechargeable battery as the main power supply and 27V external DC as the external backup power supply. The secondary power supplies required by the detector are 3.3V, 1.5V, 1.1V, and ±5V. According to the required power and purpose, a universal voltage chip is selected to realize power conversion.

[0055] refer to Figures 8-10 The core control system is built using an MCU+FPGA architecture. The FPGA is primarily responsible for coordinating with the RF module to transmit and receive signals and modifying the corresponding signal content according to the MCU's instructions. The MCU is responsible for communicating with the host computer, monitoring the power supply, configuring the FPGA program, and performing switch control.

[0056] This embodiment also includes an interface module, which includes a multi-function multiplexing interface, two antenna interfaces and two altimeter interfaces, an expansion interface, and a reference Figure 11 The multi-function multiplexing interface is used to integrate MCU program download, FPGA configuration loading and battery charging functions. Figure 12 The expansion interface includes two SPI communication pins and a general IO port for connecting new modules.

[0057] The wireless communication in this embodiment adopts a split design. To meet the confidentiality requirements, wireless communication needs to be encrypted. In this embodiment, point-to-point communication is abandoned and a networked communication form is adopted for function expansion.

[0058] Wireless communication involves audio coding. In this embodiment, wireless communication headphones are used to implement audio coding and decoding. Figure 13 The encoding and decoding process is implemented through circuits.

[0059] The host computer part is used to cooperate with the functions of the corresponding buttons, switches and other controls on the program interface. It adopts IPS industrial-grade capacitive touch screen to provide users with a comfortable and efficient human-computer interaction experience. The human-computer interaction board mainly implements the Linux system and adopts the QT interface to realize human-computer interaction. It communicates with the MCU through the SPI bus internally and issues control instructions.

[0060] The RF part is built on zero-IF software radio technology. By simplifying the mixing link in the traditional superheterodyne architecture, the hardware circuit is streamlined and miniaturized. While maintaining high-precision signal processing capabilities, the RF part effectively reduces the physical space occupied, making it particularly suitable for applications that are sensitive to size and power consumption. The entire solution consists of key modules such as the controller, filter bank, RF switch, phase-locked loop (PLL), and direct digital frequency synthesizer (DDS). Through the collaborative work of digital and analog circuits, it completes the full process from RF signal reception, processing to transmission. Figure 14 .

[0061] In this embodiment, signal processing in the receive channel begins with limiting protection. The external RF signal first passes through a limiter, whose core function is to limit the signal amplitude to a safe operating range, preventing damage to subsequent circuit components due to overload or sudden high-power signals. The limited signal then enters a preselection filter bank consisting of six independent frequency bands, with a controller selecting the filter channel for the corresponding frequency band. Each filter is designed for a specific frequency range, effectively suppressing out-of-band interference signals while ensuring low-loss transmission of the desired signal.

[0062] The pre-filtered signal enters the digitally controlled attenuator, which adjusts the attenuation using a digital control signal, dynamically adjusting the gain of the receiving channel. The controller automatically adjusts the attenuation value based on signal strength, ensuring effective amplification of small signals while preventing amplifier saturation caused by large signals. This allows the system to adapt to input signals of varying strengths and maintain stable signal processing quality. The attenuated signal is then initially amplified by a low-noise amplifier, boosting the strength of the weak signal and providing sufficient signal amplitude for subsequent demodulation. The amplifier's low noise characteristics ensure that the signal-to-noise ratio does not significantly degrade during the amplification process.

[0063] To meet the processing requirements of broadband signals, the system has set a frequency band switch at the demodulation front end. When the input signal belongs to the low frequency band, the switch directs it to the mixing channel, and performs up-conversion processing with the frequency model generated by the phase-locked loop PLL1, moving the signal to a frequency band suitable for the operation of the demodulator; when the signal is in the high frequency band, it directly enters the demodulation link through the switch pass path. The IQ demodulator receives the RF signal after frequency division processing and performs orthogonal demodulation with the broadband signal generated by the phase-locked loop PLL2 to separate the I and Q baseband signals. The two demodulated output signals are amplified and filtered to remove the high-frequency residual components to form analog signals that meet the sampling requirements of the subsequent ADC.

[0064] The transmit channel utilizes a symmetrical design architecture with the receive channel. The IQ signals generated by baseband processing are amplified and filtered before entering the IQ modulator, where they undergo quadrature modulation with the broadband signal generated by phase-locked loop (PLL2), shifting the baseband signal to the target RF band. The modulated RF signal also passes through a frequency band splitter. For bands requiring downconversion, the signal is mixed with the point-frequency signal from PLL1; for passbands, the original frequency is maintained. The subsequent digitally controlled attenuator precisely adjusts the transmit power, dynamically adjusting the transmit intensity through digital control. The driver amplifier boosts the signal power to ensure that the output signal reaches the required transmit power level. The final preselection filter bank suppresses out-of-band spurious signals from the transmit signal. Its six segmented filters effectively filter out harmonics, ensuring the spectral purity of the output signal.

[0065] In the receive channel of this embodiment, the FPGA receives the digital IQ signals sampled by the ADC and extracts phase information through amplitude thresholding. For 4PSK modulated signals, when both the I and Q signal amplitudes are within a specific range, the system determines that the current symbol phase is 45 degrees, corresponding to baseband data 00. Frequency information is obtained by calculating the phase change rate between adjacent symbols, extracting the frequency modulation characteristics of the signal. The inverse process in the transmit channel is achieved by the FPGA generating the baseband signal, mapping the data to be transmitted to the corresponding IQ amplitude combination, and converting it into an analog baseband signal through digital-to-analog conversion. The entire process uses digital algorithms to achieve modulation and demodulation.

[0066] Example 2

[0067] refer to Figure 15 This embodiment describes in detail the test function implementation and software architecture of the detector based on Example 1, taking the TACAN system in aviation radio as an example, including TACAN function testing, power sensitivity measurement and system stability assurance.

[0068] The TACAN function test process in this embodiment is as follows:

[0069] The MCU stores a table of transmit / receive frequencies corresponding to 252 channels, 1X to 126X and 1Y to 126Y. The user selects the target channel through the touch screen, and the MCU sends instructions to the FPGA to control the RF module to switch the phase-locked loop frequency and preselection filter.

[0070] The FPGA generates corresponding pulse coded signals based on the azimuth and distance values input by the host computer. The FPGA automatically generates dynamic signals at a 5° / s azimuth change rate and a 5km / s distance change rate to simulate the aircraft's motion state.

[0071] After the user triggers the identification key, the FPGA generates a continuous audio tone pattern or a Morse code random pattern, which is modulated by the RF part and output. The detector receives feedback from the onboard device through the wireless headset to verify that the identification function is normal.

[0072] The FPGA collects the amplitude of the received signal in real time, and performs Kalman filtering and dBm conversion through the MCU. The display range is -55dBm to -90dBm, with an accuracy of ±0.1dB. The peak power is captured by the FPGA at the maximum value of the signal envelope and uploaded to the host computer. The detector gradually reduces the transmit power from -55dBm to -90dBm, in steps of 5dB, until there is no response from the airborne equipment. The power value at this time is the receiving sensitivity.

[0073] This embodiment takes the air traffic control transponder system in aviation radio as an example, including A / C mode functional testing, sidelobe suppression measurement and S mode coding testing.

[0074] The air traffic control transponder function test process in this embodiment is as follows:

[0075] The detector transmits a Mode A interrogation signal to trigger the transponder on the aircraft to make a Mode A response. The aircraft batch code information is calculated from the response signal and displayed on the screen. The transponder Mode A encoding and decoding performance can be completed by checking the consistency between the screen display and the on-board settings.

[0076] The instrument uses a Mode C interrogation to trigger the transponder to respond. It receives and interprets the Gray code in the response signal, converting it into the corresponding altitude and displaying it on the screen. At this point, the transponder's Mode C encoding and decoding capabilities are verified by comparing the altitude indication on the aircraft with the instrument's altitude indication.

[0077] The detector simulates the situation where the aircraft is illuminated by side lobes by adjusting the signal amplitude of the P2 pulse in the interrogation signal, and can simulate three scenarios: "response area", "fuzzy area" and "no response area".

[0078] The checker uses a Mode S interrogation to trigger the transponder to respond. It then receives and interprets the batch code, address code, and Gray code contained in the response signal, converting them into corresponding data and displaying them on the screen. At this point, the transponder's Mode S encoding and decoding capabilities are verified by comparing the display on the aircraft's Mode S transponder control box with the checker's indications.

[0079] The software in this embodiment adopts a discrete architecture and is divided into the following units:

[0080] The monitoring unit is used to monitor battery voltage, RF signal power and temperature in real time, and abnormal conditions will trigger a three-level alarm.

[0081] The test unit integrates test modes such as TACAN, DME / P (precision ranging), and VOR (omnidirectional range finder), and supports test script editing and batch execution, such as continuously switching 10 channels and recording the results.

[0082] System setting unit, used to configure communication protocol and touch screen response time.

[0083] Example 3

[0084] This embodiment proposes a test process operation of a radio integrated detector based on embodiment 2.

[0085] refer to Figure 16 , Operation detection, operation detection is the beginning of the entire program startup, the process is as follows:

[0086] After the tester is started, the touch screen enters the standby state and continuously scans for user operation signals. At this time, the screen displays the current test mode and parameter interface, waiting for user input.

[0087] The user selects function buttons or inputs parameters through the touch screen, and the touch screen controller detects changes in capacitance signals in real time and triggers the operation detection program.

[0088] The system accurately locates the user operation area by scanning the coordinate grid of the touch screen and maps the coordinates to the current interface layout.

[0089] Based on the current display page and system status, verify whether the user operation complies with logic and permissions. If it is a valid operation, the system performs the corresponding operation, updates the interface display, and records the operation log.

[0090] If it is an invalid operation, the scan status is returned.

[0091] refer to Figure 17 , operation display interface, the display interface should show corresponding changes to inform the operator after making a correct operation, and the processor will also update the record of the current status of the display interface in real time to ensure the correctness of the operation, specifically:

[0092] After the detector is powered on, the main control part starts up and the power management module completes self-test to ensure that all voltage outputs are normal.

[0093] The Linux system starts, the QT interface framework loads the preset test configuration file, and the standby interface displays the touch screen main interface, including channel configuration, power measurement, azimuth simulation, function buttons and current parameter status.

[0094] The user triggers an operation through the touch screen, and the system enters the event response process:

[0095] Replace the original value display with the new value: For example, if the user switches from channel 31X to channel 45X, the interface will display the new channel number in real time;

[0096] Changing the displayed value: If the user slides the power adjustment bar, the value is dynamically updated from -70dBm to -75dBm.

[0097] The system classifies operations according to the type of operation, including parameter modification and function switching.

[0098] The processor responds with an operation based on the new value, releasing the original value and retaining the new value.

[0099] If the user cancels the operation, the interface returns to the original parameter display (such as channel 31X); if the user confirms the operation, the new value takes effect and continues to be displayed.

[0100] After completing the current operation, the system returns to the standby interface or jumps to the related function page (such as the continuous mode monitoring interface) and continues to wait for user input.

[0101] refer to Figure 18 Through the software architecture, all event responses in the radio integrated detector are prioritized to ensure that the system will not be stuck or run in chaos due to receiving too many response events at the same time.

[0102] The event interrupt priority is divided into level one interrupt, i.e. power failure, over-temperature; level two interrupt, i.e. communication timeout, data check error; level three interrupt: i.e. user operation instruction.

[0103] The detector may trigger various events during operation.

[0104] Determine whether there is an event currently being executed. If there is no event being executed, execute the new event directly; if there is an event being executed, enter the priority comparison process.

[0105] Comparing preset event priorities

[0106] The system determines the event priority based on preset rules: Level 1 interrupt (highest priority): power failure, overtemperature, emergency stop; Level 2 interrupt: communication timeout, data verification error; Level 3 interrupt (lowest priority): user parameter adjustment, routine test tasks.

[0107] Execute operations according to priority. When the new event has a higher priority, the current event is terminated immediately and the new event is executed. When the old event has a higher priority, the current event continues to execute and the new event is processed after completion. When the priorities are equal, the new event overwrites the old event.

[0108] The basic principles, main features, and advantages of the present invention are shown and described above. Those skilled in the art should understand that the present invention is not limited to the above embodiments. The above embodiments and descriptions are merely illustrative of the principles of the present invention. Various changes and modifications may be made to the present invention without departing from the spirit and scope of the present invention. Such changes and modifications are intended to fall within the scope of the present invention. The scope of protection claimed in the present invention is defined by the appended claims and their equivalents.

Claims

1. A radio integrated detector, characterized in that: Including main control part, host computer part and radio frequency part; The main control part is composed of MCU and FPGA. The MCU communicates with the host computer through a communication interface. The FPGA is connected to the radio frequency part through a parallel bus and is configured with a PS mode program loading interface. The radio frequency part adopts a zero-IF software radio architecture, including a receiving channel and a transmitting channel; The receiving channel includes a limiter, a preselection filter group, a digitally controlled attenuator, a low noise amplifier and a single-pole double-throw switch group in sequence; the preselection filter group is composed of filters in six independent frequency bands, which is used to suppress external interference signals in sections; The single-pole double-throw switch group in the receiving channel divides the received signal into frequency band 1 and frequency band 2. Frequency band 1 is up-converted by the point frequency signal generated by phase-locked loop PLL1, and then demodulated by the IQ demodulator and the broadband signal of phase-locked loop PLL2 to generate the baseband IQ signal; frequency band 2 is directly input into the IQ demodulator for demodulation. The transmitting channel includes an IQ modulator, a driving amplifier, a digitally controlled attenuator and a preselection filter group in sequence, and the transmitting and receiving channels share a preselection filter group of six independent frequency bands; The input end of the IQ modulator in the transmitting channel receives the baseband IQ signal and modulates it with the broadband signal of the phase-locked loop PLL2 to generate an RF signal; the single-pole double-throw switch group divides the modulated RF signal into frequency band 1 and frequency band 2, wherein frequency band 1 is down-converted by the point frequency signal generated by the phase-locked loop PLL1, and frequency band 2 is directly passed to the driver amplifier and output through the pre-selection filter group; The host computer part includes a touch screen, which is connected to the main control board through a communication interface.

2. A radio integrated detector according to claim 1, characterized in that: The preselection filter group of the receiving channel covers the L-band and microwave band. The bandwidth of each independent frequency band filter matches the operating frequency band of the airborne equipment, and the filter switching is dynamically controlled by the MCU according to the test requirements.

3. A radio integrated detector according to claim 1, characterized in that: The receiving channel and transmitting channel of the RF part are respectively connected to a dual-channel 14-bit ADC / DAC, the sampling rate of the ADC / DAC is not less than 40MHz, and the FPGA analyzes the phase and frequency information of the baseband signal through an amplitude threshold judgment algorithm.

4. A radio integrated detector according to claim 1, characterized in that: The power module of the main control part includes an 8.4V rechargeable lithium battery, a 27V external DC interface, and a 3.3V, 1.5V, 1.1V, and ±5V secondary power conversion circuit implemented by a TPS chip. The lithium battery power supply link is configured with an overvoltage / overcurrent protection circuit, and all secondary power supplies are independently powered by lithium batteries.

5. A radio integrated detector according to claim 1, characterized in that: The interface module of the detector includes two antenna interfaces and two altimeter interfaces; Multi-function multiplexing interface, integrating MCU program download, FPGA configuration loading and battery charging functions; Expansion interface, two SPI communication pins and general IO port for external sensors.

6. A radio integrated detector according to claim 1, characterized in that: The functional modules of the detector include a monitoring unit that monitors the power supply voltage, battery power and RF signal power in real time and displays alarm information through the QT interface; Test unit, including TACAN test, microwave landing test, heading test, automatic ship identification test, etc.; The system setting unit configures the communication protocol encryption parameters, the touch screen response time and the three-level event interrupt priority, and the interrupt priority is implemented through a preemptive scheduling mechanism.

7. A radio integrated detector according to claim 1, characterized in that: The phase-locked loops PLL1 and PLL2 of the radio frequency part generate a point-frequency signal and a broadband signal respectively, and the bandwidth of PLL2 covers the full operating frequency band of the IQ demodulator.

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