Flexible expansion method and device for number of switch chip port priority queues, and storage medium
By extending the binding between the FIFO scheduler and the switching chip port priority queue, the problem of insufficient number of traditional switch port queues is solved, flexible priority scheduling and precise service traffic management are achieved, and diverse business needs are met.
Patent Information
- Application Number
- CN202510256118.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-05
- Publication Date
- 2025-06-10
AI Technical Summary
The number of priority queues for traditional switches is limited, which is difficult to meet the diverse needs in complex business scenarios, especially the priority processing of various protocols and special service messages sent to CPUs is not accurate enough.
By setting up an extended FIFO scheduler, the group group binding mechanism is used to bind the extended FIFO resources to the target port's priority queue, increasing the number of queues, and achieving flexible priority scheduling through the scheduler working in concert.
It realizes flexible expansion of the number of priority queues for switching chip ports, supports more refined service traffic management, ensures priority execution of key services, and improves system flexibility and reliability.
Smart Images
Figure CN120128554A_ABST
Abstract
Description
Technical Field
[0001] The present invention belongs to the technical field of switching chips, and in particular, relates to a method, device, and storage medium for flexibly expanding the number of port priority queues of a switching chip. Background Art
[0002] The currently widely adopted solution for the port priority queue technology of switches is to configure 8 queues with different priorities on each port to meet service requirements and perform corresponding scheduling. However, with the development of network protocols and the diversification of service scenarios, when more detailed priority division is needed, this technology becomes inadequate. Due to the limited number of traditional priority queues, the distinction between priorities is not obvious enough to meet the requirements in complex service scenarios. Especially for various protocols and special service packets sent to the CPU, it is difficult to meet more priority processing requirements. The traditional 8 priority queues also cannot provide a more refined scheduling method and cannot accurately handle the diverse service traffic management needs. Summary of the Invention
[0003] To solve the above problems of the existing technical solutions, the present invention proposes a method, device, and storage medium for flexibly expanding the number of port priority queues of a switching chip to solve the above technical problems.
[0004] To achieve the above object, the present invention adopts the following technical solutions: A method for flexibly expanding the number of port priority queues of a switching chip includes the following steps:
[0005] Set up an extended FIFO scheduler. Through the group binding mechanism, bind the available FIFO resources for expansion to the priority queues of the target port without affecting the functions of the original priority queues, thereby increasing the overall number of priority queues of the target port; for the priority queues with extended FIFO bound, the original scheduler and the extended FIFO scheduler work together for scheduling management.
[0006] Further, it also includes the following steps: Using the group id as an index, configure the extended FIFO through the FifoGroupCtl table, including the enable control enable, the destination port destport of the priority queue to be expanded, the extended Exfifo resource configuration ExfifoIdBmp, the counter count for recording the number of extended FIFOs, as well as the priority bit prioritybit for determining the overall priority level of the extended FIFO group and the original priority queues of the destination port and the extended FIFO scheduling mode ModeSpEn.
[0007] Further, the width of the original destport bit is increased by 1 bit. If the highest bit is 1, the remaining bits represent the groupid. If the highest bit is 0, the remaining bits represent the destport. When the destination port destport of the service packet is set to the group id of the extended fifo, it indicates that the packet will be sent to the extended FIFO. At this time, the FifoGroupCtl register table is indexed with the groupid to confirm whether the enable is turned on. If it is not enabled, the packet will go through the normal priority queue. If it is enabled, the packet will go through the bound extended priority queue.
[0008] Further, the following steps are also included: The scheduler determines the priority relationship between the extended fifo queue and the original fifo queue according to the PriorityBit in the FifoGroupCtl table through a cooperation mechanism. When a user hopes to send a certain service packet to the extended fifo queue and requires its priority to be higher than the original 8 queues, the priority bit PriorityBit = 1 can be set to ensure that the packets in the extended FIFO are scheduled first. On the contrary, if the user hopes to reduce the priority of the extended fifo, just adjust it in the reverse direction.
[0009] The scheduling mode is determined by ModeSpEn. Setting it to 1 is the SP mode (Strict Priority strict priority mode), and setting it to 0 is the RR (Round Robin) round-robin mode. If it is the SP mode, the priority between the extended fifo queues is determined by indexing the PriorityMap in the TblExfifo with the bit position in the ExfifoIdBmp as the index.
[0010] Further, the following steps are also included: When several data packets and several ordinary multimedia packets are sent to the host for processing through the cpu port, configure the destination export extended priority queue resources Exfifo0 and Exfifo1, set the low 2 bits in the ExfifoIdMap in the FifoGroupCtl table to 1, set the BindDestPort value to the destination export, set the scheduling mode ModeSpEn = 1, set cout to 2, and set the prioritybit to 1.
[0011] The priority maps in the TblExfifo tables of the two extended FIFOs are set to 3 and 4 respectively; the destination port destport for the two- and three-layer forwarding lookups is set to the group id; the FifoGroupCtl register table is indexed by the group id to read whether enable is enabled. After enabling, if a certain data packet has a built-in priority of 3 and another data packet has a built-in priority of 4, then according to the correspondence between the built-in priority of the packet and the priority map in the TblExfifo table, the former is sent to Exfifo0 and the latter is sent to Exfifo1;
[0012] Among them, ModeSpEn being 1 means that the scheduling is based on priority. At this time, the chip will first schedule the data packets in Exfifo1 with a higher priority in the Exfifo until all the packets are forwarded, and then schedule the data packets in Exfifo0. After the forwarding of this data packet is completed, finally, the data packet with the highest priority in the regular fifo resources is scheduled, and so on until all the packets in the lowest priority queue are scheduled and forwarded.
[0013] Furthermore, when expanding the length of the original priority fifo, the resources of the extended fifo are bound to achieve the growth of the fifo length. At this time, the extended scheduler resources are not enabled.
[0014] A device for flexibly expanding the number of port priority queues of a switching chip, comprising:
[0015] An extended FIFO scheduler, which is used to bind the fifo resources available for expansion to the priority queues of the target port without affecting the functions of the original priority queues, thereby increasing the overall number of priority queues of the target port; for the priority queues with the extended FIFO already bound;
[0016] A scheduler that works in cooperation with the extended FIFO scheduler to jointly perform scheduling management.
[0017] Furthermore, the scheduler determines the priority relationship between the extended fifo queue and the original fifo queue according to the PriorityBit in the FifoGroupCtl table through a cooperation mechanism; when the user hopes to send a certain service packet to the extended fifo queue and requires its priority to be higher than the original 8 queues, the priority bit PriorityBit can be set to 1 to ensure the priority scheduling of the packets in the extended FIFO; on the contrary, if the user hopes to reduce the priority of the extended fifo, just adjust it in the reverse direction;
[0018] The scheduling mode is determined by ModeSpEn. Setting it to 1 represents the SP mode, and setting it to 0 represents the RR polling mode. If it is the SP mode, the priority between the extended fifo queues is determined by using the bit position in ExfifoIdBmp as the index to index the PriorityMap in the TblExfifo table. This flexible priority setting mechanism can handle diverse service requirements and adapt to multiple application scenarios, providing users with more accurate traffic management.
[0019] Furthermore, when several important data packets and several ordinary multimedia packets are sent to the host for processing through the cpu port together, configure the destination export extended priority queue resources Exfifo0 and Exfifo1, set the lower 2 bits in the ExfifoIdMap in the FifoGroupCtl table to 1, set the BindDestPort value to the destination export, set the scheduling mode ModeSpEn = 1, set cout to 2, and set prioritybit to 1;
[0020] The prioritymaps in the TblExfifo tables of the 2 extended fifos are set to 3 and 4 respectively; set the destination port destport of the two - three - layer forwarding lookup to the group id; through the group id, index the FifoGroupCtl register table to read whether enable is enabled. After enabling, if a certain data packet has a built - in priority of 3 and another data packet has a built - in priority of 4, then according to the correspondence between the built - in priority of the packet and the prioritymap in the TblExfifo table, send the former to Exfifo0 and the latter to Exfifo1;
[0021] Among them, ModeSpEn being 1 means that the scheduling is based on priority. At this time, the chip will first schedule the data packets in Exfifo1 with higher priority in the Exfifo until all the packets are forwarded, and then schedule the data packets in Exfifo0. After the forwarding of this data packet is completed, finally, start to schedule the data packet with the highest priority in the regular fifo resources, and so on until all the packets in the lowest - priority queue are scheduled and forwarded.
[0022] The present invention also provides a computer - readable storage medium containing a computer program. When the computer program is executed by one or more processors, it implements the method for flexibly expanding the number of port priority queues of the switching chip described in any one of the above.
[0023] The present invention realizes an increase in the number of queues by innovatively and flexibly expanding the priority FIFO queue (Extend queue fifo) and combining it with the original priority queue. Each group of expanded FIFO queues is equipped with an independent scheduler, and these schedulers are separated from the original priority queue scheduler without affecting the original functional design. Thus, it can meet the service requirements of different ports and further refine the service content. In addition, the present invention also supports a refined scheduling strategy to ensure the priority execution of critical services, thereby guaranteeing the efficiency and reliability of the service process. Description of the Drawings
[0024] Figure 1 It is a schematic diagram of the extended Fifo binding related table entries for a method and device for flexibly expanding the number of priority queues of a switching chip port according to the present invention;
[0025] Figure 2 It is an example diagram of the extended Fifo binding for a method and device for flexibly expanding the number of priority queues of a switching chip port according to the present invention;
[0026] Figure 3 It is an example diagram of the scheduler cooperation for a method and device for flexibly expanding the number of priority queues of a switching chip port according to the present invention;
[0027] Figure 4 It is an example diagram of enabling the Exfifo message scheduling for a method and device for flexibly expanding the number of priority queues of a switching chip port according to the present invention;
[0028] Figure 5 It is an example diagram of the extended fifo for increasing the length of the original fifo for a method and device for flexibly expanding the number of priority queues of a switching chip port according to the present invention. Detailed Embodiment
[0029] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without making creative efforts belong to the scope of protection of the present invention.
[0030] As Figure 1 - Figure 2 shown, a method for flexibly expanding the number of priority queues of a switching chip port includes the following steps:
[0031] An extended FIFO scheduler is set up. Through the group binding mechanism, the fifo resources available for extension are bound to the priority queues of the target ports without affecting the functions of the original priority queues, thereby increasing the overall number of priority queues of the target ports. For the priority queues with extended FIFOs bound, the original scheduler and the extended FIFO scheduler work together for scheduling management. Through the group binding mechanism of the present invention, the fifo resources available for extension are flexibly bound to the priority queues of the target ports without affecting the functions of the original priority queues, thereby increasing the overall number of priority queues of the target ports.
[0032] The group binding mechanism is specifically as follows: Taking the group id as the index, the extended fifo is configured through the FifoGroupCtl table, including enabling control enable, the destination port destport of the priority queue to be extended, the extended Exfifo resource configuration ExfifoIdBmp, the counter count for recording the number of extended fifos, as well as the priority bit prioritybit for determining the overall priority level of the extended FIFO group and the original priority queue of the destination port and the extended fifo scheduling mode ModeSpEn.
[0033] Among them, the bit width of the original destport is increased by 1 bit. If the highest bit is 1, the remaining bits represent the groupid. If the highest bit is 0, the remaining bits represent the destport. When the destination port destport of the service packet is set to the groupid of the extended fifo, it indicates that the packet will be sent to the extended FIFO. At this time, the group id is used to index the FifoGroupCtl register table to confirm whether the enable is turned on. If it is not enabled, the packet will go through the normal priority queue. If it is enabled, the packet will go through the bound extended priority queue. The priority binding of the extended fifo supports flexible configuration. Users can set the number of extended FIFOs and the overall priority of the extended FIFOs according to needs, which can be higher than the original 8 bound priority queues or lower than the 8 original priority queues, consistent with the scheduling mechanism. The packet exit is still the original destination port, only the number of priority queues is extended, and the packet content is not edited. This design not only improves the flexibility and configurability of the system but also ensures the continuity and consistency of packet processing.
[0034] Such as Figure 3As shown in the figure, the following steps are further included: The scheduler determines the priority relationship between the extended fifo queue and the original fifo queue according to the PriorityBit in the FifoGroupCtl table through a cooperation mechanism; When a user hopes to send a certain service message to the extended fifo queue and requires its priority to be higher than the original 8 queues, the priority bit PriorityBit = 1 can be set to ensure the priority scheduling of the messages in the extended FIFO; On the contrary, if the user hopes to reduce the priority of the extended fifo, just make a reverse adjustment; The scheduling mode is determined by ModeSpEn. Set 1 for the SP mode and 0 for the RR polling mode; If it is the SP mode, the priority between the extended fifo queues is determined by the PriorityMap in the TblExfifo table with the bit position in the ExfifoIdBmp as the index. This flexible priority setting mechanism can handle diverse service requirements and adapt to multiple application scenarios, providing users with more accurate traffic management.
[0035] As Figure 4 shown in the figure, the following steps are further included: When several important data messages and several ordinary multimedia messages are sent to the host for processing through the cpu port together, configure the destination export extended priority queue resources Exfifo0 and Exfifo1, set the lower 2 bits in the ExfifoIdMap in the FifoGroupCtl table to 1, set the BindDestPort value to the destination export, set the scheduling mode ModeSpEn = 1, set cout to 2, and set the prioritybit to 1;
[0036] The prioritymaps in the TblExfifo tables of the 2 extended fifos are set to 3 and 4 respectively; Set the destination port destport of the layer 2 and layer 3 forwarding lookup to the group id; Index the FifoGroupCtl register table through the group id, read whether enable is enabled. After enabling, if a certain data message has a self - carried priority of 3 or a mapped priority of 3 through internal configuration, and another data message has a self - carried priority of 4 or a mapped priority of 4 through internal configuration, then correspond the priorities one by one with the prioritymap in the TblExfifo table, and send the former to Exfifo0 and the latter to Exfifo1;
[0037] Among them, ModeSpEn is 1, which means that the scheduling is based on priority. At this time, the chip will give priority to scheduling the data packets in Exfifo1 with a higher priority in Exfifo, and then schedule the data packets in Exfifo0 after all the packets are forwarded. After the data packets are forwarded, the data packets with the highest priority in the regular fifo resources will be scheduled, and so on until all the packets in the lowest priority queue are scheduled and forwarded.
[0038] Take the vehicle network as an example: the high-priority brake control signal data message P10, intelligent driving radar sensor data message P9, intelligent driving camera data message P8, and ordinary multimedia messages P1 and P2 in the vehicle network are sent to the host for processing through the CPU port at the same time. If the priority fifo is not expanded, the intelligent driving related data P8 / P9 / P10 will usually go to the highest priority 7. For the priority 7 queue, whichever message arrives first will be processed first. However, in the automotive system, the brake signal is of paramount importance and is related to life, so it must be processed with the highest priority. The traditional solution can only squeeze the resources of other priority queues, leaving priority 7 for the most important P10, and P8 / P9 going to priority 6, etc. However, the number of important message types in the actual vehicle network far exceeds the conventional 8 priority numbers, and it cannot be avoided that multiple important data messages go to the same priority and affect each other.
[0039] The present invention configures the destination export extended priority queue resources Exfifo0 and Exfifo1, sets the lower 2 bits in ExfifoIdMap in the FifoGroupCtl table to 1, sets the BindDestPort value to the destination export, sets the scheduling mode ModeSpEn=1, cout to 2, and prioritybit to 1. The prioritymap in the TblExfifo table of the two extended fifos is set to 3 and 4 respectively.
[0040] Set the destination port destport for the second and third layer forwarding lookups to the groupid. Index the FifoGroupCtl register table through the groupid, read whether enable is enabled. After enabling, if the P9 packet is set with a priority of 3 by default or mapped to 3 through internal configuration, and the P10 packet has a priority of 4 by default or mapped to 4 through internal configuration. Then, according to the priority corresponding to the prioritymap in the TblExfifo table one by one, send P9 to Exfifo0 and P10 to Exfifo1. If ModeSpEn is 1, it means that the scheduling is based on priority. At this time, the chip will first schedule the P10 packet in Exfifo1 with a higher priority in the Exfifo until all the packets are forwarded, and then schedule the P9 packet in Exfifo0. After the P9 packet is forwarded, finally, start to schedule the P8 packet with the highest priority in the regular fifo resources, and so on until all the packets in the lowest priority queue are scheduled and forwarded. Reference Figure 4 。
[0041] The key of the present invention is to expand the existing queues implemented by conventional technologies through flexible expansion of the fifo, and at the same time, it is not necessary to modify the original technical design, which reduces the development cost and meets the increasingly rich application scenarios. The number of such expanded fifos is not limited, and the bound ports are also not limited. It is possible to support the addition of expanded fifos to multiple ports, and the number of expanded fifos for each port can be inconsistent.
[0042] Another implementation manner of the present invention can be to directly reserve fifo resources for each port in advance. When needed, enable them through unified register configuration and participate in the scheduling of the unified scheduler. However, this method is not flexible enough, consumes more resources, and has certain limitations.
[0043] The expanded fifo of the present invention is not limited to expanding the number of priority fifos. It can also support the application of increasing the length of the original priority fifo. When expanding the length of the original priority fifo, the resources of the expanded fifo can also be bound to achieve the growth of the fifo length. At this time, it is not necessary to enable the expanded scheduler resources. Reference Figure 5 。
[0044] The present invention also provides a flexible expansion device for the number of port priority queues of a switching chip, including:
[0045] An extended FIFO scheduler for binding the fifo resources available for expansion to the priority queues of the target port without affecting the functions of the original priority queues, thereby increasing the overall number of priority queues of the target port; for the priority queues with the extended FIFO already bound;
[0046] A scheduler that works in coordination with the extended FIFO scheduler to jointly perform scheduling management.
[0047] Further, the scheduler determines the priority relationship between the extended fifo queue and the original fifo queue according to the PriorityBit in the FifoGroupCtl table through a cooperation mechanism; when a user hopes to send a certain service message to the extended fifo queue and requires its priority to be higher than the original 8 queues, the priority bit PriorityBit = 1 can be set to ensure that the messages in the extended FIFO are scheduled first; on the contrary, if the user hopes to reduce the priority of the extended fifo, just make a reverse adjustment;
[0048] The scheduling mode is determined by ModeSpEn. Setting it to 1 is the SP mode, and setting it to 0 is the RR polling mode; if it is the SP mode, the priority between the extended fifo queues is determined by the PriorityMap in the TblExfifo table with the bit position in the ExfifoIdBmp as the index. This flexible priority setting mechanism can cope with diverse service requirements and adapt to various application scenarios, providing users with more accurate traffic management.
[0049] Further, when several important data messages and several ordinary multimedia messages are sent to the host for processing through the cpu port together, configure the destination export extended priority queue resources Exfifo0 and Exfifo1, set the lower 2 bits in the ExfifoIdMap in the FifoGroupCtl table to 1, set the BindDestPort value to the destination export, set the scheduling mode ModeSpEn = 1, set cout to 2, and set the prioritybit to 1;
[0050] The prioritymaps in the TblExfifo tables of the 2 extended fifos are set to 3 and 4 respectively; set the destination port destport of the layer 2 / 3 forwarding lookup to the group id; index the FifoGroupCtl register table through the group id, read whether enable is enabled, and after enabling, if a certain data message has a self - carried priority of 3 and another data message has a self - carried priority of 4, then according to the correspondence between the self - carried priority of the message and the prioritymap in the TblExfifo table, send the former to Exfifo0 and the latter to Exfifo1;
[0051] Among them, ModeSpEn is 1, indicating that the scheduling is based on priority. At this time, the chip will first schedule the data packets with higher priority in Exfifo1 in the Exfifo until all the packets are forwarded, and then schedule the data packets in Exfifo0. After the forwarding of the data packets is completed, finally, the data packets with the highest priority in the conventional fifo resources are scheduled, and so on until all the packets in the lowest priority queue are scheduled and forwarded.
[0052] The present invention also provides a computer-readable storage medium containing a computer program, which, when executed by one or more processors, implements the method for flexibly expanding the number of port priority queues of the switching chip described in any one of the above.
[0053] The present invention innovatively provides a flexibly extensible priority FIFO queue Extend queue fifo, which is combined with the original priority queue to increase the number of queues. Each group of extended FIFO queues is equipped with an independent scheduler, and these schedulers are separated from the original priority queue scheduler without affecting the original function design. Thus, it can meet the service requirements of different ports and further refine the service content. In addition, the present invention also supports a refined scheduling strategy to ensure the priority execution of critical services, thereby ensuring the efficiency and reliability of the service process.
[0054] The above is only a preferred specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present invention, according to the technical solution and inventive concept of the present invention, makes equivalent substitutions or changes, and should be covered by the protection scope of the present invention.
Claims
1. A method for flexibly expanding the number of priority queues of a switch chip port, characterized in that: The following steps are involved: Set up an extended FIFO scheduler, and bind the FIFO resources available for expansion to the priority queue of the target port through the group binding mechanism, without affecting the function of the original priority queue, thereby increasing the overall priority queue number of the target port; For the priority queue bound to the extended FIFO, the original scheduler works with the extended FIFO scheduler to jointly perform scheduling management.
2. The method for flexibly expanding the number of priority queues of a switch chip port according to claim 1, characterized in that: The following steps are also included: With group id as index, the extended fifo is configured through the FifoGroupCtl table, including enabling control enable, the destination port destport of the priority queue to be extended, the extended Exfifo resource configuration ExfifoIdBmp, the counter count that records the number of extended fifos, and the priority bit prioritybit that determines the overall priority of the extended FIFO group and the original priority queue of the destination port, and the extended fifo scheduling mode ModeSpEn.
3. The method for flexibly expanding the number of priority queues of a switch chip port according to claim 1, characterized in that: in, Increase the original destport bit width by 1 bit. If the highest bit is 1, the remaining bits represent the group id. If the highest bit is 0, the remaining bits represent destport. When the destination port destport of the service message is set to the group id of the extended fifo, it indicates that the message will be sent to the extended FIFO. At this time, use the group id to index the FifoGroupCtl register table to confirm whether it is enabled. If not enabled, the normal priority queue will be used. If enabled, the bound extended priority queue will be used.
4. The method for flexibly expanding the number of priority queues of a switch chip port according to claim 3 is characterized in that: The following steps are also included: The scheduler determines the priority relationship between the extended fifo queue and the original fifo queue according to the PriorityBit in the FifoGroupCtl table through the collaboration mechanism. When the user wants to send a service message to the extended fifo queue and requires its priority to be higher than the original 8 queues, the priority bit PriorityBit can be set to 1 to ensure that the message in the extended FIFO is scheduled first. On the contrary, if the user wants to lower the priority of the extended fifo, the reverse adjustment can be made. The scheduling mode is determined by ModeSpEn, which is set to 1 for SP mode and 0 for RR polling mode. If it is SP mode, the priority between the extended fifo queues is determined by the PriorityMap in the index table TblExfifo, with the bit position in ExfifoIdBmp as the index.
5. The method for flexibly expanding the number of priority queues of a switch chip port according to claim 4, characterized in that: The following steps are also included: When several important data packets and several common multimedia packets are sent to the host through the CPU port for processing, configure the destination egress extended priority queue resources Exfifo0 and Exfifo1, set the lower 2 bits in ExfifoIdMap in the FifoGroupCtl table to 1, set the BindDestPort value to the destination egress, set the scheduling mode ModeSpEn=1, cout to 2, and prioritybit to 1; The prioritymap in the TblExfifo table of the two extended fifos is set to 3 and 4 respectively; the destination port destport for layer 2 and 3 forwarding lookup is set to group id; the FifoGroupCtl register table is indexed by group id to read whether enable is enabled. After enabling, if a data message has a built-in priority of 3 and another data message has a built-in priority of 4, the built-in priority of the message will correspond to the prioritymap in the TblExfifo table one by one, and the former will be sent to Exfifo0 and the latter to Exfifo1; Among them, ModeSpEn is 1, which means that the scheduling is based on priority. At this time, the chip will give priority to scheduling the data packets in Exfifo1 with a higher priority in Exfifo, and then schedule the data packets in Exfifo0 after all the packets are forwarded. After the data packets are forwarded, the data packets with the highest priority in the regular fifo resources will be scheduled, and so on until all the packets in the lowest priority queue are scheduled and forwarded.
6. The method for flexibly expanding the number of priority queues of a switch chip port according to claim 5, characterized in that: When the original priority fifo length is expanded, the resources of the expanded fifo are bound to achieve the increase of the fifo length. At this time, the expansion scheduler resources are not enabled.
7. A device for flexibly expanding the number of priority queues at a switch chip port, characterized in that: include: An extended FIFO scheduler is used to bind the fifo resources available for expansion to the priority queue of the target port without affecting the function of the original priority queue, thereby increasing the overall number of priority queues of the target port; For the priority queue that has bound extended FIFO; The scheduler works together with the extended FIFO scheduler to perform scheduling management.
8. The device for flexibly expanding the number of priority queues of a switch chip port according to claim 7, characterized in that: The scheduler determines the priority relationship between the extended fifo queue and the original fifo queue according to the PriorityBit in the FifoGroupCtl table through a collaborative mechanism; when a user wants to send a service message to the extended fifo queue and requires its priority to be higher than the original 8 queues, the priority bit PriorityBit can be set to 1 to ensure that the message in the extended FIFO is scheduled first; on the contrary, if the user wants to lower the priority of the extended fifo, the reverse adjustment can be made; The scheduling mode is determined by ModeSpEn, which is set to 1 for SP mode and 0 for RR polling mode. In SP mode, the priority between extended fifo queues is determined by the PriorityMap in the index table TblExfifo, with the bit position in ExfifoIdBmp as the index. This flexible priority setting mechanism can cope with diverse business needs and adapt to a variety of application scenarios, providing users with more accurate traffic management.
9. The device for flexibly expanding the number of priority queues of a switch chip port according to claim 8, characterized in that: When several important data packets and several common multimedia packets are sent to the host through the CPU port for processing, configure the destination egress extended priority queue resources Exfifo0 and Exfifo1, set the lower 2 bits in ExfifoIdMap in the FifoGroupCtl table to 1, set the BindDestPort value to the destination egress, set the scheduling mode ModeSpEn=1, cout to 2, and prioritybit to 1; The prioritymap in the TblExfifo table of the two extended fifos is set to 3 and 4 respectively; the destination port destport for layer 2 and 3 forwarding lookup is set to group id; the FifoGroupCtl register table is indexed by group id to read whether enable is enabled. After enabling, if a data message has a built-in priority of 3 and another data message has a built-in priority of 4, the built-in priority of the message will correspond to the prioritymap in the TblExfifo table one by one, and the former will be sent to Exfifo0 and the latter to Exfifo1; Among them, ModeSpEn is 1, which means that the scheduling is based on priority. At this time, the chip will give priority to scheduling the data packets in Exfifo1 with a higher priority in Exfifo, and then schedule the data packets in Exfifo0 after all the packets are forwarded. After the data packets are forwarded, the data packets with the highest priority in the regular fifo resources will be scheduled, and so on until all the packets in the lowest priority queue are scheduled and forwarded.
10. A computer-readable storage medium containing a computer program, characterized in that: When the computer program is executed by one or more processors, the method for flexibly expanding the number of priority queues of a switch chip port as described in any one of claims 1 to 6 is implemented.