An internet of things data interaction control system and an internet of things device

Abstract

The application provides an Internet of Things data interaction control system and an Internet of Things device. A novel Internet of Things device interaction control system architecture is designed, so that complex sending and receiving timing rules and corresponding protocol stacks do not need to be designed for the data sending and receiving process. For single host or multi-host scenarios, automatic sending and receiving storage of Internet of Things data packets can be completed, work efficiency is significantly improved, software complexity is reduced, channel collision problems are effectively avoided, and high compatibility is also considered. With the high-quality Internet of Things data interaction control effect, the application has very good application value.

Description

Technical Field

[0001] This application relates to the field of the Internet of Things (IoT), specifically to an IoT data interaction control system and IoT devices. Background Technology

[0002] The Internet of Things (IoT) is a major technological development trend in recent years. The essential task of IoT is data interaction between nodes within the network, that is, to realize data exchange between nodes (in master-slave or peer-to-peer relationships) through wired or wireless means.

[0003] However, the inventors of this application have discovered that both bus-type and star-type network architectures have the following problems in data interaction:

[0004] 1) IoT hosts need to be designed and comply with transmit and receive timing rules, which are complex and consume host operating resources;

[0005] 2) For a “multi-master multi-slave” network structure or a “multi-node peer-to-peer” network structure, additional coordination must be performed between the master nodes or peer nodes to avoid transmit / receive conflicts or channel collisions.

[0006] 3) After receiving data, the host node needs to perform relevant business processing. During this period, the entire IoT network is in an "idle" state, which reduces data throughput and network utilization efficiency.

[0007] 4) There is a huge difference between the host data throughput rate and the IoT communication rate, which causes the IoT to slow down the host transaction processing efficiency;

[0008] 5) Currently, most IoT communication interfaces are serial. Due to the limitations of IoT line transceiver devices or network reliable communication speed bottlenecks, their transmission and reception speeds are far lower than the Direct Memory Access (DMA) transfer speed of the host microcontroller unit (MCU). This inevitably delays the time occupied by the host DMA controller, resulting in problems such as excessively long host MCU bus timing stealing time, excessively long DMA channel occupation time, and excessively long main memory block locking time, thus reducing host operating efficiency.

[0009] 6) Currently, most IoT transceiver access modes are in a "one-to-one" format, meaning one node device is configured with one IoT data interaction device (or physical interface). However, for IoT gateways in clustered, multi-redundant supercomputing architectures (multi-host parallel computing architectures), the existing "one-to-one" interface mode can only match one host, failing to leverage its parallel processing advantages. Simply configuring each host in this clustered architecture with a "one-to-one" IoT interface and connecting it to the network not only causes complex problems such as data synchronization, sharing and interaction, transmit / receive conflicts, and channel conflicts between multiple hosts, but also adds multiple host node addresses to the IoT, consuming valuable available IoT address resources, increasing the complexity of the entire network protocol, requiring redesign and modification of the software of all slave nodes, resulting in poor compatibility, poor usability, and difficulty in maintenance. For example, a typical 16×16 matrix supercomputing IoT gateway, after connecting to the network in this mode, would consume 16×16 IoT addresses just for the host itself. If the IoT uses a 1-byte addressing design, then slave nodes will have no addressing resources available.

[0010] It is evident that existing IoT data interaction control schemes have significant limitations in terms of practicality. Summary of the Invention

[0011] This application provides an IoT data interaction control system and IoT devices. By designing a novel IoT device interaction control system architecture, the system eliminates the need for complex timing rules and corresponding protocol stacks for data transmission and reception. Whether in single-host or multi-host scenarios, it can automatically send, receive, and store IoT data packets, significantly improving work efficiency, reducing software complexity, effectively avoiding channel collision problems, and ensuring high compatibility. With its high-quality IoT data interaction control effect, it has excellent application value.

[0012] In a first aspect, this application provides an Internet of Things (IoT) data interaction control system, which includes a data transmission and reception control logic component, a data storage component, and a storage access control logic component. The data transmission and reception control logic component is responsible for independently implementing the data transmission, reception, and conversion tasks of the IoT terminal. The data storage component is responsible for implementing the data storage and exchange tasks between the IoT terminal and the host terminal. The storage access control logic component is responsible for independently implementing the data access control and conflict control tasks between the host terminal and the data storage component.

[0013] On the one hand, the data transmission and reception control logic unit automatically reads and writes data from the data storage unit one by one and completes the parallel conversion of the data string. The Tx path serially sends data to the IoT physical layer unit, completing the data storage and transmission. On the other hand, the Rx path obtains serial data from the IoT physical layer unit, completes the parallel conversion of the data string, and writes it into the data storage unit, completing the data reception and storage.

[0014] The data storage component consists of a dual-port random access memory (RAM) and a set of registers. The dual-port RAM is composed of a data transmission and reception control logic unit and a storage access control logic unit. It randomly writes or reads data into the internal storage unit to realize the data transmission and reception exchange and storage functions of the Internet of Things. The registers are divided into a send request register, a receive request register, and an access conflict register. The data transmission and reception control logic unit and the storage access control logic unit perform ordered operations on the dual-port RAM according to the bit status in the registers to solve the access conflict and data overwrite problems.

[0015] The storage access control logic component has multiple sets of data access ports and access control logic to enable conflict-free data access to the data storage component in single-host and multi-host scenarios.

[0016] The data transmission and reception control logic unit and the storage access control logic unit are independent hardware modules.

[0017] Preferably, the data transmission and reception control logic unit consists of a read stack, an internal clock source, a write stack, a data latch T, a shift register T, a shift register R, and a data latch R;

[0018] For the data transmission and reception control logic unit, the corresponding data transmission process includes the following processing:

[0019] After the read stack checks that the data latch T is in an idle state, it checks the request flag bit in the send request register, and reads the first data to be sent from the corresponding RAM area according to the address vector mapped by the request flag bit in the send request register. The first data is then sent into the data latch T, and the data latch T is set to a busy state.

[0020] After the shift register T checks that the data latch T is busy, it reads the first data from the data latch T in parallel at once, sets the data latch T to an idle state, and then starts shifting the first data out bit by bit from the Tx line according to the first baud rate.

[0021] Preferably, for the data transmission and reception control logic unit, the corresponding data receiving process includes the following processing steps:

[0022] The shift register R detects the level transition edge on the Rx line and converts the high level state on the Rx line to 1 and the low level state to 0 according to the second baud rate, and shifts the bits into the shift register R bit by bit;

[0023] After the shift register R is full, when the data latch R is in an idle state, the second data in the shift register R is written to the data latch R, and the data latch R is set to a busy state.

[0024] When the write stack finds that the data latch R is busy, it reads the second data in the data latch R and writes the second data to the corresponding storage area in the dual-port RAM according to the address contained in the data. It sets the corresponding bit in the receive request register. If the data in the target storage area has not been read by the host during the process, it is considered that the host is abnormal and the newly received data directly overwrites the original data in the corresponding RAM area.

[0025] Preferably, for the data storage component, there are:

[0026] The send request register stores the request flag bit of the host to send data to the IoT terminal; the receive request register stores the request flag bit of the IoT terminal to notify the host to retrieve the data after the IoT terminal has received a frame of data and written it into the corresponding RAM area; the dual-port RAM stores the data to be sent or received; and the access conflict register stores the flag bit of the access conflict that occurs when the host and IoT terminal access the same address unit in the dual-port RAM at the same time.

[0027] The conditions for an access conflict to occur are as follows:

[0028] 1) The host and IoT terminals simultaneously perform write operations on the same address unit of the dual-port RAM;

[0029] 2) When the host or IoT device reads from the same address unit of the dual-port RAM, the other end performs a write operation.

[0030] 3) When writing to the same address unit of the dual-port RAM on the host or IoT end, the other end performs a read operation;

[0031] When an access conflict occurs, the BUSY line of the dual-port RAM remains low. When the conflict condition is lifted, the BUSY line of the dual-port RAM returns to high. When the host or IoT device operates on the dual-port RAM cell, it queries the access conflict register or the status of the BUSY line of the dual-port RAM, freezes the operation, and waits for the cancellation before continuing the previous read and write operation to resolve the access conflict problem.

[0032] Preferably, for the data storage component, under the condition of using a parallel bus on the host side, the following applies:

[0033] The address bus is connected to the address bus interface corresponding to the dual-port RAM, and the data bus is connected to the data bus interface corresponding to the dual-port RAM; the read signal RD, write signal WR, and conflict signal BUSY are connected to the corresponding signal interfaces, the conflict signal BUSY is connected to the main nWait signal or external interrupt signal pin, and the send request register and receive request register are connected to the host's data address bus or an I / O interface independent of the data address bus.

[0034] The send request register and receive request register directly use the storage units in the dual-port RAM and are integrated with the dual-port RAM.

[0035] Preferably, for the data storage component, under the condition of using a serial bus on the host side, the following applies:

[0036] A single host or multiple hosts can be connected to the same SPI bus, or each host can be connected to a different SPI bus and connected to its corresponding dual-port RAM. The send request register, receive request register and access conflict signal BUSY of the dual-port RAM are mapped to the corresponding bits in access conflict register A and access conflict register B, respectively. Access conflict register A is connected to the host's data bus or I / O port for querying.

[0037] Preferably, for the storage access control logic unit, under the condition of parallel bus host access mode, the following applies:

[0038] The storage access control logic unit consists of a first bus arbitration logic unit, a first bus transformation logic array, and a first access permission register;

[0039] The BUSY signal of the dual-port RAM is connected to the first bus arbitration logic unit for reading, and the CE signal of the external memory access chip of each host is connected to the first bus arbitration logic unit respectively.

[0040] The first bus arbitration logic unit queries the current chip select signal and the BUSY signal of the dual-port RAM. If there is a request and no access conflict, the corresponding bit in the first access permission register is set. The logic level of the corresponding bit in the first access permission register determines and is circuitally connected to the output enable pin (OE) of the bus tri-state buffer of the corresponding host, making the bus effectively connected. If there is no request or an access conflict exists, the corresponding bit in the first access permission register is cleared. The output enable pin (OE) of the bus tri-state buffer of the corresponding host is invalid, and the host is in a high-impedance state to the bus, which does not cause bus conflicts for other valid access hosts.

[0041] When the first bus arbitration logic unit decides that a specific host access is valid, it simultaneously sets the multiplexer in the first bus transformation logic array to be valid, so that the control bus, address bus and data bus of the corresponding specific host are connected to the bus corresponding to the data storage unit.

[0042] If an access conflict occurs during the host's read / write operation of the dual-port RAM, the first bus arbitration logic unit cancels the output enable signal OE of the host bus tri-state buffer based on the dual-port RAM's BUSY signal, thus disconnecting the corresponding host from the dual-port RAM bus. This resolves the unreliable data read / write issue when a conflict occurs. The value of the first access permission register is available for the corresponding host to query via the I / O port. If the host detects that the corresponding access permission bit has been revoked, it enters a delayed waiting state.

[0043] Preferably, for the memory access control logic unit, under the condition of serial bus access mode, the following applies:

[0044] The storage access control logic unit consists of a second bus arbitration logic unit and a second access permission register;

[0045] The access conflict register A of the data storage unit is connected to the second bus arbitration logic unit for reading. Each host uses two IO lines as request IO lines and permission query IO signal lines. The request IO lines are connected to the second bus arbitration logic unit, and the permission query IO signal lines are connected to the output pin of the second access permission register.

[0046] The second bus arbitration logic unit queries the current access request signal and the bit value in the access conflict register A. If there is a request and no access conflict, the corresponding bit in the second access permission register is set. After the corresponding bit in the second access permission register is queried by the corresponding host or accessed in interrupt mode, the data read / write process of the SPI serial bus is started. If there is no request or an access conflict exists, the corresponding bit in the second access permission register is cleared. In this case, the corresponding host will not start the SPI bus data read / write process when the access permission is invalid, and will not cause bus conflicts for other valid access hosts.

[0047] Preferably, for the storage access control logic unit, under the condition of fully parallel access mode, the following applies:

[0048] The memory access control logic unit consists of multiple write-ahead stacks, multiple read-before stacks, a write controller, and a read controller.

[0049] Each host is connected to the corresponding write stack and read stack via its own bus. Each host is independent of the others and does not affect them, working in full parallel.

[0050] The write controller is connected to the send request register. The data, address, and control bus of the write controller are connected to the dual-port RAM via the corresponding tri-state driver. The read controller is connected to the receive request register. The data, address, and control bus of the read controller are connected to the dual-port RAM via the corresponding tri-state driver. The write controller and the read controller are connected by a dedicated request I / O bus.

[0051] In the transmission priority rule, after any host writes new data to be transmitted into the corresponding advance write stack, it sets the value of the transmission request storage unit in the corresponding advance write stack. The write controller polls the transmission request storage units in each advance write stack at a certain interval. If it finds data to be transmitted, it pulls the bus exclusive request IO between itself and the corresponding read controller high to indicate that data is about to be written to the dual-port RAM. After the read controller obtains the current state through polling or interrupt mode, it cancels the output enable of its own tri-state driver and yields the bus to the write controller. The write controller enables the output enable of its own tri-state driver, acquires the bus and writes data to the dual-port RAM. After writing the data, the write controller clears the flag bit of the transmission request storage unit in the corresponding advance write stack, sets the flag bit of the host in the transmission request register, and pulls the bus exclusive request IO between itself and the corresponding read controller low to indicate that the writing process is over and yields the bus to the read controller.

[0052] In the receive priority rule, after the read controller obtains the value of the receive request register in polling or interrupt mode, if a flag bit is set, it immediately pulls low the bus exclusive request IO between itself and the read controller, indicating that data is about to be read from the dual-port RAM. After the write controller obtains this state through polling or interrupt mode, it cancels the output enable of its own tri-state driver, yielding the bus to the read controller. The read controller then enables the output of its own tri-state driver, obtains the bus, reads the data from the dual-port RAM, and sends the data into the corresponding host's subsequent read stack. At the same time, it clears the corresponding bit in the receive request register to indicate that the data has been taken. After reading the data, it sets the read data request storage unit value in the subsequent read stack, pulls high the bus exclusive request IO between itself and the write controller to indicate that the reading process is over, and yields the bus to the write controller.

[0053] Secondly, this application provides an Internet of Things (IoT) device, which is equipped with the IoT data interaction control system provided in the first aspect.

[0054] From the above, it can be concluded that this application has the following beneficial effects:

[0055] This application presents a novel IoT device interaction control system architecture, which eliminates the need for complex timing rules and protocol stacks for data transmission and reception. Whether in single-host or multi-host scenarios, it can automatically send, receive, and store IoT data packets, significantly improving work efficiency, reducing software complexity, effectively avoiding channel collision issues, and ensuring high compatibility. With its high-quality IoT data interaction control effect, it has excellent application value. Attached Figure Description

[0056] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0057] Figure 1 A schematic diagram of an overall architecture for an IoT data interaction control system application;

[0058] Figure 2 This is a schematic diagram of the data transmission and reception control logic component of this application;

[0059] Figure 3 This is a logical diagram illustrating the data transmission process corresponding to the data transmission and reception control logic component of this application.

[0060] Figure 4 This is a logical diagram illustrating the data receiving process corresponding to the data transmission and reception control logic component of this application.

[0061] Figure 5 This is a logical diagram illustrating a parallel bus access mode for the data storage component of this application.

[0062] Figure 6 This is a logical diagram illustrating a serial bus access mode for the data storage component of this application.

[0063] Figure 7 This is a logical diagram of the storage access control logic unit of this application in the parallel bus host access mode;

[0064] Figure 8 This is a logical diagram illustrating parallel bus host access for the storage access control logic component of this application.

[0065] Figure 9 This is a logic diagram of the storage access control logic unit of this application in serial bus access mode;

[0066] Figure 10A logical diagram of a storage access control logic unit in a fully parallel access mode;

[0067] Figure 11 This is a logical diagram illustrating the write process of the storage access control logic unit in the fully parallel access mode of this application.

[0068] Figure 12 This is a logic diagram illustrating the reading process of the storage access control logic unit in the fully parallel access mode of this application. Detailed Implementation

[0069] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0070] The terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments described herein can be implemented in a sequence other than that illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or device that includes a series of steps or modules is not necessarily limited to those explicitly listed, but may include other steps or modules not explicitly listed or inherent to such processes, methods, products, or devices. The naming or numbering of steps appearing in this application does not imply that the steps in the method flow must be performed in the chronological / logical order indicated by the naming or numbering. The execution order of named or numbered process steps can be changed according to the desired technical purpose, as long as the same or similar technical effect is achieved.

[0071] The module division described in this application is a logical division. In practical applications, there may be other division methods. For example, multiple modules may be combined or integrated into another system, or some features may be ignored or not executed. In addition, the coupling or direct coupling or communication connection between modules shown or discussed may be through some interfaces, and the indirect coupling or communication connection between modules may be electrical or other similar forms, none of which are limited in this application. Furthermore, the modules or sub-modules described as separate components may or may not be physically separated, may or may not be physical modules, or may be distributed in multiple circuit modules. Some or all of the modules may be selected to achieve the purpose of the solution in this application according to actual needs.

[0072] First, refer to Figure 1 The diagram shown represents an overall architecture of the IoT data interaction control system of this application. This IoT data interaction control system, specifically designed for the IoT data interaction control objective, comprises three main system components: ① a data transmission and reception control logic component, ② a data storage component, and ③ a storage access control logic component.

[0073] In short, the data transmission and reception control logic component is responsible for independently implementing the data transmission, reception, and conversion tasks of the IoT terminal; the data storage component is responsible for implementing the data storage and exchange tasks between the IoT terminal and the host terminal; and the storage access control logic component is responsible for independently implementing the data access control and conflict control tasks between the host terminal and the data storage component.

[0074] More specifically, there are:

[0075] 1) The data transceiver control logic unit automatically reads and writes data from the data storage unit one by one (address segment) and completes the parallel conversion of the data string. The Tx path serially sends the data to the IoT physical layer component, completing the data storage to transmission process (data storage-transmission process). On the other hand, the Rx path obtains serial data from the IoT physical layer component, completes the parallel conversion of the data string, and writes it to the data storage unit, completing the data reception to storage process (data reception-storage process).

[0076] Existing IoT physical layer components include, but are not limited to, RS485, RS232, CAN, fiber optic communication modules, 433MHz or other frequency band wireless data transmission modules, 4G / 5G DTUs, and NBIoT modules.

[0077] In practice, the data transceiver control logic component can be implemented by a complex programmable logic device (CPLD), a field programmable gate array (FPGA), or an embedded microcontroller (MCU), requiring only one address for the network.

[0078] 2) The data storage component consists of a dual-port RAM and a set of registers. The dual-port RAM is composed of a data transmission and reception control logic unit and a storage access control logic unit. It randomly writes or reads data to the internal storage unit (the internal storage unit of the dual-port RAM) to realize the data transmission and reception exchange and storage function of the Internet of Things. The registers in the data storage component are divided into a send (write) request register, a receive (read) request register and an access conflict register. The data transmission and reception control logic unit and the storage access control logic unit perform ordered operations on the dual-port RAM according to the bit status in the registers to solve the access conflict and data overwrite problem.

[0079] 3) The storage access control logic component has multiple sets of data access ports and access control logic to enable conflict-free data access to the data storage component in single-host and multi-host scenarios.

[0080] The storage access control logic component can be implemented using a CPLD, FPGA, or embedded microcontroller (MCU).

[0081] For the three major system components mentioned above, in practical applications, the data transceiver control logic component and the storage access control logic component are designed independently as mutually independent hardware modules. Therefore, the host (high-speed component) and the IoT interface (low-speed component) are no longer coupled, and the problem of slowing down the host's operating efficiency due to their speed difference is solved. Simultaneously, the data transceiver control logic component and the storage access control logic component interact through a data storage component (specifically, a dual-port RAM as its core), providing data temporary storage and exchange functions, effectively achieving speed matching.

[0082] Therefore, the specific benefits that can be brought about by this overall system architecture design are as follows:

[0083] 1. The data transceiver control logic unit, in conjunction with the dual-port RAM of the data storage unit, enables the automatic transmission, reception, and storage of IoT data packets (a single data transmission or reception consisting of several bytes of binary data). The IoT host or peer node (used as the master controller) no longer needs to design complex transmission and reception timing rules and corresponding protocol stacks. Simultaneously, data transmission and reception require no intervention from the host. While the host is processing data services, the transceiver can still operate independently without "waiting" (no "idle" state), improving network data throughput and utilization efficiency.

[0084] 2. The data storage component is equipped with dual-port RAM, and according to the access requirements of IoT hosts (single host or multi-host structure), it is equipped with overlapping data storage areas (also known as overlapping storage windows) and access control logic components to solve the additional coordination problem between host nodes in IoT multi-host scenarios, improve host working efficiency, reduce host software complexity, and also solve the channel collision problem.

[0085] 3. The storage access control logic unit can simultaneously adapt to high-speed storage access on the host side and low-speed storage access on the IoT transceiver side, solving the problem of mismatch between host data throughput rate and IoT communication rate. The host does not need to "wait" for the low-speed data transmission and reception process of the IoT, thus improving the host's working efficiency.

[0086] 4. The storage access control logic does not occupy (slow down) the host's DMA process, thus improving the host's storage access efficiency;

[0087] 5. It has the ability to handle multiple concurrent random access data throughput. Taking IoT gateways as an example, it is suitable for both single-host mode IoT gateways and clustered multi-redundant supercomputing IoT gateways with parallel computing architecture. At the same time, it only occupies one address for the entire network, is fully compatible with traditional single-host mode IoT, and does not require any modification to existing network protocols, thus having good compatibility.

[0088] Furthermore, it is understood that the IoT data interaction control system of this application is used to deploy on IoT devices, which are usually IoT hosts, or IoT gateways and other IoT devices that play other types of roles in the IoT network architecture. IoT nodes involved in data transmission and reception in IoT scenarios can all be IoT devices that apply the IoT data interaction control system of this application.

[0089] Next, we will further explain the optimization schemes that can be adopted in practical applications of the IoT data interaction control system designed in this application.

[0090] refer to Figure 2The diagram shown is a structural schematic of the data transmission and reception control logic component of this application. Specifically, the data transmission and reception control logic component can be composed of a read stack (11), an internal clock source (12), a write stack (13), a data latch T (14), a shift register T (15), a shift register R (16), and a data latch R (17).

[0091] Specifically, these components include:

[0092] Reading stack (11): A set of independent hardware logic components provided by the internal clock source (12) with clk clock signal, which realizes the functions of sending request register query, dual-port RAM area data reading, data latch T (14) writing and shift register control, and completes the function of sending request query-data reading-data sending. This component can be designed and implemented by CPLD or FPGA according to VHDL language, or it can be implemented by embedded MCU through software.

[0093] Internal clock source (12): refers to the hardware circuit that can provide continuous clock pulses, consisting of a quartz crystal oscillator and an oscillation circuit;

[0094] Write stack (13): An independent hardware logic component provided with clk clock pulse signal by internal clock source (12). It realizes functions such as receiving word status query, dual-port RAM area data writing, and receiving request register status update, and completes the process of data receiving-RAM writing-status update. This component can be designed and implemented by CPLD or FPGA in VHDL language, or it can be implemented by embedded MCU in software.

[0095] Data latch T(14): Temporarily stores data to be sent to shift register T(15), and has a built-in 1-bit busy / idle flag. Optimized, depending on the frequency of the data to be sent, this component can also be implemented using First-In-First-Out (FIFO) devices with different storage depths to enhance the system's data transmission and reception throughput efficiency (batch writing can reduce the frequency of query access) and reduce the channel occupancy window time to reduce the probability of collisions;

[0096] Shift register T(15): Converts the parallel data in data latch T(14) into serial mode, shifting out bit by bit from the Tx line. This completes the parallel-to-serial conversion process.

[0097] Data latch R(17): Temporarily stores the data received by shift register R(16), and has a built-in 1-bit busy / idle flag. Preferably, depending on the frequency of the data to be sent, this component can also be implemented using FIFO devices with different storage depths.

[0098] For a single RAM structure (i.e., only one dual-port RAM or multiple dual-port RAMs for capacity expansion, where both the data to be sent and the data to be received are stored), the read stack (11) and write stack (13) share the same data-address bus. Therefore, a mutually exclusive tri-state bus buffer is set in the read stack (11) and write stack (13) to avoid bus collisions between the read stack (11) and write stack (13) on the dual-port RAM side.

[0099] Preferably, for a multi-RAM structure (i.e., storing the transmitted data and the received data in two different RAM banks respectively), the read stack (11) and write stack (13) access their respective RAM banks through mutually independent address-data buses, so there is no need to set up a mutual exclusion tri-state bus buffer.

[0100] Based on the aforementioned components, as an exemplary embodiment, the data transmission control logic component may specifically include the following processing steps in its data transmission process:

[0101] 1) After the read stack (11) queries the data latch T (14) to find that it is in an idle state, it queries the request flag bit in the send request register and reads the first data to be sent from the corresponding RAM area (there are n areas in the dual-port RAM, where n is a natural number not less than 2) according to the address vector mapped by the request flag bit in the send request register. The first data is sent into the data latch T (14) and the data latch T (14) is set to a busy state.

[0102] 2) After the shift register T(15) checks that the data latch T(14) is busy, it reads the first data from the data latch T(14) in parallel at once, sets the data latch T(14) to the idle state, and then starts to shift the first data out from the Tx line bit by bit according to the first baud rate (the preset baud rate).

[0103] The idle state ("idle") or busy state ("busy") is usually represented by the corresponding busy / idle flag, and the other states are represented / determined in the same way.

[0104] Specifically, this process can also be combined with... Figure 3 The diagram shown below illustrates a logical flow diagram of the data transmission and reception control logic component of this application to provide a more intuitive understanding.

[0105] On the other hand, as an exemplary embodiment, for the data transmission and reception control logic component, the corresponding data receiving process may specifically include the following processing content:

[0106] 1) The shift register R(16) detects the level transition edge on the Rx line and converts the high level state on the Rx line to 1 and the low level state to 0 according to the second baud rate (the preset baud rate or the baud rate obtained by detecting the time difference between two adjacent transitions), and shifts the bits into the shift register R(16) bit by bit.

[0107] 2) After shift register R(16) is full, when data latch R(17) is in an idle state, the second data in shift register R is written to data latch R(17), and data latch R(17) is set to a busy state.

[0108] 3) When the write stack (13) finds that the data latch R (17) is busy, it reads the second data in the data latch R (17) and writes the second data to the corresponding storage area in the dual-port RAM according to the address (parsing mapping) contained in the data. It sets the corresponding bit in the receive request register. If the data in the target storage area has not been read by the host during the process, it is considered that the host is abnormal (it should not affect the reception of new data, so) the newly received data directly overwrites the original data in the corresponding RAM area.

[0109] Specifically, this process can also be combined with... Figure 4 The following diagram illustrates a logic flow diagram of the data transmission and reception control logic component of this application to provide a more intuitive understanding.

[0110] It is understandable that the above two embodiments, or the data interaction methods of the data transmission and reception control logic components, effectively solve the problem of independent data transmission and reception at the IoT end, making IoT data transmission and reception completely isolated from the host, eliminating the system overhead of the host in serial data transmission and reception, and the host's business processing speed is no longer limited by the speed of IoT.

[0111] In addition, for the data transmission and reception control logic unit, the corresponding address mapping methods are:

[0112] It is equipped with a transmit request register and a receive request register of variable length. Figure 2 As shown in the figure, let the value of the register be R). Each bit in the register corresponds to an IoT host. In order to test whether a certain bit is set to 1 (a send request or receive request has occurred), a mask q is set (the value of q is shifted left or right by one bit in sequence). Then the bit weight code value of a certain IoT host is P = R ∧ q.

[0113] The structure of the send / receive request register is shown in the table below:

[0114] Table 1 - Example of Send / Receive Request Register Structure

[0115]

[0116] When there is a send request event or receive request event, the corresponding bit is set to "1"; when there is no send request event or receive request event, the corresponding bit is cleared to "0".

[0117] Assume the current value of register R is 0b0…11001 (binary code value).

[0118] To test if host 1 has any requests, the mask q value should be 0b000…01.

[0119] Its positional weight code value P = R ∧ q = 0b0…11001 ∧ 0b0…00001 = 0b0…00001,

[0120] P > 0: This indicates that there is an access request event.

[0121] To test if host 2 has any requests, the mask q value should be 0b000…10.

[0122] Its positional weight code value P = R ∧ q = 0b0…11001 ∧ 0b0…00010 = 0b0…00000\,

[0123] P=0: This indicates that there were no access request events.

[0124] Based on the actual data packet length in the usage scenario, a fixed-size memory unit area block m is set for the host (e.g., m = 64 bytes / block).

[0125] The address An mapping formula for host n is:

[0126]

[0127] When the P value is greater than 0, it indicates that a memory access (send or receive) request event has occurred, and the address mapping is meaningful.

[0128] Conversely, when the P value is 0, it means that the memory region corresponding to the host does not need to be read or written, and the address mapping is meaningless (no operation is required).

[0129] Next, we focus on the data storage component in the IoT data interaction control system. As an exemplary embodiment, the data storage component can specifically include:

[0130] The send request register stores the request flag bit of the host to send data to the IoT terminal; the receive request register stores the request flag bit of the IoT terminal to notify the host to retrieve the data after the IoT terminal has received a frame of data and written it into the corresponding RAM area; the dual-port RAM stores the data to be sent or received; and the access conflict register stores the flag bit of the access conflict that occurs when the host and IoT terminal access the same address unit in the dual-port RAM at the same time.

[0131] The conditions for an access conflict to occur are as follows:

[0132] 1) The host and IoT terminals simultaneously perform write operations on the same address unit of the dual-port RAM;

[0133] 2) When the host or IoT device reads from the same address unit of the dual-port RAM, the other end performs a write operation.

[0134] 3) When writing to the same address unit of the dual-port RAM on the host or IoT end, the other end performs a read operation;

[0135] When an access conflict occurs, the BUSY line of the dual-port RAM remains low. When the conflict condition is lifted, the BUSY line of the dual-port RAM returns to high. When the host or IoT device operates on the dual-port RAM cell, it queries the access conflict register or the status of the BUSY line of the dual-port RAM, freezes the operation, and waits for the cancellation before continuing the previous read and write operation to resolve the access conflict problem.

[0136] Further reference Figure 5 The diagram illustrates a logical representation of a parallel bus access mode for the data storage component of this application. Specifically, for the data storage component, under the condition of using a parallel bus on the host side (A side), the following can be defined:

[0137] The address bus is connected to the address bus interface corresponding to the dual-port RAM (21), and the data bus is connected to the data bus interface corresponding to the dual-port RAM (21). The read signal RD, write signal WR, and conflict signal BUSY are connected to the corresponding signal interfaces. The conflict signal BUSY is connected to the main nWait signal or external interrupt signal pin. The send request register (22) and receive request register (23) are connected to the host's data address bus (data bus and address bus, unified addressing mode) or an IO interface independent of the data address bus.

[0138] Preferably, the send request register (22) and receive request register (23) directly use the storage units in the dual-port RAM (21) and are integrated with the dual-port RAM (21) without the need for additional register hardware. The dual-port RAM (21) can be composed of a single dual-port RAM or multiple dual-port RAMs (to expand the capacity or to configure dedicated RAM for different hosts).

[0139] The same configuration is applied to the IoT (B-end) side.

[0140] On the other hand, reference Figure 6The diagram illustrates a logical representation of a serial bus access mode for the data storage component of this application. Specifically, for the data storage component, under the condition of using a serial bus (such as a high-speed SPI bus or other buses) on the host side (A side), the following can be observed:

[0141] A single host or multiple hosts are connected to the same SPI bus, or they are each connected to different SPI buses (parallel conflict-free access) and connected to their respective dual-port RAM (21) (i.e. dual-port RAM-[1,2,..,n]). The send request register (22), receive request register (23) and the access conflict signal BUSY of the dual-port RAM (21) are respectively mapped to the corresponding bits in the access conflict register A (24) and access conflict register B (25). The access conflict register A (24) is connected to the host's data bus or IO port for querying.

[0142] The IoT terminal (B terminal) is similar to the above method. The read stack (11) and write stack (13) can access the dual-port RAM (21), send request register (22) and receive request register (23) through the SPI bus. The access conflict register B (25) is connected to the IO port of the read stack (11) and write stack (13) for querying.

[0143] Furthermore, the access conflict register structure can be shown in the following table:

[0144] Table 2 - Examples of Access Conflict Register Structures

[0145]

[0146] When a conflict occurs, the corresponding bit in the host is set to 1; otherwise, it is cleared to 0, or inverted as required by the circuit logic (positive logic / negative logic).

[0147] It is understandable that the above two embodiments, or the working modes of the data storage components, based on the dual-port RAM (21), the send request register (22), and the receive request register (23), provide specific dual-port RAM data storage organization schemes and data read / write coordination methods.

[0148] Next, we focus on the storage access control logic component in the IoT data interaction control system, which involves three access modes and has different design schemes.

[0149] As an exemplary embodiment, see [reference]. Figure 7 The diagram shown illustrates a logic schematic of the storage access control logic unit in the parallel bus host access mode of this application. Specifically, under the condition of parallel bus host (mutually exclusive) access mode, the storage access control logic unit can have the following features:

[0150] The storage access control logic unit consists of a first bus arbitration logic unit (31), a first bus transformation logic array (32), and a first access permission register (33);

[0151] Dual-port RAM (21) (located in) Figure 7 The BUSY signal of the data source component (A side component) shown in the dashed box is connected to the first bus arbitration logic component (31) for reading, and the external memory access chip select signal CE (CE-[1,2,..,n]) of each host (host-[1,2,..,n]) is connected to the first bus arbitration logic component (31) respectively.

[0152] The first bus arbitration logic unit (31) queries the current chip select signal (host access request) and the BUSY signal of the dual-port RAM (21). If there is a request and no access conflict (no BUSY signal), the corresponding bit in the first access permission register (33) is set. The logic level of the corresponding bit in the first access permission register (33) is determined and circuit-connected to the output enable OE pin of the bus tri-state buffer of the corresponding host, so that the bus is effectively connected. Conversely, if there is no request or an access conflict exists, the corresponding bit in the first access permission register (33) is cleared. The output enable OE pin of the bus tri-state buffer of the corresponding host is invalid, and the host is in a high impedance state to the bus, which does not cause bus conflict for other valid access hosts.

[0153] When the first bus arbitration logic unit (31) decides that a specific host access is valid, it simultaneously sets the multiplexer in the first bus transformation logic array (32) to be valid, so that the control bus, address bus and data bus of the corresponding specific host are connected to the bus corresponding to the data storage unit.

[0154] If an access conflict occurs during the reading and writing of the dual-port RAM (21) by the host, the first bus arbitration logic unit (31) cancels the output enable OE signal of the host bus tri-state buffer according to the BUSY signal of the dual-port RAM (21), so that the corresponding host is disconnected from the dual-port RAM (21) bus, in order to solve the problem of unreliable data reading and writing when a conflict occurs. The value of the first access permission register (33) is available for the corresponding host to query through the IO port. If the host finds that the corresponding access permission bit has been revoked, it enters a delayed waiting state. The window time for this conflict is extremely short and the probability of occurrence is extremely low, so it will hardly affect the speed of the host.

[0155] Among them, host (mutually exclusive) access refers to the following: when multiple IoT hosts share the same parallel bus, in order to avoid bus conflicts, it is agreed that only one host is allowed to connect to the bus at a time, and the other hosts use a tri-state buffer to maintain high impedance to the bus.

[0156] The tri-state buffer uses a common tri-state gate device, which is an essential device for parallel buses and can be designed and used by each IoT host within its own scope.

[0157] The first bus arbitration logic unit (31) can decide multiple chip select request signals CE (CE-[1,2,..,n]) in a round-robin manner, in a priority manner, or in a combination of the two (round-robin within the group, priority between groups) to meet the application requirements of different scenarios.

[0158] The corresponding access permission register structure can be seen in the table below:

[0159] Table 3 - Examples of Access Permission Register Structures

[0160]

[0161] Only one bit (master) can be set to the enabled state by the first bus arbitration logic unit (31) at any time, while the other bits are disabled to avoid bus conflicts.

[0162] The corresponding business logic process can also be referenced. Figure 8 The following diagram illustrates a logic diagram of the storage access control logic component of this application for parallel bus host access, which can be used to provide a more intuitive understanding.

[0163] As an exemplary embodiment, see [reference]. Figure 9 The diagram shown illustrates a logic schematic of the storage access control logic unit in serial bus access mode. Specifically, under serial bus access mode, the storage access control logic unit can have the following features:

[0164] The storage access control logic unit consists of a second bus arbitration logic unit (31) and a second access permission register (33);

[0165] Access conflict register A(24) of the data storage component (located in) Figure 9 The data storage component shown in the dashed box is connected to the second bus arbitration logic component (31) for reading. Each host (host-[1,2,..,n]) uses two IO lines as request IO lines and permission query IO signal lines. The request IO lines are connected to the second bus arbitration logic component (31), and the permission query IO signal lines are connected to the output pin of the second access permission register (33).

[0166] The second bus arbitration logic unit (31) queries the current access request signal and the bit value in the access conflict register A (24). If there is a request and no access conflict, the corresponding bit in the second access permission register (33) is set. After the corresponding bit in the second access permission register (33) is queried by the corresponding host or accessed in interrupt mode, the data read and write process of the SPI serial bus is started. Conversely, if there is no request or an access conflict exists, the corresponding bit in the second access permission register (33) is cleared. Then, if the access permission is invalid, the corresponding host will not start the SPI bus data read and write process and will not cause bus conflict to other valid access hosts.

[0167] The second bus arbitration logic unit (31) can decide multiple chip select request signals CE (CE-[1,2,..,n]) in a round-robin manner, in a priority manner, or in a combination of the two (round-robin within a group, priority between groups) to meet the application requirements of different scenarios.

[0168] The corresponding business logic process can also be referenced. Figure 8 To gain a more vivid understanding.

[0169] As an exemplary embodiment, see [reference]. Figure 10 The diagram shown illustrates a storage access control logic unit in a fully parallel access mode. Specifically, under the fully parallel access mode, the storage access control logic unit can have the following characteristics:

[0170] The storage access control logic unit consists of multiple write-ahead stacks (34), multiple read-behind stacks (35), a write controller (37), and a read controller (38);

[0171] Each host (host-[1,2,..,n]) is connected to the corresponding preceding write stack (34) and following read stack (35) through its own bus (parallel or serial bus). Each host is independent of each other and does not affect each other, and works in full parallel.

[0172] The write controller (37) is connected to the send request register (22). The data, address, and control buses of the write controller (37) are connected to the dual-port RAM (21) via the corresponding tri-state driver. The read controller (38) is connected to the receive request register (23). The data, address, and control buses of the read controller (38) are connected to the dual-port RAM (21) via the corresponding tri-state driver. The write controller (37) and the read controller (38) are connected by a dedicated request IO bus.

[0173] In the transmission priority rule, after any host writes new data to be transmitted into the corresponding advance write stack (34), it sets the transmission request storage unit value in the corresponding advance write stack (34). The write controller (37) polls the transmission request storage units in each advance write stack (34) at a certain interval. If it finds that there is data to be transmitted, it pulls the bus exclusive request IO between itself and the corresponding read controller (38) high to indicate that data is about to be written to the dual-port RAM (21). After the read controller (38) obtains the current state through polling or interrupt mode, it cancels its own tri-state drive. The output of the actuator is enabled, and the bus is given to the write controller (37) for use. The write controller (37) enables the output of its own tri-state driver, acquires the bus and writes data to the dual-port RAM (21). After writing the data, the write controller (37) clears the flag bit of the send request storage unit in the corresponding advance write stack (34), sets the flag bit of the host in the send request register (22), and pulls down the bus exclusive request IO between the controller and the corresponding read controller (38) to indicate that the writing process is over and gives the bus to the read controller (38) for use.

[0174] In the receiving priority rule, the reading controller (38) obtains the value of the receiving request register (23) in polling or interrupt mode. If a flag bit is set, it immediately pulls down the bus exclusive request IO between itself and the reading controller (38) to indicate that data is about to be read from the dual-port RAM (21). After the writing controller (37) obtains the current state through polling or interrupt mode, it cancels the output enable of its own tri-state driver and gives the bus to the reading controller (38) for use. The reading controller (38) enables the output enable of its own tri-state driver, obtains the bus, reads the data from the dual-port RAM (21), and sends the data into the corresponding host's subsequent reading stack (35). At the same time, it clears the corresponding bit in the receiving request register (23) to indicate that the data has been taken. After reading the data, it sets the read data request storage unit value in the subsequent reading stack (35) and pulls up the bus exclusive request IO between itself and the writing controller (37) to indicate that the reading process is over and gives the bus to the writing controller (37) for use.

[0175] The sending priority rule, or the writing process, can also be found in the following references. Figure 11 The diagram shown illustrates a logic representation of the storage access control logic unit in this application during the write operation in fully parallel access mode, providing a more intuitive understanding. For the receive priority rule, or the read operation process, please refer to... Figure 12 The following diagram illustrates a logic diagram of the storage access control logic unit of this application during the reading process in fully parallel access mode, for a more intuitive understanding.

[0176] For the two rules mentioned above, one can be selected based on application requirements. Alternatively, the rules can be dynamically switched within the application according to different business needs. The corresponding switching methods are as follows:

[0177] Any host computer sends a special (design convention) data message to the write controller (37) through the advance write stack (34). After receiving the message, the write controller (37) executes it according to the set rules. At the same time, through the single-wire asynchronous serial communication mode, the switch command is sent to the read controller (38) via the "work coordination control line" between the read controller (38). After receiving the message, the read controller (38) executes it according to the set rules.

[0178] In the above process, the host only needs to write or read data to the preceding write stack (34) or the following read stack (35). Each host works completely independently and in parallel. The host does not need to wait for the dual-port RAM (21) conflict backoff window, nor does it need to wait for the data bus exclusive window. When the bus is exclusively occupied (within the read / write freeze window), it is only the internal bus of the storage access control logic unit that is frozen, and it does not affect the host's operation on the preceding write stack (34) or the following read stack (35). Therefore, for a matrix parallel array host cluster, this system is functionally a conflict-free parallel access response.

[0179] Optimized, in Figure 10 In this design, the dual-port RAM (21) can adopt a scheme where the physical devices for "writing" and "reading" are separate. That is, the write controller (37) and the read controller (38) no longer share the same bus, but are connected to their respective dual-port RAM chip devices. There is no need for bus backoff coordination between them, which simplifies the control process and eliminates the need for bus backoff coordination. Figure 11 , Figure 12 The "read / write freeze window" can be used, but it requires additional RAM devices.

[0180] It is understandable that the above three embodiments, or the three working modes of the storage access control logic unit, provide specific coordination and optimization methods while offering specific conflict-free memory access modes.

[0181] In conclusion, this application presents a novel IoT device interaction control system architecture. This architecture eliminates the need for complex timing rules and protocol stacks for data transmission and reception. Whether in single-host or multi-host scenarios, it enables automatic sending, receiving, and storage of IoT data packets, significantly improving work efficiency, reducing software complexity, effectively avoiding channel collisions, and ensuring high compatibility. With its high-quality IoT data interaction control performance, it possesses significant application value.

[0182] Meanwhile, based on the IoT data interaction control system provided in this application, this application can also provide IoT devices that include or are equipped with the IoT data interaction control system. The specific device type of the IoT device can be the IoT host, IoT gateway, or other specific types of devices mentioned above.

[0183] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific configuration details of the IoT devices described above can be found in, for example... Figure 1 The description of the IoT data interaction control system in the corresponding embodiment will not be repeated here.

[0184] The IoT data interaction control system and IoT device provided in this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. An Internet of Things (IoT) data interaction control system, characterized in that, The IoT data interaction control system includes a data transmission and reception control logic component, a data storage component, and a storage access control logic component. The data transmission and reception control logic component is responsible for independently implementing the data transmission, reception, and conversion tasks of the IoT terminal. The data storage component is responsible for implementing the data storage and exchange tasks between the IoT terminal and the host terminal. The storage access control logic component is responsible for independently implementing the data access control and conflict control tasks between the host terminal and the data storage component. The data transceiver control logic unit automatically reads and writes data from the data storage unit one by one and completes parallel conversion of the data string. The Tx path serially sends data to the IoT physical layer component to complete data storage and transmission. On the other hand, the Rx path obtains serial data from the IoT physical layer component, completes the parallel conversion of the data string, and writes it into the data storage unit to complete data reception and storage. The data storage component consists of a dual-port RAM and a set of registers. The dual-port RAM is randomly written to or read from internal storage units by the data transceiver control logic component and the storage access control logic component to realize the data exchange and storage function of IoT. The registers are divided into a send request register, a receive request register and an access conflict register. The data transceiver control logic component and the storage access control logic component perform ordered operations on the dual-port RAM according to the bit state in the registers to solve access conflicts and data overwriting problems. The storage access control logic component has multiple sets of data access ports and access control logic to enable conflict-free data access to the data storage component in both single-host and multi-host scenarios. The data transmission and reception control logic unit and the storage access control logic unit are independent hardware modules.

2. The Internet of Things (IoT) data interaction control system according to claim 1, characterized in that, The data transceiver control logic unit consists of a read stack, an internal clock source, a write stack, a data latch T, a shift register T, a shift register R, and a data latch R. For the data transmission and reception control logic component, the corresponding data transmission process includes the following processing steps: After the reading stack checks that the data latch T is in an idle state, it then checks the request flag bit in the send request register, and reads the first data to be sent from the corresponding RAM area according to the address vector mapped by the request flag bit in the send request register, sends the first data into the data latch T, and sets the data latch T to a busy state. After the shift register T checks that the data latch T is busy, it reads the first data from the data latch T in parallel at once, sets the data latch T to an idle state, and then starts shifting the first data out from the Tx line bit by bit at the first baud rate.

3. The Internet of Things (IoT) data interaction control system according to claim 2, characterized in that, For the data transmission and reception control logic component, the corresponding data receiving process includes the following steps: The shift register R detects the level transition edge on the Rx line, and converts the high level state on the Rx line to 1 and the low level state to 0 according to the second baud rate, and shifts the bits into the shift register R bit by bit; After the shift register R is full, when the data latch R is in an idle state, the second data in the shift register R is written into the data latch R, and the data latch R is set to a busy state. When the write stack detects that the data latch R is busy, it reads the second data in the data latch R and writes the second data to the corresponding storage area in the dual-port RAM according to the address contained in the data. It sets the corresponding bit in the receive request register. If the data in the target storage area has not been read by the host during the process, it is considered that the host is abnormal and the newly received data directly overwrites the original data in the corresponding RAM area.

4. The Internet of Things (IoT) data interaction control system according to claim 1, characterized in that, For the data storage component, we have: The send request register stores the request flag bit of the host to send data to the IoT terminal. The receive request register stores the request flag bit of the IoT terminal to notify the host to retrieve the data after receiving a frame of data and writing it into the corresponding RAM area. The dual-port RAM stores data to be sent or received. The access conflict register stores the flag bit when an access conflict occurs when the host and the IoT terminal access the same address unit in the dual-port RAM at the same time. The conditions for an access conflict to occur are as follows: 1) The host terminal and the IoT terminal simultaneously perform write operations on the same address unit of the dual-port RAM; 2) When the host or the IoT terminal reads from the same address unit of the dual-port RAM, the other end performs a write operation. 3) When the host or the IoT terminal writes to the same address unit of the dual-port RAM, the other end performs a read operation; When an access conflict occurs, the BUSY line of the dual-port RAM remains low. When the conflict condition is lifted, the BUSY line of the dual-port RAM returns to high. When the host or the IoT device operates on the dual-port RAM unit, it queries the access conflict register or the status of the BUSY line of the dual-port RAM, freezes the operation, and waits for the cancellation before continuing the previous read and write operation to resolve the access conflict problem.

5. The Internet of Things (IoT) data interaction control system according to claim 4, characterized in that, For the data storage component, under the condition of the host side using a parallel bus, the following applies: The address bus is connected to the address bus interface corresponding to the dual-port RAM, and the data bus is connected to the data bus interface corresponding to the dual-port RAM. The read signal RD, write signal WR, and conflict signal BUSY are connected to the corresponding signal interfaces. The conflict signal BUSY is connected to the main nWait signal or an external interrupt signal pin. The send request register and the receive request register are connected to the host's data address bus or an I / O interface independent of the data address bus. The send request register and the receive request register directly use the storage units in the dual-port RAM and are integrated with the dual-port RAM.

6. The Internet of Things (IoT) data interaction control system according to claim 4, characterized in that, For the data storage component, under the condition of the host side using a serial bus, the following applies: A single host or multiple hosts are connected to the same SPI bus, or each is connected to a different SPI bus and connected to its corresponding dual-port RAM. The transmit request register, the receive request register, and the access conflict signal BUSY of the dual-port RAM are respectively mapped to the corresponding bits in the access conflict register A and the access conflict register B. The access conflict register A is connected to the data bus or I / O port of the host for querying.

7. The Internet of Things (IoT) data interaction control system according to claim 4, characterized in that, For the aforementioned storage access control logic unit, under the condition of parallel bus host access mode, we have: The storage access control logic unit consists of a first bus arbitration logic unit, a first bus transformation logic array, and a first access permission register. The BUSY signal of the dual-port RAM is connected to the first bus arbitration logic unit for reading, and the external memory access chip select signal CE of each host is connected to the first bus arbitration logic unit respectively. The first bus arbitration logic unit queries the current chip select signal and the BUSY signal of the dual-port RAM. If there is a request and no access conflict, the corresponding bit in the first access permission register is set. The logic level of the corresponding bit in the first access permission register determines and circuitically connects to the output enable OE pin of the bus tri-state buffer of the corresponding host, so that the bus is effectively connected. If there is no request or an access conflict exists, the corresponding bit in the first access permission register is cleared. The output enable OE pin of the bus tri-state buffer of the corresponding host is invalid, the host is in a high impedance state to the bus, and no bus conflict is caused to other valid hosts. When the first bus arbitration logic unit decides that access to a specific host is valid, it simultaneously sets the multiplexer in the first bus transformation logic array to be valid, so that the control bus, address bus and data bus corresponding to the specific host are connected to the bus corresponding to the data storage unit. If an access conflict occurs during the reading and writing of the dual-port RAM by the host, the first bus arbitration logic unit cancels the output enable signal OE of the host bus tri-state buffer according to the BUSY signal of the dual-port RAM, thereby disconnecting the corresponding host from the dual-port RAM bus to solve the problem of unreliable data reading and writing when a conflict occurs. The value of the first access permission register is available for the corresponding host to query through the IO port. If the host finds that the corresponding access permission bit has been revoked, it enters a delayed waiting state.

8. The Internet of Things (IoT) data interaction control system according to claim 4, characterized in that, For the aforementioned storage access control logic unit, under the condition of serial bus access mode, we have: The storage access control logic unit consists of a second bus arbitration logic unit and a second access permission register. The access conflict register A of the data storage component is connected to the second bus arbitration logic component for reading. Each host uses two IO lines as request IO lines and permission query IO signal lines. The request IO lines are connected to the second bus arbitration logic component and the permission query IO signal lines are connected to the output pin of the second access permission register. The second bus arbitration logic unit queries the current access request signal and the bit value in the access conflict register A. If there is a request and no access conflict, the corresponding bit in the second access permission register is set. After the corresponding bit in the second access permission register is queried by the corresponding host or accessed in interrupt mode, the data read / write process of the SPI serial bus is started. If there is no request or an access conflict exists, the corresponding bit in the second access permission register is cleared. In the case of invalid access permission, the corresponding host will not start the SPI bus data read / write process and will not cause bus conflict for other valid access hosts.

9. The Internet of Things (IoT) data interaction control system according to claim 1, characterized in that, For the aforementioned storage access control logic unit, under the condition of fully parallel access mode, we have: The storage access control logic unit consists of multiple write-ahead stacks, multiple read-before stacks, a write controller, and a read controller. Each host is connected to the corresponding preceding write stack and the following read stack via its own bus. The hosts are independent of each other and do not affect each other, working in full parallel. The write controller is connected to the send request register. The data, address, and control bus of the write controller are connected to the dual-port RAM via the corresponding tri-state driver. The read controller is connected to the receive request register. The data, address, and control bus of the read controller are connected to the dual-port RAM via the corresponding tri-state driver. The write controller and the read controller are connected by a dedicated request I / O bus. In the transmission priority rule, after any host writes new data to be transmitted into the corresponding advance write stack, it sets the value of the transmission request storage unit in the corresponding advance write stack. The write controller polls the transmission request storage units in each advance write stack at a certain interval. If it finds data to be transmitted, it pulls the bus exclusive request IO between itself and the corresponding read controller high to indicate that data is about to be written to the dual-port RAM. After the read controller obtains the current state through polling or interrupt mode, it cancels the output enable of its own tri-state driver and yields the bus to the write controller. The write controller enables the output enable of its own tri-state driver, acquires the bus, and writes data to the dual-port RAM. After writing the data, the write controller clears the flag bit of the transmission request storage unit in the corresponding advance write stack, sets the flag bit of the host in the transmission request register, pulls the bus exclusive request IO between itself and the corresponding read controller low to indicate that the writing process is over and yields the bus to the read controller. In the receive priority rule, after the read controller obtains the value of the receive request register in polling or interrupt mode, if a flag bit is set, it immediately pulls down the bus exclusive request IO between itself and the read controller, indicating that data is about to be read from the dual-port RAM. After the write controller obtains this state through polling or interrupt mode, it cancels the output enable of its own tri-state driver, yielding the bus to the read controller. The read controller then enables the output of its own tri-state driver, obtains the bus, reads the data from the dual-port RAM, and sends the data into the corresponding host's subsequent read stack. At the same time, it clears the corresponding bit in the receive request register to indicate that the data has been taken. After reading the data, it sets the read data request storage unit value in the subsequent read stack, pulls up the bus exclusive request IO between itself and the write controller to indicate that the reading process is over, and yields the bus to the write controller.

10. An Internet of Things (IoT) device, characterized in that, The IoT device is equipped with an IoT data interaction control system as described in any one of claims 1 to 9.

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