Display device and manufacturing method thereof

Abstract

The invention relates to a display device and a method for manufacturing the same. The display device includes a first pixel electrode and a second pixel electrode spaced apart from each other on a substrate; a pixel defining layer disposed on the substrate and exposing the first pixel electrode and the second pixel electrode; a bank disposed on the pixel defining layer; a first light emitting layer disposed on the first pixel electrode; a second light emitting layer disposed on the second pixel electrode; a first common electrode disposed on the first light emitting layer; and a second common electrode disposed on the second light emitting layer and the bank and spaced apart from the first common electrode, in which a width of the first common electrode and a width of the second common electrode are different from each other.

Description

[0001] Cross - reference to related applications

[0002] This application claims priority to and all benefits arising from Korean Patent Application No. 10 - 2023 - 0176570, filed on December 7, 2023, the content of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates to a display device and a method of manufacturing the same. Background Art

[0004] With the development of the information society, the demand for display devices for displaying images has increased in various forms. For example, display devices are being applied to various electronic devices such as smart phones, digital cameras, laptop computers, navigation devices, and smart TVs. The display device may be a flat panel display device such as a liquid crystal display device, a field emission display device, or an organic light - emitting display device. Among flat panel display devices, a self - emissive display device may include light - emitting elements, where each of the pixels in the display panel can emit light by itself, thereby displaying an image without a backlight unit that provides light to the display panel.

[0005] Recently, display devices are being applied to glasses - type devices to provide virtual reality and augmented reality. In order to apply a display device to a glasses - type device, it is desirable for the display device to be implemented in a relatively small size of two inches or less, but in order to achieve a relatively high resolution, the display device needs to have a relatively high pixel integration. In an embodiment, the display device may have a relatively high pixel integration of 400 pixels per inch (“PPI”) or more.

[0006] As described above, when a display device is implemented in a relatively small size but has a relatively high pixel integration, since the area of the light - emitting region where the light - emitting elements are disposed is reduced, it is difficult to implement light - emitting elements separated for each light - emitting region using a mask process. Summary of the Invention

[0007] A feature of the present disclosure provides a display device capable of forming light - emitting elements separated for each light - emitting region without using a mask process.

[0008] Another feature of the present disclosure provides a display device having a substantially small light - emission deviation and excellent brightness among a plurality of light - emitting elements.

[0009] However, the features of the present disclosure are not limited to those described herein. Through reference to the detailed description of the present disclosure given below, the above and other features of the present disclosure will become more apparent to those of ordinary skill in the art to which the present disclosure pertains.

[0010] In an embodiment of the present disclosure, a display device includes: a substrate; a first pixel electrode and a second pixel electrode spaced apart from each other on the substrate; a pixel defining layer disposed on the substrate and exposing the first pixel electrode and the second pixel electrode; a bank disposed on the pixel defining layer; a first light-emitting layer disposed on the first pixel electrode; a second light-emitting layer disposed on the second pixel electrode; a first common electrode disposed on the first light-emitting layer; and a second common electrode disposed on the second light-emitting layer and the bank and spaced apart from the first common electrode, wherein the widths of the first common electrode and the second common electrode are different from each other.

[0011] In an embodiment, the width of the first common electrode may be less than the width of the second common electrode.

[0012] In an embodiment, the width of the first common electrode may be less than the width of the first pixel electrode, and the width of the second common electrode may be greater than the width of the second pixel electrode.

[0013] In an embodiment, the first common electrode may be disposed on at least a part of a first side surface of the bank and at least a part of a second side surface of the bank different from the first side surface, and the second common electrode may be disposed on an entire third side surface of the bank, at least a part of a fourth side surface of the bank different from the third side surface, and at least a part of an upper surface of the bank.

[0014] In an embodiment, the bank may be a single film of metal or metal alloy.

[0015] In an embodiment, the display device may further include: a first inorganic layer including a main body portion disposed on the first common electrode and a wing portion disposed on the bank and spaced apart from an upper surface of the bank; and a second inorganic layer including a main body portion disposed on the second common electrode and a connecting portion disposed between the bank and the wing portion of the first inorganic layer.

[0016] In an embodiment, the connecting portion of the second inorganic layer may include a side surface that protrudes farther than a side surface of the bank and overlaps with the first pixel electrode.

[0017] In an embodiment, the wing portion of the first inorganic layer may overlap with the second common electrode in a thickness direction of the substrate.

[0018] In an embodiment, a lower surface of the connecting portion of the second inorganic layer may contact the first inorganic layer.

[0019] In an embodiment, the second inorganic layer may further include: a first wing portion disposed on the wing portion of the first inorganic layer and spaced apart from an upper surface of the wing portion of the first inorganic layer; and a second wing portion disposed on the bank and spaced apart from an upper surface of the bank.

[0020] In an embodiment, the display device may further include: a third pixel electrode disposed on the substrate and spaced apart from the first pixel electrode and the second pixel electrode; a third light-emitting layer disposed on the third pixel electrode; and a third common electrode disposed on the third light-emitting layer and the bank and spaced apart from the first common electrode and the second common electrode.

[0021] In an embodiment, the third common electrode is disposed on the entire fifth side surface of the bank, the entire sixth side surface of the bank different from the fifth side surface, and at least a part of the upper surface of the bank.

[0022] In an embodiment, the width of the third common electrode disposed on the upper surface of the bank may be different from the width of the second common electrode disposed on the upper surface of the bank.

[0023] In an embodiment, the display device may further include an organic encapsulation layer disposed between the wing portion of the first inorganic layer and the first wing portion of the second inorganic layer.

[0024] In an embodiment of the present disclosure, the display device includes: a substrate; a first pixel electrode, a second pixel electrode, and a third pixel electrode spaced apart from each other on the substrate; a pixel defining layer disposed on the substrate and exposing the first pixel electrode, the second pixel electrode, and the third pixel electrode; a bank disposed on the pixel defining layer; a first light-emitting layer and a first common electrode, the first light-emitting layer being on the first pixel electrode and the first common electrode being on the first light-emitting layer; a second light-emitting layer and a second common electrode, the second light-emitting layer being disposed on the second pixel electrode and the second common electrode being on the second light-emitting layer; a third light-emitting layer and a third common electrode, the third light-emitting layer being disposed on the third pixel electrode and the third common electrode being on the third light-emitting layer; and a first inorganic layer including a main body portion disposed on the first common electrode and a wing portion disposed on the bank and spaced apart from the upper surface of the bank, wherein the wing portion of the first inorganic layer overlaps with the second common electrode and the third common electrode in the thickness direction of the substrate.

[0025] In an embodiment, the display device may further include a second inorganic layer including a main body portion disposed on the second common electrode and a connecting portion disposed between the bank and the wing portion of the first inorganic layer, wherein the connecting portion of the second inorganic layer includes a side surface that protrudes farther than the side surface of the bank and overlaps with the first pixel electrode.

[0026] In an embodiment, the first common electrode, the second common electrode, and the third common electrode have different cross-sectional shapes from each other.

[0027] In an embodiment of the present disclosure, a method for manufacturing a display device includes: forming a plurality of pixel electrodes spaced apart from each other on a substrate, forming a pixel defining material layer on the plurality of pixel electrodes, and forming a bank material layer on the pixel defining material layer; forming a first photoresist pattern on the bank material layer; etching the bank material layer not covered by the first photoresist pattern; and etching side surfaces of the bank material layer and exposing a lower surface of the first photoresist pattern.

[0028] In an embodiment, etching the bank material layer not covered by the first photoresist pattern includes an anisotropic dry etching process, and etching side surfaces of the bank material layer and exposing a lower surface of the first photoresist pattern includes an isotropic wet etching process.

[0029] In an embodiment, the method may further include: forming a first light emitting layer on a first pixel electrode among the plurality of pixel electrodes, and forming a first light emitting pattern on the first photoresist pattern; forming a first common electrode on the first light emitting layer, and forming a first electrode pattern on the first light emitting pattern; forming a first inorganic material layer on the first common electrode and the first electrode pattern; forming a second photoresist pattern on the first inorganic material layer overlapping with the first pixel electrode; removing the first inorganic material layer not covered by the second photoresist pattern; and removing the first photoresist pattern, the second photoresist pattern, the first light emitting pattern, and the first electrode pattern.

[0030] Details of other embodiments are included in the detailed description and the drawings.

[0031] According to the display device and its manufacturing method in the embodiment, the display device may include common electrodes having different shapes or widths for each light emitting region. As the contact area between the common electrode and the bank increases, the light emitting characteristics of the display device can be improved.

[0032] However, the effects of the embodiments are not limited to the effects described herein. By referring to the claims, the above and other effects of the embodiments will become more apparent to those of ordinary skill in the art to which the embodiments pertain. Description of the Drawings

[0033] By referring to the drawings to describe the embodiments of the present disclosure in detail, the above and other advantages and features of the present disclosure will become more apparent. In the drawings:

[0034] Figure 1 is a perspective view of an embodiment of the display device;

[0035] Figure 2 is a cross-sectional view of the Figure 1 display device observed from the side;

[0036] Figure 3is a plan view showing an embodiment of the arrangement of the light-emitting regions of a display device;

[0037] Figure 4 is a exploded perspective view showing the stack of the light-emitting element layer and the lower inorganic encapsulation layer in region A1 of Figure 3 ;

[0038] Figure 5 is a cross-sectional view showing an embodiment of a part of the display device;

[0039] Figure 6 is a magnified view showing Figure 5 region A21 of

[0040] Figures 7 to 9 are cross-sectional views respectively showing in detail the first inorganic layer to the third inorganic layer in Figure 6 ;

[0041] Figure 10 is a cross-sectional view of another embodiment of a part of the display device;

[0042] Figure 11 is a cross-sectional view of another embodiment of a part of the display device; and

[0043] Figures 12 to 29 is a cross-sectional view showing an embodiment of the process for manufacturing the display device in sequence. DETAILED DESCRIPTION

[0044] Embodiments of the present disclosure will now be described more fully hereinafter with reference to the accompanying drawings, in which preferred embodiments of the invention are shown. However, the invention may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.

[0045] It will also be understood that when a layer is referred to as being "on" another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may also be present. Throughout the specification, like reference numerals refer to like components.

[0046] It will be understood that although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, without departing from the teachings of the invention, the first element discussed below could be termed the second element. Similarly, the second element could also be termed the first element.

[0047] Hereinafter, embodiments will be described with reference to the drawings.

[0048] Figure 1 This is a perspective view showing an embodiment of a display device.

[0049] Reference Figure 1 , in the embodiment, the display device 10 is included in an electronic device and can provide a screen displayed on the electronic device. The electronic device can represent all electronic devices that provide a display screen. In the embodiment, for example, the electronic device can include a television, a laptop computer, a monitor, a billboard, an Internet of Things device, a mobile phone, a smartphone, a tablet personal computer (“PC”), an electronic watch, smart glasses, a smartwatch, a watch phone, a head-mounted display, a mobile communication terminal, an electronic notebook, an e-book, a portable multimedia player (“PMP”), a navigator, a game console, a digital camera, a video camera, etc. that provide a display screen.

[0050] The shape of the display device 10 can be changed differently. In the embodiment, for example, the display device 10 can have a shape similar to a rectangle, which has a short side in the first direction DR1 and a long side in the second direction DR2. The corners where the short side in the first direction DR1 and the long side in the second direction DR2 meet can be rounded to have a curvature, but it is not limited thereto, and it can also be formed as a right angle. The planar shape of the display device 10 is not limited to a quadrilateral, and it can be formed to be similar to other polygons, a circle, or an ellipse.

[0051] The display device 10 can include a display panel 100, a display driver 200, a circuit board 300, and a touch driver 400 (see Figure 2 ).

[0052] The display panel 100 can include a main area MA and a sub-area SBA.

[0053] The main area MA can include a display area DA having pixels that display an image, and a non-display area NDA provided around the display area DA. The display area DA can emit light from a plurality of light-emitting areas or a plurality of opening areas. In the embodiment, for example, the display panel 100 can include a pixel circuit having a switching element, a pixel defining layer that defines a light-emitting area or an opening area, and a self-luminous element.

[0054] In the embodiment, for example, the self-luminous element can include at least one of the following, but is not limited thereto: an organic light-emitting diode (“LED”) including an organic light-emitting layer, a quantum dot LED including a quantum dot light-emitting layer, an inorganic LED including an inorganic semiconductor, and a micro LED.

[0055] In the display area DA, a plurality of pixels, a plurality of scan lines, a plurality of data lines, and a plurality of power lines can be provided. Each of the plurality of pixels can be defined as a minimum unit that emits light, and each of the self-emitting elements described above can be each pixel. The plurality of scan lines can supply scan signals received from a scan driver to the plurality of pixels. The plurality of data lines can supply data voltages received from the display driver 200 to the plurality of pixels. The plurality of power lines can supply power voltages received from the display driver 200 to the plurality of pixels.

[0056] The non-display area NDA can be an area outside the display area DA. The non-display area NDA can be defined as an edge area of the main area MA of the display panel 100. The non-display area NDA can include a scan driver that supplies scan signals to the scan lines, and fan-out lines that connect the display driver 200 and the display area DA.

[0057] The sub-area SBA can be an area extending from one side of the main area MA. The sub-area SBA can include a flexible material that can be bent, folded, curled, etc. In an embodiment, for example, when the sub-area SBA is bent, the sub-area SBA can overlap the main area MA in the thickness direction (third direction DR3). The sub-area SBA can include the display driver 200 and a pad portion connected to the circuit board 300. In another embodiment, the sub-area SBA can be omitted, and the display driver 200 and the pad portion can be provided in the non-display area NDA.

[0058] The display driver 200 can output signals and voltages for driving the display panel 100. The display driver 200 can supply data voltages to the data lines. The display driver 200 can supply power voltages to the power lines, and can supply scan control signals to the scan driver. The display driver 200 can be formed as an integrated circuit (“IC”), and can be provided (e.g., mounted) on the display panel 100 by a chip on glass (“COG”) method, a chip on plastic (“COP”) method, or an ultrasonic bonding method. In an embodiment, for example, the display driver 200 can be provided in the sub-area SBA, and can overlap the main area MA in the thickness direction (third direction DR3) by bending of the sub-area SBA. In another embodiment, the display driver 200 can be provided (e.g., mounted) on the circuit board 300.

[0059] The circuit board 300 can be attached to the pad portion of the display panel 100 using an anisotropic conductive film (“ACF”). The leads of the circuit board 300 can be electrically connected to the pad portion of the display panel 100. The circuit board 300 can be a flexible film such as a flexible printed circuit board, a rigid printed circuit board, or a chip on film.

[0060] Figure 2as viewed from the side Figure 1 A cross-sectional view of the display device. Specifically, Figure 2 relates to one side of the display device in a folded state Figure 1 in

[0061] Referring to Figure 2 , the display panel 100 may include a substrate SUB, a thin film transistor layer TFTL, a light emitting element layer EML, a thin film encapsulation layer TFEL, and a color filter layer CFL.

[0062] The substrate SUB may be a base substrate or a base member. The substrate SUB may be a flexible substrate that can be bent, folded, curled, etc. In an embodiment, for example, the substrate SUB may include a polymer resin such as polyimide (PI), but is not limited thereto. In another embodiment, the substrate SUB may include a glass material or a metal material.

[0063] The thin film transistor layer TFTL may be disposed on the substrate SUB. The thin film transistor layer TFTL may include a plurality of thin film transistors constituting a pixel circuit of a pixel. The thin film transistor layer TFTL may further include a scan line, a data line, a power line, a scan control line, a fan-out line connecting the display driver 200 and the data line, and a lead connecting the display driver 200 and the pad portion. Each of the thin film transistors may include a semiconductor region, a source electrode, a drain electrode, and a gate electrode. In an embodiment, for example, when the scan driver is formed on one side of the non-display area NDA of the display panel 100, the scan driver may include a thin film transistor.

[0064] The thin film transistor layer TFTL may be disposed in the display area DA, the non-display area NDA, and the sub-area SBA. The thin film transistors, the scan line, the data line, and the power line of each pixel of the thin film transistor layer TFTL may be disposed in the display area DA. The scan control line and the fan-out line of the thin film transistor layer TFTL may be disposed in the non-display area NDA. The lead of the thin film transistor layer TFTL may be disposed in the sub-area SBA.

[0065] The light emitting element layer EML may be disposed on the thin film transistor layer TFTL. The light emitting element layer EML may include a plurality of light emitting elements and a pixel defining layer defining a pixel, and the light emitting elements include a first electrode, a second electrode, and a light emitting layer to emit light. The plurality of light emitting elements of the light emitting element layer EML may be disposed in the display area DA.

[0066] In an embodiment, the light-emitting layer may be an organic light-emitting layer including an organic material. The light-emitting layer may include a hole transport layer, an organic light-emitting layer, and an electron transport layer. When the first electrode receives a voltage through the thin-film transistor of the thin-film transistor layer TFTL and the second electrode receives a cathode voltage, holes and electrons may move to the organic light-emitting layer through the hole transport layer and the electron transport layer, respectively, and may recombine with each other in the organic light-emitting layer to emit light.

[0067] In another embodiment, the light-emitting element may include a quantum dot light-emitting diode having a quantum dot light-emitting layer, an inorganic light-emitting diode having an inorganic semiconductor, or a micro light-emitting diode.

[0068] The thin-film encapsulation layer TFEL may cover the upper surface and the side surface of the light-emitting element layer EML and may protect the light-emitting element layer EML. The thin-film encapsulation layer TFEL may include at least one inorganic film and at least one organic film for encapsulating the light-emitting element layer EML.

[0069] The color filter layer CFL may be disposed on the thin-film encapsulation layer TFEL. The color filter layer CFL may include a plurality of color filters corresponding to each of the plurality of light-emitting regions. Each of the color filters may selectively transmit light of a predetermined wavelength and block or absorb light of a wavelength different from the predetermined wavelength. The color filter layer CFL may absorb a part of the light introduced from the outside of the display device 10 to reduce the reflected light caused by the external light. Accordingly, the color filter layer CFL may prevent color distortion caused by the reflection of the external light.

[0070] Since the color filter layer CFL is directly disposed on the thin-film encapsulation layer TFEL, a separate substrate for the color filter layer CFL may not be required in the display device 10. Accordingly, the display device 10 may have a relatively small thickness.

[0071] In some embodiments, the display device 10 may further include an optical device. The optical device may emit or receive light in the infrared, ultraviolet, and visible light bands. In an embodiment, for example, the optical device may be an optical sensor that senses light incident on the display device 10, such as a proximity sensor, an illumination sensor, a camera sensor, a fingerprint sensor, or an image sensor.

[0072] Figure 3 is a plan view showing an embodiment of a part of the display device. Figure 3 is a plan view showing the arrangement of the light-emitting regions EA1, EA2, and EA3 in the display region DA of the display device 10.

[0073] Reference Figure 3, the display device 10 may include a plurality of light-emitting regions EA1, EA2, and EA3 disposed in the display area DA. The light-emitting regions EA1, EA2, and EA3 may include a first light-emitting region EA1, a second light-emitting region EA2, and a third light-emitting region EA3 that emit lights of different colors. The first light-emitting region EA1, the second light-emitting region EA2, and the third light-emitting region EA3 may emit red light, green light, or blue light, respectively, and the color of the light emitted from each of the light-emitting regions EA1, EA2, and EA3 may be different according to the type of the light-emitting elements ( Figure 5 "ED1", "ED21", and "ED31" in ). In an embodiment, the first light-emitting region EA1 may emit first light of red color, the second light-emitting region EA2 may emit second light of green color, and the third light-emitting region EA3 may emit third light of blue color. However, the present disclosure is not limited thereto.

[0074] The plurality of light-emitting regions EA1, EA2, and EA3 may be arranged in a pattern, for example, a diamond pattern. In an embodiment, for example, the first light-emitting region EA1 and the third light-emitting region EA3 may be spaced apart from each other in a first direction DR1, and may be alternately arranged in the first direction DR1. In an embodiment, for example, the first light-emitting region EA1 may be repeatedly arranged in a second direction DR2, and the third light-emitting region EA3 may be repeatedly arranged in the second direction DR2. The second light-emitting region EA2 may be spaced apart from another adjacent second light-emitting region EA2 in the first direction DR1 and the second direction DR2. The second light-emitting region EA2 and the first light-emitting region EA1, or the second light-emitting region EA2 and the third light-emitting region EA3 may be alternately arranged in a plane formed by the first direction DR1 and the second direction DR2.

[0075] The first light-emitting region EA1, the second light-emitting region EA2, and the third light-emitting region EA3 may be defined by a pixel defining layer ( Figure 4 "PDL" in ) to be described later.

[0076] In the display device 10, the first light-emitting region EA1, the second light-emitting region EA2, and the third light-emitting region EA3 arranged adjacent to each other may form a pixel group. Referring to Figure 3 , region A1 indicates a pixel group. Figure 4 is an exploded perspective view showing a stack of the light-emitting element layer EML and the lower inorganic encapsulation layer TFE1 in the Figure 3 region A1 of .

[0077] Referring to Figure 4, the pixel defining layer PDL can define a first emission region EA1, a second emission region EA2, and a third emission region EA3. On the pixel defining layer PDL, a bank BN and a first inorganic layer TL11, a second inorganic layer TL21, and a third inorganic layer TL31 are sequentially stacked, and portions corresponding to the emission regions are exposed. The exposed region of the bank BN may overlap with the first emission region EA1, the second emission region EA2, and the third emission region EA3. The exposed region of the first inorganic layer TL11 may overlap with the entire second emission region EA2 and the third emission region EA3. The exposed region of the second inorganic layer TL21 may overlap with the entire first emission region EA1 and the third emission region EA3. The exposed region of the third inorganic layer TL31 may overlap with the entire first emission region EA1 and the second emission region EA2. In Figure 4 , the light-emitting element, the transistor layer, etc. are omitted.

[0078] Figure 5 is a cross-sectional view showing an embodiment of a part of the display device. Specifically, Figure 5 is Figure 3 and Figure 4 a cross-sectional view of part I-I' of Figure 5 . Referring to Figure 5 , a thin film transistor layer TFTL, a light-emitting element layer EML, a thin film encapsulation layer TFEL, and a color filter layer CFL may be sequentially stacked on a substrate SUB.

[0079] The thin film transistor layer TFTL may include a first buffer layer BF1, a lower metal layer BML, a second buffer layer BF2, a thin film transistor TFT, a gate insulating layer GI, a first interlayer insulating layer ILD1, a capacitor electrode CPE, a second interlayer insulating layer ILD2, a first connection electrode CNE1, a first passivation layer PAS1, a second connection electrode CNE2, and a second passivation layer PAS2.

[0080] The first buffer layer BF1 may be disposed on the substrate SUB. The first buffer layer BF1 may include an inorganic film capable of preventing the penetration of air or moisture. In an embodiment, for example, the first buffer layer BF1 may include a plurality of inorganic films stacked alternately.

[0081] The lower metal layer BML may be disposed on the first buffer layer BF1. In an embodiment, for example, the lower metal layer BML may include a single layer or multiple layers, or be composed of a single layer or multiple layers, and the single layer or multiple layers include any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) or any alloy thereof, or be composed of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) or any alloy thereof.

[0082] The second buffer layer BF2 may cover the first buffer layer BF1 and the lower metal layer BML. The second buffer layer BF2 may include an inorganic film capable of preventing the penetration of air or moisture. In an embodiment, for example, the second buffer layer BF2 may include a plurality of inorganic films stacked alternately.

[0083] The thin film transistor TFT may be disposed on the second buffer layer BF2 and may constitute a pixel circuit of each of a plurality of pixels. In an embodiment, for example, the thin film transistor TFT may be a driving transistor or a switching transistor of the pixel circuit. The thin film transistor TFT may include a semiconductor layer ACT, a source electrode SE, a drain electrode DE, and a gate electrode GE.

[0084] The semiconductor layer ACT may be disposed on the second buffer layer BF2. The semiconductor layer ACT may overlap the lower metal layer BML and the gate electrode GE in the thickness direction (third direction DR3) and may be insulated from the gate electrode GE by a gate insulating layer GI. In a part of the semiconductor layer ACT, the material of the semiconductor layer ACT may become a conductor to form the source electrode SE and the drain electrode DE.

[0085] The gate electrode GE may be disposed on the gate insulating layer GI. The gate electrode GE may overlap the semiconductor layer ACT in the thickness direction (third direction DR3), with the gate insulating layer GI interposed therebetween.

[0086] The gate insulating layer GI may be disposed on the semiconductor layer ACT, the source electrode SE, and the drain electrode DE. In an embodiment, for example, the gate insulating layer GI may cover the semiconductor layer ACT, the source electrode SE, the drain electrode DE, and the second buffer layer BF2 and may insulate the semiconductor layer ACT and the gate electrode GE from each other. The gate insulating layer GI may define a contact hole through which a first connection electrode CNE1 passes.

[0087] The first interlayer insulating layer ILD1 may cover the gate electrode GE and the gate insulating layer GI. The first interlayer insulating layer ILD1 may define a contact hole through which the first connection electrode CNE1 passes. The contact hole of the first interlayer insulating layer ILD1 may extend to the contact hole of the gate insulating layer GI and the contact hole of the second interlayer insulating layer ILD2.

[0088] The capacitor electrode CPE may be disposed on the first interlayer insulating layer ILD1. The capacitor electrode CPE may overlap the gate electrode GE in the thickness direction (third direction DR3). The capacitor electrode CPE and the gate electrode GE may form a capacitance.

[0089] The second interlayer insulating layer ILD2 may cover the capacitor electrode CPE and the first interlayer insulating layer ILD1. The second interlayer insulating layer ILD2 may define contact holes through which the first connection electrode CNE1 passes. The contact holes of the second interlayer insulating layer ILD2 may extend to the contact holes of the first interlayer insulating layer ILD1 and the gate insulating layer GI.

[0090] The first connection electrode CNE1 may be disposed on the second interlayer insulating layer ILD2. The first connection electrode CNE1 may electrically connect the drain electrode DE of the thin film transistor TFT and the second connection electrode CNE2 to each other. The first connection electrode CNE1 may be inserted into the contact holes defined in the second interlayer insulating layer ILD2, the first interlayer insulating layer ILD1, and the gate insulating layer GI to contact the drain electrode DE of the thin film transistor TFT.

[0091] The first passivation layer PAS1 may cover the first connection electrode CNE1 and the second interlayer insulating layer ILD2. The first passivation layer PAS1 may protect the thin film transistor TFT. The first passivation layer PAS1 may define contact holes through which the second connection electrode CNE2 passes.

[0092] The second connection electrode CNE2 may be disposed on the first passivation layer PAS1. The second connection electrode CNE2 may electrically connect the first connection electrode CNE1 and the pixel electrodes AE1, AE2, and AE3 of the light emitting element ED to each other. The second connection electrode CNE2 may be inserted into the contact holes defined in the first passivation layer PAS1 and contact the first connection electrode CNE1.

[0093] The second passivation layer PAS2 may cover the second connection electrode CNE2 and the first passivation layer PAS1. The second passivation layer PAS2 may include contact holes through which the pixel electrodes AE1, AE2, and AE3 of the light emitting element ED pass.

[0094] The light emitting element layer EML may be disposed on the thin film transistor layer TFTL. The light emitting element layer EML may include a light emitting element ED, a pixel defining layer PDL, a capping layer, and a bank BN. The light emitting element ED may include pixel electrodes AE1, AE2, and AE3, light emitting layers EL1, EL21, and EL31, and common electrodes CE1, CE21, and CE31.

[0095] Figure 6 is a magnified view of Figure 5 the light emitting element layer EML and the thin film encapsulation layer TFEL, specifically showing Figure 5 region A21 of

[0096] associated with Figure 5 refer to Figure 6, the display device 10 may include a plurality of light-emitting regions EA1, EA2, and EA3 disposed in the display area DA. The light-emitting regions EA1, EA2, and EA3 may include regions where light is emitted from light-emitting elements ED1, ED21, and ED31 including pixel electrodes AE1, AE2, and AE3, light-emitting layers EL1, EL21, and EL31, and common electrodes CE1, CE21, and CE31, and the light passes through the color filter layer CFL in the third direction DR3. The boundaries of the light-emitting regions EA1, EA2, and EA3 may be defined by a pixel defining layer PDL. The light-emitting regions EA1, EA2, and EA3 may include a first light-emitting region EA1, a second light-emitting region EA2, and a third light-emitting region EA3 that are spaced apart from each other and emit light of the same or different colors.

[0097] In an embodiment, the areas or sizes of the first light-emitting region EA1, the second light-emitting region EA2, and the third light-emitting region EA3 may be the same as each other. In an embodiment, for example, in the display device 10, the first light-emitting region EA1, the second light-emitting region EA2, and the third light-emitting region EA3 may have the same area. However, the present disclosure is not limited thereto. In the display device 10, the areas or sizes of the first light-emitting region EA1, the second light-emitting region EA2, and the third light-emitting region EA3 may be different from each other. In an embodiment, for example, the area of the second light-emitting region EA2 may be smaller than the areas of the first light-emitting region EA1 and the third light-emitting region EA3, and the area of the third light-emitting region EA3 may be larger than the area of the first light-emitting region EA1. The intensity of the light emitted from the light-emitting regions EA1, EA2, and EA3 may vary according to the areas of the light-emitting regions EA1, EA2, and EA3, and the color of the image displayed on the display device 10 may be controlled by adjusting the areas of the light-emitting regions EA1, EA2, and EA3. The areas of the light-emitting regions EA1, EA2, and EA3 are shown as being the same in Figures 3 to 5 the embodiment, but are not limited thereto.

[0098] In the display device 10, one first light-emitting region EA1, one second light-emitting region EA2, and one third light-emitting region EA3 that are adjacent to each other may form a pixel group. A pixel group may present a white gray level by including light-emitting regions EA1, EA2, and EA3 that emit light of different colors. However, the present disclosure is not limited thereto, and the combination of the light-emitting regions EA1, EA2, and EA3 constituting a pixel group may be variously modified according to the arrangement of the light-emitting regions EA1, EA2, and EA3 and the colors of the light emitted from the light-emitting regions EA1, EA2, and EA3.

[0099] The display device 10 may include a plurality of light-emitting elements ED1, ED21, and ED31 disposed in different light-emitting regions EA1, EA2, and EA3. The light-emitting elements ED1, ED21, and ED31 may include a first light-emitting element ED1 disposed in the first light-emitting region EA1, a second light-emitting element ED21 disposed in the second light-emitting region EA2, and a third light-emitting element ED31 disposed in the third light-emitting region EA3.

[0100] Each of the light-emitting elements ED1, ED21, and ED31 includes a pixel electrode (also referred to as an anode electrode) AE1, AE2, or AE3, a light-emitting layer EL1, EL21, or EL31, and a common electrode CE1, CE21, or CE31, and the light-emitting elements ED1, ED21, and ED31 disposed in different light-emitting regions EA1, EA2, and EA3 may emit light of different colors according to the materials of the light-emitting layers EL1, EL21, and EL31. In an embodiment, for example, the first light-emitting element ED1 disposed in the first light-emitting region EA1 may emit first light of red having a peak wavelength in the range of 610 nanometers (nm) to 650 nm, the second light-emitting element ED21 disposed in the second light-emitting region EA2 may emit second light of green having a peak wavelength in the range of 510 nm to 550 nm, and the third light-emitting element ED31 disposed in the third light-emitting region EA3 may emit third light of blue having a peak wavelength in the range of 440 nm to 480 nm. The first light-emitting region EA1, the second light-emitting region EA2, and the third light-emitting region EA3 constituting one pixel may present a white gray scale by including the light-emitting elements ED1, ED21, and ED31 that emit light of different colors. In an alternative embodiment, the light-emitting layers EL1, EL21, and EL31 may include two or more materials that emit light of different colors, such that one light-emitting layer may emit mixed light. In an embodiment, for example, the light-emitting layers EL1, EL21, and EL31 may emit yellow light by including a material that emits red light and a material that emits green light, or may emit white light by including a material that emits red light, a material that emits green light, and a material that emits blue light.

[0101] The pixel electrodes AE1, AE2, and AE3 may be disposed on the second passivation layer PAS2. The pixel electrodes AE1, AE2, and AE3 may be respectively disposed in the plurality of light-emitting regions EA1, EA2, and EA3. The pixel electrodes AE1, AE2, and AE3 may include a first pixel electrode AE1 disposed in the first light-emitting region EA1, a second pixel electrode AE2 disposed in the second light-emitting region EA2, and a third pixel electrode AE3 disposed in the third light-emitting region EA3. The first pixel electrode AE1, the second pixel electrode AE2, and the third pixel electrode AE3 may be spaced apart from each other on the second passivation layer PAS2.

[0102] The pixel electrodes AE1, AE2, and AE3 can be electrically connected to the drain electrode DE of the thin film transistor TFT through the first connection electrode CNE1 and the second connection electrode CNE2. The edges of the pixel electrodes AE1, AE2, and AE3 spaced apart from each other can be covered by the pixel defining layer PDL, so that the first pixel electrode AE1, the second pixel electrode AE2, and the third pixel electrode AE3 can be insulated from each other.

[0103] The pixel electrodes AE1, AE2, and AE3 can include a transparent electrode material and / or a conductive metal material. The metal material can be one or more of silver (Ag), copper (Cu), aluminum (Al), nickel (Ni), lanthanum (La), titanium (Ti), and titanium nitride (TiN). The transparent electrode material can be one or more of indium tin oxide (“ITO”), indium zinc oxide (“IZO”), and indium tin zinc oxide (“ITZO”). The pixel electrodes AE1, AE2, and AE3 can be a multilayer structure of a transparent electrode material and a conductive metal material.

[0104] The pixel defining layer PDL can be disposed on the second passivation layer PAS2, the residual pattern RP, and the pixel electrodes AE1, AE2, and AE3. The pixel defining layer PDL is completely disposed on the second passivation layer PAS2 and can cover the side surfaces of the pixel electrodes AE1, AE2, and AE3 and the residual pattern RP, thereby exposing a part of the upper surfaces of the pixel electrodes AE1, AE2, and AE3. In an embodiment, for example, the pixel defining layer PDL can expose the first pixel electrode AE1 in the first light emitting region EA1, and the first light emitting layer EL1 can be directly disposed on the first pixel electrode AE1.

[0105] The pixel defining layer PDL can include an inorganic insulating material. The pixel defining layer PDL can include at least one of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, an aluminum oxide layer, tantalum oxide, hafnium oxide, zinc oxide, and an amorphous silicon layer, but is not limited thereto.

[0106] The pixel defining layer PDL can have a side surface aligned with the side surface of the bank BN to be described later, or the pixel defining layer PDL can have a protruding side surface. The side surface of the pixel defining layer PDL (which is the boundary defining the light emitting regions EA1, EA2, and EA3) can overlap with the pixel electrodes AE1, AE2, and AE3. In the drawings, the side surface of the pixel defining layer PDL is shown aligned with the side surface of the bank BN, but the side surface of the pixel defining layer PDL can protrude much more toward the center of the pixel electrodes AE1, AE2, and AE3 than the side surface of the bank BN.

[0107] In an embodiment, the pixel defining layer PDL may be disposed on the pixel electrodes AE1, AE2, and AE3, and may be spaced apart from the upper surfaces of the pixel electrodes AE1, AE2, and AE3. The pixel defining layer PDL may partially overlap the upper surfaces of the pixel electrodes AE1, AE2, and AE3 in the thickness direction (third direction DR3) of the substrate SUB, and may not be in direct contact with the upper surfaces of the pixel electrodes AE1, AE2, and AE3, and a residual pattern RP may be disposed between the pixel defining layer PDL and the pixel electrodes AE1, AE2, and AE3. However, the pixel defining layer PDL may be in direct contact with the side surfaces of the pixel electrodes AE1, AE2, and AE3.

[0108] The residual pattern RP may be disposed on the edge of each of the pixel electrodes AE1, AE2, and AE3. Due to the residual pattern RP, the pixel defining layer PDL may not be in direct contact with the upper surfaces of the pixel electrodes AE1, AE2, and AE3. The residual pattern RP may be formed by removing a part of the sacrificial layer ( Figure 12 “SFL” in) disposed on the pixel electrodes AE1, AE2, and AE3 during the process of manufacturing the display device 10. The residual pattern RP may include a metal, an oxide semiconductor, or a transparent conductive oxide (“TCO”).

[0109] The bank BN may be disposed on the pixel defining layer PDL. The bank BN may have a single-layer or multi-layer structure. In an embodiment, the bank BN may be a single film of a metal or a metal alloy. The material of the bank BN may be a highly conductive metal, such as aluminum (Al), titanium (Ti), or molybdenum (Mo), or any alloy thereof.

[0110] The bank BN may define openings overlapping the light-emitting regions EA1, EA2, and EA3, and may expose the pixel electrodes AE1, AE2, and AE3. The bank BN may include side surfaces defining the openings. The bank BN may include a first side surface BN_S1 and a second side surface BN_S2 overlapping or adjacent to the first light-emitting region EA1. The first side surface BN_S1 and the second side surface BN_S2 of the bank BN may be different side surfaces or different sides disposed within the same opening, and may be surfaces facing each other. The bank BN may include a third side surface BN_S3 and a fourth side surface BN_S4 overlapping or adjacent to the second light-emitting region EA2. The third side surface BN_S3 and the fourth side surface BN_S4 of the bank BN may be different side surfaces or different sides disposed within the same opening, and may be surfaces facing each other. The bank BN may include a fifth side surface BN_S5 and a sixth side surface BN_S6 overlapping or adjacent to the third light-emitting region EA3. The fifth side surface BN_S5 and the sixth side surface BN_S6 of the bank BN may be different side surfaces or different sides disposed within the same opening, and may be surfaces facing each other.

[0111] The light-emitting layers EL1, EL21, and EL31 may be provided on the pixel electrodes AE1, AE2, and AE3. The light-emitting layers EL1, EL21, and EL31 may be organic light-emitting layers including or composed of an organic material, and may be formed on the pixel electrodes AE1, AE2, and AE3 by a deposition process. The light-emitting layers EL1, EL21, and EL31 may have a multilayer structure, and a hole injection material, a hole transport material, a light-emitting material, an electron transport material, and / or an electron injection material may each constitute a layer. When the thin film transistor TFT applies a predetermined voltage to the pixel electrodes AE1, AE2, and AE3 of the light-emitting elements ED1, ED21, and ED31, and the common electrodes CE1, CE21, and CE31 of the light-emitting elements ED1, ED21, and ED31 receive a common voltage or a cathode voltage, holes and electrons are each injected and transported, and the holes and electrons may recombine with each other in the light-emitting layers EL1, EL21, and EL31 to emit light.

[0112] The light-emitting layers EL1, EL21, and EL31 may include a first light-emitting layer EL1, a second light-emitting layer EL21, and a third light-emitting layer EL31 provided in different light-emitting regions EA1, EA2, and EA3. The first light-emitting layer EL1 may be provided on the first pixel electrode AE1 in the first light-emitting region EA1, the second light-emitting layer EL21 may be provided on the second pixel electrode AE2 in the second light-emitting region EA2, and the third light-emitting layer EL31 may be provided on the third pixel electrode AE3 in the third light-emitting region EA3. The first light-emitting layer EL1, the second light-emitting layer EL21, and the third light-emitting layer EL31 may be spaced apart from each other. Each of the plurality of light-emitting layers EL1, EL21, and EL31 may emit a different color, or one of the light-emitting layers EL1, EL21, or EL31 may emit mixed light. In an embodiment, the first light-emitting layer EL1 may emit red light, the second light-emitting layer EL21 may emit green light, and the third light-emitting layer EL31 may emit blue light. In another embodiment, the first light-emitting layer EL1 may emit yellow light, which is a mixed light of red light and green light, and the second light-emitting layer EL21 may emit blue light. In another embodiment, the first light-emitting layer EL1 may emit white light, which is a mixed light of red light, green light, and blue light.

[0113] The first light-emitting layer EL1, the second light-emitting layer EL21, and the third light-emitting layer EL31 are each provided to overlap with the opening of the bank BN, but their cross-sectional shapes may be different from each other. Refer to Figure 5 and Figure 6, the first light-emitting layer EL1 can be disposed only within the opening of the bank BN, and one end and the opposite end of the first light-emitting layer EL1 can be disposed on the first side surface BN_S1 and the second side surface BN_S2 of the bank BN. A part of the second light-emitting layer EL21 can be disposed within the opening of the bank BN, and another part of the second light-emitting layer EL21 can be disposed on the upper surface of the bank BN. One end of the second light-emitting layer EL21 can be disposed on the upper surface of the bank BN, and its opposite end can be disposed on the fourth side surface BN_S4 of the bank BN. A part of the third light-emitting layer EL31 can be disposed within the opening of the bank BN, and another part of the third light-emitting layer EL31 can be disposed on the upper surface of the bank BN. One end and the opposite end of the third light-emitting layer EL31 can be disposed on the upper surface of the bank BN. In a cross-section of the substrate SUB cut along the thickness direction (the third direction DR3), the first light-emitting layer EL1 can include a U-shaped or rod-shaped cross-section, the second light-emitting layer EL21 can include a substantially U-shaped cross-section (a U-shaped including one wing) with a bent end, and the third light-emitting layer EL31 can include a U-shaped cross-section (a U-shaped including two wings) with a bent end and an opposite end.

[0114] The common electrodes CE1, CE21, and CE31 can be disposed on the light-emitting layers EL1, EL21, and EL31. The common electrodes (also referred to as cathode electrodes) CE1, CE21, and CE31 include a transparent conductive material, so that the light generated in the light-emitting layers EL1, EL21, and EL31 can be emitted. The common electrodes CE1, CE21, and CE31 can receive a common voltage or a relatively low potential voltage. When the pixel electrodes AE1, AE2, and AE3 receive voltages corresponding to data voltages and the common electrodes CE1, CE21, and CE31 receive relatively low potential voltages, the light-emitting layers EL1, EL21, and EL31 can emit light due to the potential difference formed between the pixel electrodes AE1, AE2, and AE3 and the common electrodes CE1, CE21, and CE31.

[0115] The common electrodes CE1, CE21, and CE31 can include a first common electrode CE1, a second common electrode CE21, and a third common electrode CE31 disposed in different light-emitting regions EA1, EA2, and EA3. The first common electrode CE1 can be disposed on the first light-emitting layer EL1 in the first light-emitting region EA1, the second common electrode CE21 can be disposed on the second light-emitting layer EL21 in the second light-emitting region EA2, and the third common electrode CE31 can be disposed on the third light-emitting layer EL31 in the third light-emitting region EA3. The first common electrode CE1, the second common electrode CE21, and the third common electrode CE31 can be spaced apart from each other.

[0116] The first common electrode CE1, the second common electrode CE21, and the third common electrode CE31 are each arranged to overlap with the opening of the bank portion BN, but their cross-sectional shapes may be different from each other. In the cross-section of the substrate SUB cut along the thickness direction (the third direction DR3), the first common electrode CE1 may include a U-shaped cross-section, the second common electrode CE21 may include a U-shaped cross-section with a bent end (a U-shape including one wing portion), and the third common electrode CE31 may include a U-shaped cross-section with a bent end and an opposite end (a U-shape including two wing portions).

[0117] The first common electrode CE1, the second common electrode CE21, and the third common electrode CE31 may have different widths. In this specification, unless explicitly defined, the width may be the distance between one end and the opposite end measured in the extending direction of the substrate SUB. In an embodiment, referring to Figures 7 to 9 , the width d1 of the first common electrode CE1 may be smaller than the width d21 of the second common electrode CE21, and the width d21 of the second common electrode CE21 may be smaller than the width d31 of the third common electrode CE31.

[0118] The first common electrode CE1 may be arranged only within the opening of the bank portion BN. The first common electrode CE1 may be arranged on at least a part of the first side surface BN_S1 of the bank portion BN and at least a part of the second side surface BN_S2 of the bank portion BN. One end and the opposite end of the first common electrode CE1 may be arranged on the first side surface BN_S1 and the second side surface BN_S2 of the bank portion BN. The first common electrode CE1 may not be arranged on the upper surface of the bank portion BN. The heights of one end and the opposite end of the first common electrode CE1 may be the same as each other.

[0119] A part of the second common electrode CE21 may be arranged within the opening of the bank portion BN, and another part of the second common electrode CE21 may be arranged on the upper surface of the bank portion BN. The second common electrode CE21 may be arranged on the entire third side surface BN_S3 of the bank portion BN, at least a part of the fourth side surface BN_S4 of the bank portion BN, and at least a part of the upper surface of the bank portion BN. One end of the second common electrode CE21 may be arranged on the upper surface of the bank portion BN, and its opposite end may be arranged on the fourth side surface BN_S4 of the bank portion BN. The wing portion of the second common electrode CE21 may be arranged on the upper surface of the bank portion BN provided between the first light-emitting region EA1 and the second light-emitting region EA2. The height of one end of the second common electrode CE21 may be greater than the height of the opposite end of the second common electrode CE21.

[0120] A part of the third common electrode CE31 may be disposed within the opening of the bank BN, and another part of the third common electrode CE31 may be disposed on the upper surface of the bank BN. The third common electrode CE31 may be disposed on the entire fifth side surface BN_S5 of the bank BN, on the entire sixth side surface BN_S6 of the bank BN, and on at least a part of the upper surface of the bank BN. One end and the opposite end of the third common electrode CE31 may be disposed on the upper surface of the bank BN. The first wing portion of the third common electrode CE31 may be disposed on the upper surface of the bank BN disposed between the second light-emitting region EA2 and the third light-emitting region EA3, and the second wing portion of the third common electrode CE31 may be disposed on the upper surface of the bank BN disposed between the third light-emitting region EA3 and the first light-emitting region EA1. The heights of one end and the opposite end of the third common electrode CE31 may be the same as each other.

[0121] In an embodiment, referring to Figures 7 to 9 , the width d1 of the first common electrode CE1 may be smaller than the width l1 of the first pixel electrode AE1, the width d21 of the second common electrode CE21 may be larger than the width l2 of the second pixel electrode AE2, and the width d31 of the third common electrode CE31 may be larger than the width l3 of the third pixel electrode AE3.

[0122] In an embodiment, referring to Figures 7 to 9 , the width (the sum of the width d311 and the width d312) of the third common electrode CE31 disposed on the upper surface of the bank BN may be different from the width d211 of the second common electrode CE21 disposed on the upper surface of the bank BN. Referring to Figures 7 to 9 , the width (the sum of the width d311 and the width d312) of the third common electrode CE31 disposed on the upper surface of the bank BN may be larger than the width d211 of the second common electrode CE21 disposed on the upper surface of the bank BN. Referring to Figures 7 to 9 , the width d311 of the first wing portion of the third common electrode CE31 may be larger than the width d211 of the wing portion of the second common electrode CE21.

[0123] The first common electrode CE1, the second common electrode CE21, and the third common electrode CE31 may contact the bank BN, and the bank BN may include a metallic material. The common electrodes CE1, CE21, and CE31 spaced apart from each other may be electrically connected through the bank BN. The areas of contact of the first common electrode CE1, the second common electrode CE21, and the third common electrode CE31 with the bank BN may be different. The contact area between the first common electrode CE1 and the bank BN may be smaller than the contact area between the second common electrode CE21 and the bank BN, and the contact area between the second common electrode CE21 and the bank BN may be smaller than the contact area between the third common electrode CE31 and the bank BN.

[0124] A capping layer (not shown) may optionally be provided on the common electrodes CE1, CE21, and CE31. The capping layer may include an organic insulating material or an inorganic insulating material and cover the patterns provided on the light-emitting elements ED1, ED21, and ED31. The capping layer may prevent the light-emitting elements ED1, ED21, and ED31 from being damaged by external air. In an embodiment, the capping layer may include an organic material such as α-NPD (2,2'-dimethyl-N,N'-bis[(1-naphthyl)-N,N'-diphenyl]-1,1'-biphenyl-4,4'-diamine), NPB (N,N'-bis(naphthalen-1-yl)-N,N'-diphenyl-benzidine), TPD (N,N'-bis(3-methylphenyl)-N,N'-diphenyl-[1,1'-biphenyl]-4,4'-diamine), m-MTDATA (4,4',4''-[tris(3-methylphenyl)phenylamino]triphenylamine), Alq 3 (aluminum tris(8-hydroxyquinoline)), LiF, and / or CuPc (copper(II) phthalocyanine), or an inorganic material such as aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, and / or silicon oxynitride.

[0125] The thin-film encapsulation layer TFEL may be provided on the light-emitting elements ED1, ED21, and ED31 and the bank BN. The thin-film encapsulation layer TFEL may include at least one inorganic film to prevent oxygen or moisture from penetrating into the light-emitting element layer EML. The thin-film encapsulation layer TFEL may include at least one organic film to protect the light-emitting element layer EML from foreign substances such as dust.

[0126] In an embodiment, the thin-film encapsulation layer TFEL may include a lower inorganic encapsulation layer TFE1, an organic encapsulation layer TFE2, and an upper inorganic encapsulation layer TFE3 stacked in sequence.

[0127] Each of the lower inorganic encapsulation layer TFE1 and the upper inorganic encapsulation layer TFE3 may include one or more inorganic insulating materials. The inorganic insulating material may be, for example, any one of alumina, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, and / or silicon oxynitride.

[0128] The organic encapsulation layer TFE2 may include a polymer-based material. In an embodiment, the polymer-based material may include an acrylic resin, an epoxy-based resin, polyimide, polyethylene, etc. In an embodiment, the organic encapsulation layer TFE2 may include an acrylic resin, such as polymethyl methacrylate or polyacrylic acid. The organic encapsulation layer TFE2 may be formed by curing a monomer or applying a polymer.

[0129] The lower inorganic encapsulation layer TFE1 may be disposed on the light-emitting elements ED1, ED21, and ED31 and the bank BN. The lower inorganic encapsulation layer TFE1 may include a first inorganic layer TL11, a second inorganic layer TL21, and a third inorganic layer TL31, which are respectively disposed corresponding to different light-emitting regions EA1, EA2, and EA3. The first inorganic layer TL11, the second inorganic layer TL21, and the third inorganic layer TL31 may each include an inorganic insulating material to cover the light-emitting elements ED1, ED21, and ED31.

[0130] Figures 7 to 9 are cross-sectional views respectively showing in detail Figure 6 the first inorganic layer TL11, the second inorganic layer TL21, and the third inorganic layer TL31.

[0131] The lower inorganic encapsulation layer TFE1 may be formed by chemical vapor deposition (“CVD”) and may be formed along the steps of the deposited layer due to its excellent step coverage. In an embodiment, for example, the second inorganic layer TL21 may also be formed in the space between the upper surface of the bank BN and the first inorganic layer TL11, and may also be formed on the lower surface TL11_S6 of the first inorganic layer TL11 facing the upper surface of the bank BN.

[0132] The first inorganic layer TL11 may include a main body portion TL11_B, a first wing portion TL11_W1, and a second wing portion TL11_W2. The main body portion TL11_B of the first inorganic layer TL11 may be disposed on the first common electrode CE1 and may overlap with the opening of the bank portion BN and the first light-emitting region EA1. The wing portions TL11_W1 and TL11_W2 of the first inorganic layer TL11 (which are portions protruding from the main body portion TL11_B) may be disposed on the bank portion BN and spaced apart from the upper surface of the bank portion BN. The first wing portion TL11_W1 of the first inorganic layer TL11 may be disposed on the bank portion BN between the first light-emitting region EA1 and the third light-emitting region EA3, and the second wing portion TL11_W2 of the first inorganic layer TL11 may be disposed on the bank portion BN between the first light-emitting region EA1 and the second light-emitting region EA2.

[0133] The second inorganic layer TL21 may include a main body portion TL21_B, a connection portion TL21_C1, a first wing portion TL21_W1, and a second wing portion TL21_W2. The main body portion TL21_B of the second inorganic layer TL21 may be disposed on the second common electrode CE21 and may overlap with the opening of the bank portion BN and the second light-emitting region EA2. The connection portion TL21_C1 of the second inorganic layer TL21 (which is a portion connecting the main body portion TL21_B and the first wing portion TL21_W1) may be disposed in the space between the second wing portion TL11_W2 of the first inorganic layer TL11 and the bank portion BN. The first wing portion TL21_W1 of the second inorganic layer TL21 (which is a portion protruding from the connection portion TL21_C1) may be disposed on the second wing portion TL11_W2 of the first inorganic layer TL11 and may be spaced apart from the upper surface TL11_S10 of the second wing portion TL11_W2 of the first inorganic layer TL11. The second wing portion TL21_W2 of the second inorganic layer TL21 (which is a portion protruding from the main body portion TL21_B) may be disposed on the bank portion BN between the second light-emitting region EA2 and the third light-emitting region EA3 and may be spaced apart from the upper surface of the bank portion BN.

[0134] The third inorganic layer TL31 may include a main body portion TL31_B, a first connection portion TL31_C1, a second connection portion TL31_C2, a first wing portion TL31_W1, and a second wing portion TL31_W2. The main body portion TL31_B of the third inorganic layer TL31 may be disposed on the third common electrode CE31 and may overlap with the opening of the bank portion BN and the third light-emitting region EA3. The first connection portion TL31_C1 of the third inorganic layer TL31 (which is the portion connecting the main body portion TL31_B and the first wing portion TL31_W1) may be disposed in the space between the second wing portion TL21_W2 of the second inorganic layer TL21 and the bank portion BN. The first wing portion TL31_W1 of the third inorganic layer TL31 (which is the portion protruding from the first connection portion TL31_C1) may be disposed on the second wing portion TL21_W2 of the second inorganic layer TL21 and may be spaced apart from the upper surface TL21_S10 of the second wing portion TL21_W2 of the second inorganic layer TL21. The second connection portion TL31_C2 of the third inorganic layer TL31 (which is the portion connecting the main body portion TL31_B and the second wing portion TL31_W2) may be disposed in the space between the first wing portion TL11_W1 of the first inorganic layer TL11 and the bank portion BN. The second wing portion TL31_W2 of the third inorganic layer TL31 (which is the portion protruding from the second connection portion TL31_C2) may be disposed on the first wing portion TL11_W1 of the first inorganic layer TL11 and may be spaced apart from the upper surface TL11_S9 of the first wing portion TL11_W1 of the first inorganic layer TL11.

[0135] During the manufacturing process, due to the undercut structure on the lower side of the first inorganic layer TL11, the second inorganic layer TL21, and the photoresist patterns ( Figure 12 "PR1" in Figure 20 "PR3" in

[0136] the materials deposited on the front surface may not be connected and may be disconnected. By using deposition and etching processes without using a mask process, the spaced-apart light-emitting layers EL1, EL21, and EL31 and the common electrodes CE1, CE21, and CE31 for each of the light-emitting regions EA1, EA2, and EA3 can be formed.

[0137] The side surface TL21_S3 of the connection part TL21_C1 of the second inorganic layer TL21 may protrude further toward the center of the first light-emitting region EA1 than the second side surface BN_S2 of the bank part BN. A part of the second inorganic layer TL21 may overlap with the first light-emitting region EA1, and the side surface TL21_S3 of the connection part TL21_C1 of the second inorganic layer TL21 may overlap with the first pixel electrode AE1.

[0138] The side surface TL31_S3 of the first connection part TL31_C1 of the third inorganic layer TL31 may protrude further toward the center of the second light-emitting region EA2 than the fourth side surface BN_S4 of the bank part BN. A part of the third inorganic layer TL31 may overlap with the second light-emitting region EA2, and the side surface TL31_S3 of the first connection part TL31_C1 of the third inorganic layer TL31 may overlap with the second pixel electrode AE2.

[0139] The side surface TL31_S4 of the second connection part TL31_C2 of the third inorganic layer TL31 may protrude further toward the center of the first light-emitting region EA1 than the first side surface BN_S1 of the bank part BN. A part of the third inorganic layer TL31 may overlap with the first light-emitting region EA1, and the side surface TL31_S4 of the second connection part TL31_C2 of the third inorganic layer TL31 may overlap with the first pixel electrode AE1.

[0140] The first inorganic layer TL11, the second inorganic layer TL21, and the third inorganic layer TL31 may completely cover the upper surface of the light-emitting element layer EML in the display area DA. The first inorganic layer TL11, the second inorganic layer TL21, and the third inorganic layer TL31 may be in contact with each other. The bonding between the inorganic materials on the outer surface of the light-emitting element layer EML may improve the encapsulation characteristics of the display device 10. The upper surface TL11_S2 of the main body portion TL11_B of the first inorganic layer TL11, the undercut surfaces TL11_S4 and TL11_S6, and the side surface TL11_S8 of the second wing portion TL11_W2 may be in contact with the surfaces TL21_S1, TL21_S3, TL21_S5, and TL21_S7 of the connecting portion TL21_C1 of the second inorganic layer TL21. The upper surface TL21_S2 of the main body portion TL21_B of the second inorganic layer TL21, the undercut surfaces TL21_S4 and TL21_S6, and the side surface TL21_S8 of the second wing portion TL21_W2 may be in contact with the surfaces TL31_S1, TL31_S3, TL31_S5, and TL31_S7 of the first connecting portion TL31_C1 of the third inorganic layer TL31. The upper surface TL11_S1 of the main body portion TL11_B of the first inorganic layer TL11, the undercut surfaces TL11_S3 and TL11_S5, and the side surface TL11_S7 of the first wing portion TL11_W1 may be in contact with the surfaces TL31_S2, TL31_S4, TL31_S6, and TL31_S8 of the second connecting portion TL31_C2 of the third inorganic layer TL31.

[0141] When depositing the second light-emitting layer EL21 and the second common electrode CE21, the wing portions TL11_W1 and TL11_W2 of the first inorganic layer TL11 may disconnect the second light-emitting layer EL21 and the second common electrode CE21. The second wing portion TL11_W2 of the first inorganic layer TL11 may overlap the second light-emitting layer EL21 and the second common electrode CE21 in the thickness direction (the third direction DR3) of the substrate SUB.

[0142] When depositing the third light-emitting layer EL31 and the third common electrode CE31, the first wing portion TL11_W1 of the first inorganic layer TL11 and the wing portions TL21_W1 and TL21_W2 of the second inorganic layer TL21 can disconnect the third light-emitting layer EL31 and the third common electrode CE31. The first wing portion TL11_W1 of the first inorganic layer TL11 and the second wing portion TL21_W2 of the second inorganic layer TL21 can overlap the third light-emitting layer EL31 and the third common electrode CE31 in the thickness direction (the third direction DR3) of the substrate SUB. In an embodiment, the first wing portion TL21_W1 of the second inorganic layer TL21 may include surfaces TL21_S9, TL21_S11, and TL21_S12.

[0143] The organic encapsulation layer TFE2 is disposed on the first inorganic layer TL11, the second inorganic layer TL21, and the third inorganic layer TL31 of the lower inorganic encapsulation layer TFE1. A part of the organic encapsulation layer TFE2 may be disposed between the wing portions of the first inorganic layer TL11, the second inorganic layer TL21, and the third inorganic layer TL31. The organic encapsulation layer TFE2 may be disposed between the first wing portion TL11_W1 of the first inorganic layer TL11 and the second wing portion TL31_W2 of the third inorganic layer TL31, between the second wing portion TL11_W2 of the first inorganic layer TL11 and the first wing portion TL21_W1 of the second inorganic layer TL21, and between the second wing portion TL21_W2 of the second inorganic layer TL21 and the first wing portion TL31_W1 of the third inorganic layer TL31. The organic encapsulation layer TFE2 may not be in direct contact with the bank portion BN in the display area DA. In an embodiment, the first wing portion TL31_W1 of the third inorganic layer TL31 may include surfaces TL31_S9, TL31_S11, and TL31_S13. In an embodiment, the second wing portion TL31_W2 of the third inorganic layer TL31 may include surfaces TL31_S10, TL31_S12, and TL31_S14.

[0144] The upper inorganic encapsulation layer TFE3 may be disposed on the organic encapsulation layer TFE2. The upper inorganic encapsulation layer TFE3 may include alumina, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, and / or silicon oxynitride.

[0145] A light blocking layer (not shown) may be optionally provided on the thin film encapsulation layer TFEL. The light blocking layer may be provided between the light emitting regions EA1, EA2, and EA3. The light blocking layer may include a light absorbing material. In an embodiment, for example, the light blocking layer may include an inorganic black pigment or an organic black pigment. The inorganic black pigment may be carbon black, and the organic black pigment may include at least one of lactam black, perylene black, and aniline black, but is not limited thereto. The light blocking layer may prevent visible light from penetrating and mixing colors between the first light emitting region EA1, the second light emitting region EA2, and the third light emitting region EA3, thereby improving the color reproducibility of the display device 10.

[0146] Reference Figure 5 , the display device 10 may include a plurality of color filters CF1, CF2, and CF3 provided on the light emitting elements ED1, ED21, and ED31 in the light emitting regions EA1, EA2, and EA3. Each of the plurality of color filters CF1, CF2, and CF3 may include a filtering pattern region and a light blocking region. The filtering pattern region may be formed to overlap with the light emitting regions EA1, EA2, and EA3, and may form a light output region from which light emitted from the light emitting regions EA1, EA2, and EA3 is emitted. The light blocking region is a region where light may not be transmitted due to the plurality of color filters CF1, CF2, and CF3 being stacked therein.

[0147] The color filters CF1, CF2, and CF3 may include a first color filter CF1, a second color filter CF2, and a third color filter CF3, which are respectively provided to correspond to different light emitting regions EA1, EA2, and EA3. The color filters CF1, CF2, and CF3 may include a colorant such as a dye or a pigment that absorbs light in a wavelength band other than a predetermined wavelength band, and may be provided to correspond to the colors of light emitted from the light emitting regions EA1, EA2, and EA3. In an embodiment, for example, the first color filter CF1 may be a red color filter provided to overlap with the first light emitting region EA1 and only transmit the first light of red. The second color filter CF2 may be a green color filter provided to overlap with the second light emitting region EA2 and only transmit the second light of green, and the third color filter CF3 may be a blue color filter provided to overlap with the third light emitting region EA3 and only transmit the third light of blue.

[0148] In the display device 10, since the color filters CF1, CF2, and CF3 are provided to overlap each other, the intensity of reflected light caused by external light can be reduced. In addition, the color of the light reflected by the external light can also be controlled by adjusting the arrangement, shape, and area of the color filters CF1, CF2, and CF3 in the plan view.

[0149] An outer coating OC may be provided on the color filters CF1, CF2, and CF3 to planarize the upper ends of the color filters CF1, CF2, and CF3. The outer coating OC may be a colorless light-transmitting layer that has no color in the visible light band. In an embodiment, the outer coating OC may include a colorless light-transmitting organic material, such as an acrylic-based resin.

[0150] Figure 10 is a cross-sectional view showing another embodiment of a portion A22 of the display device 10. Figure 10 The wings TL12_W1 and TL12_W2 of the first inorganic layer TL12 and the wings TL22_W1 and TL22_W2 of the second inorganic layer TL22 in Figure 6 have a width wider than the width of the corresponding wings in Figure 10 The width d22 of the second common electrode CE22 in Figure 8 may be smaller than the width d21 of the second common electrode CE21 in Figure 10 The width d32 of the third common electrode CE32 in Figure 9 may be smaller than the width d31 of the third common electrode CE31 in Figure 10 In

[0151] Figure 11 is a cross-sectional view showing another embodiment of a portion A23 of the display device 10. Figure 11 Differing from Figure 6 is that some of the wings of the first inorganic layer TL13, the second inorganic layer TL23 to the third inorganic layer TL33 are removed. In forming as in Figure 6After the first inorganic layer TL11, the second inorganic layer TL21, and the third inorganic layer TL31 shown, some wings provided on the upper side can be removed by a dry etching process. Figure 11 The second inorganic layer TL23 in Figure 11 does not have a wing on the upper side of the second wing TL13_W2 of the first inorganic layer TL13, and may include a wing TL23_W2 provided on a side surface of the first connection portion TL33_C1 of the third inorganic layer TL33. The third inorganic layer TL33 does not have a wing on the upper side of the second wing TL13_W2 of the first inorganic layer TL13 and the wing TL23_W2 of the second inorganic layer TL23. By adjusting the dry etching process, the removal amount and remaining shape of the wings of the first inorganic layer TL13, the second inorganic layer TL23, and the third inorganic layer TL33 can be controlled. In an embodiment, the first inorganic layer TL13 may further include a main body portion TL13_B and a first wing TL13_W1, the second inorganic layer TL23 may further include a main body portion TL23_B and a connection portion TL23_C1, and the third inorganic layer TL33 may further include a main body portion TL33_B and a second connection portion TL33_C2. In an embodiment, the second light-emitting element ED23 may include a second light-emitting layer EL23 and a second common electrode CE23. In an embodiment, the third light-emitting element ED33 may include a third light-emitting layer EL33 and a third common electrode CE33.

[0152] Hereinafter, a process of manufacturing the display device 10 in the embodiment will be described with reference to other drawings.

[0153] Figures 12 to 29 are cross-sectional views sequentially showing embodiments of a process for manufacturing a display device.

[0154] Figures 12 to 29 Schematically shows a process of forming a bank structure and a light-emitting element ED as a light-emitting element layer EML of the display device 10 and forming a thin-film encapsulation layer TFEL. Hereinafter, a description of the formation process of each layer in the process of manufacturing the display device 10 will be omitted, and the formation order of each layer will be described.

[0155] Reference Figure 12 , a plurality of pixel electrodes AE1, AE2, and AE3, a sacrificial layer SFL, a pixel defining material layer PDLL, and a bank material layer BNL are formed on the second passivation layer PAS2 so as to be integrally spaced apart. First photoresist patterns PR1 may be spaced apart from each other on the bank material layer BNL and may be arranged to expose regions overlapping with the plurality of pixel electrodes AE1, AE2, and AE3.

[0156] Although not shown in the drawings, a thin-film transistor layer TFTL may be provided on the substrate SUB, and the structure of the thin-film transistor layer TFTL is the same as that described above with reference toFigure 5 The detailed description thereof is omitted.

[0157] Next, refer to Figure 13 , a first etching process is performed to etch a portion of the bank material layer BNL using the first photoresist pattern PR1 as a mask. A hole may be formed by the first etching process. In an embodiment, the first etching process may be performed as anisotropic dry etching. A hole may be formed in a region overlapping with the plurality of pixel electrodes AE1, AE2, and AE3.

[0158] Next, refer to Figure 14 , the undercut structure of the bank BN may be formed by etching the side surface of the bank material layer BNL through a second etching process and exposing the lower surface of the first photoresist pattern PR1. The side surface of the first photoresist pattern PR1 may be formed to protrude more than the side surface of the bank BN. In an embodiment, the second etching process may be an isotropic wet etching. The second etching process may use an alkaline etchant.

[0159] Next, if Figure 15 As shown, a portion of the pixel defining material layer PDLL and the sacrificial layer SFL may be removed by a third etching process. The third etching process may include a dry etching step of removing a portion of the pixel defining material layer PDLL, and a wet etching step of forming a residual pattern RP by removing a portion of the sacrificial layer SFL. In the step of removing the pixel defining material layer PDLL, the sacrificial layer SFL may protect the pixel electrodes AE1, AE2, and AE3 from the influence of plasma.

[0160] Next, if Figure 16 As shown, the first light emitting element ED1 is formed by depositing a first light emitting layer EL1 and a first common electrode CE1 on the first pixel electrode AE1. In this case, since the first light emitting layer EL1 and the first common electrode CE1 are formed on the entire surface of the substrate SUB, the first light emitting pattern ELP1 and the first electrode pattern CEP1 may also be formed on the first photoresist pattern PR1.

[0161] By the tip of the first photoresist pattern PR1, the first light emitting layer EL1 and the first light emitting pattern ELP1 may be separated, and the first common electrode CE1 and the first electrode pattern CEP1 may be separated. While the first light emitting layer EL1 is formed on the first pixel electrode AE1, the first light emitting pattern ELP1 may be formed on the first photoresist pattern PR1. While the first common electrode CE1 is formed on the first light emitting layer EL1, the first electrode pattern CEP1 may be formed on the first light emitting pattern ELP1.

[0162] The first light-emitting layer EL1 and the first common electrode CE1 can be formed by a thermal deposition process. Within the undercut structure of the bank BN, due to the tip of the first photoresist pattern PR1, the material may not be deposited smoothly. However, since the materials of the first light-emitting layer EL1 and the first common electrode CE1 are deposited in an inclined direction rather than a direction perpendicular to the upper surface of the substrate, deposition can also be performed on the area covered by the tip of the first photoresist pattern PR1.

[0163] Compared with the deposition process for forming the first light-emitting layer EL1, the deposition process for forming the first common electrode CE1 can be performed to be inclined to a more nearly horizontal direction. Thus, the first common electrode CE1 can have a larger contact area with the side surface of the bank BN than the first light-emitting layer EL1. In an alternative embodiment, the first common electrode CE1 can be deposited on the side surface of the bank BN to a position higher than the first light-emitting layer EL1.

[0164] Next, a first inorganic material layer TLL1 covering the first light-emitting element ED1 is formed. The first inorganic material layer TLL1 can be formed to completely cover the outer surfaces of the first light-emitting element ED1, the bank BN, the first photoresist pattern PR1, the first light-emitting pattern ELP1, and the first electrode pattern CEP1 without any discontinuous portions. Specifically, the first inorganic material layer TLL1 is formed on the upper surface of the first common electrode CE1, the side surface of the bank BN, the lower surface and side surface of the first photoresist pattern PR1, and the upper surface of the first electrode pattern CEP1.

[0165] Next, refer to Figure 17 , a second photoresist pattern PR2 covering the first light-emitting element ED1 and its peripheral region is applied. The second photoresist pattern PR2 can be applied up to a position close to the side surface of the bank BN adjacent to the second pixel region. According to the application area of the second photoresist pattern PR2, the length of the wings of the first inorganic layer TL1 (e.g., see Figure 18 ) to be formed later can be determined.

[0166] Next, refer to Figure 18 , a fourth etching process is performed to expose the first electrode pattern CEP1 by removing a part of the first inorganic material layer TLL1. In an embodiment, the fourth etching process can include isotropic dry etching. The first inorganic material layer TLL1 not covered by the second photoresist pattern PR2 can be removed. The first wing and the second wing of the first inorganic layer TL1 can be obtained by the fourth etching process.

[0167] Next, refer to Figure 19, a fifth etching process for removing the first photoresist pattern PR1 and the second photoresist pattern PR2, the first light-emitting pattern ELP1 and the first electrode pattern CEP1 is performed. In an embodiment, the fifth etching process may be an isotropic wet etching. Not only can the first electrode pattern CEP1 and the first light-emitting pattern ELP1 provided on the first photoresist pattern PR1 be removed, but also the first light-emitting pattern ELP1 and the first electrode pattern CEP1 in the second light-emitting region EA2 and the third light-emitting region EA3 can be removed. The first photoresist pattern PR1, the first light-emitting pattern ELP1, and the first electrode pattern CEP1 provided between the wing portion and the bank portion BN of the first inorganic layer TL1 can also be removed, and an undercut structure of the first inorganic layer TL1 can be formed. Through the fifth etching process, the upper surface of the bank portion BN can be exposed.

[0168] Next, as Figure 20 shown, a third photoresist pattern PR3 covering the first light-emitting element ED1 and the third pixel electrode AE3 is applied. The third photoresist pattern PR3 may be arranged to expose the second pixel electrode AE2 and partially overlap with the second pixel electrode AE2. The third photoresist pattern PR3 may have a tip structure in which its side surface protrudes much more than the fourth side surface BN_S4 of the bank portion BN, and the bank portion BN may have an undercut structure on the lower surface of the tip.

[0169] Next, referring to Figure 21 , the second light-emitting element ED2 is formed by depositing a second light-emitting layer EL2 and a second common electrode CE2 on the second pixel electrode AE2. After that, a second inorganic material layer TLL2 covering the second light-emitting element ED2 is formed. In this process, as Figure 21 shown, the material is deposited on the entire surface of the substrate SUB, but since the material is disconnected by the wing portion of the first inorganic layer TL1 and the tip of the third photoresist pattern PR3, the upper layer and the lower layer are separated. Since the side surface of the wing portion of the first inorganic layer TL1 does not protrude more than the third side surface BN_S3 of the bank portion BN, the second light-emitting layer EL2 and the second common electrode CE2 can also be formed on the upper surface of the bank portion BN. According to the length of the wing portion of the first inorganic layer TL1, the width and area of the second light-emitting layer EL2 and the second common electrode CE2 formed on the upper surface of the bank portion BN can vary. The second light-emitting pattern ELP2 and the second electrode pattern CEP2 may be provided on the third photoresist pattern PR3.

[0170] Next, a second inorganic material layer TLL2 covering the second light-emitting element ED2 is formed. The second inorganic material layer TLL2 may also be formed in the space between the wing portion and the bank portion BN of the first inorganic layer TL1, and may be formed to completely cover the bank portion BN, the second common electrode CE2, the second electrode pattern CEP2, and the upper surface and side surfaces of the first inorganic layer TL1 without a discontinuous portion.

[0171] Next, as Figure 22 shown, a fourth photoresist pattern PR4 covering the second light-emitting element ED2 and its peripheral region is applied. The fourth photoresist pattern PR4 may be applied up to a position close to the side surface of the bank portion BN adjacent to the third pixel region. Based on the application region of the fourth photoresist pattern PR4, the length of the wing portion of the second inorganic layer TL2 (see Figure 23 ) to be formed later can be determined.

[0172] Next, referring to Figure 23 and Figure 24 , a part of the second inorganic material layer TLL2 can be removed, and the third photoresist pattern PR3, the fourth photoresist pattern PR4, the second light-emitting pattern ELP2, and the second electrode pattern CEP2 can be removed. Such a process can be performed similar to that described in Figure 18 and Figure 19 . The second inorganic layer TL2 having a wing portion can be formed.

[0173] Next, as Figure 25 shown, a third light-emitting layer EL3, a third light-emitting pattern ELP3, a third common electrode CE3, a third electrode pattern CEP3, and a third inorganic material layer TLL3 can be formed. Such a process can be performed similar to that described in Figure 21 , but it differs in that the deposited material is interrupted by the wing portion of the second inorganic layer TL2 instead of the wing portion of the first inorganic layer TL1 and the tip of the photoresist pattern.

[0174] Next, as Figures 26 to 28 shown, by removing the third light-emitting pattern ELP3 and the third electrode pattern CEP3, a third inorganic layer TL3 including a wing portion can be obtained. When a fifth photoresist pattern PR5 covering the third light-emitting element ED3 and its peripheral region is applied and then the process shown in Figure 23 and Figure 24 is repeated, the first light-emitting element ED1, the second light-emitting element ED2, and the third light-emitting element ED3 as shown in Figure 28 , and the first inorganic layer TL1, the second inorganic layer TL2, and the third inorganic layer TL3 can be obtained.

[0175] Optionally, when performing the removal Figure 28When performing a dry etching process on a part of the upper portions of the first inorganic layer TL1, the second inorganic layer TL2, and the third inorganic layer TL3, inorganic layers TL13, TL23, and TL33 with a part of the wing portions removed as shown in Figure 29 and Figure 11 can be obtained.

[0176] Next, although not shown in the drawings, a display device 10 is manufactured by forming an organic encapsulation layer TFE2 and an upper inorganic encapsulation layer TFE3, a light blocking layer, a color filter layer CFL, and an outer coating OC of a thin film encapsulation layer TFEL on the light-emitting elements ED1, ED2, and ED3 and the bank structure. Since the structures of the thin film encapsulation layer TFEL, the light blocking layer, the color filter layer CFL, and the outer coating OC are the same as those described above, detailed descriptions thereof will be omitted.

[0177] The embodiments of the present disclosure have been described above with reference to the drawings. However, those of ordinary skill in the art to which the present disclosure pertains will understand that various modifications and changes can be made without departing from the technical spirit or basic features of the present disclosure. Therefore, it should be understood that the embodiments described above are illustrative in all features and not restrictive.

Claims

1. A display device, comprising: substrate; a first pixel electrode and a second pixel electrode, spaced apart from each other on the substrate; a pixel defining layer, disposed on the substrate and exposing the first pixel electrode and the second pixel electrode; a bank portion, disposed on the pixel defining layer; A first light-emitting layer is disposed on the first pixel electrode; A second light emitting layer is disposed on the second pixel electrode; A first common electrode, disposed on the first light-emitting layer; as well as a second common electrode disposed on the second light emitting layer and the bank and spaced apart from the first common electrode; Wherein, a width of the first common electrode and a width of the second common electrode are different from each other.

2. The display device according to claim 1, wherein: The width of the first common electrode is smaller than the width of the second common electrode.

3. The display device according to claim 1, wherein: The width of the first common electrode is smaller than the width of the first pixel electrode, and The width of the second common electrode is greater than the width of the second pixel electrode.

4. The display device according to claim 1, wherein: The first common electrode is disposed on at least a portion of a first side surface of the bank and at least a portion of a second side surface of the bank that is different from the first side surface, and The second common electrode is disposed on the entire third side surface of the bank, at least a portion of a fourth side surface of the bank different from the third side surface, and at least a portion of an upper surface of the bank.

5. The display device according to claim 1, wherein: The bank is a single film of metal or metal alloy.

6. The display device according to claim 1, further comprising: a first inorganic layer including a main body portion disposed on the first common electrode, and a wing portion disposed on the bank portion and spaced apart from an upper surface of the bank portion; as well as The second inorganic layer includes a main body portion disposed on the second common electrode and a connecting portion disposed between the bank portion and the wing portion of the first inorganic layer.

7. The display device according to claim 6, wherein: The connection portion of the second inorganic layer includes a side surface that protrudes farther than a side surface of the bank and overlaps with the first pixel electrode.

8. The display device according to claim 6, wherein: The wing portion of the first inorganic layer overlaps the second common electrode in a thickness direction of the substrate.

9. The display device according to claim 6, wherein: A lower surface of the connection portion of the second inorganic layer contacts the first inorganic layer.

10. The display device according to claim 6, wherein: The second inorganic layer further comprises: a first wing portion disposed on the wing portion of the first inorganic layer and spaced apart from an upper surface of the wing portion of the first inorganic layer; and A second wing portion is disposed on the bank and is spaced apart from the upper surface of the bank.

11. The display device according to claim 6, further comprising: a third pixel electrode, disposed on the substrate and spaced apart from the first pixel electrode and the second pixel electrode; A third light-emitting layer is arranged on the third pixel electrode; as well as A third common electrode is disposed on the third light emitting layer and the bank and is spaced apart from the first common electrode and the second common electrode.

12. The display device according to claim 11, wherein: The third common electrode is disposed on an entire fifth side surface of the bank, an entire sixth side surface of the bank different from the fifth side surface, and at least a portion of the upper surface of the bank.

13. The display device according to claim 12, wherein: A width of the third common electrode disposed on the upper surface of the bank is different from a width of the second common electrode disposed on the upper surface of the bank. 14 . The display device of claim 10 , further comprising an organic encapsulation layer disposed between the wing portion of the first inorganic layer and the first wing portion of the second inorganic layer.

15. A display device comprising: substrate; A first pixel electrode, a second pixel electrode and a third pixel electrode are spaced apart from each other on the substrate; a pixel defining layer, disposed on the substrate and exposing the first pixel electrode, the second pixel electrode and the third pixel electrode; a bank portion, disposed on the pixel defining layer; A first light-emitting layer and a first common electrode, wherein the first light-emitting layer is on the first pixel electrode, and the first common electrode is on the first light-emitting layer; a second light-emitting layer and a second common electrode, wherein the second light-emitting layer is disposed on the second pixel electrode, and the second common electrode is on the second light-emitting layer; a third light-emitting layer and a third common electrode, wherein the third light-emitting layer is disposed on the third pixel electrode, and the third common electrode is on the third light-emitting layer; as well as a first inorganic layer including a main body portion disposed on the first common electrode and a wing portion disposed on the bank portion and spaced apart from an upper surface of the bank portion, The wing portion of the first inorganic layer overlaps with the second common electrode and the third common electrode in the thickness direction of the substrate.

16. The display device according to claim 15, further comprising a second inorganic layer, the second inorganic layer comprising a main body portion provided on the second common electrode, and a connecting portion provided between the bank portion and the wing portion of the first inorganic layer, in, The connection portion of the second inorganic layer includes a side surface that protrudes farther than a side surface of the bank and overlaps with the first pixel electrode.

17. The display device according to claim 15, wherein: The first common electrode, the second common electrode, and the third common electrode have cross-sectional shapes different from each other.

18. A method for manufacturing a display device, the method comprising: forming a plurality of pixel electrodes spaced apart from each other on a substrate, forming a pixel defining material layer on the plurality of pixel electrodes, and forming a bank material layer on the pixel defining material layer; forming a first photoresist pattern on the bank material layer; etching the bank material layer not covered by the first photoresist pattern; as well as A side surface of the bank material layer is etched and a lower surface of the first photoresist pattern is exposed.

19. The method according to claim 18, wherein: Etching the bank material layer not covered by the first photoresist pattern comprises an anisotropic dry etching process, and Etching the side surface of the bank material layer and exposing the lower surface of the first photoresist pattern includes an isotropic wet etching process.

20. The method of claim 18, further comprising: forming a first light emitting layer on a first pixel electrode among the plurality of pixel electrodes, and forming a first light emitting pattern on the first photoresist pattern; forming a first common electrode on the first light emitting layer, and forming a first electrode pattern on the first light emitting pattern; forming a first inorganic material layer on the first common electrode and the first electrode pattern; forming a second photoresist pattern on the first inorganic material layer overlapping the first pixel electrode; removing the first inorganic material layer not covered by the second photoresist pattern; as well as The first photoresist pattern, the second photoresist pattern, the first light emitting pattern, and the first electrode pattern are removed.

Images