Clock doubler with correction for outputting clock cycle and clock duty cycle

Abstract

A synthesizable clock double multiplier is disclosed. The clock doubler is implemented using a unique combination of logical cells from a standard cell library. The core of the clock doubler is a high frequency ring oscillator that generates timing information for clock measurement. A replica ring oscillator is used to generate a programmable delay for correction of output clock defects, such as cycle-to-cycle variations and duty cycles of a double clock.

Description

[0001] Cross - Reference to Related Applications

[0002] This application claims priority to U.S. Provisional Patent Application No. 63 / 412,915, filed on Oct. 4, 2022, entitled “CLOCK DOUBLER WITH CORRECTION FOR OUTPUT CLOCK CYCLE AND CLOCK DUTY CYCLE”, which is hereby incorporated by reference in its entirety. Technical Field

[0003] The present disclosure relates generally to electronic devices and systems, and more particularly to circuits for generating clock signals for electronic components. Background Art

[0004] In electronic instrumentation and signal processing, a clock is a circuit that generates clock signals for timing operations of electronic components such as analog - to - digital converters (ADCs), digital - to - analog converters (DACs), etc. Clocks are used in many different applications such as automotive, communication, aerospace, defense, etc.

[0005] Various factors can affect the cost, quality, and robustness of a clock. Physical constraints such as space / surface area can impose further constraints on clock requirements or specifications, and thus trade - offs must be made and ingenuity exercised when designing a clock that is optimal for a given application. Summary of the Invention

[0006] The following presents a simplified summary of one or more aspects in order to provide a basic understanding of such aspects. This summary is not an extensive overview of all contemplated aspects, and is neither intended to identify key or critical elements of all aspects nor to delineate the scope of any or all aspects. Its sole purpose is to present some concepts of one or more aspects in a simplified form as a prelude to the more detailed description that is presented later.

[0007] According to one example, a clock doubler may include a calibration circuit that includes a ring oscillator and a first counter. The ring oscillator may be configured to identify timing information for clock measurement associated with an output clock frequency. The first counter may be configured to output the timing information for calibration of a clock having an input clock frequency. The clock doubler may further include a delay circuit that includes a replica ring oscillator and a second counter. The replica ring oscillator may be configured to determine a delay value for correction of the input clock frequency based on a defined delay value. The second counter may be configured to output the delay value for correction of the output clock frequency, which has a clock frequency that is a multiple of the input clock frequency.

[0008] According to another example, a method for clock cycle correction may include: identifying timing information for clock measurement associated with an output clock frequency via a ring oscillator. The method may further include: outputting the timing information via a first counter for calibration of a clock having an input clock frequency. The method may further include: determining a delay value for correction of the input clock frequency via a replica ring oscillator based on a defined delay value. The method may further include: outputting the delay value via the second counter for correction of the output clock frequency, which has a clock frequency that is a multiple of the input clock frequency.

[0009] According to an additional example, a clock doubler may include: means for identifying timing information for clock measurement associated with an output clock frequency. The clock doubler may further include: means for outputting the timing information for calibration of a clock having an input clock frequency. The clock doubler may further include: means for determining a delay value for correction of the input clock frequency based on a defined delay value. The clock doubler may additionally include: means for outputting the delay value for correction of the output clock frequency, which has a clock frequency that is a multiple of the input clock frequency. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] To provide a more thorough understanding of the present disclosure and its features and advantages, the following description is presented in conjunction with the accompanying drawings, in which like reference numerals represent like parts, and in which:

[0011] Figure 1 A block diagram of a clock doubler according to some embodiments of the present disclosure is provided;

[0012] Figure 2 An illustration of an example clock doubler according to some embodiments of the present disclosure is provided;

[0013] Figure 3Illustrations of example calibration circuits for a clock doubler according to some embodiments of the present disclosure are provided;

[0014] Figure 4 Illustrations of example programmable delay circuits for a clock doubler according to some embodiments of the present disclosure are provided;

[0015] Figure 5 is a flowchart of an example method for clock cycle correction according to some embodiments of the present disclosure;

[0016] Figure 6 Schematic illustrations of example systems in which one or more clock doublers may be implemented according to some embodiments of the present disclosure are provided;

[0017] Figure 7 is a block diagram of an example electrical device that may include one or more clock doublers according to some embodiments of the present disclosure; and

[0018] Figure 8 A block diagram of an example data processing system is provided that may be configured to control the operation of one or more clock doublers, which shows an example data processing system according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0019] The systems, methods, and apparatuses of the present disclosure each have several innovative aspects, no single one of which is solely responsible for all of the desired attributes disclosed herein. Details of one or more implementations of the subject matter described in the present disclosure are set forth in the following description and the accompanying drawings.

[0020] A synthesizable clock doubler is disclosed. The clock doubler is implemented using a unique combination of logic cells from a standard cell library. The core of the clock doubler is a high-frequency ring oscillator that generates timing information for clock measurement. Replica ring oscillators are used to generate programmable delays for correcting output clock defects such as cycle-to-cycle variations and duty cycles of the doubled clock.

[0021] As will be understood by those skilled in the art, aspects of the present disclosure, particularly aspects of the clock doubler presented herein, may be embodied in various ways (e.g., as a method, system, computer program product, or computer-readable storage medium). Thus, aspects of the present disclosure may take the form of an entirely hardware embodiment, an entirely software embodiment (including firmware, resident software, microcode, etc.), or an embodiment combining software aspects and hardware aspects (generally referred to herein as "circuits", "modules", or "systems"). The functions described in the present disclosure may be implemented as algorithms executed by one or more hardware processing units (e.g., one or more microprocessors) of one or more computers. In various embodiments, different steps and portions of steps of each method described herein may be executed by different processing units. Additionally, aspects of the present disclosure may take the form of a computer program product embodied in one or more computer-readable media, which are preferably non-transitory, having embodied thereon (e.g., stored thereon) computer-readable program code. In various embodiments, such computer programs may be, for example, downloaded (updated) to existing devices and systems (e.g., to existing ADCs, DACs, other electronic components, digital signal processing (DSP) cores, and / or their controllers, etc.) or stored at the time of manufacturing of these devices and systems.

[0022] The following detailed description presents various descriptions of specific certain embodiments. However, the innovations described herein may be embodied in many different ways, for example, as defined and covered by the selected examples.

[0023] In the following description, reference is made to the accompanying drawings, in which like reference numerals may indicate like or functionally similar elements. It will be understood that the elements shown in the drawings are not necessarily drawn to scale. Additionally, some embodiments may incorporate any suitable combination of features from two or more of the drawings. Further, it will be understood that certain embodiments may include more elements than shown in the drawings and / or a subset of the elements shown in the drawings. Generally, while some of the drawings provided herein illustrate various aspects of a clock doubler and systems in which such circuits may be implemented, the details of these systems may vary in different embodiments. For example, the various components of the clock doubler presented herein may have additional components included therein or coupled thereto that are not specifically shown in the drawings, such as logic, storage, passive elements (e.g., resistors), or other elements. In another example, details shown in some of the drawings herein, such as the specific arrangements and example implementation details of the various components of the clock doubler presented herein (e.g., duty cycle correction circuits, delay circuits, etc.), the specific arrangements of the coupling connections between the outputs of the stages of the clock doubler and the logic elements of the clock doubler, etc., may vary in different embodiments, where the illustrations of the present drawings only provide some examples of how these components are used together to implement a clock doubler with relatively low area and power consumption. In yet another example, although some of the embodiments shown in the present drawings show a certain number of components (e.g., a certain number of delay circuits), it should be understood that these embodiments may be implemented in a clock doubler or in any other device or system having any number of these components in accordance with the description provided herein. Additionally, although certain elements such as the various elements of the clock doubler may be depicted in the drawings as communicatively coupled using a single depicted line, in some embodiments, any of these elements may be coupled by a plurality of conductive lines such as those that may be present in a bus or those involved in differential signaling.

[0024] This description may use the phrases "in one embodiment" or "in embodiments", which may each refer to one or more of the same or different embodiments. Unless otherwise specified, the use of ordinal adjectives "first", "second", and "third", etc. to describe common objects merely indicates different instances of the same object being referred to, and is not intended to imply that the objects so described must be in a given sequence in terms of time, space, rank, or in any other way. Additionally, for the purposes of this disclosure, the phrase "A and / or B" or the symbol "A / B" means (A), (B), or (A and B), and the phrase "A, B, and / or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C). As used herein, the symbol "A / B / C" means (A, B, and / or C). The term "between" when used in reference to a measurement range includes the ends of the measurement range.

[0025] The various aspects of the exemplary embodiments are described using terms commonly employed by those skilled in the art to convey the substance of their work to other technicians in the field. For example, the term "connected" refers to a direct electrical connection between the things being connected without any intermediate device / component, while the term "coupled" refers to a direct electrical connection between the things being connected, or an indirect electrical connection through one or more passive or active intermediate devices / components. In another example, the term "circuit" or "circuitry" (which may be used interchangeably) refers to one or more passive and / or active components that are arranged to cooperate with each other to provide a desired function. Sometimes, in this specification, the term "circuit" may be omitted (e.g., a clock doubler circuit may be simply referred to as a "clock doubler", etc.). If used, based on the context of a specific value as described herein or known in the art, terms such as "substantially", "approximately", "about", etc. may generally refer to within + / - 10% of the target value, e.g., within + / - 5% of the target value or within + / - 2% of the target value.

[0026] Figure 1 A block diagram of a clock doubler 100 according to some embodiments of the present disclosure is provided. As shown, the clock doubler 100 may be configured to receive an input clock signal 102 (or simply referred to as "input clock") and output an output clock signal 104 (or simply referred to as "output clock"), where the output clock signal 104 is a double clock signal compared to the input clock signal 102 (i.e., the output clock signal 104 is a clock signal having a frequency that is substantially double the frequency of the input clock signal 102). As Figure 1As further shown, the clock doubler 100 may include a ring oscillator 110 and one or more replica ring oscillators 120. The ring oscillator 110 may be configured to generate timing information for clock measurement. In some embodiments, the ring oscillator 110 may be a high-frequency ring oscillator. The replica ring oscillator 120 may be configured to generate programmable delays for correction of output clock defects such as cycle-to-cycle variations and duty cycles of the doubled clock generated by the clock doubler 100. Figure 1 As further shown, in some embodiments, the clock doubler 100 may further include a calibration circuit 130 and / or a programmable delay circuit 140.

[0027] The clock doubler 100 can be a clock that is relatively easy to implement without analog components such as resistors and capacitors and without using analog blocks such as comparators. The clock doubler 100 can be implemented using only logic cells from a standard cell library and can thus be fully synthesizable and can be easily reused in various technologies. For example, in some implementations, the output clock signal 104 of the clock doubler 100 can be directly used for clock operation of one or more ADCs and / or one or more DACs.

[0028] Typically, the phase noise, cycle-to-cycle variations, and duty cycle of the doubled clock are the main areas of concern. In the clock doubler 100, the ring oscillator 110 may be a high-frequency self-oscillating ring oscillator for generating timing information for clock measurement and correction. The absolute error after clock calibration and correction may be limited by the clock period of the ring oscillator 110. When the ratio of the ring oscillator frequency to the doubled clock frequency is large, the relative error may be small. The clock period and duty cycle can be characterized by counting the number of ring oscillator clock cycles. The clock characterization engine can have six operating modes: input clock period measurement, input clock duty cycle measurement, doubled clock period and duty cycle measurement with the clock aligned with the high logic region of the input clock, and doubled clock period and duty cycle measurement with the clock aligned with the low logic region of the input clock. The input clock duty cycle measurement result and the doubled clock period measurement result can be used for input clock duty cycle correction. The input clock duty cycle correction can be accomplished using a single delay chain that can act on either the rising or falling edge of the clock to correct duty cycle errors above or below a target (e.g., 50% target). The replica ring oscillator 120 and a counter can be used to generate timing information that ensures the doubled clock has a duty cycle close to 50%. The ring oscillator 110 and the counter together can be considered a programmable wrap-around delay line that has the potential to generate long delays using only a few logic gates.

[0029] Figure 2 FIG. 200 illustrates an example clock doubler in accordance with some embodiments of the present disclosure. The clock doubler 200 may be an example of the clock doubler 100 of Figure 1 . To that end, some components of the clock doubler 100 are shown in the clock doubler 200. In particular, as Figure 2 shown, the clock doubler 200 may include a calibration circuit 130 that includes a ring oscillator 110, and the clock doubler 200 may further include two programmable delay circuits 140 (labeled as a first delay circuit 140-1 and a second delay circuit 140-2 in Figure 2 ), and each of the two programmable delay circuits may include a respective replica ring oscillator 120. Although not specifically shown in Figure 2 , respective counters are included in each of the calibration circuit 130 and the programmable delay circuits 140.

[0030] There are many ways to implement a clock doubler, such as XOR of an input clock with a delayed version of the input clock, using a delay-locked loop, using resistor-capacitor (RC) time constants to generate the required timing information, etc. The clock doubler 200 is a novel extension of an XOR-based clock doubler that has a built-in time reference and clock measurement and correction circuitry to generate a nearly perfect clock at twice the input clock frequency. The resulting clock doubler can consume relatively low power, have good phase noise performance, and can be fully synthesizable and easily reusable in newer technologies. A free-running ring oscillator with synchronous start control and a counter is an effective way to generate programmable long delays. The ring oscillator can also provide an input clock-independent time reference for clock measurement and correction. Overall, the clock doubler 200 is a relatively simple all-digital design suitable for software-defined radio.

[0031] The clock doubler 200 may have a wide input range for the frequency of the input clock signal 102, e.g., from about 10 megahertz (MHz) to about 80 MHz. The clock doubler 200 may be synthesizable, and all standard cell implementations have calibration for double clock cycle-to-cycle variation and duty cycle. The clock doubler 200 may use a free-running ring oscillator as a time reference for calibration and two replica ring oscillators 120 for long clock delay generation. The clock doubler 200 may implement process-voltage-temperature (PVT) tracking of multiple ring oscillators. Calibration of the clock doubler 200 may be done in the background without affecting the clock path. The clock doubler 200 may implement clock non-ideal correction that is substantially free of false signals.

[0032] Figure 3An illustration of an example calibration circuit 300 for a clock doubler (eg, clock doublers 100 and 200) is provided according to some embodiments of the present disclosure. The calibration circuit 300 may be Figure 1 An example of a calibration circuit 130 is shown.

[0033] The calibration circuit 300 may include a pulse generator 302 configured to receive a clock and count start signal and output pulses to a ring oscillator 304 and a counter 306. The ring oscillator 304 and the counter 306 may be configured to provide clock period and clock pulse width measurements. The clock period and clock pulse width may be measured as the number of ring oscillator clock cycles. The measurement results based on the reference ring oscillator may be applied to generate programmable delays using a delay circuit based on a replica ring oscillator.

[0034] Figure 4 A diagram of an example programmable delay circuit 400 for a clock doubler (eg, clock doublers 100 and 200) is provided according to some embodiments of the present disclosure. Delay circuit 400 may be Figure 1 An example of the delay circuit 140 is shown in FIG.

[0035] Delay circuit 400 may include a programmable delay circuit based on ring oscillator 402 and counter 404. When oscillator 402 starts, counter 404 may start at the value set by P[M-1:0], and a delayed pulse may be generated when counter 404 counts down to 0.

[0036] Figure 5 is a flow chart of an example method 500 for clock cycle correction. The example method 500 may be performed by the clock doubler 100 and / or 200, which may include the following: Figures 1 to 4 One or more of the components discussed in and may be based on Figures 6 to 8 to operate with the additional electrical or electronic components discussed in.

[0037] At block 502, method 500 may identify timing information for clock measurements associated with an output clock frequency. For example, calibration circuit 130 of clock doubler 100 or 200 may identify or otherwise determine timing information such as a clock period and a clock pulse width via ring oscillator 110 or 304 for clock measurements associated with an output clock (i.e., of output clock signal 104).

[0038] At block 504, method 500 may output the timing information for calibration of a clock providing the input clock frequency. For example, the calibration circuit 130 of clock doubler 100 or 200 may output the timing information via a first counter (i.e., counter 306) for calibration of a clock providing the input clock frequency.

[0039] At block 506, method 500 may determine a delay value for correction of the input clock frequency based on a defined delay value. For example, the programmable delay circuit 140 of clock doubler 100 or 200 may determine or otherwise receive a delay value for correction of the frequency of the input clock (i.e., of input clock signal 102) based on a defined delay value (i.e., delay[M-1:0]) via replica ring oscillator 120 or 402.

[0040] At block 508, method 500 may output the delay value for correction of the output clock frequency, which has a clock frequency that is a multiple of the input clock frequency. For example, the programmable delay circuit 140 of clock doubler 100 or 200 may output the delay value via a second counter (i.e., counter 404) for correction of the frequency of the output clock (i.e., of output clock signal 104), which has a clock frequency that is a multiple (i.e., double) of the input clock frequency.

[0041] In some examples, the clock period and clock pulse width may be identified based on the number of clock cycles of a ring oscillator (of ring oscillator 110).

[0042] In some examples, the delay value may be further based on the timing information (i.e., clock period and clock pulse width).

[0043] In some examples, correction of the frequency of the output clock (i.e., of output clock signal 104) may include at least one of correction of the cycle-to-cycle variation of the double clock or correction of the duty cycle of the double clock.

[0044] In some examples, the replica ring oscillator may be configured to determine a delay value based on a counter value corresponding to zero.

[0045] In some examples, the delay circuit includes two replica ring oscillators.

[0046] In various embodiments, a controller may be used to control various aspects of operation of a clock doubler 100 as described herein. Such a controller may be implemented, for example, as Figure 8 the data processing system shown.

[0047] Clock doubler 100 may be implemented in various electronic devices and systems. In Figure 6and Figure 7 Some examples are shown in

[0048] Figure 6 A schematic illustration of an example system 600 in which one or more clock doublers 100 and 200 may be implemented in accordance with some embodiments of the present disclosure is provided. In particular, Figure 6 it is shown that the clock doublers 100 and 200 may be included as part of a DSP core or DSP circuitry 610, or may be communicatively coupled to the DSP core or DSP circuitry 610. The system 600 may further include a controller 620 configured to control various aspects of operating the clock doublers 100 and 200 as described herein.

[0049] Figure 7 is a block diagram of an example electrical device 600 that may include one or more clock doublers 100 in accordance with any one of the embodiments disclosed herein. For example, any suitable component of the components of the electrical device 700 may include one or more of the clock doublers 200 disclosed herein. Figure 7 A number of components included in the electrical device 700 are shown, but any one or more of these components may be omitted or duplicated to suit the application. In some embodiments, some or all of the components included in the electrical device 700 may be attached to one or more main boards. In some embodiments, some or all of these components are fabricated on a single system-on-chip (SoC).

[0050] Additionally, in various embodiments, the electrical device 700 may not include Figure 7 one or more of the components shown, but the electrical device 700 may include interface circuitry for coupling to the one or more components. For example, the electrical device 700 may not include a display device 706, but may include display device interface circuitry (e.g., connectors and driver circuitry) to which the display device 706 may be coupled. In another set of examples, the electrical device 700 may not include an audio input device 718 or an audio output device 708, but may include audio input or output device interface circuitry (e.g., connectors and support circuitry) to which the audio input device 718 or the audio output device 708 may be coupled.

[0051] The electrical device 700 may include a processing device 702 (e.g., one or more processing devices). As used herein, the term "processing device" or "processor" may refer to any device or portion of a device that processes electronic data from registers and / or memory to transform the electronic data into other electronic data that may be stored in registers and / or memory. The processing device 702 may include one or more DSPs, application specific integrated circuits (ASICs), central processing units (CPUs), graphics processing units (GPUs), cryptographic processors (specialized processors that execute cryptographic algorithms in hardware), server processors, or any other suitable processing device. The electrical device 700 may include a memory 704, which itself may include one or more memory devices, such as volatile memory (e.g., dynamic RAM (DRAM)), non-volatile memory (e.g., read only memory (ROM)), flash memory, solid state memory, and / or a hard disk drive. In some embodiments, the memory 704 may include a memory that shares a die with the processing device 702. The memory may be used as a cache memory and may include embedded DRAM (eDRAM) or spin transfer torque magnetic RAM (STT-MRAM).

[0052] In some embodiments, the electrical device 700 may include a communication chip 712 (e.g., one or more communication chips). For example, the communication chip 712 may be configured to manage wireless communication for data transfer to and from the electrical device 700. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communication channels, etc. that may convey data by using modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they may not.

[0053] The communication chip 712 can implement any wireless standard or protocol among a variety of wireless standards or protocols, including but not limited to Institute of Electrical and Electronics Engineers (IEEE) standards, including Wi-Fi (IEEE 802.11 series), IEEE 802.16 standard (e.g., IEEE 802.16-2005 amendment), Long Term Evolution (LTE) program, and any amendments, updates, and / or revisions (e.g., Advanced LTE program, Ultra Mobile Broadband (UMB) program (also known as "3GPP2"), etc.). IEEE 802.16 compliant broadband wireless access (BWA) networks are generally referred to as WiMAX networks, which is an acronym representing Worldwide Interoperability for Microwave Access and is a certification mark for products that pass the conformance and interoperability tests of the IEEE 802.16 standard. The communication chip 712 can operate according to Global System for Mobile Communications (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE networks. The communication chip 712 can operate according to GSM Enhanced Data rates for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The communication chip 712 can operate according to Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution-Data Optimized (EV-DO), and their derivatives, and any other wireless protocols designated as 3G, 4G, 5G, and higher generations. In other embodiments, the communication chip 712 can operate according to other wireless protocols. The electrical device 700 can include an antenna 722 to facilitate wireless communication and / or receive other wireless communications (such as AM or FM radio transmissions).

[0054] In some embodiments, the communication chip 712 can manage wired communications, such as electrical communication protocols, optical communication protocols, or any other suitable communication protocol (e.g., Ethernet). As described above, the communication chip 712 can include multiple communication chips. For example, a first communication chip 712 can be dedicated to short-range wireless communications such as Wi-Fi or Bluetooth, and a second communication chip 712 can be dedicated to long-range wireless communications such as Global Positioning System (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, or others. In some embodiments, the first communication chip 712 can be dedicated to wireless communications, and the second communication chip 712 can be dedicated to wired communications.

[0055] The electrical device 700 may include a battery / power circuitry 714. The battery / power circuitry 714 may include one or more energy storage devices (e.g., batteries or capacitors) and / or circuitry for coupling components of the electrical device 700 to an energy source (e.g., AC line power) separate from the electrical device 700.

[0056] The electrical device 700 may include a display device 706 (or corresponding interface circuitry, as described above). The display device 706 may include any visual indicator, such as a heads-up display, a computer monitor, a projector, a touchscreen display, a liquid crystal display (LCD), a light-emitting diode display, or a flat panel display.

[0057] The electrical device 700 may include an audio output device 708 (or corresponding interface circuitry, as described above). The audio output device 708 may include any device that generates an audible indicator, such as a speaker, headphones, or earbuds.

[0058] The electrical device 700 may include an audio input device 718 (or corresponding interface circuitry, as described above). The audio input device 718 may include any device that generates a signal representative of sound, such as a microphone, a microphone array, or a digital musical instrument (e.g., an instrument having a Musical Instrument Digital Interface (MIDI) output).

[0059] The electrical device 2100 may include a GPS device 716 (or corresponding interface circuitry, as described above). The GPS device 716 may communicate with a satellite-based system and may receive the location of the electrical device 700, as is known in the art.

[0060] The electrical device 700 may include another output device 710 (or corresponding interface circuitry, as described above). Examples of other output devices 710 may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or additional storage devices.

[0061] The electrical device 700 may include another input device 720 (or corresponding interface circuitry, as described above). Examples of other input devices 720 may include an accelerometer, a gyroscope, a compass, an image capture device, a keyboard, a cursor control device such as a mouse, a stylus, a touchpad, a barcode reader, a Quick Response (QR) code reader, any sensor, or a radio frequency identification (RFID) reader.

[0062] The electrical device 700 can have any desired form factor, such as a handheld or mobile electrical device (e.g., a cell phone, smartphone, mobile Internet device, music player, tablet computer, laptop computer, netbook computer, ultrabook computer, personal digital assistant (PDA), ultra-mobile personal computer, etc.), a desktop electrical device, a server device or other networked computing components, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a vehicle control unit, a digital camera, a digital video recorder or a wearable electrical device. In some embodiments, the electrical device 700 can be any other electronic device that processes data.

[0063] Figure 8 A block diagram is provided showing an example data processing system 800 in accordance with some embodiments of the present disclosure, which example data processing system can be configured to control the operation of one or more clock doublers 100. For example, the data processing system 800 can be configured to implement or control the clock doubler 100, the clock doubler 200, or portions of any additional embodiments of the clock doublers described herein. In another example, the data processing system 800 can be configured to implement the controller 520 or at least portions of any other controller configured to control various aspects of operating a clock doubler as described herein.

[0064] As Figure 8 shown, the data processing system 800 can include at least one processor 802 (e.g., a hardware processor 802) that is coupled to a memory element 804 via a system bus 806. As such, the data processing system can store program code within the memory element 804. Additionally, the processor 802 can execute the program code retrieved from the memory element 804 via the system bus 806. In one aspect, the data processing system can be implemented as a computer suitable for storing and / or executing program code. However, it should be understood that the data processing system 800 can be implemented in the form of any system including a processor and a memory that is capable of performing the functions described within the present disclosure.

[0065] In some embodiments, the processor 802 can execute software or algorithms to perform the activities discussed in the present disclosure, particularly those related to a clock doubler as described herein. The processor 802 can include any combination of hardware, software, or firmware that provides programmable logic, including, by way of non-limiting example, a microprocessor, a DSP, a field programmable gate array (FPGA), a programmable logic array (PLA), an application specific IC (ASIC), or a virtual machine processor. The processor 802 can be communicatively coupled to the memory element 804 (e.g., in a direct memory access (DMA) configuration) such that the processor 802 can read from or write to the memory element 804.

[0066] In general, memory element 804 may include any suitable volatile or non-volatile memory technology, including double data rate (DDR) random access memory (RAM), synchronous RAM (SRAM), dynamic RAM (DRAM), flash memory, read-only memory (ROM), optical media, virtual memory regions, magnetic or tape memory, or any other suitable technology. Unless otherwise stated, any memory element among the memory elements discussed herein shall be construed as being included within the broad term "memory". Information measured, processed, tracked, or transmitted to or from any component of data processing system 2200 may be provided in any database, register, control list, cache, or storage structure, all of which may be referenced within any suitable time frame. Any such storage option may be included within the broad term "memory" as used herein. Similarly, any of the potential processing elements, modules, and machines described herein shall be construed as being included within the broad term "processor". Each of the elements shown in this figure (e.g., Figures 1 to 4 any element of clock doubler 100 shown in

[0067] In certain example embodiments, the mechanisms for implementing one or more clock doublers as outlined herein may be implemented by logic encoded in one or more tangible media (e.g., embedded logic provided in an ASIC, DSP instructions, software (potentially including object code and source code) to be executed by a processor or other similar machine, etc.), and the one or more tangible media may include non-transitory media. In some of these instances, a memory element (such as Figure 8 memory element 804 shown in Figure 8The processor 802 shown in [Figure] can transform an element or article (e.g., data) from one state or thing to another. In another example, the activities outlined herein can be implemented using fixed logic or programmable logic (e.g., software / computer instructions executed by a processor), and the elements identified herein can be a programmable processor of some type, programmable digital logic (e.g., FPGA, DSP, erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM)), or an ASIC that includes digital logic, software, code, electronic instructions, or any suitable combination thereof.

[0068] The memory element 804 can include one or more physical memory devices, such as, for example, local memory 808 and one or more mass storage devices 810. Local memory can refer to RAM or other non-persistent memory devices that are typically used during the actual execution of program code. The mass storage device can be implemented as a hard disk drive or other persistent data storage device. The processing system 800 can also include one or more cache memories (not shown) that provide temporary storage of at least some program code to reduce the number of times program code must be retrieved from the mass storage device 810 during execution.

[0069] As Figure 8 shown, the memory element 804 can store an application 818. In various embodiments, the application 818 can be stored in the local memory 808, one or more mass storage devices 810, or separately from the local memory and the mass storage device. It should be understood that the data processing system 800 can further execute an operating system ( Figure 8 not shown in [Figure]) that can facilitate the execution of the application 818. The application 818, implemented in the form of executable program code, can be executed by the data processing system 800, e.g., by the processor 802. In response to executing the application, the data processing system 800 can be configured to perform one or more of the operations or method steps described herein.

[0070] Input / output (I / O) devices depicted as input device 812 and output device 814 may optionally be coupled to the data processing system. Examples of input devices may include, but are not limited to, keyboards, pointing devices such as mice, etc. Examples of output devices may include, but are not limited to, monitors or displays, speakers, etc. In some embodiments, output device 814 may be any type of screen display, such as a plasma display, a liquid crystal display (LCD), an organic light emitting diode (OLED) display, an electroluminescent (EL) display, or any other indicator, such as a dial, a barometer, or an LED. In some implementations, the system may include a driver (not shown) for output device 814. The input and / or output devices 812, 814 may be coupled to the data processing system directly or through an intermediate I / O controller.

[0071] In one embodiment, the input and output devices may be implemented as a combined input / output device (shown in Figure 8 where the dashed line encloses input device 812 and output device 814). An example of such a combined device is a touch-sensitive display, sometimes also referred to as a "touchscreen display" or simply a "touchscreen". In such embodiments, input to the device may be provided by the movement of a physical object, such as a user's stylus or finger, on or near the touchscreen display.

[0072] Optionally, network adapter 816 may also be coupled to the data processing system to enable it to be coupled to other systems, computer systems, remote network devices, and / or remote storage devices through an intermediate private or public network. The network adapter may include a data receiver for receiving data sent to the data processing system 800 by the systems, devices, and / or networks, and a data transmitter for sending data from the data processing system 800 to the systems, devices, and / or networks. Modems, cable modems, and Ethernet cards are examples of different types of network adapters that may be used with the data processing system 800.

[0073] The following paragraphs provide various examples of the embodiments disclosed herein.

[0074] Example 1 provides a clock doubler configured to perform clock measurement using a synchronously triggered self-excited ring oscillator as a time reference and a counter.

[0075] Example 2 provides a clock doubler configured to perform long programmable delay generation using a synchronously triggered self-excited replica ring oscillator and a counter.

[0076] Example 3 provides a clock doubler configured to use background clock calibration and a clock correction technique that is substantially free of false signals.

[0077] Example 4 provides an electronic device that includes a clock doubler according to any one of the foregoing examples and / or according to any embodiment of the present disclosure.

[0078] Example 5 provides the electronic device according to Example 4, wherein the electronic device is a digital signal processing core or a digital signal processing circuitry.

[0079] Example 6 provides the electronic device according to Example 4 or 5, wherein the clock doubler is used for clock operation of one or more ADCs and / or one or more DACs.

[0080] Example 7 provides a method for operating a clock doubler according to any embodiment described herein.

[0081] Example 8 provides a non-transitory computer-readable storage medium that includes instructions for execution, which are operable to perform the operations of the method according to Example 7 when executed by a processor.

[0082] Although the embodiments of the present disclosure have been described above with reference to exemplary embodiments as Figures 1 to 8 illustrated, those skilled in the art will recognize that the various teachings above are applicable to a large number of other embodiments.

[0083] In the discussion of the above embodiments, components of the system, such as counters, logic elements (e.g., XOR gates) and / or other components can be readily replaced, substituted, or otherwise modified to accommodate the needs of a particular circuitry. Additionally, it should be noted that using complementary electronic devices, hardware, software, etc. provides equally viable options for implementing the teachings of the present disclosure related to implementing one or more clock doublers.

[0084] Portions of the various systems for implementing one or more clock doublers as presented herein can include electronic circuitry for performing the functions described herein. In some cases, one or more portions of the system can be provided by a processor specifically configured to perform the functions described herein. For example, the processor can include one or more dedicated components, or can include programmable logic gates configured to perform the functions described herein. The circuitry can operate in the analog domain, digital domain, or in a mixed-signal domain. In some instances, the processor can be configured to perform the functions described herein by executing one or more instructions stored on a non-transitory computer-readable storage medium.

[0085] In some embodiments, any number of the circuits of this figure can be implemented on the board of an associated electronic device. The board can be a general-purpose circuit board that can house various components of the internal electronic system of the electronic device and further provide connectors for other peripheral devices. More specifically, the board can provide electrical connections through which other components of the system can communicate electrically. Any suitable processor (including DSP, microprocessor, support chipset, etc.), computer-readable non-transitory memory elements, etc. can be appropriately coupled to the board based on specific configuration requirements, processing needs, computer design, etc. Other components (such as external storage, additional sensors, controllers for audio / video display, and peripheral devices) can be attached to the board via a cable as a plug-in card or integrated into the board itself. In various embodiments, the functions described herein can be implemented in emulation form as software or firmware running within one or more configurable (e.g., programmable) elements arranged in a structure that supports these functions. The software or firmware providing the emulation can be provided on a non-transitory computer-readable storage medium including instructions that allow a processor to execute these functions.

[0086] In some embodiments, the circuits in this figure can be implemented as stand-alone modules (e.g., devices having associated components and circuitry configured to perform a particular application or function), or as plug-in modules into the dedicated hardware of an electronic device. Note that particular embodiments of the present disclosure can be readily included, in part or in whole, in a system-on-chip (SOC) package. An SOC represents an IC that integrates the components of a computer or other electronic system onto a single chip. It can contain digital signals, analog signals, mixed signals, and typically RF functions: all of these functions can be provided on a single chip substrate. Other embodiments can include multi-chip modules (MCMs), where a plurality of separate ICs are located within a single electronic package and are configured to interact closely with each other through the electronic package.

[0087] All specifications, dimensions, and relationships outlined herein (e.g., the number of components or parts of a clock doubler shown in this figure, etc.) are provided for purposes of example and teaching only. Such information can vary quite significantly without departing from the spirit of the present disclosure or the scope of the appended claims. The description is applicable only to one non-limiting example, and thus, they should be so construed. In the foregoing description, exemplary embodiments have been described with reference to specific processors and / or component arrangements. Various modifications and changes can be made to such embodiments without departing from the scope of the appended claims. Accordingly, the description and drawings are to be regarded as illustrative, rather than restrictive.

[0088] Note that, using the numerous examples provided herein, interactions can be described with two, three, four, or more electronic components. However, this is done solely for clarity and example purposes. It should be understood that the system can be integrated in any suitable manner. Along similar design alternatives, any one of the components, modules, and elements shown in this figure can be combined in a variety of possible configurations, all of which are clearly within the broad scope of this disclosure. In some cases, it may be easier to describe one or more of the functionalities of a given set of processes by referring only to a limited number of electrical components. It should be understood that the circuits of this figure and its teachings are readily extensible and can accommodate a large number of components as well as more complex or elaborate arrangements and configurations. Accordingly, the examples provided should not limit the scope of the circuits or inhibit the broad teachings of the circuits, as the circuits are potentially applicable to numerous other architectures.

[0089] In addition, the functions related to implementing one or more clock doublers as presented herein only show some of the possible functions that can be performed by or within the systems shown in this figure. Some of these operations can be deleted or removed where appropriate, or can be substantially modified or changed without departing from the scope of this disclosure. In addition, substantial changes can be made to the timing of these operations. The foregoing operational flow is provided for purposes of example and discussion. The embodiments described herein provide substantial flexibility because any suitable arrangement, schedule, configuration, and timing mechanism can be provided without departing from the teachings of this disclosure.

[0090] Note that all optional features of the above devices can also be implemented with respect to the methods or processes described herein, and the specific details in the examples can be used anywhere in one or more of the embodiments.

[0091] Those skilled in the art can determine many other changes, substitutions, variations, alterations, and modifications, and this disclosure is intended to embrace all such changes, substitutions, variations, alterations, and modifications as falling within the scope of the appended claims.

Claims

1. A clock doubler, the clock doubler comprises: a calibration circuit, the calibration circuit includes a ring oscillator and a first counter, wherein the ring oscillator is configured to identify timing information for clock measurement associated with an output clock frequency; and the first counter is configured to output the timing information for providing calibration of a clock of an input clock frequency; a delay circuit, the delay circuit includes a replica ring oscillator and a second counter, wherein the replica ring oscillator is configured to determine a delay value based on a defined delay value for correction of the input clock frequency; and the second counter is configured to output the delay value for correction of the output clock frequency, the output clock frequency having a clock frequency that is a multiple of the input clock frequency.

2. The clock doubler according to claim 1, wherein the timing information includes a clock period and a clock pulse width.

3. The clock doubler according to claim 2, wherein the clock period and the clock pulse width are identified based on the number of ring oscillator clock cycles.

4. The clock doubler according to claim 1, wherein the delay value is further based on the timing information.

5. The clock doubler according to claim 1, wherein the correction of the output clock frequency includes at least one of correction of double clock cycle-to-cycle variation or correction of the duty cycle of the double clock.

6. The clock doubler according to claim 1, wherein the replica ring oscillator is configured to determine a delay value based on a counter value corresponding to zero.

7. The clock doubler according to claim 1, wherein the delay circuit includes two replica ring oscillators.

8. A method for clock cycle correction, the method comprises: identifying timing information via a ring oscillator for clock measurement associated with an output clock frequency; outputting the timing information via a first counter for providing calibration of a clock of an input clock frequency; determining a delay value via a replica ring oscillator based on a defined delay value for correction of the input clock frequency; and outputting the delay value via the second counter for correction of the output clock frequency, the output clock frequency having a clock frequency that is a multiple of the input clock frequency.

9. The method according to claim 8, wherein the timing information includes a clock period and a clock pulse width.

10. The method according to claim 9, wherein the clock period and the clock pulse width are identified based on the number of ring oscillator clock cycles.

11. The method according to claim 8, wherein the delay value is further based on the timing information.

12. The method according to claim 8, wherein the correction of the output clock frequency includes at least one of correction of double clock cycle-to-cycle variation or correction of the duty cycle of the double clock.

13. The method according to claim 8, wherein the replica ring oscillator is configured to determine a delay value based on a counter value corresponding to zero.

14. The method according to claim 8, wherein the delay circuit includes two replica ring oscillators.

15. A clock doubler, the clock doubler comprising: means for identifying timing information for clock measurement associated with an output clock frequency; and means for outputting the timing information for calibration of a clock providing an input clock frequency; means for determining a delay value based on a defined delay value for correction of the input clock frequency; and means for outputting the delay value for correction of the output clock frequency, the output clock frequency having a clock frequency that is a multiple of the input clock frequency.

16. The clock doubler according to claim 15, wherein the timing information includes a clock period and a clock pulse width.

17. The clock doubler according to claim 16, wherein the clock period and the clock pulse width are identified based on the number of ring oscillator clock cycles.

18. The clock doubler according to claim 16, wherein the delay value is further based on the timing information.

19. The clock doubler according to claim 16, wherein the correction of the output clock frequency includes at least one of correction of a double clock cycle-to-cycle variation or correction of a duty cycle of the double clock.

20. The clock doubler according to claim 16, wherein the replica ring oscillator is configured to determine a delay value based on a counter value corresponding to zero.

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