Display panel and display device thereof

Abstract

The invention provides a display panel and a display device thereof. The display panel comprises a substrate; the gate conductive layer is located on the substrate; the gate insulating layer is positioned on one side, deviating from the substrate, of the gate conductive layer; the semiconductor layer is located on the side, away from the substrate, of the gate insulating layer; the etching barrier layer is located on the side, away from the substrate, of the semiconductor layer; the etching barrier layer comprises a first contact hole; the source-drain layer is positioned on one side, deviating from the substrate, of the etching barrier layer; the source drain layer is connected with the semiconductor layer through the first contact hole.

Description

Display panel and display device thereof Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display panel and a display device thereof. Background Art

[0002] Thin-film transistors (TFTs) are the primary driving components in current liquid crystal displays (LCDs) and active-matrix organic light-emitting diodes (AMOLEDs), directly impacting the display performance of these devices. Most LCDs currently on the market are backlit, consisting of a liquid crystal display panel and a backlight module. Oxide semiconductor materials such as indium gallium zinc oxide (IGZO) are widely used in display devices due to their high mobility and on-state current. However, current technologies can render oxide products conductive, causing damage and thus impacting performance.

[0003] Taking liquid crystal displays (LCDs) and active matrix organic light-emitting diodes (AMOLEDs) as examples, both include array substrates, on which a large number of data lines and gate lines are arranged. However, electrostatic discharge (ESD) often occurs at the intersection of the gate and data lines due to the release of charge on the data and gate lines, causing a short circuit between the data and gate lines and resulting in poor display.

[0004] Summary of the Invention

[0005] The display panel provided by the embodiment of the present disclosure includes:

[0006] substrate;

[0007] A gate conductive layer is located on the substrate;

[0008] a gate insulating layer, located on a side of the gate conductive layer facing away from the substrate;

[0009] a semiconductor layer, located on a side of the gate insulating layer facing away from the substrate;

[0010] an etch stop layer, located on a side of the semiconductor layer facing away from the substrate; the etch stop layer includes a first contact hole;

[0011] The source and drain layers are located on a side of the etch stop layer away from the substrate; the source and drain layers are connected to the semiconductor layer through the first contact hole.

[0012] In some possible implementations, the display panel includes a shift register, and the shift register includes an output transistor;

[0013] The semiconductor layer includes: an active layer of the output transistor;

[0014] The source-drain layer includes: a first electrode and a second electrode of the output transistor;

[0015] The first contact hole includes a first sub-contact hole and a second sub-contact hole; the first electrode is connected to the active layer through the first sub-contact hole, and the second electrode is connected to the active layer through the second sub-contact hole;

[0016] The etch stop layer further includes a second contact hole, wherein the orthographic projection of the second contact hole on the base substrate is located between the orthographic projection of the first electrode and the orthographic projection of the second electrode on the base substrate, and the orthographic projection of the second contact hole on the base substrate has an overlapping area with the orthographic projection of the active layer on the base substrate;

[0017] The source-drain layer also includes: a first virtual electrode, the orthographic projection of the first virtual electrode on the base substrate is located between the orthographic projections of the first electrode and the second electrode on the base substrate, and the orthographic projection of the first virtual electrode on the base substrate covers the orthographic projection of the second contact hole on the base substrate.

[0018] In some possible implementations, the active layer includes a plurality of sub-active layers, the plurality of sub-active layers are spaced apart from each other along a first direction, and the first electrode, the first dummy electrode, and the second electrode are spaced apart from each other along a second direction;

[0019] Each of the plurality of sub-active layers corresponds to the first sub-contact hole, the second sub-contact hole, and the second contact hole, respectively.

[0020] In some possible implementations, the first sub-contact hole, the second contact hole, and the second sub-contact hole are spaced apart from each other along the second direction;

[0021] An edge of the first sub-contact hole and an edge of the second contact hole have a first length in the second direction;

[0022] An edge of the second sub-contact hole and an edge of the second contact hole have a second length in the second direction;

[0023] The ratio between the first length and the second length is 0.8-1.

[0024] In some possible implementations, the active layer has a first width in the first direction.

[0025] The first sub-contact hole has a second width in the first direction, the second sub-contact hole has a third width in the first direction, and the second contact hole has a fourth width in the first direction.

[0026] At least one of the second width, the third width, and the fourth width is greater than the first width.

[0027] In some possible implementations, two or more of the second width, the third width, and the fourth width are the same.

[0028] In some possible implementations, the base substrate includes a display area and a non-display area;

[0029] The display area includes sub-pixels arranged in an array;

[0030] The non-display area includes a first area position; the first area position includes a plurality of cascaded shift registers, a plurality of transfer holes, a plurality of common voltage signal lines, a first dummy filling area, and a second dummy filling area;

[0031] The shift register and the orthographic projection of the sub-pixel on the base substrate are located on different sides of the orthographic projection of the common voltage signal line on the base substrate;

[0032] The orthographic projection of the transfer hole on the base substrate is located between the orthographic projection of the shift register on the base substrate and the orthographic projection of the common voltage signal line on the base substrate;

[0033] The orthographic projection of the first dummy filling area on the base substrate is located between the sub-pixel and the orthographic projection of the common voltage signal line on the base substrate; the first dummy filling area includes a plurality of second dummy electrodes spaced apart from each other;

[0034] The orthographic projection of the second dummy filling area on the base substrate is located between the transfer hole and the orthographic projection of the common voltage signal line on the base substrate; the second dummy filling area includes a plurality of second dummy electrodes spaced apart from each other;

[0035] The first region is located at a corner of the base substrate.

[0036] In some possible implementations, the non-display area further includes: a second area position; the second area position includes a plurality of cascaded shift registers, a plurality of transfer electrodes, a plurality of common voltage signal lines, a plurality of data fan-out lines, a third dummy filling area, a fourth dummy filling area, and a fifth dummy filling area;

[0037] The shift register and the orthographic projection of the sub-pixel on the base substrate are located on different sides of the orthographic projection of the common voltage signal line on the base substrate;

[0038] The orthographic projection of the switching electrode on the base substrate is located between the shift register and the orthographic projection of the common voltage signal line on the base substrate;

[0039] The orthographic projection of the data fan-out line on the base substrate is located between the common voltage signal line and the orthographic projection of the sub-pixel on the base substrate;

[0040] The orthographic projection of the third dummy filling area on the base substrate is located between the sub-pixel and the orthographic projection of the data fan-out line on the base substrate; the third dummy filling area includes a plurality of second dummy electrodes spaced apart from each other;

[0041] The orthographic projection of the fourth dummy filling area on the base substrate is located between the orthographic projection of the common voltage signal line and the data fan-out line on the base substrate; the fourth dummy filling area includes a plurality of second dummy electrodes spaced apart from each other;

[0042] The orthographic projection of the fifth dummy filling area on the base substrate is located between the common voltage signal line and the orthographic projection of the switching electrode on the base substrate; the fifth dummy filling area includes a plurality of second dummy electrodes spaced apart from each other;

[0043] Wherein, the second region is located at a corner of the base substrate.

[0044] In some possible implementations, the non-display area further includes a third area; the third area includes a grid-shaped hollow area formed by a plurality of common signal lines intersecting each other, a transfer area, a dummy transistor area, a sixth dummy filling area, and a seventh dummy filling area;

[0045] The orthographic projection of the transfer area on the base substrate overlaps with the orthographic projection of a portion of the common signal line on the base substrate;

[0046] The orthographic projection of the dummy transistor region on the substrate is located between the transfer region and the orthographic projection of the sub-pixel on the substrate;

[0047] The orthographic projection of the sixth dummy filling area on the base substrate overlaps with the orthographic projection of the grid-shaped hollow area on the base substrate; the sixth dummy filling area includes a plurality of second dummy electrodes spaced apart from each other;

[0048] The orthographic projection of the seventh dummy filling region on the base substrate is located between the orthographic projections of the dummy transistor region and the transfer region on the base substrate; the seventh dummy filling region includes a plurality of second dummy electrodes spaced apart from each other.

[0049] In some possible implementations, the non-display area further includes a fourth region; the fourth region includes a plurality of input terminals, a plurality of first conductive signal lines, a plurality of second conductive signal lines, a plurality of test signal lines, and a plurality of second virtual electrodes spaced apart from each other;

[0050] The plurality of test signal lines are arranged in a one-to-one correspondence with the plurality of input terminals; the first conductive signal line is located on both sides of the input terminal; and the second conductive signal line is located on one side of the input terminal;

[0051] The orthographic projection of the second virtual electrode on the base substrate does not overlap with the orthographic projections of the first conductive signal line, the input terminal, and the second conductive signal line on the base substrate;

[0052] The orthographic projection of the second virtual electrode on the base substrate overlaps and / or does not overlap with the orthographic projections of the plurality of test signal lines on the base substrate.

[0053] In some possible implementations, a distance between adjacent second virtual electrodes along the first direction is a first distance, and a distance between adjacent second virtual electrodes along the second direction is a second distance;

[0054] The values ​​of the length of the second virtual electrode, the width of the second virtual electrode, the first spacing, and the second spacing are maintained between 2 micrometers and 10 micrometers.

[0055] In some possible embodiments, the etching stop layer has multiple first through holes, at least one second virtual electrode is arranged corresponding to at least one first through hole, and the orthographic projection of the second virtual electrode on the substrate covers the orthographic projection of the corresponding first through hole on the substrate.

[0056] In some possible implementations, the etch stop layer further has at least one transfer virtual hole;

[0057] The orthographic projection of the transfer virtual hole on the base substrate does not overlap with the orthographic projection of the shift register on the base substrate; the shift register is located in a first shift register area, and the transfer virtual hole is located in the first shift register area;

[0058] Wherein, the first shift register area is located at a corner of the base substrate.

[0059] In some possible implementations, the transfer virtual hole further penetrates the gate insulating layer;

[0060] a first insulating layer located on a side of the source and drain electrodes facing away from the substrate, wherein the transfer virtual hole further penetrates the first insulating layer;

[0061] The second insulating layer is located on a side of the first insulating layer facing away from the base substrate, and the transfer virtual hole also passes through the second insulating layer.

[0062] In some possible implementations, the gate conductive layer includes the plurality of gate lines, and the display panel further includes at least one dummy transistor;

[0063] One end of at least one gate line among the plurality of gate lines is connected to at least one dummy transistor.

[0064] In some possible implementations, the same end of each of the plurality of gate lines is connected to at least one of the dummy transistors.

[0065] In some possible implementations, the display panel includes a display area and a non-display area, the display area includes sub-pixels arranged in an array; the non-display area includes a plurality of shift registers, and the display area includes a plurality of gate lines; the plurality of shift registers and the plurality of gate lines are correspondingly connected;

[0066] The shift register is provided with an orthographic projection of at least one dummy transistor on the substrate between an orthographic projection of the substrate and an orthographic projection of the corresponding gate line on the substrate.

[0067] In some possible implementations, the plurality of shift registers are located in a second shift register area;

[0068] The shift registers in the second shift register area are arranged sequentially along the second direction; the orthographic projection of the dummy transistor on the base substrate is located between the orthographic projection of the sub-pixel on the base substrate and the orthographic projection of the second shift register area on the base substrate;

[0069] The dummy transistor is away from one side of the sub-pixel along a first direction; and the adjacent dummy transistors are arranged opposite to each other along the second direction on the orthographic projection of the substrate.

[0070] In some possible implementations, the plurality of shift registers are located in a third shift register area; and a plurality of data fan-out lines are provided between the third shift register area and the sub-pixels;

[0071] The orthographic projection of a dummy transistor connected to one end of the gate line close to the shift register on the substrate is located between the data fan-out line and the orthographic projection of the sub-pixel on the substrate; wherein the dummy transistor is away from one side of the sub-pixel along the first direction; and the orthographic projections of adjacent dummy transistors on the substrate are arranged opposite to each other along the second direction.

[0072] In some possible implementations, the semiconductor layer further includes: a first active layer and a second active layer of the dummy transistor;

[0073] The source-drain layer further includes: a first electrode and a second electrode of the dummy transistor;

[0074] The etch stop layer further includes a third contact hole and a fourth contact hole;

[0075] The first electrode of the dummy transistor is connected to the first active layer through the third contact hole, and the second electrode of the dummy transistor is connected to the second active layer through the fourth contact hole.

[0076] In some possible implementations, the first active layer and the second active layer are arranged spaced apart from each other along the second direction, and the first electrode and the second electrode of the dummy transistor are arranged spaced apart from each other along the second direction.

[0077] The display device provided by the embodiment of the present disclosure includes the above-mentioned display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0078] FIG1 is a schematic cross-sectional view of a display panel along the CC′ direction according to an embodiment of the present disclosure;

[0079] FIG2 is some equivalent circuit diagrams of the shift register in the embodiment of the present disclosure;

[0080] FIG3 is a schematic diagram of some structures of a shift register in an embodiment of the present disclosure;

[0081] FIG4 is a schematic diagram of some structures of a display panel in an embodiment of the present disclosure;

[0082] FIG5 is a schematic diagram of another structure of a display panel in an embodiment of the present disclosure;

[0083] FIG6 is a schematic diagram of some further structures of a display panel in an embodiment of the present disclosure;

[0084] FIG7 is a schematic diagram of some further structures of a display panel in an embodiment of the present disclosure;

[0085] FIG8 is a schematic diagram of some further structures of a display panel in an embodiment of the present disclosure;

[0086] FIG9 is a schematic diagram of some further structures of a display panel in an embodiment of the present disclosure;

[0087] FIG10 is a schematic diagram of some further structures of a display panel in an embodiment of the present disclosure;

[0088] FIG11 is a schematic diagram of some further structures of a display panel in an embodiment of the present disclosure;

[0089] FIG12 is a schematic diagram of some further structures of a display panel in an embodiment of the present disclosure;

[0090] FIG13 is a schematic diagram of some further structures of a display panel in an embodiment of the present disclosure;

[0091] FIG14 is a schematic diagram of some further structures of a display panel in an embodiment of the present disclosure;

[0092] FIG15 is a schematic diagram of some further structures of a display panel in an embodiment of the present disclosure;

[0093] FIG16 is a schematic diagram of some further structures of a display panel in an embodiment of the present disclosure;

[0094] FIG17 is a schematic diagram of some further structures of a display panel in an embodiment of the present disclosure;

[0095] FIG18 is a schematic diagram of some further structures of a display panel in an embodiment of the present disclosure;

[0096] FIG19 is a schematic diagram of some further structures of a display panel in an embodiment of the present disclosure;

[0097] FIG20 is a schematic diagram of some further structures of a display panel in an embodiment of the present disclosure;

[0098] FIG21 is a schematic diagram of some further structures of a display panel in an embodiment of the present disclosure;

[0099] FIG22 is a schematic diagram of some further structures of a display panel in an embodiment of the present disclosure;

[0100] FIG23 is a schematic diagram of some further structures of a display panel in an embodiment of the present disclosure;

[0101] FIG24 is a schematic diagram of some further structures of a display panel in an embodiment of the present disclosure;

[0102] FIG25 is a schematic diagram of some further structures of a display panel in an embodiment of the present disclosure;

[0103] FIG26 is a schematic diagram of some further structures of a display panel in an embodiment of the present disclosure;

[0104] FIG27 is a schematic diagram of some further structures of the display panel in the embodiment of the present disclosure. DETAILED DESCRIPTION

[0105] In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. And in the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be combined with each other. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0106] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by persons of ordinary skill in the field to which this disclosure belongs. The words "first", "second" and similar terms used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" mean that the elements or objects preceding the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

[0107] It should be noted that the sizes and shapes of the figures in the accompanying drawings do not reflect the actual scale and are only for the purpose of illustrating the present invention. The same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions.

[0108] The display panel provided by the embodiment of the present disclosure, as shown in FIG1 , includes:

[0109] Base substrate 10;

[0110] The gate conductive layer 20 is located on the base substrate 10;

[0111] The gate insulating layer 30 is located on a side of the gate conductive layer 20 facing away from the base substrate 10;

[0112] The semiconductor layer 40 is located on the side of the gate insulating layer 30 facing away from the substrate 10;

[0113] The etch stop layer 50 is located on the side of the semiconductor layer 40 facing away from the substrate 10 ; the etch stop layer 50 includes a first contact hole 510 ;

[0114] The source-drain layer 60 is located on the side of the etch stop layer 50 facing away from the substrate; the source-drain layer 60 is connected to the semiconductor layer 40 through the first contact hole 510 .

[0115] The present disclosure provides a substrate, a gate conductive layer, a semiconductor layer, an etch stop layer and a source / drain layer, and connects the source / drain layer to the semiconductor layer through a first contact hole in the etch stop layer. This ensures that the etching process of the source / drain layer and the etch stop layer will not adversely affect the characteristics of the oxide product in the display panel, further improves the conductivity of the oxide product, reduces damage and thus improves performance.

[0116] It should be noted that the etch stop layer can serve as a protective layer during the etching process of the source and drain layers, thereby preventing damage to the semiconductor layer during the etching process, thereby preventing adverse effects on the product.

[0117] Exemplarily, as shown in FIG1 , the display panel further includes: a first insulating layer 70 located on the side of the source / drain layer 60 facing away from the base substrate; and a second insulating layer 80 located on the side of the first insulating layer 70 facing away from the base substrate.

[0118] Exemplarily, the gate conductive layer and the source and drain layers are made of conductive materials, for example, the conductive material is metal, such as titanium (Ti), gold (Au), silver (Ag), molybdenum (Mo), copper (Cu), aluminum (Al), etc., which are not limited here.

[0119] For example, the material of the semiconductor layer may include oxide, amorphous silicon, low-temperature polysilicon, etc., which is not limited here.

[0120] Illustratively, the gate insulating layer, the etch stop layer, the first insulating layer, and the second insulating layer are all formed of insulating materials. As needed, organic insulating materials such as polyimide, resin materials, etc. can be selected, or inorganic insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, etc. can be selected. The embodiments of the present disclosure do not specifically limit the materials of each functional layer.

[0121] For example, the equivalent circuit diagram of the shift register shown in FIG2 includes: a first transistor M1, a second transistor M2, a third transistor M3, an output transistor M4, a fifth transistor M5A, a fifth control transistor M5B, a sixth transistor M6A, a sixth control transistor M6B, a seventh transistor M7A, a seventh control transistor M7B, an eighth transistor M8A, an eighth control transistor M8B, an eleventh transistor M11, a twelfth transistor M12A, a twelfth control transistor M12B, a thirteenth transistor M13A, a thirteenth control transistor M13B, a fifteenth transistor M15, and a first capacitor C1; the gate of the first transistor M1 is connected to the first transistor M1. The first electrode of the first transistor M1 is coupled to the first output control signal terminal Out_C(n-1), the second electrode of the first transistor M1 is coupled to the first electrode of the second transistor M2; the gate of the second transistor M2 is coupled to the third output control signal terminal Out_C(n+1), the second electrode of the second transistor M2 is coupled to the first level signal terminal LVGL; the gate of the third transistor M3 is coupled to the first electrode of the first capacitor C1, the first electrode of the third transistor M3 is coupled to the first clock signal terminal CLK, the second electrode of the third transistor M3 is coupled to the first cascade output terminal Gout(n); the second electrode of the first capacitor C1 is coupled to the first cascade output terminal Gout(n); the output transistor The gate of the body transistor M4 is coupled to the second cascade output terminal Gout(n+1), the first electrode of the output transistor M4 is coupled to the second electrode of the third transistor M3, and the second electrode of the output transistor M4 is coupled to the second level signal terminal VGL; the gate of the fifth transistor M5A is coupled to the first electrode of the fifth transistor M5A, the first electrode of the fifth transistor M5A is coupled to the second clock signal terminal CLKB, and the second electrode of the fifth transistor M5A is coupled to the first node PD1; the gate of the fifth control transistor M5B is coupled to the first electrode of the fifth control transistor M5B, the first electrode of the fifth control transistor M5B is coupled to the first clock signal terminal CLK, and the second electrode of the fifth control transistor M5B is coupled to the second node PD2; A gate of the sixth transistor M6A is coupled to the third node PU, a first electrode of the sixth transistor M6A is coupled to the first node PD1, and a second electrode of the sixth transistor M6A is coupled to the first level signal terminal LVGL; a gate of the sixth control transistor M6B is coupled to the first electrode of the first capacitor C1, a first electrode of the sixth control transistor M6B is coupled to the second node PD2, and a second electrode of the sixth control transistor M6B is coupled to the first level signal terminal LVGL; a gate of the seventh transistor M7A is coupled to the first output control signal terminal Out_C(n-1), a first electrode of the seventh transistor M7A is coupled to the first node PD1, and a second electrode of the seventh transistor M7A is coupled to the first level signal terminal LVGL;The gate of the seventh control transistor M7B is coupled to the first output control signal terminal Out_C(n-1), the first electrode of the seventh control transistor M7B is coupled to the second node PD2, and the second electrode of the seventh control transistor M7B is coupled to the first level signal terminal LVGL; the gate of the eighth transistor M8A is coupled to the first node PD1, the first electrode of the eighth transistor M8A is coupled to the second electrode of the first transistor M1, and the second electrode of the eighth transistor M8A is coupled to the first level signal terminal LVGL; the gate of the eighth control transistor M8B is coupled to the second node PD2, and the eighth control A first electrode of the eighth control transistor M8B is coupled to the second electrode of the first transistor M1, and a second electrode of the eighth control transistor M8B is coupled to the first level signal terminal LVGL; a gate of the eleventh transistor M11 is coupled to the first electrode of the first capacitor C1, a first electrode of the eleventh transistor M11 is coupled to the first clock signal terminal CLK, and a second electrode of the eleventh transistor M11 is coupled to the second output control signal terminal Out_C(n); a gate of the twelfth transistor M12A is coupled to the first node PD1, and a first electrode of the twelfth transistor M12A is coupled to the second output control signal terminal Out _C(n), the second electrode of the twelfth transistor M12A is coupled to the first level signal terminal LVGL; the gate of the twelfth control transistor M12B is coupled to the second node PD2, the first electrode of the twelfth control transistor M12B is coupled to the second output control signal terminal Out_C(n), and the second electrode of the twelfth control transistor M12B is coupled to the first level signal terminal LVGL; the gate of the thirteenth transistor M13A is coupled to the first node PD1, the first electrode of the thirteenth transistor M13A is coupled to the first cascade output terminal Gout(n), and the thirteenth transistor The second electrode of M13A is coupled to the second level signal terminal VGL; the gate of the thirteenth control transistor M13B is coupled to the second node PD2, the first electrode of the thirteenth control transistor M13B is coupled to the first cascade output terminal Gout(n), and the second electrode of the thirteenth control transistor M13B is coupled to the second level signal terminal VGL; the gate of the fifteenth transistor M15 is coupled to the reset signal terminal T_RST, the first electrode of the fifteenth transistor M15 is coupled to the second electrode of the first transistor M1, and the second electrode of the fifteenth transistor M15 is coupled to the first level signal terminal LVGL.

[0122] For example, in a shift register, transistors with a small channel width-to-length ratio (W / L) are prone to the undesirable phenomenon of conductorization. Conductorization refers to the transistor losing its ability to control its on or off state, becoming a conductor and thus unable to operate. For example, output transistor M4 has a small channel width-to-length ratio (W / L), making it more susceptible to conductorization, which can affect the normal operation of the shift register. W represents the transistor's channel width, and L represents the transistor's channel length.

[0123] In some embodiments of the present disclosure, as shown in FIG3 and FIG4 , the display panel 100 includes a shift register 200 , and the shift register 200 includes an output transistor M4 ;

[0124] The semiconductor layer 40 includes: an active layer 41 of the output transistor M4;

[0125] The source-drain layer 60 includes: a first electrode SD1 and a second electrode SD2 of the output transistor M4;

[0126] The first contact hole 510 includes a first sub-contact hole 511 and a second sub-contact hole 512 ; the first electrode SD1 is connected to the active layer 41 through the first sub-contact hole 511 , and the second electrode SD2 is connected to the active layer 41 through the second sub-contact hole 512 .

[0127] Exemplarily, as shown in FIG1 , the gate conductive layer 20 includes a gate of the output transistor M4 .

[0128] 1 and 4 , the first electrode SD1 is the source of the output transistor M4 , and the second electrode SD2 is the drain of the output transistor M4 , or the first electrode SD1 is the drain of the output transistor M4 , and the second electrode SD2 is the source of the output transistor M4 , which is not limited herein.

[0129] Illustratively, the embodiment of the present disclosure can form the first electrode and the second electrode by directly etching the source and drain layers for patterning.

[0130] In some embodiments of the present disclosure, as shown in FIG4 , the etch stop layer 50 further includes a second contact hole 520 . The orthographic projection of the second contact hole 520 on the base substrate 10 is located between the orthographic projections of the first electrode SD1 and the second electrode SD2 on the base substrate 10 . The orthographic projection of the second contact hole 520 on the base substrate overlaps with the orthographic projection of the active layer 41 on the base substrate.

[0131] The source-drain layer 60 also includes: a first virtual electrode FSD1, the orthographic projection of the first virtual electrode FSD1 on the base substrate 10 is located between the orthographic projection of the first electrode SD1 and the second electrode SD2 on the base substrate 10, and the orthographic projection of the first virtual electrode FSD1 on the base substrate 10 covers the orthographic projection of the second contact hole 520 on the base substrate 10.

[0132] 1 and 4 , the orthographic projection of the first electrode SD1 on the base substrate 10 covers the orthographic projection of the first sub-contact hole 511 on the base substrate 10 ; the orthographic projection of the second electrode SD2 on the base substrate 10 covers the orthographic projection of the second sub-contact hole 512 on the base substrate 10 .

[0133] Exemplarily, as shown in FIG. 4 , the shape of the orthographic projection of the first dummy electrode FSD1 on the base substrate 10 is the same as the shapes of the orthographic projections of the first electrode SD1 and the second electrode SD2 on the base substrate 10 .

[0134] In some embodiments of the present disclosure, as shown in FIG4 , the active layer 41 includes a plurality of sub-active layers 410 , which are spaced apart from each other along a first direction F1 , and the first electrode SD1 , the first dummy electrode FSD1 , and the second electrode SD2 are spaced apart from each other along a second direction F2 ;

[0135] Each of the plurality of sub-active layers 410 corresponds to the first sub-contact hole 511 , the second sub-contact hole 512 , and the second contact hole 520 .

[0136] In some embodiments of the present disclosure, as shown in FIG1 and FIG4 , the first sub-contact hole 511 , the second sub-contact hole 512 , and the second contact hole 520 are spaced apart from each other along the second direction F2 ;

[0137] The edge of the first sub-contact hole 511 and the edge of the second contact hole 520 have a first length L1 in the second direction F2;

[0138] The edge of the second sub-contact hole 512 and the edge of the second contact hole 520 have a second length L2 in the second direction F2;

[0139] The ratio between the first length L1 and the second length L2 is 0.8-1.

[0140] Exemplarily, the ratio between the first length L1 and the second length L2 is 0.8, 0.85, 0.9, 0.95, 1, etc., which is not limited here.

[0141] In some embodiments of the present disclosure, as shown in Figure 4, the sub-active layer 410 has a first width W1 in the first direction F1, the first sub-contact hole 511 has a second width W2 in the first direction F1, the second sub-contact hole 512 has a third width W3 in the first direction F1, and the second contact hole 520 has a fourth width W4 in the first direction F1, and at least one of the second width W2, the third width W3 and the fourth width W4 is greater than the first width W1.

[0142] Exemplarily, the second width W2 is greater than the first width W1 , the third width W3 is greater than the first width W1 , the fourth width W4 is greater than the first width W1 , and so on, which is not limited here.

[0143] In some embodiments of the present disclosure, as shown in FIG. 4 , two or more of the second width W2 , the third width W3 , and the fourth width W4 are the same.

[0144] Exemplarily, the second width W2, the third width W3 and the fourth width W4 are all the same; or the second width W2 and the third width W3 are the same; or the third width W3 and the fourth width W4 are the same; or the second width W2 and the fourth width W4 are the same, which is not limited here.

[0145] The disclosed embodiment adds a first dummy electrode between the first and second electrodes of the output transistor, ensures that the first, second, and first dummy electrodes have the same dimensions, and controls the ratio of the first length to the second length. This ensures that processes such as etching the source / drain layer and the etch stop layer do not adversely affect the characteristics of the output transistor, reduces the possibility of the output transistor becoming conductive, and reduces the impact on the on-state current of the output transistor.

[0146] In some embodiments of the present disclosure, as shown in FIG5 and FIG6 , the base substrate includes a display area AA and a non-display area BB;

[0147] The display area AA includes sub-pixels spx arranged in an array;

[0148] The non-display area BB includes a first area position B1; the first area position B1 includes a plurality of cascaded shift registers 200, a plurality of transfer holes Z0, a plurality of common voltage signal lines 11, a first dummy filling area FB1, and a second dummy filling area FB2;

[0149] The orthographic projections of the shift register 200 and the sub-pixel spx on the base substrate 10 are located on different sides of the orthographic projection of the common voltage signal line 11 on the base substrate 10 ;

[0150] The orthographic projection of the transfer hole Z0 on the base substrate 10 is located between the shift register 200 and the orthographic projection of the common voltage signal line 11 on the base substrate 10 ;

[0151] The orthographic projection of the first dummy filling area FB1 on the base substrate 10 is located between the sub-pixel spx and the orthographic projection of the common voltage signal line 11 on the base substrate 10 ; the first dummy filling area FB1 includes a plurality of second dummy electrodes FSD2 spaced apart from each other;

[0152] The orthographic projection of the second dummy filling area FB2 on the base substrate is located between the transfer hole Z0 and the orthographic projection of the common voltage signal line 11 on the base substrate 10; the second dummy filling area FB2 includes a plurality of second dummy electrodes FSD2 spaced apart from each other;

[0153] The first region position B1 is located at a corner of the base substrate 10 .

[0154] Exemplarily, via Z0 can electrically connect gate lines, reset signal lines, and power voltage signal lines, preventing static electricity buildup and subsequent electrostatic breakdown caused by longer signal lines crossing over other signal lines, which can affect display quality. Exemplarily, the gate lines and reset signal lines are located in the gate conductive layer 20; the power voltage signal lines are located in the source and drain layer 60.

[0155] For example, as shown in FIG6 , the non-display area BB may further include a ground signal line 12, a common signal line 13, and a driving signal line 14; wherein, on one side of the ground signal line 12, there are a plurality of second virtual electrodes FSD2 spaced apart from each other; and the orthographic projection of some driving signal lines 14 on the base substrate 10 overlaps with the orthographic projection of the second virtual electrode FSD2 on the base substrate 10.

[0156] In some embodiments of the present disclosure, as shown in FIG5 , FIG7 and FIG8 , the non-display area BB further includes: a second area position B2; the second area position B2 includes a plurality of cascaded shift registers 200, a plurality of transfer electrodes ZD, a plurality of common voltage signal lines 11, a plurality of data fan-out lines 15, a third dummy filling area FB3, a fourth dummy filling area FB4 and a fifth dummy filling area FB5;

[0157] The shift register 200 and the orthographic projection of the sub-pixel on the base substrate 10 are located on different sides of the orthographic projection of the common voltage signal line 11 on the base substrate 10 ;

[0158] The orthographic projection of the transfer electrode ZD on the base substrate 10 is located between the shift register 200 and the orthographic projection of the common voltage signal line 11 on the base substrate 10 ;

[0159] The orthographic projection of the data fan-out line 15 on the base substrate 10 is located between the common voltage signal line 11 and the orthographic projection of the sub-pixel spx on the base substrate 10;

[0160] The orthographic projection of the third dummy filling area FB3 on the base substrate 10 is located between the sub-pixel spx and the orthographic projection of the data fan-out line 15 on the base substrate 10; the third dummy filling area FB3 includes a plurality of second dummy electrodes FSD2 spaced apart from each other;

[0161] The orthographic projection of the fourth dummy filling area FB4 on the base substrate 10 is located between the orthographic projections of the common voltage signal line 11 and the data fan-out line 15 on the base substrate; the fourth dummy filling area FB4 includes a plurality of second dummy electrodes FSD2 spaced apart from each other;

[0162] The orthographic projection of the fifth dummy filling area FB5 on the base substrate 10 is located between the orthographic projection of the common voltage signal line 11 and the transfer electrode ZD on the base substrate 10; the fifth dummy filling area FB5 includes a plurality of second dummy electrodes FSD2 spaced apart from each other;

[0163] The second region position B2 is located at a corner of the base substrate 10 .

[0164] In some embodiments of the present disclosure, as shown in FIG5 , FIG9 , and FIG10 , the non-display area BB further includes a third area position B3 ; the third area position B3 includes a grid-shaped hollow area B31 formed by a plurality of common signal lines 16 intersecting each other, a transfer area B32 , a dummy transistor area B33 , a sixth dummy filling area FB6 , and a seventh dummy filling area FB7 ;

[0165] The orthographic projection of the transfer area B32 on the base substrate 10 overlaps with the orthographic projection of a portion of the common signal line 16 on the base substrate 10 ;

[0166] The orthographic projection of the dummy transistor region B33 on the base substrate 10 is located between the transfer region B33 and the orthographic projection of the sub-pixel spx on the base substrate 10;

[0167] The orthographic projection of the sixth dummy filling area FB6 on the base substrate 10 overlaps with the orthographic projection of the grid-shaped hollow area B31 on the base substrate 10 ; the sixth dummy filling area FB6 includes a plurality of second dummy electrodes FSD2 spaced apart from each other;

[0168] The orthographic projection of the seventh dummy filling region FB7 on the base substrate 10 is located between the orthographic projections of the dummy transistor region B33 and the transfer region B33 on the base substrate 10 ; the seventh dummy filling region FB7 includes a plurality of second dummy electrodes FSD2 spaced apart from each other.

[0169] Illustratively, the common signal line 16 may be electrically connected to the common electrode layer through the transfer area B32; wherein the common electrode layer is located on a side of the second insulating layer facing away from the base substrate.

[0170] In some embodiments of the present disclosure, as shown in FIG5 , FIG11 , and FIG12 , the non-display area further includes a fourth area position B4 ; the fourth area position B4 includes a plurality of input terminals IN, a plurality of first conduction signal lines 17 , a plurality of second conduction signal lines 18 , a plurality of test signal lines 19 , and a plurality of second virtual electrodes FSD2 spaced apart from each other;

[0171] A plurality of test signal lines 19 are provided corresponding to a plurality of input terminals IN one by one; a first conductive signal line 17 is located on both sides of the input terminal IN; a second conductive signal line 18 is located on one side of the input terminal IN;

[0172] The orthographic projection of the second virtual electrode FSD on the base substrate 10 does not overlap with the orthographic projections of the first conductive signal line 17 , the input terminal IN, and the second conductive signal line 18 on the base substrate;

[0173] The orthographic projection of the second virtual electrode FSD on the base substrate 10 overlaps and / or does not overlap with the orthographic projections of the plurality of test signal lines 19 on the base substrate.

[0174] Exemplarily, as shown in FIG11 , the orthographic projection of the shift register (not shown in the figure) located in the non-display area is located on both sides of the orthographic projection of the input terminal on the substrate; the input terminal includes a plurality of output pins; the output pins of the input terminal are electrically connected to the shift register in the non-display area through a first conductive signal line, thereby providing the required signal to the shift register. The second conductive signal line is electrically connected to the output pin of the input terminal, thereby providing the required signal to the shift register. The test signal line is electrically connected to the input terminal for subsequent testing of the display panel. Exemplarily, the input terminal can be an integrated circuit chip (IC).

[0175] In some embodiments of the present disclosure, as shown in Figure 13, the spacing between the second virtual electrodes FSD2 adjacent to each other along the first direction F1 is a first spacing H1, and the spacing between the second virtual electrodes FSD2 adjacent to each other along the second direction F2 is a second spacing H2; wherein, the values ​​of the length FL2 of the second virtual electrode, the width FW2 of the second virtual electrode, the first spacing H1 and the second spacing H2 are maintained between 2 microns and 10 microns.

[0176] In some embodiments of the present disclosure, as shown in Figure 14, the etching stop layer 50 has a plurality of first through holes K1, at least one second virtual electrode FSD2 is arranged corresponding to at least one first through hole K1, and the orthographic projection of the second virtual electrode FSD2 on the base substrate 10 covers the orthographic projection of the corresponding first through hole K1 on the base substrate 10.

[0177] It should be noted that the distance between the second virtual electrode FSD2 and surrounding areas such as the shift register and the display area is maintained at 3.5-5 microns.

[0178] For example, uneven distribution of source / drain layers and etch-stop layers in a display panel can easily lead to transistors in the display panel becoming conductorized. The present disclosure, by providing multiple second dummy electrodes FSD2, can prevent uneven distribution of transistors and non-graphic areas in the display panel, thereby reducing the likelihood of transistor conductorization and improving display quality. It can also avoid display defects caused by insufficient frame sealant support due to missing film layers.

[0179] For example, the length FL2 of the second dummy electrode, the width FW2 of the second dummy electrode, the first spacing H1, and the second spacing H2 may all be the same, partially the same, or completely different, and are not limited here. For example, the length FL2 of the second dummy electrode, the width FW2 of the second dummy electrode, the first spacing H1, and the second spacing H2 are all 4.5 microns. Alternatively, the length FL2 of the second dummy electrode, the width FW2 of the second dummy electrode are all 5 microns, and the first spacing H1 and the second spacing H2 are all 3 microns, and the like, and are not limited here.

[0180] In some embodiments of the present disclosure, as shown in Figure 8, the etch stop layer 50 has a plurality of first through holes K1, at least one second virtual electrode FSD2 is arranged corresponding to at least one first through hole K1, and the orthographic projection of the second virtual electrode FSD2 on the substrate covers the orthographic projection of the corresponding first through hole K1 on the substrate.

[0181] It should be noted that the etch stop layer has a plurality of first through holes, and the first through holes belong to the hollow area, so the etch stop layer is present at positions other than the first through holes.

[0182] The present embodiment of the present disclosure, by providing a second dummy electrode FSD2, can prevent poor conductivity caused by missing source and drain layers in parts of the display panel or by extremely uneven density of the source and drain layers. However, it cannot significantly optimize or improve the conductivity caused by uneven density of the etch stop layer. The present disclosure, by providing at least one second dummy electrode FSD2 corresponding to at least one first through hole K1, can avoid conductivity problems caused by uneven density of the etch stop layer.

[0183] For example, the length and width of the first through hole K1 can be 2-5 microns, such as 2 microns, 2.5 microns, 3 microns, 5 microns, etc., which are not limited here. For example, the length and width of the first through hole K1 are 0-2 microns smaller than the length and width of the second dummy electrode FSD2.

[0184] In some embodiments of the present disclosure, as shown in Figures 15, 17, and 19, the etch stop layer 50 further has at least one transfer virtual hole FK1; wherein, the orthographic projection of the transfer virtual hole FK1 on the base substrate 10 does not overlap with the orthographic projection of the shift register 200 on the base substrate 10; the shift register 200 is located in the first shift register area G1, and the transfer virtual hole FK1 is located in the first shift register area G1; wherein, the first shift register area G1 is located at a corner of the base substrate 10.

[0185] In some embodiments of the present disclosure, as shown in Figures 1, 15, 17, and 19, the transfer virtual hole FK1 also penetrates the gate insulation layer 30; the first insulation layer 70 located on the side of the source and drain layer 60 away from the base substrate 10, the transfer virtual hole FK1 also penetrates the first insulation layer 70; the second insulation layer 80 located on the side of the first insulation layer 70 away from the base substrate 10, the transfer virtual hole FK1 also penetrates the second insulation layer 80.

[0186] For example, as shown in Figures 15, 17, and 19, the shift register includes an output transistor M4, a third transistor M3, and an eleventh transistor M11. The orthographic projections of the output transistor M4, the third transistor M3, and the eleventh transistor M11 on the substrate 10 are located between the transfer virtual hole FK1 and the orthographic projection of the common voltage signal line 11 on the substrate 10. The output transistor M4, the third transistor M3, and the eleventh transistor M11 are transistors that are relatively close to the common voltage signal line 11 among the multiple transistors in the shift register. The orthographic projection of the transfer virtual hole FK1 on the substrate 10 is located on one side of the orthographic projection of the output transistor M4 on the substrate 10.

[0187] For example, as shown in Figures 15, 17 and 19, the shift register also has a plurality of second virtual electrodes FSD2 spaced apart from each other, wherein the orthographic projection of the second virtual electrode FSD2 on the base substrate 10 does not overlap with the orthographic projection of the transistor in the shift register on the base substrate 10; the orthographic projection of the second virtual electrode FSD2 on the base substrate 10 does not overlap with the orthographic projection of the transfer virtual hole FK1 on the base substrate 10.

[0188] For example, as shown in Figures 15, 17, and 19, in the corners of the display panel, due to routing requirements, the output transistor M4, the third transistor M3, and the eleventh transistor M11 of at least one shift register need to be a certain distance (e.g., 30um to 500um) from the other transistors in the shift register. This may leave blank areas, resulting in uneven film layers. The present disclosure can improve film layer unevenness and avoid conductorization by providing transfer dummy holes in the remaining blank areas of the shift register.

[0189] For example, as shown in Figures 15, 17, and 19, the transfer virtual hole includes film layers such as the gate conductive layer and the source and drain layer, as well as film layers such as the etching stop layer, the first insulating layer, and the second insulating layer, which effectively improves the film layers around the shift register, making the surrounding film layers more uniform, thereby avoiding poor conductivity of the transistors in the shift register.

[0190] For example, FIG16 is a diagram of through holes in the etch stop layer in FIG15 ; FIG18 is a diagram of through holes in the etch stop layer in FIG17 ; and FIG20 is a diagram of through holes in the etch stop layer in FIG19 .

[0191] In some embodiments of the present disclosure, as shown in Figures 21 to 26, the gate conductive layer 20 includes multiple gate lines GA, and the display panel further includes at least one dummy transistor M0; one end of at least one gate line GA among the multiple gate lines GA is connected to the at least one dummy transistor M0.

[0192] In some embodiments of the present disclosure, as shown in FIG. 21 to FIG. 26 , the same end of each gate line GA of the plurality of gate lines GA is connected to at least one dummy transistor M0 .

[0193] In some embodiments of the present disclosure, as shown in Figures 21 to 24, the display panel includes a display area AA and a non-display area BB, the display area AA includes sub-pixels spx arranged in an array; the non-display area BB includes a plurality of shift registers 200, and the display area AA includes a plurality of gate lines GA; the plurality of shift registers 200 and the plurality of gate lines GA are correspondingly connected; at least one virtual transistor M0 is provided with an orthographic projection on the substrate substrate 10 between the orthographic projection of the shift register 200 on the substrate substrate 10 and the orthographic projection of the correspondingly connected gate line GA on the substrate substrate 10.

[0194] In some embodiments of the present disclosure, as shown in Figures 21 and 22, multiple shift registers are located in the second shift register area G2; the shift registers in the second shift register area G2 are arranged in sequence along the second direction F2; the orthographic projection of the dummy transistor M0 on the substrate 10 is located between the orthographic projection of the sub-pixel spx on the substrate 10 and the orthographic projection of the second shift register area G2 on the substrate 10; wherein, the dummy transistor M0 is away from the side of the sub-pixel spx along the first direction F1; the orthographic projections of adjacent dummy transistors M0 on the substrate 10 are relatively arranged along the second direction F2.

[0195] Exemplarily, as shown in FIG. 21 and FIG. 22 , the second shift register region is located at a vertical edge of the base substrate.

[0196] Exemplarily, the dummy transistor does not have a corresponding pixel electrode, etc.

[0197] In some embodiments of the present disclosure, as shown in Figures 23 and 24, multiple shift registers are located in the third shift register area G3; multiple data fan-out lines 15 are also provided between the third shift register area G3 and the sub-pixel spx; the orthographic projection of the dummy transistor M0 connected to the gate line GA near one end of the shift register 200 on the substrate 10 is located between the data fan-out line 15 and the orthographic projection of the sub-pixel spx on the substrate 10; wherein, the dummy transistor M0 is away from one side of the sub-pixel spx along the first direction F1; and the orthographic projections of adjacent dummy transistors M0 on the substrate 10 are relatively arranged along the second direction F2.

[0198] Exemplarily, as shown in FIG. 23 and FIG. 24 , the third shift register region is located at a corner of the substrate.

[0199] Exemplarily, as shown in Figure 25, multiple shift registers are located in the first shift register area G1; there are multiple common voltage signal lines 11 between the first shift register area G1 and the sub-pixel spx; the virtual transistor M0 connected to the gate line GA near one end of the shift register 200 has its positive projection on the substrate 10 located between the data fan-out line 15 and the positive projection of the sub-pixel spx on the substrate 10; wherein, the virtual transistor M0 is away from the side of the sub-pixel spx along the first direction F1; the positive projections of adjacent virtual transistors M0 on the substrate 10 are relatively arranged along the second direction F2.

[0200] In some embodiments of the present disclosure, as shown in FIG27 , the semiconductor layer 40 further includes: a first active layer 401 and a second active layer 402 of the dummy transistor M0;

[0201] The source-drain layer 60 further includes: a first electrode 61 and a second electrode 62 of the dummy transistor M0;

[0202] The etch stop layer 50 further includes a third contact hole 530 and a fourth contact hole 540;

[0203] The first electrode 61 of the dummy transistor M0 is connected to the first active layer 401 through the third contact hole 530 , and the second electrode 62 of the dummy transistor M0 is connected to the second active layer 402 through the fourth contact hole 540 .

[0204] In some embodiments of the present disclosure, as shown in FIG. 27 , the first active layer 401 and the second active layer 402 are spaced apart from each other along the second direction F2 , and the first electrode 61 and the second electrode 62 of the dummy transistor M0 are spaced apart from each other along the second direction F2 .

[0205] For example, since transistors at the edge of the display area are prone to conductorization or electrostatic discharge, the prior art generally adopts the setting of virtual sub-pixels to prevent the conductorization or electrostatic discharge of transistors at the edge of the display area from causing problems. However, in pursuit of a narrow frame, there is no room left for setting virtual sub-pixels. The present disclosure sets virtual transistors that are the same size as the transistors in the sub-pixels or have a small size difference at both ends of the gate line (the specific position can be set according to the space and is not necessarily adjacent to the sub-pixels in the display area). This setting can meet the narrow frame requirements and avoid conductorization and electrostatic discharge.

[0206] Exemplarily, as shown in FIG27 , the distance between the first active layer and the second active layer is h (generally h is not less than 2 um). If electrostatic discharge occurs, the position of the dummy transistor can be broken down first to avoid breaking down the transistor in the display area.

[0207] Based on the same disclosed concept, the present disclosure also provides a display device, including the display panel provided in the present disclosure. The principles of this display device are similar to those of the aforementioned display panel, so the implementation of this display device can refer to the implementation of the aforementioned display panel, and the repeated parts will not be repeated here.

[0208] In specific implementations, in the embodiments of the present disclosure, the display device can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigation system, or the like. Other essential components of the display device are well understood by those skilled in the art and are not detailed here, nor should they be construed as limitations of the present disclosure.

[0209] Although the preferred embodiments of the present disclosure have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concepts. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present disclosure.

[0210] Obviously, those skilled in the art may make various changes and modifications to the embodiments of the present disclosure without departing from the spirit and scope of the embodiments of the present disclosure. Thus, if such changes and modifications of the embodiments of the present disclosure fall within the scope of the claims of the present disclosure and their equivalents, the present disclosure is intended to include such changes and modifications.

Claims

1. A display panel, comprising: substrate substrate; A gate conductive layer, located on the substrate; A gate insulating layer, located on a side of the gate conductive layer away from the substrate; A semiconductor layer, located on a side of the gate insulating layer away from the substrate; An etch stop layer is located on a side of the semiconductor layer away from the substrate; the etch stop layer comprises a first contact hole; The source-drain layer is located on a side of the etch stop layer away from the substrate; the source-drain layer is connected to the semiconductor layer through the first contact hole.

2. The display panel according to claim 1, wherein: The display panel includes a shift register, and the shift register includes an output transistor; The semiconductor layer includes: an active layer of the output transistor; The source-drain layer includes: a first electrode and a second electrode of the output transistor; The first contact hole includes a first sub-contact hole and a second sub-contact hole; the first electrode is connected to the active layer through the first sub-contact hole, and the second electrode is connected to the active layer through the second sub-contact hole; The etching stop layer further includes a second contact hole, the orthographic projection of the second contact hole on the base substrate is located between the orthographic projections of the first electrode and the second electrode on the base substrate, and the orthographic projection of the second contact hole on the base substrate has an overlapping area with the orthographic projection of the active layer on the base substrate; The source-drain layer also includes: a first virtual electrode, the orthographic projection of the first virtual electrode on the base substrate is located between the orthographic projections of the first electrode and the second electrode on the base substrate, and the orthographic projection of the first virtual electrode on the base substrate covers the orthographic projection of the second contact hole on the base substrate.

3. The display panel according to claim 2, wherein: The active layer includes a plurality of sub-active layers, the plurality of sub-active layers are arranged at intervals from each other along a first direction, and the first electrode, the first dummy electrode and the second electrode are arranged at intervals from each other along a second direction; Each of the plurality of sub-active layers corresponds to the first sub-contact hole, the second sub-contact hole, and the second contact hole, respectively.

4. The display panel according to claim 3, wherein: The first sub-contact hole, the second contact hole and the second sub-contact hole are arranged in a spaced relationship with each other along a second direction; An edge of the first sub-contact hole and an edge of the second contact hole have a first length in the second direction; An edge of the second sub-contact hole and an edge of the second contact hole have a second length in the second direction; The ratio between the first length and the second length is 0.8-1.

5. The display panel according to claim 4, wherein: The active layer has a first width in a first direction, The first sub-contact hole has a second width in the first direction, the second sub-contact hole has a third width in the first direction, and the second contact hole has a fourth width in the first direction. At least one of the second width, the third width, and the fourth width is greater than the first width.

6. The display panel according to claim 5, wherein: Two or more of the second width, the third width, and the fourth width are the same.

7. The display panel according to any one of claims 1 to 6, wherein: The base substrate includes a display area and a non-display area; The display area includes sub-pixels arranged in an array; The non-display area includes a first area position; the first area position includes a plurality of cascaded shift registers, a plurality of transfer holes, a plurality of common voltage signal lines, a first dummy filling area, and a second dummy filling area; The shift register and the orthographic projection of the sub-pixel on the substrate are located on different sides of the orthographic projection of the common voltage signal line on the substrate; The orthographic projection of the transfer hole on the base substrate is located between the orthographic projection of the shift register on the base substrate and the orthographic projection of the common voltage signal line on the base substrate; The orthographic projection of the first virtual filling area on the base substrate is located between the sub-pixel and the orthographic projection of the common voltage signal line on the base substrate; the first virtual filling area includes a plurality of second virtual electrodes spaced apart from each other; The orthographic projection of the second virtual filling area on the base substrate is located between the transfer hole and the orthographic projection of the common voltage signal line on the base substrate; the second virtual filling area includes a plurality of second virtual electrodes spaced apart from each other; Wherein, the first region is located at a corner of the substrate.

8. The display panel according to claim 7, wherein: The non-display area further includes: a second area position; the second area position includes a plurality of cascaded shift registers, a plurality of transfer electrodes, a plurality of common voltage signal lines, a plurality of data fan-out lines, a third dummy filling area, a fourth dummy filling area and a fifth dummy filling area; The shift register and the orthographic projection of the sub-pixel on the base substrate are located on different sides of the orthographic projection of the common voltage signal line on the base substrate; The orthographic projection of the switching electrode on the base substrate is located between the orthographic projection of the shift register and the common voltage signal line on the base substrate; The orthographic projection of the data fan-out line on the substrate is located between the common voltage signal line and the orthographic projection of the sub-pixel on the substrate; The orthographic projection of the third virtual filling area on the base substrate is located between the sub-pixel and the orthographic projection of the data fan-out line on the base substrate; the third virtual filling area includes a plurality of second virtual electrodes spaced apart from each other; The orthographic projection of the fourth virtual filling area on the base substrate is located between the orthographic projections of the common voltage signal line and the data fan-out line on the base substrate; the fourth virtual filling area includes a plurality of second virtual electrodes spaced apart from each other; The orthographic projection of the fifth virtual filling area on the substrate is located between the orthographic projection of the common voltage signal line and the switching electrode on the substrate; the fifth virtual filling area includes A plurality of second virtual electrodes spaced apart from each other; Wherein, the second region is located at a corner of the substrate.

9. The display panel according to claim 7, wherein: The non-display area also includes a third area position; the third area position includes a grid-shaped hollow area composed of a plurality of common signal lines intersecting each other, a transfer area, a dummy transistor area, a sixth dummy filling area and a seventh dummy filling area; The orthographic projection of the transfer area on the base substrate overlaps with the orthographic projection of part of the common signal line on the base substrate; The orthographic projection of the dummy transistor region on the substrate is located between the transfer region and the orthographic projection of the sub-pixel on the substrate; The orthographic projection of the sixth virtual filling area on the base substrate overlaps with the orthographic projection of the grid-shaped hollow area on the base substrate; the sixth virtual filling area includes a plurality of second virtual electrodes spaced apart from each other; The orthographic projection of the seventh virtual filling area on the base substrate is located between the orthographic projections of the virtual transistor area and the transfer area on the base substrate; the seventh virtual filling area includes a plurality of second virtual electrodes spaced apart from each other.

10. The display panel according to claim 7, wherein: The non-display area further includes a fourth region position; the fourth region position includes a plurality of input terminals, a plurality of first conduction signal lines, a plurality of second conduction signal lines, a plurality of test signal lines, and a plurality of second virtual electrodes spaced apart from each other; The plurality of test signal lines are arranged in one-to-one correspondence with the plurality of input terminals; the first conduction signal line is located at both sides of the input terminal; The second conduction signal line is located at one side of the input terminal; The orthographic projection of the second virtual electrode on the base substrate does not overlap with the orthographic projection of the first conductive signal line, the input terminal, and the second conductive signal line on the base substrate; The orthographic projection of the second virtual electrode on the base substrate overlaps and / or does not overlap with the orthographic projections of the plurality of test signal lines on the base substrate.

11. The display panel according to any one of claims 7 to 10, wherein: The spacing between the second virtual electrodes adjacent to each other in the first direction is a first spacing, and the spacing between the second virtual electrodes adjacent to each other in the second direction is a second spacing; The values ​​of the length of the second virtual electrode, the width of the second virtual electrode, the first spacing and the second spacing are maintained between 2 micrometers and 10 micrometers.

12. The display panel according to claim 11, wherein: The etching stop layer has a plurality of first through holes, at least one of the second virtual electrodes is arranged corresponding to at least one of the first through holes, and the orthographic projection of the second virtual electrode on the substrate covers the orthographic projection of the corresponding first through hole on the substrate.

13. The display panel according to any one of claims 1 to 12, wherein: The etching stop layer also has at least one transfer virtual hole; The orthographic projection of the transfer virtual hole on the substrate substrate does not overlap with the orthographic projection of the shift register on the substrate substrate; the shift register is located in a first shift register area, and the transfer virtual hole is located in the first shift register area; Wherein, the first shift register area is located at a corner of the substrate.

14. The display panel according to claim 13, wherein: The transfer virtual hole also penetrates the gate insulating layer; A first insulating layer located at a side of the source and drain electrodes away from the substrate, wherein the transfer virtual hole also penetrates the first insulating layer; The second insulating layer is located on a side of the first insulating layer away from the base substrate, and the transfer virtual hole also passes through the second insulating layer.

15. The display panel according to any one of claims 1 to 14, wherein: The gate conductive layer includes the plurality of gate lines, and the display panel further includes at least one dummy transistor; One end of at least one gate line among the plurality of gate lines is connected to at least one of the dummy transistors.

16. The display panel according to claim 15, wherein: The same end of each of the plurality of gate lines is connected to at least one of the dummy transistors.

17. The display panel according to claim 15, wherein: The display panel comprises a display area and a non-display area, the display area comprises sub-pixels arranged in an array; the non-display area comprises a plurality of shift registers, and the display area comprises a plurality of gate lines; the plurality of shift registers and the plurality of gate lines are connected correspondingly; The shift register is provided with at least one orthographic projection of the dummy transistor on the substrate between the orthographic projection of the substrate and the orthographic projection of the correspondingly connected gate line on the substrate.

18. The display panel according to claim 17, wherein: The plurality of shift registers are located in a second shift register area; The shift registers in the second shift register area are arranged in sequence along the second direction; the orthographic projection of the dummy transistor on the base substrate is located between the orthographic projection of the sub-pixel on the base substrate and the orthographic projection of the second shift register area on the base substrate; The dummy transistor is away from one side of the sub-pixel along the first direction; and the adjacent dummy transistors are arranged opposite to each other along the second direction on the orthographic projection of the substrate.

19. The display panel according to claim 17, wherein: The plurality of shift registers are located in a third shift register area; and a plurality of data fan-out lines are provided between the third shift register area and the sub-pixel; The virtual transistor connected to the gate line at one end close to the shift register has its orthographic projection on the substrate located between the data fan-out line and the orthographic projection of the sub-pixel on the substrate; wherein the virtual transistor is away from one side of the sub-pixel along the first direction; and the orthographic projections of the adjacent virtual transistors on the substrate are relatively arranged along the second direction.

20. The display panel according to claim 17, wherein: The semiconductor layer further includes: a first active layer and a second active layer of the dummy transistor; The source-drain layer further includes: a first electrode and a second electrode of the dummy transistor; The etching stop layer further includes a third contact hole and a fourth contact hole; The first electrode of the dummy transistor is connected to the first active layer through the third contact hole, and the second electrode of the dummy transistor is connected to the second active layer through the fourth contact hole.

21. The display panel according to claim 20, wherein: The first active layer and the second active layer are arranged at intervals from each other along the second direction, and the first electrode of the dummy transistor and the second electrode of the dummy transistor are arranged at intervals from each other along the second direction.

22. A display device, wherein: Comprising a display panel as described in any one of claims 1-21.

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