Display substrate, manufacturing method thereof and display device

Abstract

The invention discloses a display substrate, a manufacturing method of the display substrate and a display device. The driving circuit layer is arranged on the substrate; the plurality of switching electrodes are arranged on one side, far away from the substrate, of the driving circuit layer and are electrically connected with the driving circuit layer; the multiple light-emitting chips are arranged on the sides, away from the substrate, of the multiple switching electrodes, each light-emitting chip comprises a first electrode and a light-emitting main body layer which are sequentially arranged in the direction away from the substrate, and each first electrode is bonded with one switching electrode; the first voltage line comprises a first conductive layer and a second conductive layer, the first conductive layer and the switching electrode are arranged on the same layer, and the second conductive layer and the first electrode are arranged on the same layer; and the first conductive layer is bonded with the second conductive layer.

Description

Display substrate, manufacturing method thereof, and display device Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display substrate and a manufacturing method thereof, and a display device. Background Art

[0002] Micro-inorganic light-emitting diodes include MiniLED and MicroLED. MiniLED refers to light-emitting diode (LED) chips with a grain size of approximately 100 to 300 microns. MicroLED refers to LED chips with a grain size of less than 100 microns. MiniLED / MicroLED display devices offer advantages such as low power consumption, high brightness, high resolution, high color saturation, fast response, long life, and high efficiency. Furthermore, multiple Mini-LED / Micro-LED display devices can be seamlessly spliced ​​together to create ultra-large display products, which have broad application prospects in large-scale display areas such as command and monitoring centers, commercial centers, high-end conferences, and cinemas.

[0003] Summary of the Invention

[0004] In a first aspect, the present disclosure provides a display substrate, comprising:

[0005] substrate;

[0006] A driving circuit layer is provided on the base substrate;

[0007] a plurality of transfer electrodes, arranged on a side of the driving circuit layer away from the base substrate and electrically connected to the driving circuit layer;

[0008] A plurality of light-emitting chips are arranged on a side of the plurality of transfer electrodes away from the base substrate, the light-emitting chips comprising first electrodes and a light-emitting main layer sequentially arranged in a direction away from the base substrate, and each of the first electrodes is bonded to one of the transfer electrodes;

[0009] The first voltage line includes a first conductive layer and a second conductive layer, the first conductive layer and the switching electrode are arranged in the same layer, and the second conductive layer and the first electrode are arranged in the same layer; the first conductive layer and the second conductive layer are bonded.

[0010] In some embodiments, the orthographic projections of the first electrode and the switching electrode connected thereto on the base substrate coincide with each other; and the orthographic projections of the first conductive layer and the second conductive layer on the base substrate coincide with each other.

[0011] In some embodiments, the driving circuit layer includes a plurality of thin film transistors, and the switching electrodes are electrically connected to the thin film transistors;

[0012] The first voltage line further includes: a third conductive layer provided on the same layer as the source and the drain of the thin film transistor, and the first conductive layer is electrically connected to the third conductive layer.

[0013] In some embodiments, the switching electrode includes: a reflective layer and a bonding layer sequentially arranged in a direction away from the substrate;

[0014] The first conductive layer includes: a first conductive sublayer and a second conductive sublayer. The first conductive sublayer is disposed in the same layer as the reflective layer, and the second conductive sublayer is disposed in the same layer as the bonding layer.

[0015] In some embodiments, the display substrate further includes a planarization layer located between the driving circuit layer and the plurality of switching electrodes, and the switching electrodes are electrically connected to the driving circuit layer through the first via holes penetrating the planarization layer.

[0016] In some embodiments, the light-emitting chip also includes a second electrode, which is located on the side of the light-emitting main layer away from the base substrate; the first voltage line also includes a fourth conductive layer electrically connected to the second conductive layer, and the fourth conductive layer is arranged in the same layer as the second electrode and is electrically connected.

[0017] In some embodiments, the display substrate further comprises:

[0018] an encapsulation layer, located on a side of the driving circuit layer away from the base substrate; the encapsulation layer has a plurality of first accommodating portions, and the first electrode and the light-emitting main layer of each light-emitting chip are located in one of the first accommodating portions;

[0019] The fourth conductive layer is electrically connected to the second conductive layer through a second via hole penetrating the packaging layer.

[0020] In some embodiments, the light-emitting chip is configured to emit light of a first color; and the display substrate further comprises:

[0021] a light shielding layer, the light shielding layer having a plurality of second accommodating portions, each of the second accommodating portions exposing at least a portion of one of the second electrodes;

[0022] a plurality of light emitting portions, each of the light emitting portions being disposed in one of the second receiving portions and located on a side of the second electrode away from the base substrate; the plurality of light emitting portions comprising: a plurality of first light emitting portions, a plurality of second light emitting portions, and a plurality of third light emitting portions, the first light emitting portions transmitting the first color light emitted by the light emitting chip; the second light emitting portions being configured to convert the first color light into a second color light; and the third light emitting portions being configured to convert the first color light into a third color light;

[0023] A plurality of color resist blocks are provided, each of the color resist blocks is arranged on a side of the light emitting portion away from the base substrate, and the color of the color resist block is the same as the color of the light emitted by the corresponding light emitting portion.

[0024] In some embodiments, the light-emitting chip is a mini-LED light-emitting chip or a Micro-LED light-emitting chip.

[0025] In a second aspect, the present disclosure provides a method for manufacturing a display substrate, comprising:

[0026] forming a driving circuit layer on the base substrate;

[0027] forming a first bonding layer on a side of the driving circuit layer away from the base substrate;

[0028] Providing an epitaxial wafer, the epitaxial wafer comprising a second bonding layer and an epitaxial layer stacked;

[0029] Transferring the epitaxial wafer to a side of the first bonding layer away from the substrate, and bonding the first bonding layer to the second bonding layer;

[0030] Etching the epitaxial layer to form a first pattern; etching the second bonding layer to form a second pattern; etching the first bonding layer to form a third pattern;

[0031] Among them, the first graphic includes a light-emitting main layer of multiple light-emitting chips, the second graphic includes the first electrodes of the multiple light-emitting chips and the second conductive layer of the first voltage line, and the third graphic includes multiple switching electrodes and the first conductive layer of the first voltage line; the switching electrodes are electrically connected to the driving circuit layer.

[0032] In some embodiments, the step of etching the second bonding layer and the step of etching the first bonding layer are performed in the same patterning process.

[0033] In some embodiments, the step of forming a driving circuit layer on the base substrate includes: forming a plurality of thin film transistors on the base substrate, wherein the switching electrodes are electrically connected to the thin film transistors;

[0034] Wherein, while forming the source and drain electrodes of the plurality of thin film transistors, the third conductive layer of the first voltage line is also formed; and the first conductive layer is electrically connected to the third conductive layer.

[0035] In some embodiments, the first bonding layer includes a reflective material layer and a bonding material layer sequentially disposed in a direction away from the substrate;

[0036] The switching electrode includes: a reflective layer and a bonding layer; the first conductive layer includes: a first conductive sublayer and a second conductive sublayer;

[0037] The first conductive sublayer and the reflective layer are formed by etching the reflective material layer, and the second conductive sublayer and the bonding layer are formed by etching the bonding material layer.

[0038] In some embodiments, before the step of forming the first bonding layer, the manufacturing method further includes:

[0039] forming a planarization layer on a side of the driving circuit layer away from the base substrate;

[0040] forming a first via hole on the planarization layer at a position corresponding to the switching electrode;

[0041] Wherein, the switching electrode is electrically connected to the driving circuit layer through the first via hole.

[0042] In some embodiments, the manufacturing method further comprises:

[0043] Simultaneously forming the second electrodes of the plurality of light-emitting chips and the fourth conductive layers of the plurality of first voltage lines;

[0044] The fourth conductive layer is electrically connected to the second conductive layer and the second electrode, and the second electrode is located on a side of the light-emitting main layer away from the base substrate.

[0045] In some embodiments, before the step of simultaneously forming the second electrodes of the plurality of light-emitting chips, the manufacturing method further comprises:

[0046] forming a packaging layer having a plurality of first receiving portions and a plurality of second via holes;

[0047] The first electrode and the light-emitting main layer of each light-emitting chip are located in one of the first receiving portions, and the fourth conductive layer is electrically connected to the second conductive layer through the second via hole.

[0048] In some embodiments, the light-emitting chip is configured to emit light of a first color; and the manufacturing method further comprises:

[0049] forming a light shielding layer having a plurality of second accommodation portions;

[0050] A light emitting portion is formed in each of the second receiving portions, the light emitting portion being located on a side of the second electrode away from the base substrate; the light emitting portions in the plurality of second receiving portions include: a first light emitting portion, a second light emitting portion, and a third light emitting portion, the first light emitting portion transmitting the first color light emitted by the light emitting chip, the second light emitting portion being used to convert the first color light into a second color light; and the third light emitting portion being used to convert the first color light into a third color light;

[0051] A color block is formed on a side of each light emitting portion away from the base substrate, and the color of the color block is the same as the color of the light emitted by the corresponding light emitting portion.

[0052] In a third aspect, the present disclosure provides a display device, which includes the display substrate in the above embodiment. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] The accompanying drawings are used to provide a further understanding of the present disclosure and constitute a part of the specification. Together with the following detailed description, they are used to explain the present disclosure but do not constitute a limitation of the present disclosure. In the accompanying drawings:

[0054] FIG1 is a schematic diagram of a display substrate provided in some embodiments of the present disclosure.

[0055] FIG2 is a schematic diagram of a display substrate provided in some other embodiments of the present disclosure.

[0056] FIG3 is a schematic diagram of a display substrate provided in some other embodiments of the present disclosure.

[0057] 4 to 18 are schematic diagrams of a manufacturing process of a display substrate provided in some embodiments of the present disclosure. DETAILED DESCRIPTION

[0058] The following describes the specific embodiments of the present disclosure in detail with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are only used to illustrate and explain the present disclosure and are not intended to limit the present disclosure.

[0059] To make the purpose, technical solutions, and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0060] Unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present disclosure should have the usual meanings understood by people with ordinary skills in the field to which the present disclosure belongs. The "first", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0061] As used herein, "parallel" and "perpendicular" include the conditions described and conditions similar to the conditions described, and the range of the similar conditions is within an acceptable deviation range, wherein the acceptable deviation range is determined by a person of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the specific quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallelism and approximate parallelism, wherein the acceptable deviation range for approximate parallelism can be, for example, a deviation within 5°; "perpendicular" includes absolute perpendicularity and approximate perpendicularity, wherein the acceptable deviation range for approximate perpendicularity can also be, for example, a deviation within 5°.

[0062] It will be understood that when a layer or element is referred to as being on another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may be present therebetween.

[0063] Exemplary embodiments are described herein with reference to cross-sectional and / or plan views that are idealized exemplary drawings. In the drawings, the thicknesses of layers and regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are contemplated. Therefore, the exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include deviations in shape due to, for example, manufacturing. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0064] In related art, the manufacturing process for display panels using MiniLED or MicroLED light-emitting chips includes: arranging multiple light-emitting chips on the display area of ​​a driver backplane through a mass transfer process and a mass bonding process. The driver backplane includes a base substrate and a drive circuit layer disposed on the base substrate. The drive circuit layer is electrically connected to the first electrode of the light-emitting chip to provide a drive signal to the light-emitting chip. In addition, the driver backplane also includes a first voltage line electrically connected to the second electrode of the light-emitting chip to provide a first voltage signal to the second electrode.

[0065] However, due to the high prices of MiniLED and MicroLED light-emitting chips, the cost of display panels using MiniLED or MicroLED light-emitting chips is relatively high; in addition, the mass transfer process and mass bonding process are relatively difficult.

[0066] Figure 1 is a schematic diagram of a display substrate provided in some embodiments of the present disclosure, Figure 2 is a schematic diagram of a display substrate provided in other embodiments of the present disclosure, and Figure 3 is a schematic diagram of a display substrate provided in other embodiments of the present disclosure. As shown in Figures 1 to 3, the display substrate includes a base substrate SUB and a driving circuit layer, a first voltage line 20, a plurality of switching electrodes 40, and a plurality of light-emitting chips 30 arranged on the base substrate SUB.

[0067] The substrate SUB may be a rigid substrate made of an inorganic material, for example, the substrate SUB may be made of glass materials such as soda-lime glass, quartz glass, and sapphire glass. Alternatively, the substrate SUB may be a flexible substrate made of an organic material, for example, the substrate SUB may be made of polymethyl methacrylate (PMMA), polyvinyl alcohol (PVA), polyimide (PI), polycarbonate (PC), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), or a combination thereof.

[0068] The driving circuit layer is used to provide driving signals for the light emitting chip 30 .

[0069] A plurality of transfer electrodes 40 are disposed on a side of the driving circuit layer away from the base substrate SUB, wherein the transfer electrodes 40 may comprise a first material.

[0070] Multiple light-emitting chips 30 are disposed in the display area of ​​the display substrate. The light-emitting chips 30 include first electrodes 31 and a light-emitting main layer 33, which are sequentially arranged in a direction away from the base substrate SUB. Each first electrode 31 corresponds to a transfer electrode 40. For example, there is a one-to-one correspondence between the first electrodes 31 and the transfer electrodes 40. Each first electrode 31 is electrically connected to the driving circuit layer via the corresponding transfer electrode 40. The first electrodes 31 include the second material.

[0071] The first voltage line 20 includes a first conductive layer 21 and a second conductive layer 22 sequentially arranged in a direction away from the substrate SUB, wherein the first conductive layer 21 is arranged on the same layer as the switching electrode 40 , and the second conductive layer 22 is arranged on the same layer as the first electrode 31 .

[0072] It should be noted that the "same-layer arrangement" in the embodiment of the present disclosure means that the two structures are formed by the same material layer through a composition process, so the two are in the same layer in terms of the stacking relationship; but this does not mean that the distance between the two and the substrate SUB must be the same.

[0073] Each first electrode 31 is bonded to a corresponding switching electrode 40 , and the first conductive layer 21 is bonded to the second conductive layer 22 .

[0074] Optionally, the first electrode 31 and the transition electrode 40, and the first conductive layer 21 and the second conductive layer 22 are bonded using eutectic bonding to improve bonding strength. That is, a eutectic metal layer formed by the reaction of the first material and the second material is formed between the first electrode 31 and the transition electrode 40, and between the first conductive layer 21 and the second conductive layer 22.

[0075] In the embodiment of the present disclosure, the combination of the first material and the second material can be selected from any one of the following: copper (Cu) and tin (Sn); copper (Cu) and indium (In); gold (Au) and indium (In); gold (Au) and tin (Sn); indium tin oxide (ITO) and indium tin oxide (ITO).

[0076] In the embodiment of the present disclosure, the first conductive layer 21 and the transfer electrode 40 are provided in the same layer, the second conductive layer 22 and the first electrode 31 are provided in the same layer, the first electrode 31 is bonded to the transfer electrode 40, and the first conductive layer 21 is bonded to the second conductive layer 22. Therefore, in the process of manufacturing the display substrate, a first bonding layer can be first formed on the base substrate SUB on which the driving circuit layer is formed, and then the epitaxial wafer including the second bonding layer and the epitaxial layer is transferred as a whole to the base substrate SUB, and the first bonding layer is bonded to the second bonding layer, thereby forming a eutectic metal layer therebetween; thereafter, the epitaxial layer is etched to form a pattern including multiple light-emitting main layers 33; the second bonding layer is etched to form a pattern including multiple second conductive layers 22 and multiple first electrodes 31; and the first bonding layer is etched to form a pattern including multiple first conductive layers 21 and multiple transfer electrodes 40. This method eliminates the need to transfer and bond a large number of light-emitting chips 30 through mass transfer and mass bonding processes. Instead, it only requires transferring, bonding, and patterning the entire epitaxial wafer, thus reducing process complexity. Furthermore, compared to a large number of light-emitting chips 30, the price of a single epitaxial wafer is lower, thereby reducing the production cost of the display substrate.

[0077] In some embodiments, as shown in FIG. 1 to FIG. 3 , the orthographic projections of the first electrode 31 and the switching electrode 40 connected thereto on the base substrate SUB coincide with each other; the orthographic projections of the first conductive layer 21 and the second conductive layer 22 on the base substrate SUB coincide with each other.

[0078] When transferring the light-emitting chip to the driver circuit layer using a mass transfer process, the electrodes above the driver circuit layer that connect to the light-emitting chip typically need to be designed larger to ensure accurate alignment. However, in the disclosed embodiment, during the display substrate fabrication process, the second bonding layer and the first bonding layer can be etched using the same patterning process to form the first electrode 31 and the transfer electrode 40, whose orthographic projections overlap, as well as the second conductive layer 22 and the first conductive layer 21, whose orthographic projections overlap. This simplifies the fabrication process while ensuring the connection stability between the first electrode 31 and the transfer electrode 40.

[0079] 1 to 3 , the orthographic projections of the first electrode 31 and the light emitting body layer 33 on the substrate SUB overlap. Of course, the orthographic projections of the first electrode 31 and the light emitting body layer 33 on the substrate SUB may not completely overlap.

[0080] In some embodiments, as shown in Figures 1 to 3, a buffer layer BFL is disposed on a substrate SUB. The buffer layer BFL can prevent or reduce the diffusion of metal atoms and / or impurities from the substrate SUB into the semiconductor layer. For example, the buffer layer BFL can include an inorganic material such as silicon oxide (SiOx), silicon nitride (SiNx), and / or silicon oxynitride (SiON), and can be formed as a multilayer or single layer.

[0081] As shown in Figures 1 to 3, the drive circuit layer is disposed on the side of the buffer layer BFL away from the base substrate SUB. The drive circuit layer may include a pixel drive circuit, with each light-emitting chip 30 corresponding to one pixel drive circuit. Each pixel drive circuit includes multiple thin-film transistors 11. Figure 1 schematically illustrates only one thin-film transistor 11 in the pixel drive circuit. The thin-film transistor 11 may be a top-gate thin-film transistor or a bottom-gate thin-film transistor. The present disclosure uses a top-gate thin-film transistor as an example for description.

[0082] As shown in Figures 1 to 3, the semiconductor layer is provided on a side of the buffer layer BFL away from the substrate SUB. The semiconductor layer may include, for example, an inorganic semiconductor material (e.g., polycrystalline silicon, amorphous silicon, etc.), an organic semiconductor material, or an oxide semiconductor material. The semiconductor layer may include an active layer 11a of a plurality of thin film transistors 11. The active layer 11a may include a channel region overlapping with a gate 11g and a source region and a drain region respectively provided on both sides of the channel region. Both the source region and the drain region may include impurities with a higher impurity concentration than that of the channel region. The impurities may include N-type impurities or P-type impurities.

[0083] As shown in Figures 1 to 3, the first gate insulating layer GI1 is provided on a side of the semiconductor layer away from the substrate SUB. The first gate insulating layer GI1 may include, for example, a silicon compound or a metal oxide. For example, the first gate insulating layer GI1 may include silicon oxynitride (SiON), silicon oxide (SiOx), silicon nitride (SiNx), silicon oxycarbide (SiOxCy), silicon carbide nitride (SiCxNy), aluminum oxide (AlOx), aluminum nitride (AlNx), tantalum oxide (TaOx), hafnium oxide (HfOx), zirconium oxide (ZrOx), titanium oxide (TiOx), etc. The first gate insulating layer GI1 may be formed as a single layer or multiple layers.

[0084] As shown in FIG1 to FIG3, the gate electrodes 11g of the plurality of thin film transistors 11 are disposed on a side of the first gate insulating layer GI1 away from the substrate SUB. The gate electrodes 11g may include, for example, a metal, a metal alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. For example, the gate electrodes 11g may include gold (Au), a gold alloy, silver (Ag), a silver alloy, aluminum (Al), an aluminum alloy, aluminum nitride (AlNx), tungsten (W), tungsten nitride (WNx), copper (Cu), a copper alloy, nickel (Ni), chromium (Cr), chromium nitride (CrNx), molybdenum (Mo), a molybdenum alloy, titanium (Ti), titanium nitride (TiNx), platinum (Pt), tantalum (Ta), tantalum nitride (TaNx), neodymium (Nd), scandium (Sc), strontium ruthenium oxide (SRO), zinc oxide (ZnOx), tin oxide (SnOx), indium oxide (InOx), gallium oxide (GaOx), indium tin oxide (ITO), indium zinc oxide (IZO), etc. The gate electrode 11g may have a single layer or multiple layers.

[0085] As shown in Figures 1 to 3, the second gate insulating layer GI2 may include silicon oxynitride (SiON), silicon oxide (SiOx), silicon nitride (SiNx), silicon oxycarbide (SiOxCy), silicon carbide nitride (SiCxNy), aluminum oxide (AlOx), aluminum nitride (AlNx), tantalum oxide (TaOx), hafnium oxide (HfOx), zirconium oxide (ZrOx), titanium oxide (TiOx), etc. The second gate insulating layer GI2 may be formed as a single layer or a multilayer.

[0086] The source-drain conductive layer is arranged on the side of the second gate insulating layer GI2 away from the substrate SUB. The first voltage line 20 includes a third conductive layer 23, which is arranged in the same layer as the source 11s and drain 11d of the thin film transistor 11, and is all located in the source-drain conductive layer. Among them, the source 11s of the thin film transistor 11 is electrically connected to the source region, and the drain 11d is electrically connected to the drain region. In the embodiment of the present disclosure, the source-drain conductive layer may include a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. For example, the source-drain conductive layer can be a single layer or multiple layers composed of a metal, such as Mo / Al / Mo or Ti / Al / Ti.

[0087] As shown in Figures 1 to 3, the planarization layer PLN is arranged on the side of the driving circuit layer away from the base substrate SUB. The planarization layer PLN may include an organic insulating material, such as polyimide, epoxy resin, acrylic, polyester, photoresist, polyacrylate, polyamide, silicone and other resin materials.

[0088] The thickness of the planarization layer PLN may be between 2 and 5 μm, for example, 2 μm, 3 μm, 4 μm, or 5 μm, thereby facilitating improved surface flatness of the planarization layer PLN. In one example, the flatness of the surface of the planarization layer PLN away from the substrate SUB (i.e., the height difference between the highest point and the lowest point) does not exceed 100 nm.

[0089] As shown in Figures 1 to 3, multiple transfer electrodes 40 and the first conductive layer 21 of the first voltage line are located on the side of the planarization layer PLN away from the base substrate SUB. Each transfer electrode 40 is electrically connected to the thin-film transistor 11 in the drive circuit layer via a first via V1 that penetrates the planarization layer PLN. Each transfer electrode 40 can be connected to a single thin-film transistor 11. The first conductive layer 21 is electrically connected to the corresponding third conductive layer 23 via a third via V3 that penetrates the planarization layer PLN.

[0090] As shown in Figures 1 to 3, the switching electrode 40 includes a reflective layer 41 and a bonding layer 42, which are sequentially arranged in a direction away from the base substrate SUB. The orthographic projections of the reflective layer 41 and the bonding layer 42 on the base substrate SUB may overlap. The bonding layer 42 is made of the first material described above.

[0091] The material of the reflective layer 41 can include at least one of silver (Ag), aluminum (Al), molybdenum (Mo), titanium (Ti), and chromium (Cr). For example, the reflective layer 41 can be made of silver (Ag), which has good reflective properties. The thickness of the reflective layer 41 can be between 10 and 200 nm. The provision of the reflective layer 41 can improve the light extraction efficiency of the top-emitting light-emitting chip 30.

[0092] The first conductive layer 21 includes a first conductive sublayer 211 and a second conductive sublayer 212 . The first conductive sublayer 211 is disposed on the same layer as the reflective layer 41 , and the second conductive sublayer 212 is disposed on the same layer as the bonding layer 42 .

[0093] Multiple light-emitting chips 30 are arranged on a side of the multiple transfer electrodes 40 away from the substrate SUB. The light-emitting chips 30 can be mini-LED light-emitting chips 30 or micro-LED light-emitting chips 30. The first electrodes 31 of the light-emitting chips 30 are bonded to the transfer electrodes 40 in a one-to-one correspondence. An IMC eutectic metal layer is formed between the first electrodes 31 and the corresponding transfer electrodes 40. This eutectic metal layer is generated by the reaction of the first material of the bonding layer 42 and the second material of the first electrode 31. The second conductive layer 22 is arranged on the same layer as the first electrode 31 and is bonded to the first conductive layer 21, thereby forming a eutectic metal layer between the first conductive layer 21 and the second conductive layer 22.

[0094] In the embodiment of the present disclosure, since a planarization layer PLN is provided on the side of the driving circuit layer away from the base substrate SUB, the transfer electrode 40 can be placed on a substantially flat surface, thereby improving the bonding effect between the transfer electrode 40 and the first electrode 31 .

[0095] As shown in Figures 1 to 3, the light-emitting main layer 33 is located on the side of the first electrode 31 away from the substrate SUB. The light-emitting main layer 33 may include a first semiconductor layer 331, an active layer 333, a second semiconductor layer 332, and a buffer layer 334, which are sequentially arranged in a direction away from the substrate SUB. The buffer layer 334 may include GaN, AlN, AlGaN, or InGaN.

[0096] The first semiconductor layer 331 may include In x Al y Ga 1-x-y The n-type nitride semiconductor layer may be composed of N (0≤x<1, 0≤y<1, 0≤x+y<1), and the n-type impurity may be silicon. For example, the first semiconductor layer 331 may contain n-type GaN. The second semiconductor layer 332 may contain In x Al y Ga 1-x-y N (0 ≤ x < 1, 0 ≤ y < 1, 0 ≤ x + y < 1) composition p-type nitride semiconductor layer, the p-type impurity can be magnesium. For example, the second semiconductor layer 332 can be a single layer structure, but as in some example embodiments, it can have a multilayer structure containing different components. The active layer 333 can have a multi-quantum well (MQW) structure, in which quantum well layers and quantum barrier layers are alternately stacked with each other. For example, the quantum well layer and the quantum barrier layer can respectively include In x Al y Ga 1-x-yDifferent components of N(0≤x≤1, 0≤y≤1, 0≤x + y≤1). In one example, the quantum well layer may include In x Ga 1-x components of N(0 < x≤1), and the quantum barrier layer may include GaN or AlGaN. The active layer 333 is not limited to the MQW structure and may have a single quantum well (SQW) structure.

[0097] As shown in FIGS. 1 to 3, the encapsulation layer 50 is located on the side of the planarization layer PLN away from the substrate SUB. The encapsulation layer 50 has a plurality of first accommodating portions, and the first accommodating portions may correspond to the light-emitting chips 30 one by one. The first electrode 31 and the light-emitting main body layer 33 of each light-emitting chip 30 are located in a corresponding first accommodating portion.

[0098] Wherein, the surface of the encapsulation layer 50 away from the substrate SUB may be flush or substantially flush with the surface of the light-emitting main body layer 33 away from the substrate SUB.

[0099] As shown in FIGS. 1 to 3, the light-emitting chip 30 further includes a second electrode 32, and the second electrode 32 is located on the side of the light-emitting main body layer 33 away from the substrate SUB. The first voltage line 20 further includes a fourth conductive layer 24, and the fourth conductive layer 24 is disposed on the same layer as the second electrode 32 of the light-emitting chip 30, both being located on the side of the encapsulation layer 50 away from the substrate SUB. The fourth conductive layer 24 is electrically connected to the second conductive layer 22 through a second via hole V2 penetrating the encapsulation layer 50. Wherein, both the second electrode 32 and the fourth conductive layer 24 may be made of a transparent conductive material such as indium tin oxide (ITO), and the thicknesses of the second electrode 32 and the fourth conductive layer 24 may both be between 50 and 500 nm.

[0100] In some embodiments, as shown in FIG. 2, the second electrodes 32 and the fourth conductive layers 24 of the plurality of light-emitting chips 30 may be connected into an integral structure, thereby simplifying the structure and manufacturing process of the display substrate.

[0101] In some embodiments, the number of the first voltage lines 20 may be one or more. The first voltage line 20 may be located in the display area. For example, the display area of the display substrate includes a plurality of pixel areas, and a light-emitting chip 30 is disposed in each pixel area. The first voltage line 20 is disposed in the interval area between adjacent two rows of pixel areas, or in the interval area between adjacent two columns of pixel areas. Of course, in some other embodiments, the first voltage line 20 may also be disposed in the peripheral area around the display area, and the second electrodes 32 of the plurality of light-emitting chips 30 are connected into a second electrode 32 layer and extended to the peripheral area, so as to be electrically connected to the fourth conductive layer 24 of the first voltage line 20.

[0102] As shown in Figure 3, a light shielding layer 60 is disposed on the side of the encapsulation layer 50 away from the substrate SUB. The light shielding layer 60 has multiple second accommodating portions, each of which exposes at least a portion of the second electrode 32 of a light-emitting chip 30. Multiple light emitting portions 70 are disposed on the side of the light-emitting chips 30 away from the substrate SUB, with each light emitting portion 70 corresponding to each of the second accommodating portions. The light shielding layer 60 is used to prevent light leakage between adjacent light-emitting chips 30. In one example, the thickness of the light shielding layer 60 can be between 2 and 7 μm.

[0103] Each light-emitting chip 30 is configured to emit light of a first color. The plurality of light-emitting portions 70 include: a plurality of first light-emitting portions 71, a plurality of second light-emitting portions 72, and a plurality of third light-emitting portions 73. For example, the plurality of light-emitting portions 70 can be divided into a plurality of repeating units, each repeating unit including a first light-emitting portion 71, a second light-emitting portion 72, and a third light-emitting portion 73. The first light-emitting portion 71 transmits the first color light emitted by the light-emitting chip 30; the second light-emitting portion 72 is configured to convert the first color light into second color light; and the third light-emitting portion 73 is configured to convert the first color light into third color light. For example, the first color light emitted by the light-emitting chip 30 is blue light; the second color light is red light; and the third color light is green light, thereby achieving full-color display.

[0104] The first light exiting portion 71 may include a transparent substrate and may also include heat dissipation particles doped in the transparent substrate. The second light exiting portion 72 and the third light exiting portion 73 may both include quantum dot materials.

[0105] The thickness of each light emitting portion 70 may be between 1 μm and 5 μm, for example, 1 μm, 2 μm, 3 μm, 4 μm, or 5 μm.

[0106] As shown in Figure 3, the display substrate also includes a plurality of color resist blocks 80. Each color resist block 80 corresponds one-to-one with each light exit portion 70. Each color resist block 80 is positioned on the side of a corresponding light exit portion 70 facing away from the base substrate SUB. The color of each color resist block 80 matches the color of the light emitted by the corresponding light exit portion 70. The provision of color resist blocks 80 helps to narrow the wavelength of the quantum dot material's emission, improving the display substrate's color gamut. Furthermore, this prevents ambient light from directly exciting the quantum dot material and affecting the displayed image.

[0107] The thickness of the color resist block 80 may be between 1 μm and 2 μm, for example, 1 μm, 1.5 μm, or 2 μm.

[0108] 3 , the display substrate may further include a protective layer 90 covering the plurality of color resist blocks 80 and the light shielding layer 60. The protective layer 90 may include an organic film layer and / or an inorganic film layer.

[0109] The present disclosure also provides a method for manufacturing the display substrate. The method comprises:

[0110] S10, forming a driving circuit layer on the base substrate.

[0111] S20 , forming a first bonding layer on a side of the driving circuit layer away from the base substrate.

[0112] S30 , providing an epitaxial wafer, wherein the epitaxial wafer includes a second bonding layer and an epitaxial layer that are stacked.

[0113] S40, transferring the epitaxial wafer to a side of the first bonding layer away from the substrate, and bonding the first bonding layer to the second bonding layer.

[0114] S50 , etching the epitaxial layer to form a first pattern; etching the second bonding layer to form a second pattern; and etching the first bonding layer to form a third pattern.

[0115] Among them, the first graphic includes a light-emitting main layer of multiple light-emitting chips, the second graphic includes the first electrodes of multiple light-emitting chips and the second conductive layer of the first voltage line, and the third graphic includes multiple switching electrodes and the first conductive layer of the first voltage line; the switching electrodes are electrically connected to the driving circuit layer.

[0116] In the disclosed embodiments, there's no need to transfer and bond a large number of light-emitting chips through mass transfer and mass bonding processes. Instead, only the entire epitaxial wafer needs to be transferred, bonded, and patterned, reducing process complexity. Furthermore, compared to a large number of light-emitting chips, the price of a single epitaxial wafer is lower, thereby reducing the production cost of display substrates.

[0117] In the embodiments of the present disclosure, the base substrate can be a rigid substrate or a flexible substrate. The light-emitting chip can be a top-emitting structure or a bottom-emitting structure. Figures 4 to 18 are schematic diagrams of the manufacturing process of the display substrate provided in some embodiments of the present disclosure. The following is a detailed description of the manufacturing method in the embodiments of the present disclosure, with the base substrate SUB being a flexible substrate and the light-emitting chip 30 being a top-emitting structure, in conjunction with the accompanying drawings. The manufacturing method of the display substrate includes:

[0118] S10, forming a driving circuit layer on the substrate SUB. Specifically, this step includes S11 and S12:

[0119] S11, as shown in FIG4, a flexible base substrate SUB is formed on a carrier substrate SUB0. The carrier substrate SUB0 may be a glass substrate or a hard substrate of other materials. The base substrate SUB may be made of polyimide, for example, and may have a thickness of 3 to 20 μm.

[0120] S12. As shown in FIG5 , a plurality of thin film transistors 11 are formed on the substrate SUB. Specifically, step S12 includes: first, forming a buffer layer; then, forming active layers 11a of the plurality of thin film transistors 11; then, forming a first gate insulating layer; then, forming gates 11g of the plurality of thin film transistors 11; then, forming a second gate insulating layer; and finally, forming source electrodes 11s and drain electrodes 11d of the plurality of thin film transistors 11.

[0121] While forming the source electrodes 11s and drain electrodes 11d of the plurality of thin film transistors 11, the third conductive layer 23 of the first voltage line 20 is also formed. That is, a source / drain metal layer is formed and patterned to form a pattern including the source electrodes 11s and drain electrodes 11d of the plurality of thin film transistors 11 and the third conductive layer 23.

[0122] S15 . As shown in FIG. 6 , a planarization layer PLN is formed on a side of the driving circuit layer away from the base substrate SUB; and a plurality of first via holes V1 and third via holes V3 are formed on the planarization layer PLN.

[0123] S20: As shown in FIG7 , a first bonding layer 40a is formed on a side of the driving circuit layer away from the base substrate SUB. The first bonding layer 40a is electrically connected to the driving circuit layer through each first via V1.

[0124] In one example, the first bonding layer 40a includes a reflective material layer 41a and a bonding material layer 42a disposed sequentially in a direction away from the substrate SUB. The reflective material layer 41a may be a layer of material such as Ag, Al, Mo, Ti, or Cr, and may have a thickness between 10 and 200 nm. The bonding material layer 42a includes the aforementioned first material, and may have a thickness between 100 nm and 2 μm.

[0125] S30 . As shown in FIG8 , an epitaxial wafer 3 a is provided. The epitaxial wafer 3 a includes a second bonding layer 31 a and an epitaxial layer 30 a stacked together.

[0126] In one example, the epitaxial wafer 3a may further include a substrate 32a. The second bonding layer 31a is located on a side of the epitaxial layer 30a away from the substrate 32a. The material of the substrate 32a may be sapphire, Si, SiC, etc., and the material of the second bonding layer 31a includes the aforementioned second material. In the disclosed embodiments, a sapphire substrate 32a is used as an example for description.

[0127] S40 , as shown in FIG9 , transfer the epitaxial wafer 3 a to the side of the first bonding layer 40 a away from the substrate SUB, and bond the first bonding layer 40 a to the second bonding layer 31 a .

[0128] In one example, the epitaxial wafer 3a is transferred to the side of the first bonding layer 40a away from the substrate SUB, and the epitaxial wafer 3a and the first bonding layer 40a are hot-pressed and integrated. During the hot-pressing process, the first bonding layer 40a and the second bonding layer 31a are metal-bonded to achieve ohmic conduction.

[0129] S41 , as shown in FIG10 , peeling off the substrate 32 a by laser dissociation.

[0130] S50 , etching the epitaxial layer 30 a to form a first pattern; etching the second bonding layer 31 a to form a second pattern; and etching the first bonding layer 40 a to form a third pattern.

[0131] Wherein, step S50 includes S51-S52:

[0132] S51 , as shown in FIG11 , uses a photolithography patterning process to etch the epitaxial layer 30 a to form a first pattern. The first pattern includes the light-emitting body layers 33 of the plurality of light-emitting chips 30 .

[0133] S52 , using the same photolithography patterning process, synchronously etching the second bonding layer 31 a and the first bonding layer 40 a to form a second pattern and a third pattern.

[0134] As shown in Figure 11, the second pattern includes the first electrodes 31 of the plurality of light-emitting chips 30 and the second conductive layer 22 of the first voltage line 20. The third pattern includes the plurality of switching electrodes 40 and the first conductive layer 21 of the first voltage line 20. The switching electrodes 40 are electrically connected to the driving circuit layer through the first via V1. Specifically, the switching electrodes 40 are electrically connected to the drain electrode 11d of the thin-film transistor 11 through the first via V1. The first conductive layer 21 is electrically connected to the third conductive layer 23 through the third via V3.

[0135] The switching electrode 40 includes a reflective layer 41 and a bonding layer 42. The first conductive layer 21 includes a first conductive sublayer 211 and a second conductive sublayer 212. The first conductive sublayer 211 and the reflective layer 41 are formed by etching the reflective material layer 41a, while the second conductive sublayer 212 and the bonding layer 42 are formed by etching the bonding material layer 42a.

[0136] S60: As shown in Figure 12, a packaging layer 50 having a plurality of first receiving portions and a plurality of second via holes V2 is formed, wherein the first electrode 31 and the light emitting body layer 33 of each light emitting chip 30 are located in one first receiving portion.

[0137] S70: As shown in FIG13 , simultaneously form the second electrodes 32 of the plurality of light-emitting chips 30 and the fourth conductive layer 24 of the plurality of first voltage lines 20. The fourth conductive layer 24 is electrically connected to the second conductive layer 22 and the second electrode 32 of each light-emitting chip 30; the second electrode 32 is located on a side of the light-emitting body layer 33 away from the substrate SUB.

[0138] Specifically, a transparent conductive layer may be formed first, and then photolithography patterning may be performed on the transparent conductive layer to form the second electrodes 32 of the plurality of light emitting chips 30 and the fourth conductive layer 24 of the plurality of first voltage lines 20 .

[0139] S80 , as shown in FIG. 14 , forming a light shielding layer 60 having a plurality of second receiving portions Sp2 ; each second receiving portion Sp2 exposes at least a portion of the second electrode 32 of one light emitting chip 30 .

[0140] S90. As shown in FIG15 , a light emitting portion 70 is formed in each second accommodating portion, and the light emitting portion 70 is located on a side of the second electrode 32 away from the base substrate SUB; the light emitting portions 70 in the plurality of second accommodating portions include: a first light emitting portion 71, a second light emitting portion 72, and a third light emitting portion 73, the first light emitting portion 71 transmits the first color light emitted by the light emitting chip 30, the second light emitting portion 72 is used to convert the first color light into the second color light; the third light emitting portion 73 is used to convert the first color light into the third color light.

[0141] The thickness of each light-emitting layer is between 1 μm and 5 μm.

[0142] S100 , as shown in FIG16 , a color resist block 80 is formed on a side of each light emitting portion 70 away from the base substrate SUB. The color of the color resist block 80 is the same as the color of the light emitted by the corresponding light emitting portion 70 .

[0143] The thickness of the color resist block 80 may be between 1 μm and 2 μm.

[0144] S110: As shown in FIG17 , a protective layer 90 is formed to cover the plurality of color resist blocks 80 and the light shielding layer 60. The protective layer 90 may include an organic film layer and / or an inorganic film layer.

[0145] S120 , removing the carrier substrate SUB0 by laser or mechanical separation to obtain the structure shown in FIG18 , thereby achieving flexibility of the display substrate.

[0146] The present disclosure also provides a display device comprising the display substrate of the above embodiment. The display device can be a product or component with a display function, such as a mobile phone, a television, a monitor, a tablet computer, or a navigation system.

[0147] It is understood that the above embodiments are merely exemplary embodiments for illustrating the principles of the present disclosure, and the present disclosure is not limited thereto. Those skilled in the art may make various modifications and improvements without departing from the spirit and substance of the present disclosure, and such modifications and improvements are also considered to be within the scope of protection of the present disclosure.

Claims

1. A display substrate, comprising: substrate substrate; A driving circuit layer is arranged on the base substrate; A plurality of switching electrodes are arranged on a side of the driving circuit layer away from the base substrate and are electrically connected to the driving circuit layer; A plurality of light-emitting chips are arranged on a side of the plurality of transfer electrodes away from the base substrate, the light-emitting chips include first electrodes and a light-emitting main body layer arranged in sequence in a direction away from the base substrate, and each of the first electrodes is bonded to one of the transfer electrodes; The first voltage line includes a first conductive layer and a second conductive layer, the first conductive layer and the switching electrode are arranged in the same layer, and the second conductive layer and the first electrode are arranged in the same layer; the first conductive layer and the second conductive layer are bonded.

2. The display substrate according to claim 1, wherein: The orthographic projections of the first electrode and the switching electrode connected thereto on the base substrate overlap; the orthographic projections of the first conductive layer and the second conductive layer on the base substrate overlap.

3. The display substrate according to claim 1 or 2, wherein: The driving circuit layer includes a plurality of thin film transistors, and the switching electrodes are electrically connected to the thin film transistors; The first voltage line further includes: a third conductive layer disposed on the same layer as the source and the drain of the thin film transistor, and the first conductive layer is electrically connected to the third conductive layer.

4. The display substrate according to any one of claims 1 to 3, wherein: The switching electrode comprises: a reflective layer and a bonding layer which are sequentially arranged in a direction away from the substrate; The first conductive layer includes: a first conductive sublayer and a second conductive sublayer, the first conductive sublayer and the reflective layer are disposed in the same layer, and the second conductive sublayer and the bonding layer are disposed in the same layer.

5. The display substrate according to any one of claims 1 to 4, wherein: The display substrate further includes a planarization layer located between the driving circuit layer and the plurality of switching electrodes, and the switching electrodes are electrically connected to the driving circuit layer through the first via holes penetrating the planarization layer.

6. The display substrate according to any one of claims 1 to 5, wherein: The light-emitting chip also includes a second electrode, which is located on a side of the light-emitting main layer away from the base substrate; the first voltage line also includes a fourth conductive layer electrically connected to the second conductive layer, and the fourth conductive layer is arranged on the same layer as the second electrode and is electrically connected.

7. The display substrate according to claim 6, wherein: The display substrate further comprises: The encapsulation layer is located on a side of the driving circuit layer away from the base substrate; the encapsulation layer has a plurality of first accommodating portions, and the first electrode and the light-emitting main layer of each light-emitting chip are located in one of the first accommodating portions; The fourth conductive layer is electrically connected to the second conductive layer through a second via hole penetrating the packaging layer.

8. The display substrate according to claim 7, wherein: The light emitting chip is used to emit a first color light; the display substrate further comprises: a light shielding layer, the light shielding layer having a plurality of second accommodating portions, each of the second accommodating portions exposing at least a portion of one of the second electrodes; A plurality of light emitting parts, each of which is arranged in one of the second accommodating parts and is located on a side of the second electrode away from the substrate; the plurality of light emitting parts comprises: a plurality of first light emitting parts, a plurality of second light emitting parts and a plurality of third light emitting parts, the first light emitting parts transmit the first color light emitted by the light emitting chip; the second light emitting parts are used to convert the first color light into the second color light; the third light emitting parts are used to convert the first color light into the third color light; A plurality of color resist blocks, each of which is arranged on a side of the light emitting portion away from the base substrate, and the color of the color resist block is the same as the color of the light emitted by the corresponding light emitting portion.

9. The display substrate according to any one of claims 1 to 8, wherein: The light-emitting chip is a mini-LED light-emitting chip or a Micro-LED light-emitting chip.

10. A method for manufacturing a display substrate, comprising: forming a driving circuit layer on the base substrate; forming a first bonding layer on a side of the driving circuit layer away from the base substrate; Providing an epitaxial wafer, the epitaxial wafer comprising a second bonding layer and an epitaxial layer which are stacked; Transferring the epitaxial wafer to a side of the first bonding layer away from the substrate, and bonding the first bonding layer to the second bonding layer; Etching the epitaxial layer to form a first pattern; Etching the second bonding layer to form a second pattern; Etching the first bonding layer to form a third pattern; The first pattern includes a light-emitting main body layer of a plurality of light-emitting chips, the second pattern includes first electrodes of the plurality of light-emitting chips and a second conductive layer of a first voltage line, and the third pattern includes a plurality of switching electrodes and a first conductive layer of the first voltage line; The switching electrode is electrically connected to the driving circuit layer.

11. The method according to claim 10, wherein: The step of etching the second bonding layer and the step of etching the first bonding layer are performed in the same patterning process.

12. The production method according to claim 10 or 11, wherein: The step of forming a driving circuit layer on the base substrate comprises: forming a plurality of thin film transistors on the base substrate, wherein the switching electrodes are electrically connected to the thin film transistors; Wherein, while forming the source and drain of a plurality of thin film transistors, the third conductive layer of the first voltage line is also formed; the first conductive layer is electrically connected to the third conductive layer.

13. The production method according to any one of claims 10 to 12, wherein: The first bonding layer includes a reflective material layer and a bonding material layer sequentially arranged in a direction away from the substrate; The switching electrode includes: a reflective layer and a bonding layer; the first conductive layer includes: a first conductive sublayer and a second conductive sublayer; The first conductive sublayer and the reflective layer are formed by etching the reflective material layer, and the second conductive sublayer and the bonding layer are formed by etching the bonding material layer.

14. The production method according to any one of claims 10 to 13, wherein: Before the step of forming the first bonding layer, the manufacturing method further includes: forming a planarization layer on a side of the driving circuit layer away from the base substrate; forming a first via hole on the planarization layer at a position corresponding to the switching electrode; Wherein, the switching electrode is electrically connected to the driving circuit layer through the first via hole.

15. The production method according to any one of claims 9 to 14, wherein: The production method also includes: Simultaneously forming the second electrodes of the plurality of light-emitting chips and the fourth conductive layers of the plurality of the first voltage lines; The fourth conductive layer is electrically connected to the second conductive layer and the second electrode, and the second electrode is located on a side of the light-emitting main layer away from the base substrate.

16. The method according to claim 15, wherein: Before the step of synchronously forming the second electrodes of the plurality of light-emitting chips, the manufacturing method further comprises: forming a packaging layer having a plurality of first receiving portions and a plurality of second via holes; The first electrode and the light-emitting main layer of each of the light-emitting chips are located in one of the first receiving portions, and the fourth conductive layer is electrically connected to the second conductive layer through the second via hole.

17. The method according to claim 16, wherein: The light-emitting chip is used to emit a first color light; the manufacturing method further includes: forming a light shielding layer having a plurality of second accommodation portions; A light emitting portion is formed in each of the second accommodating portions, and the light emitting portion is located on a side of the second electrode away from the base substrate; the light emitting portions in the plurality of second accommodating portions include: a first light emitting portion, a second light emitting portion, and a third light emitting portion, the first light emitting portion transmits the first color light emitted by the light emitting chip, the second light emitting portion is used to convert the first color light into the second color light; the third light emitting portion is used to convert the first color light into the third color light; A color block is formed on a side of each light emitting portion away from the base substrate, and the color of the color block is the same as the color of the light emitted by the corresponding light emitting portion.

18. A display device, wherein: include: The display substrate according to any one of claims 1 to 9.

Images