Display substrate and display device

Abstract

A display substrate and a display device, the display substrate comprises a substrate, and a plurality of element groups (Z1), a plurality of first-type signal lines and a plurality of first-type connecting lines arranged on the substrate, on a plane parallel to the display substrate, the plurality of element groups (Z1) are arranged in an array, the plurality of first-type signal lines extend along a column direction and are arranged at intervals along a row direction, and the plurality of first-type connecting lines are arranged on the substrate. The plurality of first type connecting lines extend along the row direction and are arranged at intervals along the column direction, and the row direction intersects with the column direction; in the direction perpendicular to the plane where the display substrate is located, the first type signal lines and the first type connecting lines are located on different conducting layers. The first-type signal lines are electrically connected with at least two non-adjacent first-type connecting lines, and the first-type connecting lines are electrically connected with at least part of the element groups (Z1) in one row of element groups.

Description

Display substrate and display device Technical Field

[0001] This article relates to but is not limited to the field of display technology, and in particular to a display substrate and a display device. Background Art

[0002] Transparent display technology can not only display the image on the display, but also the objects behind the display, showing a broad range of applications. Transparent display technology has been widely used in display windows, transparent televisions, in-vehicle displays, virtual reality (VR), augmented reality (AR), and other fields.

[0003] Summary of the Invention

[0004] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0005] Embodiments of the present disclosure provide a display substrate and a display device.

[0006] In a first aspect, embodiments of the present disclosure provide a display substrate, comprising: a base substrate, and a plurality of component groups, a plurality of first-type signal lines, and a plurality of first-type connecting lines disposed on the base substrate, wherein the plurality of component groups are arranged in an array on a plane parallel to the display substrate, the plurality of first-type signal lines extend in a column direction and are spaced apart in a row direction, and the plurality of first-type connecting lines extend in the row direction and are spaced apart in the column direction, wherein the row direction intersects the column direction; and in a direction perpendicular to the plane of the display substrate, the first-type signal lines and the first-type connecting lines are located on different conductive layers;

[0007] The first-type signal line is electrically connected to at least two non-adjacent first-type connecting lines, and the first-type connecting lines are electrically connected to at least part of the component groups in one row of component groups.

[0008] In some exemplary embodiments, the multiple first-class signal lines and the multiple first-class connecting lines each include at least one, each first-class signal line is electrically connected to one of the first-class connecting lines, the number of at least one first-class connecting lines is 2M, and in the column direction, the same 2M first-class connecting lines are arranged in sequence along the column direction, and the i-th and M+i-th first-class connecting lines are electrically connected to one of the first-class signal lines, where i is an integer greater than or equal to 1 and less than or equal to M, and M is an integer greater than or equal to 1.

[0009] In some exemplary embodiments, the types of the multiple first-class signal lines include at least a first power line, the types of the multiple first-class connection lines include at least a first power connection line, the number of the first power lines is multiple, the number of the first power connection lines is 2M, and in the column direction, the 2M first power connection lines are arranged in sequence, and the i-th and M+i-th first power connection lines are electrically connected to one of the first power lines.

[0010] In some exemplary embodiments, in the row direction, at least one of the first power connection lines is located between two adjacent rows of component groups; in the column direction, at least one of the first power connection lines is located between two adjacent columns of component groups.

[0011] In some exemplary embodiments, the plurality of component groups form 2M rows, and each first power connection line is configured to be electrically connected to a row of component groups adjacent thereto.

[0012] In some exemplary embodiments, the display substrate further includes a plurality of second-category signal lines and a plurality of third-category signal lines; on a plane parallel to the display substrate, the plurality of second-category signal lines and the plurality of third-category signal lines all extend along the column direction and are arranged at intervals along the row direction; the plurality of element groups form 2M rows, and in a column of element groups, the 1st to Mth row element groups are electrically connected to the second-category signal lines, and the M+1th to 2Mth row element groups are electrically connected to the third-category signal lines.

[0013] In some exemplary embodiments, the display substrate further includes at least one driving circuit, the display substrate includes a display area, the multiple element groups are arranged in the display area, and the driving circuit is arranged on one side of the display area in a direction parallel to the plane where the display substrate is located. One end of the first type signal line, the second type signal line, and the third type signal line is electrically connected to the corresponding driving circuit, and the other end extends to the display area.

[0014] In some exemplary embodiments, the second type of signal lines includes a plurality of first data signal lines, and the third type of signal lines includes a plurality of second data signal lines. In the column direction, the first data signal lines run through the display area, and the second data signal lines extend from the 2Mth row element group to the M+1th row element group in the display area.

[0015] In some exemplary embodiments, the display substrate further includes a plurality of common potential signal lines and a plurality of fixed potential signal lines electrically connected to the plurality of columns of component groups, respectively. The plurality of first-type signal lines include a plurality of first power lines. On a plane parallel to the display substrate, the plurality of common potential signal lines and the plurality of fixed potential signal lines all extend along the column direction and are arranged at intervals along the row direction. In the row direction, among the signal lines electrically connected to one column of component groups, the fixed potential signal line and the first power line are respectively located on both sides of the common potential signal line, and the orthographic projection of the common potential signal line on the base substrate at least partially overlaps with the orthographic projection of the column of component groups on the base substrate.

[0016] In some exemplary embodiments, the element group includes a first type of light-emitting element and a second type of light-emitting element, and the fixed potential signal line includes a first fixed potential signal line and a second fixed potential signal line, the first fixed potential signal line is electrically connected to the first type of light-emitting element, and the second fixed potential signal line is electrically connected to the second type of light-emitting element.

[0017] In some exemplary embodiments, in the row direction, the common potential signal line is larger than the first fixed potential signal line and the first type of signal line, and the second fixed potential signal line is smaller than the first fixed potential signal line and the first type of signal line.

[0018] In some exemplary embodiments, in the row direction, a size of the common potential signal line is 1.5 to 3 times a size of the second fixed potential signal line.

[0019] In some exemplary embodiments, the element group further includes a control circuit, which is electrically connected to the first type of light-emitting element, the second type of light-emitting element, the first power line and the common potential signal line, and is electrically connected to one of the first data signal line and the second data signal line. Among the signal lines electrically connected to one column of the element groups, in the row direction, the common potential signal line is located on one side of the control circuit, and the first data signal line and the second data signal line are located on the other side of the control circuit.

[0020] In some exemplary embodiments, in the row direction, among the signal lines electrically connected to one column of the element groups, the first data signal line and the second data signal line are located between the common potential signal line and the first power line.

[0021] In some exemplary embodiments, in the row direction, among the signal lines electrically connected to one column of component groups, a first distance between the common potential signal line and the first data signal line is greater than a second distance between the common potential signal line and the second fixed potential signal line.

[0022] In some exemplary embodiments, in the row direction, between two adjacent common potential signal lines, the first data signal line, the first power line, the first fixed potential signal line, and the second fixed potential signal line are arranged in sequence, and the distance between two adjacent signal lines is consistent with the second distance.

[0023] In a second aspect, an embodiment of the present disclosure provides a display device comprising at least one display substrate as described in any of the above embodiments.

[0024] Still other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The accompanying drawings are intended to provide a further understanding of the technical solutions of the present disclosure and constitute part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solutions of the present disclosure and do not constitute a limitation of the technical solutions of the present disclosure. The shapes and sizes of one or more components in the accompanying drawings do not reflect the actual scale and are intended only to illustrate the contents of the present disclosure.

[0026] FIG1 is a schematic diagram of a display substrate according to at least one embodiment of the present disclosure;

[0027] FIG2 is a schematic diagram of a display substrate provided by an exemplary embodiment of the present disclosure;

[0028] FIG3 is an enlarged schematic diagram of the position of M1 in FIG1 ;

[0029] FIG4 is an enlarged schematic diagram of the position of M1 in FIG1 ;

[0030] FIG5 is an enlarged schematic diagram of the position of M2 in FIG3 ;

[0031] FIG6 is a schematic diagram of the cross-sectional structure at position BB in FIG5 ;

[0032] FIG7 is a schematic diagram of a display device according to at least one embodiment of the present disclosure;

[0033] FIG8 is a schematic diagram of a display device according to at least one embodiment of the present disclosure. DETAILED DESCRIPTION

[0034] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. The embodiments can be implemented in a variety of different forms. A person skilled in the art can easily understand that the method and content can be transformed into one or more forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments of the present disclosure and the features in the embodiments can be combined with each other in any way.

[0035] In the drawings, the size of one or more components, layer thicknesses, or regions may be exaggerated for clarity. Therefore, one embodiment of the present disclosure is not necessarily limited to these dimensions, and the shapes and sizes of components in the drawings do not reflect true proportions. Furthermore, the drawings schematically illustrate idealized examples, and one embodiment of the present disclosure is not limited to the shapes or values ​​shown in the drawings.

[0036] In this specification, ordinal numbers such as "first", "second", and "third" are provided to avoid confusion among constituent elements, rather than to limit the quantity. The "plurality" in this disclosure may include two or more.

[0037] In this specification, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of constituent elements with reference to the accompanying drawings. This is merely for the purpose of facilitating the description of this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limiting the present disclosure. The positional relationships of constituent elements may be appropriately changed depending on the direction in which the constituent elements are described. Therefore, the present disclosure is not limited to the words and phrases described in the specification and may be appropriately replaced according to the circumstances.

[0038] In this specification, unless otherwise specified or limited, the terms "mounted," "connected," and "connected" should be interpreted broadly. For example, they can refer to fixed, removable, or integral connections; mechanical or electrical connections; direct connections, indirect connections through intermediaries, or internal communication between two components. Those skilled in the art will understand the meaning of these terms in this disclosure based on the specific circumstances.

[0039] In this specification, "electrically connected" includes components connected together via an element having some electrical function. There are no particular limitations on the "element having some electrical function" as long as it enables the transfer of electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with one or more functions.

[0040] In this specification, a transistor refers to a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain) and a source electrode (source electrode terminal, source region, or source), and current can flow through the drain electrode, the channel region, and the source electrode. In this disclosure, the channel region refers to the region through which current primarily flows.

[0041] In this specification, in order to distinguish the two electrodes of a transistor other than the gate electrode, one electrode is referred to as the first electrode and the other electrode is referred to as the second electrode. The first electrode can be a source electrode or a drain electrode, and the second electrode can be a drain electrode or a source electrode. In addition, the gate electrode of a transistor can be referred to as a control electrode. In cases where transistors with opposite polarity are used or where the direction of current changes during circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Therefore, in this specification, the "source electrode" and the "drain electrode" can be interchanged.

[0042] In this specification, "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°, and thus includes a state where the angle is greater than -5° and less than 5°. Furthermore, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°, and thus includes a state where the angle is greater than 85° and less than 95°.

[0043] In this specification, triangles, rectangles, trapezoids, pentagons or hexagons are not in the strict sense, but may be approximate triangles, rectangles, trapezoids, pentagons or hexagons, etc. There may be some small deformations caused by tolerances, and there may be chamfers, arc edges and deformations.

[0044] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced with "conductive film." Similarly, "insulating film" may be replaced with "insulating layer."

[0045] In this specification, "approximately" and "substantially" are used without strict limits and allow for process and measurement errors. In this specification, "substantially the same" may refer to values ​​that differ by less than 10%.

[0046] In the present disclosure, “thickness” and “height” refer to the vertical distance between the surface of the film layer away from the substrate and the surface of the film layer close to the substrate.

[0047] During LCD display, light emitted from the backlight passes through polarizers and color filters, resulting in significant energy loss. Mini / Micro LED displays, on the other hand, utilize a self-luminous sub-pixel structure using three primary colors. This reduces power consumption by approximately 10% compared to LCD displays. Mini / Micro LEDs utilize inorganic materials for light emission, resulting in higher luminous efficiency. OLEDs utilize organic materials for light emission, resulting in lower power consumption than OLEDs. Furthermore, unlike OLEDs, which use organic materials, Mini / Micro LEDs utilize gallium nitride (GaN) in their light-emitting components, which significantly surpasses OLED in brightness. In Mini / Micro LED display products, each Mini / Micro LED is a self-luminous pixel. Furthermore, individual Mini / Micro LEDs are micron-sized, enabling very high resolution. In related technologies, Mini / Micro LED displays can achieve pixel densities exceeding 1500 PPI, compared to approximately 800 PPI and 400 PPI for LCD and OLED screens, respectively.

[0048] Based on the above advantages, Mini / Micro LED displays will become the next generation of displays after LCD displays and OLED displays, and have broad application prospects.

[0049] Micro-LEDs (Micro Light Emitting Diodes) and Mini-LEDs (Mini Light Emitting Diodes) are primarily manufactured by miniaturizing, arraying, and thinning traditional LEDs using micro-processing technologies. The LED thin films are then transferred in bulk to a driver backplane using mass transfer technology. Mini-LEDs and Micro-LEDs offer significant advantages in transparent displays, characterized by high brightness and a small luminous area. Transparent displays are widely used in display windows, transparent televisions, automotive displays, and VR glasses.

[0050] Currently, large-scale transparent display products on the market face issues such as high power consumption and uneven display due to the increased number of pixels passing through each signal line due to the larger display panel size. Furthermore, as the pitch (the shortest distance between two adjacent pixels) decreases, the number of output lines increases, resulting in lower overall transmittance for transparent display products. Therefore, improving the transmittance and display uniformity of transparent displays is a pressing issue.

[0051] This embodiment provides a display substrate, which may include: a base substrate; and a plurality of component groups, a plurality of first-type signal lines, and a plurality of first-type connecting lines disposed on the base substrate. The plurality of component groups are arranged in an array on a plane parallel to the display substrate. The plurality of first-type signal lines extend in a column direction and are spaced apart in a row direction. The plurality of first-type connecting lines extend in a row direction and are spaced apart in a column direction, with the row direction intersecting the column direction. In a direction perpendicular to the plane of the display substrate, the first-type signal lines and the first-type connecting lines are located on different conductive layers.

[0052] The first type of signal line is electrically connected to at least two non-adjacent first type of connection lines, and the first type of connection lines is electrically connected to at least part of the component groups in one row of component groups.

[0053] In the display substrate provided by the embodiment of the present disclosure, the first type signal line is electrically connected to at least two non-adjacent first type connection lines, which can reduce the number of the first type signal lines and thus improve the transmittance of the display substrate.

[0054] As shown in FIG1 , a display substrate provided by an embodiment of the present disclosure may include: a base substrate, and a plurality of component groups Z1, a plurality of first-type signal lines, and a plurality of first-type connecting lines disposed on the base substrate. In a direction parallel to the plane of the display substrate, the plurality of component groups Z1 are arranged in an array, the plurality of first-type signal lines extend along a column direction Y and are spaced apart along a row direction X, and the plurality of first-type connecting lines extend along a row direction X and are spaced apart along a column direction Y, where the row direction X intersects the column direction Y. In a direction perpendicular to the plane of the display substrate, the first-type signal lines and the first-type connecting lines are located on different conductive layers.

[0055] The first type signal line is electrically connected to at least two non-adjacent first type connecting lines, and the first type connecting lines are electrically connected to at least part of the component groups Z1 in one row of component groups.

[0056] In an exemplary embodiment, as shown in FIG1 , the plurality of first-class signal lines and the plurality of first-class connecting lines each include at least one, each first-class signal line is electrically connected to one of the first-class connecting lines, the number of the at least one first-class connecting lines is 2M, and in the column direction, the 2M first-class connecting lines of the same kind are arranged in sequence along the column direction Y, and the i-th and M+i-th first-class connecting lines are electrically connected to one of the first-class signal lines, where i is an integer greater than or equal to 1 and less than or equal to M, and M is an integer greater than or equal to 1.

[0057] In an exemplary embodiment, as shown in FIG1 , the types of the plurality of first-category signal lines include at least a first power line VCC, the types of the plurality of first-category connection lines include at least a first power connection line VCC1, the number of the first power lines VCC is multiple, the number of the first power connection lines VCCL may be 2M, and in the column direction Y, the 2M first power connection lines VCCL are arranged sequentially, and the i-th and M+i-th first power connection lines VCCL are electrically connected to one of the first power lines VCC.

[0058] In an exemplary embodiment, the i-th and M+i-th first power connection lines VCCL are electrically connected to one of the first power lines VCC. That is, one first power line VCC can provide a first power signal for a row of component groups in the upper half screen and a row of component groups in the lower half screen of the display substrate. While improving display uniformity, the number of first-type signal lines can be reduced, thereby improving the transmittance of the display substrate.

[0059] In an exemplary embodiment, at least one first power connection line VCCL is located between two adjacent rows of component groups in the row direction X, and at least one first power line VCC is located between two adjacent columns of component groups in the column direction Y. The first power connection line VCCL is located between two adjacent rows of component groups, and the first power line VCC is located between two adjacent columns of component groups. This minimizes obstruction of component group Z1, thereby improving the transmittance of the display substrate.

[0060] In an exemplary embodiment, multiple component groups Z1 form 2M rows, and each first power connection line VCCL is configured to be electrically connected to a row of component groups adjacent to it. This can reduce the length of the connecting line between the first power connection line VCCL and the component group Z1, minimize voltage drop, and save space.

[0061] In an exemplary embodiment, the display substrate may further include a plurality of second-category signal lines and a plurality of third-category signal lines; on a plane parallel to the display substrate, the plurality of second-category signal lines and the plurality of third-category signal lines all extend along the column direction Y and are arranged at intervals along the row direction X; a plurality of element groups Z1 form 2M, and in a column of element groups, the element groups from the 1st to the Mth rows are electrically connected to the second-category signal lines, and the element groups from the M+1th to the 2Mth rows are electrically connected to the third-category signal lines, that is, the second-category signal lines provide signals to the upper half of the display substrate, and the third-category signal lines provide signals to the lower half of the display substrate, which can improve the display uniformity of the display substrate.

[0062] In an exemplary embodiment, the second type of signal line may include multiple first data signal lines Data1, and the third type of signal line includes multiple second data signal lines Data2. In a column of element groups Z1, the 1st to Mth row element groups Z1 are electrically connected to the first data signal lines Data1, and the M+1th to 2Mth row element groups are electrically connected to the second data signal lines Data2.

[0063] In an exemplary embodiment, the display substrate may further include at least one driver circuit. The display substrate may include a display area, with multiple element groups Z1 disposed in the display area. The driver circuit is disposed on one side of the display area in a direction parallel to the plane of the display substrate. One end of the first-category signal line, the second-category signal line, and the third-category signal line are electrically connected to the corresponding driver circuits, and the other ends extend to the display area AA. In an exemplary embodiment, as shown in FIG. 2 , the driver circuit 200 is disposed on one side of the display area AA in a direction parallel to the plane of the display substrate. One end of the first power line VCC, the first data signal line Data1, and the second data signal line Data2 are electrically connected to the corresponding driver circuits 200, and the other ends extend to the display area AA.

[0064] In an exemplary embodiment, as shown in FIG. 1 and FIG. 2 , since a display substrate generally forms a bonding area at an edge of at least one side in a column direction Y, the driving circuit 200 may be disposed in the bonding area.

[0065] In an exemplary embodiment, the driver circuit 200 can utilize flip-chip technology (e.g., chip on film, COF) to electrically connect to the signal traces in the display substrate. The COF device receives a serial peripheral interface (SPI) communication signal from the driver circuit 200, converts the SPI signal into a data signal and a first power signal, transmits the data signal to a first data signal line, Data1, and a second data signal line, Data2, and transmits the first power signal to a first power line, VCC. A first power connection line, VCCL, electrically connected to the first power line, VCC, transmits the first power signal to the corresponding component group. In an exemplary embodiment, multiple driver circuits 200 can be used to drive the display substrate in different zones, enabling the realization of a large-scale display substrate.

[0066] In an exemplary embodiment, in the column direction Y, the first data signal line Data1 runs through the display area AA, and the second data signal line Data2 extends from the 2Mth row element group Z1 to the M+1th row element group Z1 in the display area AA, so that the first data signal line Data1 can be electrically connected to the 1st to Mth row element groups of one column in its display area AA, and the second data signal line Data2 can be electrically connected to the M+1th row element group Z1 to the 2Mth row element group Z1 in the display area AA. In addition, the second data signal line Data2 does not need to extend to the 1st to Mth rows. While improving the display uniformity of the display substrate, the transmittance of the display substrate can be improved.

[0067] In an exemplary embodiment, as shown in Figures 1 and 2, the display substrate may further include a plurality of common potential signal lines GND and a plurality of fixed potential signal lines electrically connected to the plurality of columns of element groups Z1, respectively. The plurality of common potential signal lines GND and the plurality of fixed potential signal lines all extend along the column direction Y and are arranged at intervals along the row direction X. In the row direction X, among the signal lines electrically connected to one column of element groups Z1, the fixed potential signal line and the first power line VCC are respectively located on either side of the common potential signal line GND, and the orthographic projection of the common potential signal line GND on the base substrate at least partially overlaps with the orthographic projection of the corresponding column of element groups Z1 on the base substrate.

[0068] In an exemplary embodiment, the base substrate may be a transparent substrate that allows visible light to pass through. In some embodiments, the transparent substrate may be made of glass, quartz, plastic, polyimide, or the like.

[0069] In an exemplary embodiment, the display substrate provided by the present disclosure can be applied to transparent display fields such as smart transportation, smart windows, and outdoor displays. In Figure 1, a plurality of pixel areas Pi are separated by dotted lines. Within a pixel area Pi, the wiring (e.g., the first fixed potential signal line VGB, the second fixed potential signal line VR, the common potential signal line GND, the first data signal line Data1, the second data signal line Data2, the first power line VCC, the first power connection line VCCL), the connecting line 103, the connecting electrode area 102, and the pad area Pa are opaque areas, and the rest are translucent areas. The area ratio of the opaque area to the translucent area is in the range of 25:75 to 35:65 (e.g., 30:70).

[0070] In an exemplary embodiment, in the row direction X, the fixed potential signal line can be located between two adjacent columns of element groups Z1, and the first data signal line Data1 and the second data signal line Data2 electrically connected to one column of element groups Z1 are located between the common potential signal line GND and the first power line VCC electrically connected to the column of element groups Z1, thereby avoiding obstruction of the element groups and improving the transmittance of the display substrate.

[0071] In an exemplary embodiment, as shown in FIG3 , which is an enlarged schematic diagram of the position of M1 in FIG1 , the element group Z1 may include a light-emitting element LD, the light-emitting element LD may include a first type of light-emitting element LD1 and a second type of light-emitting element LD2, and the fixed potential signal line includes a first fixed potential signal line VGB and a second fixed potential signal line VR, the first fixed potential signal line VGB is electrically connected to the first type of light-emitting element LD1, and the second fixed potential signal line VR is electrically connected to the second type of light-emitting element LD2.

[0072] In an exemplary embodiment, in the row direction X, the size of the common potential signal line GND is larger than the size of the first fixed potential signal line VGB and the first type of signal line, and the size of the second fixed potential signal line VR is smaller than the size of the first fixed potential signal line VGB and the first type of signal line, which can reduce the space occupied by the second fixed potential signal line.

[0073] In an exemplary embodiment, multiple common potential signal lines GND can be electrically connected to multiple element groups Z1 in the multiple columns of element groups, multiple first fixed potential signal lines VGB can be electrically connected to multiple element groups Z1 in the multiple columns of element groups, and multiple second fixed potential signal lines VR can be electrically connected to multiple element groups Z1 in the multiple columns of element groups; alternatively, the common potential signal line GND, the first fixed potential signal line VGB, and the second fixed potential signal line VR can be first-type signal lines, that is, one signal line can provide signals for a row of element groups in the upper half screen and a row of element groups in the lower half screen of the display substrate. Under the premise of improving display uniformity, the number of first-type signal lines can be reduced, thereby improving the transmittance of the display substrate; alternatively, the common potential signal line GND, the first fixed potential signal line VGB, and the second fixed potential signal line VR can be second-type signal lines or third-type signal lines, that is, the second-type signal lines provide signals to the upper half screen of the display substrate, and the third-type signal lines provide signals to the lower half screen of the display substrate. Under the premise of improving display uniformity of the display substrate, the transmittance of the display substrate can be improved. The present disclosure is not limited here.

[0074] In an exemplary embodiment, as shown in Figures 1 to 3, in the row direction X, the size of the common potential signal line GND is larger than the size of the first fixed potential signal line VGB and the first power line VCC, and the size of the second fixed potential signal line VR is smaller than the size of the first fixed potential signal line VGB and the first power line VCC.

[0075] In an exemplary embodiment, the size of the common potential signal line GND may be 1.5 to 3 times the size of the second fixed potential signal line VR in the row direction X. The larger size of the common potential signal line GND in the row direction X can reduce voltage drop, thereby improving display uniformity of the display substrate.

[0076] In an exemplary embodiment, the light emitting assembly Z1 may include a control circuit for controlling the first type light emitting element LD1 and the second type light emitting element LD2. In an exemplary embodiment, the control circuit may be a micro driver chip, or a driver circuit composed of at least two thin film transistors and a capacitor.

[0077] In an exemplary embodiment, the control circuit can be electrically connected to the first type light-emitting element LD1, the second type light-emitting element LD2, the first power line VCC and the common potential signal line GND, and electrically connected to one of the first data signal line Data1 and the second data signal line Data2. Among the signal lines electrically connected to one column element group Z1, in the row direction X, the common potential signal line GND can be located on one side of the control circuit, and the first data signal line Data1 and the second data signal line Data2 can be located on the other side of the control circuit.

[0078] In an exemplary embodiment, as shown in Figure 3, the control circuit in the element group Z1 can be a micro-driving chip 10, and the micro-driving chip 10 can be electrically connected to the first type light-emitting element LD1, the second type light-emitting element LD2, the first power line VCC and the common potential signal line GND. The micro-driving chip 10 can also be electrically connected to one of the first data signal line Data1 and the second data signal line Data2. Among the signal lines electrically connected to one column of the element groups, in the row direction X, the common potential signal line GND can be located on one side of the micro-driving chip 10, and the first data signal line Data1 and the second data signal line Data2 can be located on the other side of the micro-driving chip 10.

[0079] In an exemplary embodiment, as shown in FIG. 1 to FIG. 3 , in the row direction X, among the signal lines electrically connected to one column of element groups, the first data signal line Data1 and the second data signal line Data2 may be located between the common potential signal line GND and the first power line VCC.

[0080] In an exemplary embodiment, as shown in FIG3 , in the row direction X, among the signal lines electrically connected to one column of the component groups, a first distance R1 between the common potential signal line GND and the first data signal line Data1 is greater than a second distance R2 between the common potential signal line GND and the second fixed potential signal line VR, thereby allowing the micro driver chip 10 to be accommodated between the common potential signal line GND and the first data signal line Data1.

[0081] In an exemplary embodiment, in the row direction X, between two adjacent common potential signal lines GND, the first data signal line Data1, the first power line VCC, the first fixed potential signal line VGB, and the second fixed potential signal line VR are arranged in sequence, and the distance between two adjacent signal lines is consistent with the second distance R2. The consistency of the distance between two adjacent signal lines with the second distance R2 can ensure uniform distribution of the signal lines, thereby improving display uniformity.

[0082] In an exemplary embodiment, as shown in Figures 1 to 3, to achieve color display, the first type of light-emitting element LD1 and the second type of light-emitting element LD2 are configured to emit light in different wavelength bands, respectively. The second type of light-emitting element LD2 emits light in a wavelength band of 615nm to 650nm, while the first type of light-emitting element LD1 emits light in a wavelength band of 440nm to 550nm. For example, the second type of light-emitting element LD2 includes only one type of light-emitting element, which is configured to emit red light in the wavelength range of 615nm to 650nm, and its peak wavelength may be 600nm. The first type of light-emitting element LD1 includes two types of light-emitting elements, which are configured to emit blue light in the wavelength range of 440nm to 480nm and green light in the wavelength range of 495nm to 550nm, respectively, and their peak wavelengths may be 450nm and 530nm, respectively.

[0083] In an exemplary embodiment, both the first type of light emitting element LD1 and the second type of light emitting element LD2 can be inorganic light emitting diodes (LEDs). The type of inorganic light emitting diodes is not limited here, and LEDs with quantum well junctions, LEDs with columnar structures, LEDs with double heterojunctions, etc. can be used. The LED can be a structure with a size of hundreds of microns, that is, Mini LED or Micro LED, etc. The area of ​​the light emitting region of the LED can be 1mm 2 Below, or can be 10000μm 2 Below, or can be 3000μm 2 Below, or can be 700μm 2 Below, or can be 200μm 2 the following.

[0084] In an exemplary embodiment, as shown in Figures 3 and 5, Figure 5 is an enlarged schematic diagram of the position M2 in Figure 3, and the first type light-emitting element LD1 and the second type light-emitting element LD2 in the element group Z1 both include a first electrode "+" and a second electrode "-", wherein the first electrode "+" of the first type light-emitting element LD1 is connected to the corresponding first fixed potential signal line VR through a connecting line 103, and the first electrode "+" of the second type light-emitting element LD2 is connected to the corresponding first fixed potential signal line VGB through a connecting line 103, and the second electrode "-" of the first type light-emitting element LD1 and the second type light-emitting element LD2 are both connected to the micro-driving chip 10 through the connecting line 103, and the micro-driving chip 10 is also electrically connected to the common potential signal line GND, the data signal line (the first data signal line Data1 or the second data signal line Data2) and the first power line VCC respectively through the connecting line 103.

[0085] In an exemplary embodiment, as shown in Figures 3 to 5, Figures 3 and 4 are schematic structural diagrams of a pixel area Pi, and Figure 5 is an enlarged structural diagram of the position M2 in Figure 3. The micro-driver chip 10 can be bound and connected to the pad area Pa, and the pad area Pa can be electrically connected to the corresponding signal traces or light-emitting elements through the connecting line 103, so that the micro-driver chip 10 can be electrically connected to the corresponding signal traces and light-emitting elements. For example, as shown in Figure 5, the pad area Pa can include a first pad area Pa1, a second pad area Pa2, a third pad area Pa3, a fourth pad area Pa4, a fifth pad area Pa5, and a sixth pad area Pa6, wherein, in the same pixel area Pi, the first pad area Pa1 can be connected through The connecting line 103 is electrically connected to the second electrode “-” of the second-type light-emitting element LD2, the second pad area Pa2 can be electrically connected to the second electrode “-” of one of the first-type light-emitting elements LD1 through the connecting line 103, the third pad area Pa3 can be electrically connected to the second electrode “-” of another first-type light-emitting element LD1 through the connecting line 103, the fourth pad area Pa4 can be electrically connected to the first data signal line Data1 or the second data signal line Data through the connecting line 103, the fifth pad area Pa5 can be electrically connected to the first power connection line VCCL through the connecting line 103 (refer to Figures 3 and 4), and the sixth pad area Pa6 can be electrically connected to the common potential signal line GND through the connecting line 103.

[0086] In an exemplary embodiment, as shown in Figure 5, the electrode connection area 102 of each light-emitting element LD may include a first electrode "+" connection area 1021 and a second electrode "-" connection area 1022, the first electrode "+" connection area 1021 can connect the first electrode "+" of the corresponding light-emitting element LD and the corresponding routing (for example, the first fixed potential signal line VGB or the second fixed potential signal line VR), and the second electrode "-" connection area 1022 can connect the second electrode "-" of the corresponding light-emitting element LD and the corresponding pad area (for example, one of the first pad area Pa1 to the third pad area Pa3).

[0087] In an exemplary embodiment, the first power line VCC can transmit either a DC signal or a digital signal. The first power line VCC is used to power the connected micro-driver chip 10. The first data signal line Data1 and the second data signal line Data2 transmit digital signals. The micro-driver chip 10 receives the digital signal transmitted by the first data signal line Data1 or the second data signal line Data2 to determine the light-emitting time of each light-emitting element in the driver element group Z1, thereby controlling the brightness of each light-emitting element. The common potential signal line GND transmits a set potential signal, which is used to provide a constant potential. The first electrode "+" of the second-type light-emitting element LD2 is connected to the second fixed potential signal line VR, and the second electrode "-" is connected to the common potential signal line GND through the micro-driver chip 10. The second fixed potential signal line VR is used to provide a second fixed potential. The micro-driver chip 10 can control the conduction and disconnection between the second-type light-emitting element LD2 and the common potential signal line GND, thereby controlling the light-emitting time of the second-type light-emitting element LD2 by controlling the conduction time of the second-type light-emitting element LD2. Similarly, the first electrode "+" of the first-type light-emitting element LD1 is connected to the first fixed potential signal line VGB, and the second electrode "-" is connected to the common potential signal line GND via the micro-driver chip 10. The first fixed potential signal line VGB is used to provide a first fixed potential. The micro-driver chip 10 can control the conduction and disconnection between the first-type light-emitting element LD1 and the common potential signal line GND, thereby controlling the light-emitting duration of the first-type light-emitting element LD1 by controlling the conduction time of the first-type light-emitting element LD1. When the first-type light-emitting element LD1 includes two light-emitting elements, as shown in FIG3, the first electrodes "+" of the two light-emitting elements can be connected to the first fixed potential line VGB respectively. Alternatively, as shown in FIG4, the first electrodes "+" of the two light-emitting elements can be connected and then connected to the first fixed potential line VGB; the second electrodes "-" of the two light-emitting elements are respectively connected to the micro-driver chip 10.

[0088] In some embodiments, as shown in FIG6 , which is a cross-sectional view taken along line BB in FIG5 , the display substrate may include a first conductive layer L1 and a second conductive layer L2. In some embodiments, a first power connection line VCCL may be located in the first conductive layer L1, and a first power line VCC may be located in the second conductive layer L2. The first and second power connection lines VCCL and VCC may be electrically connected via a via that penetrates an insulating layer (e.g., the stacked first inorganic insulating layer PVX1-1, the first organic insulating layer OC1, and the second inorganic insulating layer PVX1-2).

[0089] In an exemplary embodiment, as shown in FIG1 to FIG6 , a display substrate may include a first conductive layer L1 and a second conductive layer L2. A first power line VCC, a first fixed potential signal line VGB, a second fixed potential signal line VR, a common potential signal line GND, a first data signal line Data1, and a second data signal line Data2 may be provided on the first conductive layer L1. A first power connection line VCCL and multiple types of connection lines 103 may be provided on the second conductive layer L2. These connection lines 103 may be used to connect the first fixed potential signal line VGB to the first type of light-emitting element LD1, the second fixed potential signal line VR to the second type of light-emitting element LD2, the first type of light-emitting element LD1 to the micro-driver chip 10, the second type of light-emitting element LD2 to the micro-driver chip 10, the micro-driver chip 10 to the first data signal line Data1 or the second data signal line Data2, and the micro-driver chip 10 to the first power connection line VCCL. In an exemplary embodiment, the connection line 103 for connecting the micro-driver chip 10 to the first power connection line VCCL is integrally provided with the first power connection line VCCL.

[0090] In an exemplary embodiment, the number of columns of the component group Z1 arranged along the row direction X and the number of rows arranged along the column direction Y may be different. For example, when the number of columns of the component group Z1 arranged along the row direction X is greater than the number of rows of the component group Z1 arranged along the column direction Y, only the same number of first power lines VCC as the number of columns of the component group Z1 need to be provided. The first power lines VCC are electrically connected to corresponding first power connection lines VCCL through vias in the insulating layer. When the arrangement of the component group Z1 changes, the via connection method between the first power lines VCC and the first power connection lines VCCL can be adaptively adjusted, which is not limited in the embodiments of the present disclosure.

[0091] In an exemplary embodiment, the number of first power lines VCC and the number of first power connection lines VCCL may be different. For example, the number of first power connection lines VCCL may be twice the number of first power lines VCC. In an exemplary embodiment, the number of rows of the element group Z1 arranged along the column direction Y may be twice the number of columns arranged along the row direction X.

[0092] In an exemplary embodiment, as shown in Figure 6, the display substrate may further include a buffer layer (PVX0) located between the first conductive layer L1 and the base substrate 101. The buffer layer (PVX0) may be made of insulating materials such as silicon nitride to offset the deformation of the base substrate 101 that may be caused during the preparation of the signal lines in the first conductive layer L1. When signal lines are set on both sides of the base substrate 101, the stresses between the corresponding signal lines offset each other and will not cause deformation of the base substrate 101. Therefore, the buffer layer (PVX0) may not be set.

[0093] In an exemplary embodiment, as shown in FIG6 , the display substrate may further include a protective layer (e.g., a stacked third inorganic insulating layer PVX2 and a second organic insulating layer OC2) disposed on the side of the second conductive layer L2 facing away from the base substrate 101. The third inorganic insulating layer may be made of a material such as silicon nitride and directly covers the surface of the second conductive layer L2 facing away from the base substrate 101, thereby providing insulation and protection for the signal lines of the second conductive layer L2. In an exemplary embodiment, the protective layer includes vias that expose the connection electrode region 102 and the pad region Pa bonded to the micro-driver chip 10.

[0094] The embodiment of the present disclosure further provides a display device, comprising at least one display substrate as described in any of the above embodiments, as shown in FIG7 , which is a schematic diagram of a display device of at least one embodiment of the present disclosure. As shown in FIG4 , the present embodiment provides a display device 91, comprising: a display substrate 910. Among them, the display substrate 910 can be a Micro-LED display substrate or a Mini-LED display substrate. The display device 91 can be: a car window glass, a shopping mall cabinet, an augmented reality (AR, Augmented Reality) device, a virtual reality (VR, Virtual Reality) device, or any other product or component with a transparent display function. However, this embodiment is not limited to this.

[0095] In an exemplary embodiment, a display device can be formed by splicing multiple display substrates to achieve a large-screen display. As shown in FIG8 , a display device is formed by splicing four display substrates. The four display substrates form two rows and two columns. The gaps between adjacent columns and between adjacent rows can be processed by splicing exposure, so that the splicing gaps are small or even invisible. In an exemplary embodiment, in a display device formed by splicing multiple display substrates, the driving circuit 200 can be located on both sides of the display device in the column direction Y. As shown in FIG8 , among the four display substrates in two rows and two columns in the display device, (1,1) is the display substrate in the first row and first column, (1,2) is the display substrate in the first row and second column, (2,1) is the display substrate in the second row and first column, and (2,2) is the display substrate in the second row and second column.

[0096] In the display substrate and display device provided by the embodiments of the present disclosure, the first type of signal line in the display substrate is electrically connected to at least two non-adjacent first type connecting lines, which can reduce the number of first type signal lines and thus improve the transmittance of the display substrate.

[0097] The drawings in this disclosure only relate to the structures involved in this disclosure, and other structures may refer to the general design. In the absence of conflict, the embodiments of this disclosure and the features in the embodiments may be combined with each other to obtain new embodiments. It should be understood by those skilled in the art that the technical solutions of this disclosure may be modified or replaced by equivalents without departing from the spirit and scope of the technical solutions of this disclosure, and should be included in the scope of the claims of this disclosure.

Claims

1. A display substrate, comprising: A base substrate and a plurality of component groups, a plurality of first-type signal lines and a plurality of first-type connecting lines arranged on the base substrate, wherein the plurality of component groups are arranged in an array on a plane parallel to the display substrate, the plurality of first-type signal lines extend along a column direction and are arranged at intervals along a row direction, the plurality of first-type connecting lines extend along the row direction and are arranged at intervals along the column direction, and the row direction intersects the column direction; in a direction perpendicular to the plane where the display substrate is located, the first-type signal lines and the first-type connecting lines are located in different conductive layers; The first-type signal line is electrically connected to at least two non-adjacent first-type connection lines, and the first-type connection lines are electrically connected to at least part of the component groups in one row of component groups.

2. The display substrate according to claim 1, wherein: The multiple first-class signal lines and the multiple first-class connecting lines each include at least one, each first-class signal line is electrically connected to one of the first-class connecting lines, the number of the at least one first-class connecting lines is 2M, and in the column direction, the same 2M first-class connecting lines are arranged in sequence along the column direction, and the i-th and M+i-th first-class connecting lines are electrically connected to one of the first-class signal lines, where i is an integer greater than or equal to 1 and less than or equal to M, and M is an integer greater than or equal to 1.

3. The display substrate according to claim 2, wherein: The types of the multiple first-category signal lines include at least first power lines, the types of the multiple first-category connecting lines include at least first power connecting lines, the number of the first power lines is multiple, the number of the first power connecting lines is 2M, and in the column direction, the 2M first power connecting lines are arranged in sequence, and the i-th and M+i-th first power connecting lines are electrically connected to one of the first power lines.

4. The display substrate according to claim 3, wherein: In the row direction, at least one of the first power connection lines is located between two adjacent rows of component groups; in the column direction, at least one of the first power connection lines is located between two adjacent columns of component groups.

5. The display substrate according to claim 3 or 4, wherein: The plurality of component groups form 2M rows, and each first power connection line is configured to be electrically connected to a row of component groups adjacent thereto.

6. The display substrate according to claim 1 further includes a plurality of second-category signal lines and a plurality of third-category signal lines; on a plane parallel to the display substrate, the plurality of second-category signal lines and the plurality of third-category signal lines all extend along the column direction and are arranged at intervals along the row direction; the plurality of element groups form 2M rows, and in one column of element groups, the 1st to Mth row element groups are electrically connected to the second-category signal lines, and the M+1th to 2Mth row element groups are electrically connected to the third-category signal lines.

7. The display substrate according to claim 6 further includes at least one driving circuit, the display substrate includes a display area, the multiple component groups are arranged in the display area, and the driving circuit is arranged on one side of the display area in a direction parallel to the plane where the display substrate is located, and one end of the first type signal line, the second type signal line, and the third type signal line is electrically connected to the corresponding driving circuit, and the other end extends to the display area.

8. The display substrate according to claim 6, wherein: The second type of signal lines includes multiple first data signal lines, and the third type of signal lines includes multiple second data signal lines. In the column direction, the first data signal lines run through the display area, and the second data signal lines extend from the 2Mth row element group to the M+1th row element group in the display area.

9. The display substrate according to claim 8 further includes a plurality of common potential signal lines and a plurality of fixed potential signal lines electrically connected to the plurality of columns of component groups respectively, the plurality of first-type signal lines include a plurality of first power lines, and on a plane parallel to the display substrate, the plurality of common potential signal lines and the plurality of fixed potential signal lines all extend along the column direction and are arranged at intervals along the row direction, and in the row direction, among the signal lines electrically connected to one column of component groups, the fixed potential signal line and the first power line are respectively located on both sides of the common potential signal line, and the orthographic projection of the common potential signal line on the base substrate at least partially overlaps with the orthographic projection of the column of component groups on the base substrate.

10. The display substrate according to claim 9, wherein: The element group includes a first type of light-emitting element and a second type of light-emitting element, and the fixed potential signal line includes a first fixed potential signal line and a second fixed potential signal line, the first fixed potential signal line is electrically connected to the first type of light-emitting element, and the second fixed potential signal line is electrically connected to the second type of light-emitting element.

11. The display substrate according to claim 10, wherein: In the row direction, the common potential signal line is larger than the first fixed potential signal line and the first type signal line, and the second fixed potential signal line is smaller than the first fixed potential signal line and the first type signal line.

12. The display substrate according to claim 11, wherein: In the row direction, a size of the common potential signal line is 1.5 to 3 times a size of the second fixed potential signal line.

13. The display substrate according to claim 10, wherein: The element group also includes a control circuit, which is electrically connected to the first type of light-emitting elements, the second type of light-emitting elements, the first power line and the common potential signal line, and is electrically connected to one of the first data signal line and the second data signal line. Among the signal lines electrically connected to one column of the element groups, in the row direction, the common potential signal line is located on one side of the control circuit, and the first data signal line and the second data signal line are located on the other side of the control circuit.

14. The display substrate according to claim 13, wherein: In the row direction, among the signal lines electrically connected to one column of the element groups, the first data signal line and the second data signal line are located between the common potential signal line and the first power supply line.

15. The display substrate according to claim 14, wherein: In the row direction, among the signal lines electrically connected to one column of element groups, a first distance between the common potential signal line and the first data signal line is greater than a second distance between the common potential signal line and the second fixed potential signal line.

16. The display substrate according to claim 15, wherein: In the row direction, between two adjacent common potential signal lines, the first data signal line, the first power line, the first fixed potential signal line, and the second fixed potential signal line are arranged in sequence, and the distance between two adjacent signal lines is consistent with the second distance.

17. A display device comprising at least one display substrate according to any one of claims 1 to 16.

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