Display substrate and display device

Abstract

A display substrate and a display device, the display substrate comprising a substrate (101), and a second power line (VSS) and at least one second power line (VSSL) disposed on one side of the substrate (101), the substrate comprising a display area (100) and a bezel area (300), the bezel area (300) being located around the display area (100) on a plane parallel to the display substrate, the bezel area (300) being located around the display area (100), the bezel area (300) being located around the display area (100), and the bezel area (300) being located around the display area (100). The second power lines (VSS) are arranged on the frame area (300) and at least located on the two opposite sides of the display area (100); the at least one second power supply connecting line (VSSL) is located in the display area (100), extends to two opposite sides of the display area (100), and is electrically connected with the second power supply line (VSSL) located on at least one side of the display area (100).

Description

Display substrate, display device Technical Field

[0001] The present disclosure relates to, but is not limited to, the field of display technology, and in particular to a display substrate and a display device. Background Art

[0002] Organic Light Emitting Diodes (OLEDs) and Quantum-dot Light Emitting Diodes (QLEDs) are active light-emitting display devices with advantages such as self-luminescence, wide viewing angles, high contrast, low power consumption, extremely fast response times, thinness, flexibility, and low cost. With the continuous advancement of display technology, flexible displays using OLEDs or QLEDs as light-emitting devices and thin-film transistors (TFTs) for signal control have become mainstream products in the display field.

[0003] Summary of the Invention

[0004] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0005] In a first aspect, an embodiment of the present disclosure provides a display substrate, comprising a base and a second power line and at least one second power connection line arranged on one side of the base, wherein the base comprises a display area and a frame area, and on a plane parallel to the display substrate, the frame area is located around the display area, and the second power line is arranged in the frame area and is located at least on two opposite sides of the display area; the at least one second power connection line is located in the display area and extends to two opposite sides of the display area, and is electrically connected to the second power line located on at least one side of the display area.

[0006] In an exemplary embodiment, the display substrate further includes a second power transfer electrode and a second power transfer line located in the border area. On a plane parallel to the display substrate, the second power transfer line is located between the display area and the second power line, and the second power connection line is connected to the second power transfer line. In a direction perpendicular to the plane of the display substrate, the second power transfer electrode is located on a side of the second power connection line and the second power line away from the substrate, and the second power line and the second power transfer line are electrically connected through the second power transfer electrode.

[0007] In an exemplary embodiment, the orthographic projection of the second power transfer electrode on the substrate at least partially overlaps with the orthographic projections of the second power transfer line and the second power line on the substrate, and the second power transfer electrode is electrically connected to the second power line and the second power transfer line respectively through vias.

[0008] In an exemplary embodiment, the border area includes a first border area and a second border area located on both sides of the display area along the second direction, and a third border area and a fourth border area located on both sides of the display area along the first direction. The second border area is provided with at least one drive signal connection line, and the third border area and the fourth border area are respectively provided with at least one drive signal line. The same drive signal lines located in the third border area and the fourth border area are electrically connected through one of the drive signal connection lines. On a plane parallel to the display substrate, the drive signal connection line is located between the second power line and the second power adapter line, and the drive signal line is located between the second power line and the display area. The first direction intersects with the second direction.

[0009] In an exemplary embodiment, the border area further includes a binding area, and on a plane parallel to the display substrate, the binding area is located on one side of the display area, the second power line is located at least in the binding area and on a side of the display area away from the binding area, and the at least one second power connection line extends from the binding area to the display area; the binding area is located in the first border area, and the second power transfer electrode and the second power transfer line are located in the first border area and the second border area.

[0010] In an exemplary embodiment, the display substrate further includes a first power signal supply line. In a direction parallel to the plane of the display substrate, the first power signal supply line is arranged in the border area and is located around the display area. In the first border area or the second border area, the first power signal supply line is located between the second power adapter line and the display area. In the third border area or the fourth border area, the first power signal supply line is located between the drive signal line and the display area.

[0011] In an exemplary embodiment, the display substrate further includes a plurality of first power connection lines and a plurality of first power lines located in the display area, the display area further including a plurality of sub-pixels arranged in an array, the plurality of first power connection lines extending along the first direction and arranged at intervals along the second direction, and the plurality of first power lines extending along the second direction and arranged at intervals along the first direction;

[0012] The two ends of the first power connection line are electrically connected to the first power signal supply lines located at the third frame and the fourth frame, respectively, and the middle part of the first power connection line is electrically connected to at least one row of sub-pixels; in a direction perpendicular to the plane where the display substrate is located, the first power line is located on the side of the first power connection line and the first power signal supply line away from the substrate, the middle part of the first power line is electrically connected to the multiple first power lines, and the two ends are electrically connected to the first power signal supply lines located in the first frame area and the second frame area, respectively.

[0013] In an exemplary embodiment, in the second direction, the first power signal supply line and the second power line are both larger than the second power adapter line.

[0014] In an exemplary embodiment, the display substrate further includes an anode conductive layer and a cathode layer, and in a direction perpendicular to the plane of the display substrate, the cathode layer is located on a side of the anode conductive layer away from the substrate; the second power switching electrode is located in the anode conductive layer, and its orthographic projection on the substrate at least partially overlaps with the orthographic projection of the cathode layer on the substrate, and the second power switching electrode is electrically connected to the cathode layer.

[0015] In an exemplary embodiment, there are multiple second power connection lines, the display area includes a plurality of sub-pixels arranged in an array, the multiple second power connection lines are arranged along a row direction and extend along a column direction, at least one second power connection line is arranged between two adjacent columns of sub-pixels, and on a plane parallel to the display substrate, the row direction and the column direction intersect.

[0016] In an exemplary embodiment, the display area further includes a plurality of initial signal lines and a plurality of initial signal connecting lines, the plurality of initial signal lines being configured to be electrically connected to a plurality of rows of sub-pixels, respectively, and the initial signal connecting lines being configured to be electrically connected to at least some of the initial signal lines; in a direction parallel to the plane where the display substrate is located, the plurality of initial signal lines extend along the row direction and are arranged at intervals along the column direction, the plurality of initial signal connecting lines extend along the column direction and are arranged at intervals along the row direction, and in a direction perpendicular to the plane where the display substrate is located, the plurality of initial signal connecting lines and the plurality of initial signal lines are located on different conductive layers.

[0017] In an exemplary embodiment, the plurality of initial signal lines include a plurality of first initial signal lines and a plurality of second initial signal lines, at least some of the sub-pixels include a plurality of transistors, the plurality of transistors including at least a first transistor and a seventh transistor; the plurality of first initial signal lines are configured to be electrically connected to the first transistors in the plurality of rows of sub-pixels, respectively, and the plurality of second initial signal lines are configured to be electrically connected to the seventh transistors in the plurality of rows of sub-pixels, respectively.

[0018] The multiple initial signal connection lines include multiple first initial signal connection lines and multiple second initial signal connection lines; the first initial signal connection lines are configured to be electrically connected to the multiple first initial signal lines, and the second initial signal connection lines are configured to be electrically connected to the multiple second initial signal lines.

[0019] In an exemplary embodiment, in a direction perpendicular to the plane of the display substrate, the display substrate includes a semiconductor layer, a second conductive layer, a third conductive layer, and a fourth conductive layer sequentially arranged on the base, and the multiple initial signal lines are arranged in one of the film layers of the semiconductor layer, the second conductive layer, and the third conductive layer; the multiple initial signal connection lines are arranged in the fourth conductive layer.

[0020] In an exemplary embodiment, the multiple sub-pixels form a plurality of pixel units arranged in an array, at least some of the pixel units include at least three sub-pixels arranged in sequence along the row direction, and the second power connection line, the first initial signal connection line, and the second initial signal connection line are arranged between two adjacent columns of pixel units.

[0021] In an exemplary embodiment, the second power connection lines, the first initial signal connection lines, and the second initial signal connection lines are periodically arranged along the row direction.

[0022] In an exemplary embodiment, within one cycle, the second power connection line, the first initial signal connection line, and the second initial signal connection line are arranged sequentially along the row direction, R columns of pixel units are spaced between the second power connection line and the first initial signal connection line, R columns of pixel units are spaced between the first initial signal connection line and the second initial signal connection line, and R columns of pixel units are spaced between the second initial signal connection line and the second power connection line in the adjacent cycle, where R is an integer greater than or equal to 1.

[0023] In an exemplary embodiment, one period includes two first initial signal connection lines, two second initial signal connection lines, and one second power connection line. In the row direction, the two first initial signal connection lines and the two second initial signal connection lines are located on both sides of the second power connection line. On the same side of the second power connection line, the first initial signal connection line and the second initial signal connection line are arranged sequentially along the row direction.

[0024] In the same cycle, there are R columns of pixel units between the first initial signal connection line and the adjacent second initial signal connection line, and there are R columns of pixel units between the second power connection line and the adjacent first initial signal connection line and the second initial signal connection line, where R is an integer greater than or equal to 1.

[0025] In an exemplary embodiment, the display substrate further includes a shielding layer and a circuit structure layer disposed on the base, and the shielding layer is located between the base and the circuit structure layer in a direction perpendicular to the plane of the display substrate.

[0026] In an exemplary embodiment, the display area is provided with a plurality of sub-pixels, at least some of the sub-pixels include first to seventh transistors located in the circuit structure layer and at least one blocking structure located in the blocking layer, and in the same sub-pixel, each of the blocking structures is configured to block the channel region of at least one transistor among the first to seventh transistors.

[0027] In an exemplary embodiment, in the same sub-pixel, the blocking layer includes one or more of the first to seventh blocking structures, wherein the orthographic projection of the first blocking structure on the substrate at least partially overlaps with the orthographic projection of the first transistor on the substrate; the orthographic projection of the second blocking structure on the substrate at least partially overlaps with the orthographic projection of the second transistor on the substrate; the orthographic projection of the third blocking structure on the substrate at least partially overlaps with the orthographic projection of the third transistor on the substrate; the orthographic projection of the fourth blocking structure on the substrate at least partially overlaps with the orthographic projection of the fourth transistor on the substrate; the orthographic projection of the fifth blocking structure on the substrate at least partially overlaps with the orthographic projection of the fifth transistor on the substrate; the orthographic projection of the sixth blocking structure on the substrate at least partially overlaps with the orthographic projection of the sixth transistor on the substrate; and the orthographic projection of the seventh blocking structure on the substrate at least partially overlaps with the orthographic projection of the seventh transistor on the substrate.

[0028] In an exemplary embodiment, the multiple sub-pixels form multiple sub-pixel rows, the blocking layer includes a second blocking structure and a fourth blocking structure, and in the same sub-pixel row, the second blocking structure located in one of the sub-pixels and the fourth blocking structure located in the adjacent sub-pixel are an integrally formed structure.

[0029] In an exemplary embodiment, the multiple sub-pixels form multiple sub-pixel rows, the blocking layer includes a third blocking structure, and in the same sub-pixel row, in the row direction, the distance between the two third blocking structures located in two adjacent sub-pixels is greater than the size of the channel region of the fourth transistor.

[0030] In an exemplary embodiment, the shielding structure in the shielding layer in the same sub-pixel is an integrated structure; and the shielding layers of the plurality of sub-pixels are interconnected to form an integrated structure.

[0031] In an exemplary embodiment, the display substrate further includes a first power signal supply line, which is arranged in the border area and located on the periphery of the display area. In a direction perpendicular to the plane where the display substrate is located, the first power signal supply line is located on the side of the shielding layer away from the substrate, and the shielding layer of multiple sub-pixels located on the side of the display area close to the border area is electrically connected to the first power signal supply line.

[0032] In an exemplary embodiment, the display substrate further includes a shielding transfer line, which is located at least on both sides of a set of opposite sides of the display area. On a plane parallel to the display substrate, the shielding transfer line is located between the second power line and the display area. The shielding layer of multiple sub-pixels located on the side of the display area close to the border area is connected to the shielding transfer line. The first power signal supply line is electrically connected to the shielding transfer line through a via, and the orthographic projection of the first power signal supply line on the substrate at least partially overlaps with the orthographic projection of the shielding transfer line on the substrate.

[0033] In a second aspect, an embodiment of the present disclosure further provides a display device, comprising the display substrate described in any of the above embodiments.

[0034] Still other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] The accompanying drawings are intended to provide a further understanding of the technical solutions of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solutions of the present disclosure and do not constitute a limitation of the technical solutions of the present disclosure. The shapes and sizes of each component in the drawings do not reflect the actual scale and are intended only to illustrate the contents of the present disclosure.

[0036] FIG1 is a schematic structural diagram of a display device;

[0037] FIG2 is a schematic diagram of a planar structure of a display substrate;

[0038] FIG3 is a schematic diagram of a cross-sectional structure of a display substrate;

[0039] FIG4 is a schematic diagram of an equivalent circuit of a pixel driving circuit;

[0040] FIG5 a is a schematic plan view of a display substrate provided by an exemplary embodiment of the present disclosure;

[0041] FIG5 b is a schematic plan view of a display substrate provided by an exemplary embodiment of the present disclosure;

[0042] FIG5 c is a schematic plan view of a display substrate provided by an exemplary embodiment of the present disclosure;

[0043] FIG5 d is a schematic plan view of a display substrate provided by an exemplary embodiment of the present disclosure;

[0044] FIG6 a is a schematic structural diagram of a display substrate provided by an exemplary embodiment of the present disclosure;

[0045] FIG6 b is a schematic structural diagram of a display substrate provided by an exemplary embodiment of the present disclosure;

[0046] FIG6 c is a schematic structural diagram of a display substrate provided by an exemplary embodiment of the present disclosure;

[0047] FIG6 d is a schematic structural diagram of a display substrate provided by an exemplary embodiment of the present disclosure;

[0048] FIG7 a is a schematic structural diagram of a display substrate provided by an exemplary embodiment of the present disclosure;

[0049] FIG7 b is a schematic structural diagram of a display substrate provided by an exemplary embodiment of the present disclosure;

[0050] FIG7 c is a schematic structural diagram of a display substrate provided by an exemplary embodiment of the present disclosure;

[0051] FIG7 d is a schematic structural diagram of a display substrate provided by an exemplary embodiment of the present disclosure;

[0052] FIG7e is a schematic structural diagram of a display substrate provided by an exemplary embodiment of the present disclosure;

[0053] FIG8 a is a schematic plan view of a display substrate provided by an exemplary embodiment of the present disclosure;

[0054] FIG8b is a plan view schematically showing the shielding layer in FIG8a;

[0055] FIG8 c is a schematic cross-sectional view of a display substrate provided by an exemplary embodiment of the present disclosure;

[0056] FIG9 is a schematic diagram showing a display substrate provided by an exemplary embodiment of the present disclosure after a shielding layer pattern is formed;

[0057] FIG10 a is a schematic diagram showing a display substrate provided by an exemplary embodiment of the present disclosure after a semiconductor layer pattern is formed;

[0058] FIG10 b is a schematic diagram showing a semiconductor layer in a display substrate provided by an exemplary embodiment of the present disclosure;

[0059] FIG10c is a schematic diagram showing a semiconductor layer in a display substrate provided by an exemplary embodiment of the present disclosure;

[0060] FIG11a is a schematic diagram showing a display substrate provided by an exemplary embodiment of the present disclosure after a first conductive layer pattern is formed;

[0061] FIG11 b is a schematic diagram of a first conductive layer in a display substrate provided by an exemplary embodiment of the present disclosure;

[0062] FIG12a is a schematic diagram showing a display substrate provided by an exemplary embodiment of the present disclosure after a second conductive layer pattern is formed;

[0063] FIG12 b is a schematic diagram showing a second conductive layer in a display substrate provided by an exemplary embodiment of the present disclosure;

[0064] FIG13 is a schematic diagram showing a display substrate provided by an exemplary embodiment of the present disclosure after a fourth insulating layer pattern is formed;

[0065] FIG14a is a schematic diagram showing a display substrate provided by an exemplary embodiment of the present disclosure after a third conductive layer pattern is formed;

[0066] FIG14 b is a schematic diagram showing a third conductive layer in a display substrate provided by an exemplary embodiment of the present disclosure;

[0067] FIG14c is a schematic diagram showing a third conductive layer in a display substrate provided by an exemplary embodiment of the present disclosure;

[0068] FIG15 is a schematic diagram showing a display substrate provided by an exemplary embodiment of the present disclosure after a first planarization layer pattern is formed;

[0069] FIG16a is a schematic diagram showing a display substrate provided by an exemplary embodiment of the present disclosure after a fourth conductive layer pattern is formed;

[0070] FIG16 b is a schematic diagram showing a fourth conductive layer in a display substrate provided by an exemplary embodiment of the present disclosure;

[0071] FIG16c is a schematic diagram showing a display substrate provided by an exemplary embodiment of the present disclosure after a fourth conductive layer pattern is formed;

[0072] FIG16d is a schematic diagram showing a fourth conductive layer in a display substrate provided by an exemplary embodiment of the present disclosure;

[0073] FIG16e is a schematic diagram showing a display substrate provided by an exemplary embodiment of the present disclosure after a fourth conductive layer pattern is formed;

[0074] FIG17 is a schematic diagram showing a second planarization layer pattern formed according to an exemplary embodiment of the present disclosure;

[0075] FIG18 is a schematic diagram showing a display substrate provided by an exemplary embodiment of the present disclosure after an anode conductive layer pattern is formed;

[0076] FIG19 is a schematic diagram showing a display substrate provided by an exemplary embodiment of the present disclosure after a pixel definition layer pattern is formed;

[0077] FIG20 is a schematic diagram showing a third conductive layer in a display substrate provided by an exemplary embodiment of the present disclosure;

[0078] FIG21 is a schematic diagram showing a third conductive layer in a display substrate provided by an exemplary embodiment of the present disclosure;

[0079] FIG22 is a schematic diagram showing a display substrate provided by an exemplary embodiment of the present disclosure after a shielding layer pattern is formed;

[0080] FIG23a is a schematic diagram showing a display substrate provided by an exemplary embodiment of the present disclosure after a semiconductor layer pattern is formed;

[0081] FIG23 b is a schematic diagram showing a semiconductor layer in a display substrate provided by an exemplary embodiment of the present disclosure;

[0082] FIG24 a is a schematic diagram showing a display substrate provided by an exemplary embodiment of the present disclosure after a first conductive layer pattern is formed;

[0083] FIG24 b is a schematic diagram showing a first conductive layer in a display substrate provided by an exemplary embodiment of the present disclosure;

[0084] FIG25 a is a schematic diagram showing a display substrate provided by an exemplary embodiment of the present disclosure after a second conductive layer pattern is formed;

[0085] FIG25 b is a schematic diagram showing a second conductive layer in a display substrate provided by an exemplary embodiment of the present disclosure;

[0086] FIG26 is a schematic diagram showing a display substrate provided by an exemplary embodiment of the present disclosure after a fourth insulating layer pattern is formed;

[0087] FIG27 a is a schematic diagram showing a display substrate provided by an exemplary embodiment of the present disclosure after a third conductive layer pattern is formed;

[0088] FIG27 b is a schematic diagram showing a third conductive layer in a display substrate provided by an exemplary embodiment of the present disclosure;

[0089] FIG28 is a schematic diagram showing a display substrate provided by an exemplary embodiment of the present disclosure after a first planarization layer pattern is formed;

[0090] FIG29 a is a schematic diagram showing a display substrate provided by an exemplary embodiment of the present disclosure after a fourth conductive layer pattern is formed;

[0091] FIG29 b is a schematic diagram showing a fourth conductive layer in a display substrate provided by an exemplary embodiment of the present disclosure. DETAILED DESCRIPTION

[0092] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. The embodiments can be implemented in a number of different forms. A person of ordinary skill in the art can easily understand the fact that the methods and contents can be transformed into various forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. Unless there is a conflict, the embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined with each other. In order to keep the following description of the embodiments of the present disclosure clear and concise, the present disclosure omits detailed descriptions of some known functions and known components. The drawings of the embodiments of the present disclosure only involve structures related to the embodiments of the present disclosure. Other structures can refer to the general design

[0093] The scales of the figures in this disclosure are intended to serve as a reference for actual processes, but are not intended to be limiting. For example, the thickness and spacing of each film layer, and the width and spacing of each signal line, can be adjusted based on actual conditions. The figures described in this disclosure are merely schematic diagrams of the structures, and one embodiment of this disclosure is not limited to the shapes or values ​​shown in the figures.

[0094] In this specification, ordinal numbers such as “first”, “second” and “third” are provided to avoid confusion among constituent elements, and are not intended to limit the number.

[0095] In this specification, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of constituent elements with reference to the accompanying drawings. This is merely for the purpose of facilitating the description of this specification and simplifying the description, and is not intended to indicate or imply that the device or element referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limitations on the present disclosure. The positional relationships of constituent elements may be appropriately changed depending on the direction in which each constituent element is described. Therefore, the present disclosure is not limited to the words and phrases described in the specification and may be appropriately replaced depending on the circumstances.

[0096] In this specification, unless otherwise specified or limited, the terms "mounted," "connected," and "connected" should be understood broadly. For example, they can refer to fixed, removable, or integral connections; mechanical or electrical connections; direct connections, indirect connections through intermediaries, or internal communication between two components. Those skilled in the art will understand the specific meanings of these terms in this disclosure.

[0097] In this specification, a transistor refers to a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0098] In this specification, the first electrode can be a drain electrode and the second electrode can be a source electrode, or the first electrode can be a source electrode and the second electrode can be a drain electrode. In cases where transistors with opposite polarities are used or the direction of current changes during circuit operation, the functions of the "source electrode" and "drain electrode" are sometimes interchangeable. Therefore, in this specification, "source electrode" and "drain electrode" can be interchangeable, and "source terminal" and "drain terminal" can be interchangeable. In the disclosed embodiments, the gate electrode can be referred to as the control electrode.

[0099] In this specification, "electrically connected" includes components connected together via an element having some electrical function. There are no particular limitations on the "element having some electrical function" as long as it enables the transfer of electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0100] In this specification, "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°, and thus also includes a state where the angle is greater than -5° and less than 5°. Furthermore, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°, and thus also includes a state where the angle is greater than 85° and less than 95°.

[0101] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced with "conductive film." Similarly, "insulating film" may be replaced with "insulating layer."

[0102] The triangles, rectangles, trapezoids, pentagons or hexagons in this specification are not in the strict sense, but may be approximate triangles, rectangles, trapezoids, pentagons or hexagons, etc. There may be some small deformations caused by tolerances, and there may be chamfers, arc edges and deformations.

[0103] The term "about" in the embodiments of the present disclosure does not strictly define the limits and allows for numerical values ​​within the range of process and measurement errors.

[0104] FIG1 is a schematic diagram of the structure of a display device. As shown in FIG1 , the display device may include a timing controller, a data driver, a scan driver, a light-emitting driver, and a pixel array. The timing controller is respectively connected to the data driver, the scan driver, and the light-emitting driver. The data driver is respectively connected to a plurality of data signal lines (D1 to Dn). The scan driver is respectively connected to a plurality of scan signal lines (S1 to Sm). The light-emitting driver is respectively connected to a plurality of light-emitting signal lines (E1 to Eo). The pixel array may include a plurality of sub-pixels Pxij, where i and j may be natural numbers. At least one sub-pixel Pxij may include a circuit unit and a light-emitting unit connected to the circuit unit. The circuit unit may include a pixel driving circuit, and the pixel driving circuit may be respectively connected to the scan signal lines, the data signal lines, and the light-emitting signal lines. In an exemplary embodiment, the timing controller may provide grayscale values ​​and control signals suitable for the specifications of the data driver to the data driver, may provide clock signals, scan start signals, etc. suitable for the specifications of the scan driver to the scan driver, and may provide clock signals, emission stop signals, etc. suitable for the specifications of the light-emitting driver to the light-emitting driver. The data driver can generate data voltages to be supplied to data signal lines D1, D2, D3, ..., and Dn using grayscale values ​​and control signals received from a timing controller. For example, the data driver can sample grayscale values ​​using a clock signal and apply data voltages corresponding to the grayscale values ​​to data signal lines D1 to Dn on a pixel row basis, where n can be a natural number. The scan driver can generate scan signals to be supplied to scan signal lines S1, S2, S3, ..., and Sm by receiving clock signals, scan start signals, and the like from the timing controller. For example, the scan driver can sequentially supply scan signals having on-level pulses to scan signal lines S1 to Sm. For example, the scan driver can be configured as a shift register and can generate scan signals by sequentially transmitting scan start signals provided in the form of on-level pulses to the next stage circuit under the control of a clock signal, where m can be a natural number. The light driver can generate emission signals to be supplied to light signal lines E1, E2, E3, ..., and Eo by receiving clock signals, emission stop signals, and the like from the timing controller. For example, the light emitting driver may sequentially provide an emission signal having an off-level pulse to the light emitting signal lines E1 to Eo. For example, the light emitting driver may be configured in the form of a shift register and may generate an emission signal in a manner such that an emission stop signal provided in the form of an off-level pulse is sequentially transmitted to a next-stage circuit under the control of a clock signal. o may be a natural number.

[0105] Figure 2 is a schematic diagram of a planar structure of a display substrate. In an exemplary embodiment, the display substrate may include a plurality of pixel units P arranged in a matrix. At least one pixel unit P may include a first sub-pixel P1 emitting a first color light, a second sub-pixel P2 emitting a second color light, and a third sub-pixel P3 emitting a third color light. Each of the three sub-pixels may include a circuit unit and a light-emitting unit. The circuit unit may include a pixel driving circuit, which is respectively connected to a scan signal line, a data signal line, and a light-emitting signal line. The pixel driving circuit is configured to receive a data voltage transmitted by the data signal line under the control of the scan signal line and the light-emitting signal line, and output a corresponding current to the light-emitting unit. The light-emitting unit is configured to emit light of a corresponding brightness in response to the current output by the connected pixel driving circuit.

[0106] In an exemplary embodiment, the first subpixel P1 may be a red subpixel (R) that emits red light, the second subpixel P2 may be a blue subpixel (B) that emits blue light, and the third subpixel P3 may be a green subpixel (G) that emits green light. In an exemplary embodiment, the subpixels may be rectangular, diamond, pentagonal, or hexagonal, and the three subpixels may be arranged horizontally, vertically, or in a herringbone pattern.

[0107] In another exemplary embodiment, the pixel unit P may include four sub-pixels, and the four sub-pixels may be arranged in a horizontal parallel arrangement, a vertical parallel arrangement, a diamond shape, a square shape, etc., which is not limited in the present disclosure.

[0108] Figure 3 is a schematic cross-sectional view of a display substrate, illustrating the structure of three sub-pixels on the display substrate. As shown in Figure 3, in a plane perpendicular to the display substrate, the display substrate may include a drive circuit layer 102 disposed on a base 101, a light-emitting structure layer 103 disposed on a side of the drive circuit layer 102 away from the base, and an encapsulation structure layer 104 disposed on a side of the light-emitting structure layer 103 away from the base. In some possible implementations, the display substrate may include other film layers, such as spacers, etc., which are not limited in this disclosure.

[0109] In an exemplary embodiment, the substrate 101 may be a flexible substrate or a rigid substrate. The driving circuit layer 102 (which may be referred to as a circuit structure layer) of each sub-pixel may include a plurality of circuit units, and the circuit unit may include a pixel driving circuit composed of a plurality of transistors and a storage capacitor. FIG3 only illustrates the pixel driving circuit as comprising a driving transistor and a storage capacitor. The light-emitting structure layer 103 of each sub-pixel may include a plurality of light-emitting units, and the light-emitting unit may include an anode, a pixel definition layer, an organic light-emitting layer and a cathode. The anode is connected to the drain electrode of the driving transistor through a via, the organic light-emitting layer is connected to the anode, and the cathode is connected to the organic light-emitting layer. The organic light-emitting layer emits light of corresponding colors under the drive of the anode and the cathode. The encapsulation structure layer 104 may include a first encapsulation layer, a second encapsulation layer and a third encapsulation layer stacked together. The first encapsulation layer and the third encapsulation layer may be made of inorganic materials, and the second encapsulation layer may be made of organic materials. The second encapsulation layer is arranged between the first encapsulation layer and the third encapsulation layer to ensure that external water vapor cannot enter the light-emitting structure layer 103.

[0110] In an exemplary embodiment, the organic light-emitting layer may include an emissive layer (EML), and any one or more of the following: a hole injection layer (HIL), a hole transport layer (HTL), an electron blocking layer (EBL), a hole blocking layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL). In an exemplary embodiment, the hole injection layer, electron injection layer, hole transport layer, electron transport layer, hole blocking layer, and electron blocking layer of all light-emitting units may be a common layer connected together, and the light-emitting layers of adjacent light-emitting units may have a small amount of overlap or may be isolated.

[0111] FIG4 is a schematic diagram of an equivalent circuit of a pixel driving circuit. In an exemplary embodiment, the pixel driving circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, or 8T1C structure. As shown in FIG4 , the pixel driving circuit may include seven transistors (a first transistor T1 to a seventh transistor T7) and a storage capacitor C. The pixel driving circuit is connected to nine signal lines (a data signal line D, a scan signal line Gate, a first reset control line Reset1, a second reset control line Reset2, a light emitting signal line E, a first initial signal line Vinit1, a second initial signal line Vinit2, a first power line VDD, and a second power line VSS).

[0112] In an exemplary embodiment, the pixel driving circuit may include a first node N1, a second node N2, a third node N3, and a fourth node N4. The first node N1 is connected to the first electrode of the third transistor T3, the second electrode of the fourth transistor T4, and the second electrode of the fifth transistor T5, respectively. The second node N2 is connected to the second electrode of the first transistor, the first electrode of the second transistor T2, the control electrode of the third transistor T3, and the second end of the storage capacitor C, respectively. The third node N3 is connected to the second electrode of the second transistor T2, the second electrode of the third transistor T3, and the first electrode of the sixth transistor T6, respectively. The fourth node N4 is connected to the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7, respectively.

[0113] In an exemplary embodiment, a first end of the storage capacitor C is connected to the first power line VDD, and a second end of the storage capacitor C is connected to the second node N2 , ie, the second end of the storage capacitor C is connected to the control electrode of the third transistor T3 .

[0114] The control electrode of the first transistor T1 is connected to the first reset control line Reset1, the first electrode of the first transistor T1 is connected to the initialization signal line Vinit1, and the second electrode of the first transistor is connected to the second node N2. When the on-level scanning signal is applied to the first reset control line Reset1, the first transistor T1 transmits the initialization voltage to the control electrode of the third transistor T3, thereby initializing the charge amount of the control electrode of the third transistor T3.

[0115] The control electrode of the second transistor T2 is connected to the scan signal line Gate, the first electrode of the second transistor T2 is connected to the second node N2, and the second electrode of the second transistor T2 is connected to the third node N3. When an on-level scan signal is applied to the scan signal line Gate, the second transistor T2 connects the control electrode of the third transistor T3 to the second electrode.

[0116] The control electrode of the third transistor T3 is connected to the second node N2, that is, the control electrode of the third transistor T3 is connected to the second end of the storage capacitor C. The first electrode of the third transistor T3 is connected to the first node N1, and the second electrode of the third transistor T3 is connected to the third node N3. The third transistor T3 can be called a driving transistor. The third transistor T3 determines the amount of driving current flowing between the first power line VDD and the second power line VSS based on the potential difference between the control electrode and the first electrode.

[0117] The control electrode of the fourth transistor T4 is connected to the scan signal line Gate, the first electrode of the fourth transistor T4 is connected to the data signal line D, and the second electrode of the fourth transistor T4 is connected to the first node N1. The fourth transistor T4 can be called a switching transistor, a scan transistor, etc. When an on-level scan signal is applied to the scan signal line Gate, the fourth transistor T4 inputs the data voltage of the data signal line D to the pixel driving circuit.

[0118] The control electrode of the fifth transistor T5 is connected to the light-emitting signal line E, the first electrode of the fifth transistor T5 is connected to the first power line VDD, and the second electrode of the fifth transistor T5 is connected to the first node N1. The control electrode of the sixth transistor T6 is connected to the light-emitting signal line E, the first electrode of the sixth transistor T6 is connected to the third node N3, and the second electrode of the sixth transistor T6 is connected to the first electrode of the light-emitting device EL. The fifth transistor T5 and the sixth transistor T6 can be referred to as light-emitting transistors. When an on-level light-emitting signal is applied to the light-emitting signal line E, the fifth transistor T5 and the sixth transistor T6 form a drive current path between the first power line VDD and the second power line VSS, thereby causing the light-emitting device EL to emit light.

[0119] The control electrode of the seventh transistor T7 is connected to the second reset control line Reset2, the first electrode of the seventh transistor T7 is connected to the second initialization signal line Vinit2, and the second electrode of the seventh transistor T7 is connected to the first electrode of the light-emitting device EL. When the on-level scan signal is applied to the second reset control line Reset2, the seventh transistor T7 transmits an initialization voltage to the first electrode of the light-emitting device EL to initialize or release the charge accumulated in the first electrode of the light-emitting device EL.

[0120] In an exemplary embodiment, the light-emitting device EL can be an OLED, including a stacked first electrode (anode), an organic light-emitting layer and a second electrode (cathode), or can be a QLED, including a stacked first electrode (anode), a quantum dot light-emitting layer and a second electrode (cathode).

[0121] In an exemplary embodiment, the second electrode of the light emitting device EL is connected to the second power line VSS, the signal of the second power line VSS is a continuously provided low level signal, and the signal of the first power line VDD is a continuously provided high level signal.

[0122] In an exemplary embodiment, the first transistor T1 to the seventh transistor T7 may be a P-type transistor or an N-type transistor. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the manufacturing difficulty of the display panel, and improve the product yield. In some possible implementations, the first transistor T1 to the seventh transistor T7 may include P-type transistors and N-type transistors.

[0123] In an exemplary embodiment, the first transistor T1 to the seventh transistor T7 may be low-temperature polysilicon thin-film transistors, or oxide thin-film transistors, or both. The active layer of the low-temperature polysilicon thin-film transistor is made of low-temperature polysilicon (LTPS), and the active layer of the oxide thin-film transistor is made of oxide semiconductor (Oxide). Low-temperature polysilicon thin-film transistors have advantages such as high mobility and fast charging, while oxide thin-film transistors have advantages such as low leakage current. Integrating low-temperature polysilicon thin-film transistors and oxide thin-film transistors on a display substrate to form a low-temperature polycrystalline oxide (LTPO) display substrate can leverage the advantages of both, enabling low-frequency driving, reducing power consumption, and improving display quality.

[0124] In an exemplary embodiment, taking the seven transistors in the pixel driving circuit of FIG. 4 as P-type transistors OLED as an example, the operation process of the pixel driving circuit may include:

[0125] The first phase A1 is called the reset phase. The signal on the first reset control line Reset1 is a low-level signal, while the signals on the scanning signal line Gate and the light-emitting signal line E are high-level signals. The low-level signal on the first reset control line Reset1 turns on the first transistor T1. The signal on the initialization signal line INIT is supplied to the second node N2, initializing the storage capacitor C and clearing the existing data voltage in the storage capacitor. The high-level signals on the scanning signal line Gate, the second reset control line Reset2, and the light-emitting signal line E turn off the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7. During this phase, the OLED does not emit light.

[0126] In the second phase A2, also known as the data writing phase or threshold compensation phase, the signals on the scan signal line Gate and the second reset control line Reset2 are low-level signals, the signals on the first reset control line Reset1 and the light-emitting signal line E are high-level signals, and the data signal line D outputs a data voltage. During this phase, since the second end of the storage capacitor C is at a low level, the third transistor T3 is turned on. The low-level signals on the scan signal line Gate and the second reset control line Reset2 turn on the second transistor T2, the fourth transistor T4, and the seventh transistor T7. The conduction of the second transistor T2 and the fourth transistor T4 causes the data voltage output by the data signal line D to be supplied to the second node N2 via the first node N1, the turned-on third transistor T3, the third node N3, and the turned-on second transistor T2. The difference between the data voltage output by the data signal line D and the threshold voltage of the third transistor T3 is then charged into the storage capacitor C. The voltage at the second end of the storage capacitor C (the second node N2) is Vd-|Vth|, where Vd is the data voltage output by the data signal line D and Vth is the threshold voltage of the third transistor T3. When the seventh transistor T7 is turned on, the initial voltage of the initialization signal line INIT is supplied to the first electrode of the OLED, initializing (resetting) the first electrode of the OLED and clearing the pre-stored voltage within it. This completes the initialization and ensures that the OLED does not emit light. The signal of the first reset control line Reset1 is high, turning off the first transistor T1. The signal of the light-emitting signal line E is high, turning off the fifth transistor T5 and the sixth transistor T6.

[0127] In the third phase A3, known as the light-emitting phase, the signal on the light-emitting signal line E is a low-level signal, while the signals on the scanning signal line Gate, the second reset control line Reset2, and the first reset control line Reset1 are high-level signals. The low-level signal on the light-emitting signal line E turns on the fifth transistor T5 and the sixth transistor T6. The power supply voltage output from the first power supply line VDD provides a driving voltage to the first electrode of the OLED through the turned-on fifth transistor T5, the third transistor T3, and the sixth transistor T6, driving the OLED to emit light.

[0128] During the driving process of the pixel driving circuit, the driving current flowing through the third transistor T3 (driving transistor) is determined by the voltage difference between its gate electrode and the first electrode. Since the voltage of the second node N2 is Vd-|Vth|, the driving current of the third transistor T3 is: I=K*(Vgs-Vth) 2 =K*[(Vdd-Vd+|Vth|)-Vth] 2 =K*[(Vdd-Vd)] 2

[0129] Wherein, I is the driving current flowing through the third transistor T3, that is, the driving current driving the OLED, K is a constant, Vgs is the voltage difference between the gate electrode and the first electrode of the third transistor T3, Vth is the threshold voltage of the third transistor T3, Vd is the data voltage output by the data signal line D, and Vdd is the power supply voltage output by the first power supply line VDD.

[0130] With the development of OLED display technology, the size of display products has also increased. Since the signal lines in large-size display products are relatively long, the voltage drop on the signal lines is large, resulting in inconsistent signals provided by the signal lines to different areas of the display product, causing the display product to have poor display uniformity.

[0131] An exemplary embodiment of the present disclosure provides a display substrate, which may include a base and a second power line and at least one second power connection line arranged on one side of the base. The base may include a display area and a frame area. On a plane parallel to the display substrate, the frame area is located around the display area. The second power line is arranged in the frame area and is located at least on two opposite sides of the display area. The at least one second power connection line is located in the display area and extends to two opposite sides of the display area, and is electrically connected to the second power line located on at least one side of the display area.

[0132] In the display substrate provided by the embodiment of the present disclosure, at least one second power connection line is located in the display area and extends to two opposite sides of the display area, and is electrically connected to the second power line located on at least one side of the display area. This can reduce the voltage drop of the second power line, making the second power signals at different positions on the second power line as consistent as possible, thereby improving display uniformity.

[0133] In an exemplary embodiment, the solution provided by the embodiment of the present disclosure can be applied to display panels of larger sizes, and can improve the display uniformity of large-size display panels. The solution provided by the embodiment of the present disclosure is not limited to large-size display panels, for example, it can be applied to small and medium-sized display panels.

[0134] As shown in Figures 5a and 5b, the display substrate may include a base and a second power line VSS and at least one second power connection line VSSL located on one side of the base. The base may include a display area 100 and a frame area 300. On a plane parallel to the display substrate, the frame area 300 is located around the display area 100. The second power line VSS is arranged in the frame area 300 and is located at least on two opposite sides of the display area 100. The at least one second power connection line VSSL may be located in the display area 100 and extend to two opposite sides of the display area 100, and be electrically connected to the second power line VSSL located on at least one side of the display area 100.

[0135] In an exemplary embodiment, the second power connection line VSSL may include a plurality of second power connection lines VSSL, and the plurality of second power connection lines VSSL may be arranged at intervals along the first direction X. In the display substrate structure shown in FIG5 a and FIG5 b , since the second power line VSS is arranged around the periphery of the display area 100, when the display substrate is relatively large, the length of the second power line VSS is long, resulting in a voltage drop on the second power line VSS. The signals of the second power line VSS received by different areas of the display substrate may differ to a certain extent, resulting in a decrease in the display uniformity of the display substrate. In the solution provided by the embodiment of the present disclosure, the second power lines VSS located on at least one side of the display area 100 are electrically connected through the second power connection lines VSSL. The second power lines VSS and the second power connection lines VSSL form a grid, which can reduce the voltage drop on the second power line VSS, thereby improving the display uniformity of the display substrate.

[0136] In an exemplary embodiment, as shown in Figures 5a to 5d, the display substrate may further include a second power transfer electrode VSSZ2 and a second power transfer line VSSZ1 located in the border area 300. In a plane parallel to the display substrate, the second power transfer line VSSZ1 is located between the display area 100 and the second power line VSS. The second power connection line VSSL has two ends connected to the second power transfer lines VSSZ1 located on opposite sides of the display area 100. In a direction perpendicular to the plane of the display substrate, the second power transfer electrode VSSZ2 may be located on a side of the second power connection line VSSL and the second power line VSS away from the substrate. The second power line VSS and the second power transfer line VSSZ1 may be electrically connected via the second power transfer electrode VSSZ2. Figure 5c shows a schematic diagram of the second power transfer electrode VSSZ2 formed based on Figure 5a, and Figure 5d shows a schematic diagram of the second power transfer electrode VSSZ2 formed based on Figure 5b.

[0137] In an exemplary embodiment, as shown in Figures 5c and 5d, the orthographic projection of the second power transfer electrode VSSZ2 on the substrate at least partially overlaps with the orthographic projections of the second power transfer line VSSZ1 and the second power line VSS on the substrate, and the second power transfer electrode VSSZ2 is electrically connected to the second power line VSS and the second power transfer line VSSZ1 through vias, respectively.

[0138] In an exemplary embodiment, as shown in Figures 5a to 5d, the border area 300 may include a first border area B1 and a second border area B2 located on both sides of the display area 100 along the second direction Y, and a third border area B3 and a fourth border area B4 located on both sides of the display area 100 along the first direction X. The second border area B2 is provided with at least one drive signal connection line GOAL, and the third border area B3 and the fourth border area B4 are respectively provided with at least one drive signal line GOAL0. The same drive signal lines GOAL0 located in the third border area B3 and the fourth border area B4 are electrically connected through one of the drive signal connection lines GOAL. On a plane parallel to the display substrate, the drive signal connection line GOAL can be located between the second power line VSS and the second power adapter line VSSZ1, and the drive signal line GOAL0 can be located between the second power line VSS and the display area 100. The first direction X intersects with the second direction Y.

[0139] In an exemplary embodiment, the disclosed embodiment electrically connects the same drive signal lines GOAL0 located in the third border area 300 and the fourth border area 300 via one of the drive signal connection lines GOAL. This allows the signals provided by the same drive signal lines GOAL0 located in the third border B3 and the fourth border B4 to be kept as consistent as possible, thereby improving the display uniformity of the display substrate. In an exemplary embodiment, each drive signal connection line GOAL is electrically connected to one of the drive signal lines GOAL0.

[0140] In an exemplary embodiment, the driving signal line GOAL0 may include: a clock signal line, a gate driving signal line, an initial signal power supply line, etc. For example, the same clock signal line located in the third frame B3 and the same clock signal line located in the fourth frame area B4 may be electrically connected through one of the driving signal connection lines GOAL.

[0141] As shown in FIG. 5 a to FIG. 5 d , the display area 100 may include at least one corner area, the frame area 300 may include at least one corner area, and the at least one corner area of ​​the display area 100 corresponds to the at least one corner area of ​​the frame area 300 .

[0142] In an exemplary embodiment, as shown in Figure 5a, at least one corner area of ​​the border area 300 may include: a first corner area C1 connecting the first border area B1 and the third border area B3, a second corner area C2 connecting the third border area B3 and the second border area B2, a third corner area C3 connecting the second border area B2 and the fourth border area B4, and a fourth corner area C4 connecting the fourth border area B4 and the first border area B1.

[0143] In an exemplary embodiment, as shown in Figures 5a and 5b, the substrate may further include a binding region 200. The binding region 200 may be located on one side of the display region 100 in a plane parallel to the display substrate. The second power line VSS may be located at least in the binding region 200 and on a side of the display region 100 away from the binding region 200. At least one second power connection line VSSL may extend from the binding region 200 to the display region 100. In an exemplary embodiment, as shown in Figures 5a and 5b, the second power connection line VSSL may extend along a second direction Y. In the disclosed embodiment, the second power line VSS located in the binding region 200 and located on a side of the display region 100 away from the binding region 200 are electrically connected via the second power connection line VSSL. This allows the potentials of the second power line VSS located in the binding region 200 and on the side of the display region 100 away from the binding region 200 to be kept as consistent as possible, thereby improving display uniformity across the display substrate.

[0144] In an exemplary embodiment, as shown in FIG. 5 a to FIG. 5 d , the binding area 200 may be located in the first border area B1 , and the second power transfer electrode VSSZ2 and the second power transfer line VSSZ1 may be located in the first border area B1 and the second border area B2 .

[0145] In an exemplary embodiment, as shown in Figures 5a and 5b, the display substrate may further include a first power signal supply line VDD0. In a direction parallel to the plane where the display substrate is located, the first power signal supply line VDD0 can be set in the border area 300 and located around the display area 100. In the first border area B1 or the second border area B2, the first power signal supply line VDD0 can be located between the second power adapter line VSSZ1 and the display area 100. In the third border area B3 or the fourth border area B4, the first power signal supply line VDD0 can be located between the drive signal line GOAL0 and the display area 100.

[0146] In an exemplary embodiment, the display substrate may further include a plurality of first power connection lines VDDL and a plurality of first power lines VDD located in the display area 100. The display area 100 may further include a plurality of sub-pixels arranged in an array. The plurality of first power connection lines VDDL may extend along the first direction X and be arranged at intervals along the second direction Y. The plurality of first power lines VDD may extend along the second direction Y and be arranged at intervals along the first direction X.

[0147] The two ends of the first power connection line VDDL are electrically connected to the first power signal supply line VDD0 located on the third frame B3 and the fourth frame B4, respectively, and the middle part of the first power connection line VDDL is electrically connected to at least one row of sub-pixels; in the direction perpendicular to the plane where the display substrate is located, the first power line VDD can be located on the side of the first power connection line VDDL and the first power signal supply line VDD0 away from the substrate, the middle part of the first power line VDD is electrically connected to multiple first power connection lines VDDL, and the two ends are electrically connected to the first power signal supply line VDD0 located in the first frame area B1 and the second frame area B2, respectively.

[0148] In an exemplary embodiment, the first power signal supply line VDD0 and the second power line VSS can each be larger than the second power adapter line VSSZ1 in the second direction Y. For example, in the second border area B2, the first power signal supply line VDD0 and the second power line VSS can each be larger than the second power adapter line VSSZ1. Since the second power connection line VSSL is provided in the display area 100, the width (dimension along the second direction Y) of the second power adapter line VSSZ1 can be appropriately reduced. This reduces the voltage drop of the second power line VSS while also saving on the border area.

[0149] In an exemplary embodiment, the middle portion of the first power line VDD can be electrically connected to the plurality of first power connection lines VDDL via a via, and the ends can be electrically connected to the first power signal supply line VDD0 located in the first border area B1 and the second border area B2 via vias. In an exemplary embodiment, the drive signal connection line GOAL and the first power line VDD can be located in the second source-drain metal layer, and the first power signal supply line VDD0 and the first power connection line VDDL can be located in the first source-drain metal layer. In an exemplary embodiment, the first power signal supply line VDD0 and the plurality of first power connection lines VDDL can be integrally formed.

[0150] In an exemplary embodiment, the display substrate may further include an anode conductive layer and a cathode layer. The cathode layer may be located on a side of the anode conductive layer away from the substrate, perpendicular to the plane of the display substrate. A second power transfer electrode VSSZ2 may be located on the anode conductive layer, with the orthographic projection of the second power transfer electrode VSSZ2 on the substrate at least partially overlapping with the orthographic projection of the cathode layer on the substrate. The second power transfer electrode VSSZ2 and the cathode layer may be electrically connected. In an exemplary embodiment, the second power transfer electrode VSSZ2 and the cathode layer may be electrically connected via a via, or via a trench. In an exemplary embodiment, the anode conductive layer may be located on a side of the second source / drain metal layer away from the substrate. In an exemplary embodiment, the second power connection line VSSL may be located on the second source / drain metal layer, and the second power line VSS may be a dual-layer structure, located on the first source / drain metal layer and the second, remote metal layer. The dual-layer structure of the second power line VSS reduces the voltage drop across the second power line VSS, ensuring that the second power signal provided to the display substrate remains as consistent as possible, thereby improving display uniformity.

[0151] In an exemplary embodiment, the binding area 200 can be provided with a data driving circuit (or can be called a data driving IC) and a gate driving circuit (or can be called a gate driving IC) in the first direction X, and the gate driving circuit can be provided on both sides of the data driving circuit; the first power signal supply line VDD0 can be electrically connected to the data driving circuit of the binding area 200, and the data driving circuit provides a first power signal to the first power signal supply line VDD0; the second power line VSS can be electrically connected to the data driving circuit or the gate driving circuit of the binding area 200, and the data driving circuit or the gate driving circuit is electrically connected to provide a second power signal to the second power line VSS; the third border area B3 and the fourth border area B4 can be provided with a gate driving circuit (which can be an array substrate row driving circuit, the full English name is Gate Driver on The GOA circuit may be located between the second power line VSS and the display area 100. The input end of the GOA circuit may be electrically connected to a plurality of drive signal lines GOAL0. The output end of the GOA circuit may be electrically connected to a sub-pixel located in the display area 100. Each GOA circuit may be configured to provide a GOA signal (or scan signal) to one or more rows of sub-pixels in the display area 100.

[0152] In an exemplary embodiment, as shown in FIG6a , the number of second power connection lines VSSL may be multiple, and the display area 100 may include a plurality of sub-pixels Pxij arranged in an array. The plurality of second power connection lines VSSL may be arranged along a row direction X and extend along a column direction Y. At least one second power connection line VSSL may be disposed between two adjacent columns of sub-pixels. In a plane parallel to the display substrate, the row direction X may intersect with the column direction Y. In an exemplary embodiment, the row direction X may be the first direction X described above, and the column direction Y may be the second direction Y described above.

[0153] In an exemplary embodiment, the display area 100 may further include a plurality of initial signal lines and a plurality of initial signal connection lines. The plurality of initial signal lines may be configured to be electrically connected to a plurality of rows of sub-pixels, respectively, and the initial signal connection lines may be configured to be electrically connected to at least some of the initial signal lines. In a direction parallel to the plane where the display substrate is located, the plurality of initial signal lines extend along a row direction X and are arranged at intervals along a column direction Y. The plurality of initial signal connection lines extend along a column direction Y and are arranged at intervals along a row direction X. In a direction perpendicular to the plane where the display substrate is located, the plurality of initial signal connection lines and the plurality of initial signal lines may be located in different conductive layers. For example, the plurality of initial signal connection lines may be located on a side of the plurality of initial signal lines away from the substrate.

[0154] In an exemplary embodiment, as shown in FIG6a , the plurality of initial signal lines may include a plurality of first initial signal lines Vinit1 and a plurality of second initial signal lines Vinit2, at least some of the sub-pixels may include a plurality of transistors, the plurality of transistors including at least a first transistor and a seventh transistor; the plurality of first initial signal lines Vinit1 are configured to be electrically connected to the first transistors in the plurality of rows of sub-pixels, respectively, and the plurality of second initial signal lines Vinit2 are configured to be electrically connected to the seventh transistors in the plurality of rows of sub-pixels, respectively.

[0155] The multiple initial signal connection lines may include multiple first initial signal connection lines 61 and multiple second initial signal connection lines 62; the first initial signal connection lines 61 are configured to be electrically connected to the multiple first initial signal lines Vinit1, and the second initial signal connection lines 62 are configured to be electrically connected to the multiple second initial signal lines Vinit2.

[0156] In the embodiment of the present disclosure, by electrically connecting the first initial signal connection line 61 to multiple first initial signal lines Vinit1, the first initial signals received by multiple sub-pixels located in the same column can have basically the same potential, and by electrically connecting the second initial signal connection line 62 to multiple second initial signal lines Vinit2, the second initial signals received by multiple sub-pixels located in the same column can have basically the same potential, thereby improving the display uniformity of the display substrate.

[0157] In an exemplary embodiment, the display substrate may include a semiconductor layer, a second conductive layer, a third conductive layer, and a fourth conductive layer sequentially disposed on a base in a direction perpendicular to the plane of the display substrate. The multiple initial signal lines may be disposed in one of the semiconductor layer, the second conductive layer, and the third conductive layer. As shown in Figure 6b , the multiple initial signal lines may be disposed in the semiconductor layer; as shown in Figure 6c , the multiple initial signal lines may be disposed in the second conductive layer; and as shown in Figure 6d , the multiple initial signal lines may be disposed in the third conductive layer. In an exemplary embodiment, the multiple initial signal connection lines may be disposed in the fourth conductive layer. In the structure shown in FIG6b, multiple initial signal lines are arranged in the semiconductor layer, and the multiple initial signal lines do not need to be electrically connected to the active layer through vias, which reduces the number of vias, saves space on the display substrate to a certain extent, and can improve the PPI (Pixels Per Inch, which can be called pixel density) of the display substrate. In the structures shown in FIG6c and FIG6d, multiple initial signal lines need to be electrically connected to the active layer through vias, which increases the space for setting vias compared to the structure shown in FIG6b. Therefore, the PPI of the display substrates in FIG6c and FIG6d is relatively lower than the PPI of the display substrate in FIG6b.

[0158] In an exemplary embodiment, as shown in FIG6a , a plurality of sub-pixels may form a plurality of pixel units P arranged in an array, at least some of the pixel units include at least three sub-pixels arranged sequentially along a row direction X, and a second power connection line VSSL, a first initial signal line Vinit1, and a second initial signal line Vinit2 are disposed between two adjacent columns of pixel units.

[0159] In an exemplary embodiment, the second power supply link lines VSSL, the first initial signal link lines 61 , and the second initial signal link lines 62 may be arranged along the row direction X in a periodic manner.

[0160] In an exemplary embodiment, within one cycle, the second power connection line VSSL, the first initial signal connection line 61, and the second initial signal connection line 62 are sequentially arranged along the row direction X, R columns of pixel units are spaced between the second power connection line VSSL and the first initial signal connection line 61, R columns of pixel units are spaced between the first initial signal connection line 61 and the second initial signal connection line 62, and R columns of pixel units are spaced between the second initial signal connection line 62 and the second power connection line VSSL in the adjacent cycle, where R is an integer greater than or equal to 1.

[0161] In an exemplary embodiment, one period may include two first initial signal connection lines 61, two second initial signal connection lines 62, and one second power connection line VSSL. In the row direction X, the two first initial signal connection lines 61 and the two second initial signal connection lines 62 may be located on both sides of the second power connection line VSSL. On the same side of the second power connection line VSSL, the first initial signal connection line 61 and the second initial signal connection line 62 are sequentially arranged along the row direction X.

[0162] In the same cycle, there are R columns of pixel units between the first initial signal connection line 61 and the adjacent second initial signal connection line 62, and there are R columns of pixel units between the second power connection line VSSL and the adjacent first initial signal connection line 61 and the second initial signal connection line 62, where R is an integer greater than or equal to 1.

[0163] In an exemplary embodiment, as shown in Figures 6b, 7a to 7e, the display substrate may further include a shielding layer and a circuit structure layer disposed on the base. The shielding layer may be located between the base and the circuit structure layer in a direction perpendicular to the plane of the display substrate.

[0164] In an exemplary embodiment, as shown in Figures 6b, 7a to 7e, the display area 100 is provided with a plurality of sub-pixels Pxij, and at least some of the sub-pixels include a first transistor T1 to a seventh transistor T7 located in the circuit structure layer and at least one shielding structure located in the shielding layer. In the same sub-pixel, each shielding structure is configured to shield the channel region of at least one transistor from the first transistor to the seventh transistor. By shielding the transistor located in the circuit structure layer by the shielding structure, the stability of the corresponding transistor can be improved. In an exemplary embodiment, a PI layer (polyimide layer) is provided in the substrate. During the operation of the display substrate, the PI layer can accumulate charge, which will affect the transistors provided on the substrate, making the transistor operation unstable, resulting in the presence of afterimages and bright spot defects in the display panel. By shielding the transistors by the shielding layer, the influence of the charge of the PI layer on the transistors can be reduced to a certain extent.

[0165] In an exemplary embodiment, in the same sub-pixel, the blocking layer may include one or more of the first blocking structure 11 to the seventh blocking structure 17, wherein the orthographic projection of the first blocking structure 11 on the substrate at least partially overlaps with the orthographic projection of the first transistor on the substrate; the orthographic projection of the second blocking structure 12 on the substrate at least partially overlaps with the orthographic projection of the second transistor on the substrate; the orthographic projection of the third blocking structure 13 on the substrate at least partially overlaps with the orthographic projection of the third transistor on the substrate; the orthographic projection of the fourth blocking structure 14 on the substrate at least partially overlaps with the orthographic projection of the fourth transistor on the substrate; the orthographic projection of the fifth blocking structure 15 on the substrate at least partially overlaps with the orthographic projection of the fifth transistor on the substrate; the orthographic projection of the sixth blocking structure 16 on the substrate at least partially overlaps with the orthographic projection of the sixth transistor on the substrate; and the orthographic projection of the seventh blocking structure 17 on the substrate at least partially overlaps with the orthographic projection of the seventh transistor on the substrate. For example, the orthographic projection of the channel region of the first transistor on the substrate is located within the range of the orthographic projection of the first blocking structure 11 on the substrate; the orthographic projection of the channel region of the second transistor on the substrate is located within the range of the orthographic projection of the second blocking structure 12 on the substrate; the orthographic projection of the channel region of the third transistor on the substrate is located within the range of the orthographic projection of the third blocking structure 13 on the substrate; the orthographic projection of the channel region of the fourth transistor on the substrate is located within the range of the orthographic projection of the fourth blocking structure 14 on the substrate; the orthographic projection of the channel region of the fifth transistor on the substrate is located within the range of the orthographic projection of the fifth blocking structure 15 on the substrate; the orthographic projection of the channel region of the sixth transistor on the substrate is located within the range of the orthographic projection of the sixth blocking structure 16 on the substrate; and the orthographic projection of the channel region of the seventh transistor on the substrate is located within the range of the orthographic projection of the seventh blocking structure 17 on the substrate.

[0166] In an exemplary embodiment, as shown in FIG6b , the blocking layer may include first to fourth blocking structures 11 to 14 and a seventh blocking structure 17, so that the channels of the first to fourth transistors T1 to T4 and the seventh transistor T7 can be blocked, and the stability of the first to fourth transistors T1 to T4 and the seventh transistor T7 can be improved; as shown in FIG7a , the blocking structure layer may include second to third blocking structures 12 to 13, so that the channels of the second transistor T2 and the third transistor T3 can be blocked, and the stability of the second to third transistors T3 can be improved; as shown in FIG7b , the blocking structure layer may include first to fourth blocking structures 11 to 14, so that the channels of the first to fourth transistors T1 to T4 can be blocked, and the stability of the first to fourth transistors T1 to T4 can be improved; as shown in FIG7c , the blocking structure layer may include second to third blocking structures 12 to 13 and a seventh blocking structure 17, so that the channels of the second to third transistors T2, T3 and T7 can be blocked. The channels of the second transistor T2 to the third transistor T3 and the seventh transistor T7 can be blocked, thereby improving the stability of the second transistor T2 to the third transistor T3 and the seventh transistor T7; as shown in Figure 7d, the blocking structure layer may include second blocking structures 12 to third blocking structures 13, and fifth blocking structures 15 to sixth blocking structures 16, so that the channels of the second transistor T2, the third transistor T3, the fifth transistor T5, and the sixth transistor T6 can be blocked, thereby improving the stability of the second transistor T2 to the third transistor T3, the fifth transistor T5 to the sixth transistor T6, wherein the blocking structures 15 / 16 of the fifth transistor T5 and the sixth transistor may be strip structures; as shown in Figure 7e, the blocking structure layer may include first blocking structures 11 to seventh blocking structures 17, so that the channels of the first transistor T1 to the seventh transistor T7 can be blocked, thereby improving the stability of the first transistor T1 to the seventh transistor T7.

[0167] In an exemplary embodiment, as shown in Figures 9 to 10a, multiple sub-pixels can form multiple sub-pixel rows, the blocking layer can include a second blocking structure 12 and a fourth blocking structure 14, and in the same sub-pixel row, the second blocking structure 12 located in one of the sub-pixels can be an integrally formed structure with the fourth blocking structure 14 located in the adjacent sub-pixel.

[0168] In an exemplary embodiment, as shown in FIG. 9 to FIG. 10 a , the plurality of sub-pixels may form a plurality of sub-pixel rows, the blocking layer may include a third blocking structure 13 , and in the same sub-pixel row, the distance between two third blocking structures 13 located in two adjacent sub-pixels in the row direction X is greater than the size of the channel region of the fourth transistor T4 . In other words, the distance between two adjacent third blocking structures 13 along the row direction X is greater than the size of the channel region of the fourth transistor T4 along the row direction X.

[0169] In an exemplary embodiment, the blocking structure in the blocking layer in the same sub-pixel can be an integrated structure; the blocking layers of multiple sub-pixels are interconnected as an integrated structure, which can make the signals of the blocking layers in multiple sub-pixels as consistent as possible, thereby improving display uniformity.

[0170] In an exemplary embodiment, as shown in FIG7e , the shielding layer may further include a first connecting structure 110 to a seventh connecting structure 170, wherein in the second direction Y, the sixth connecting structure 160 may be located on both sides of the fifth shielding structure 15 and the sixth shielding structure 16, one end of the first shielding structure 11 is connected to the shielding layer of the adjacent row through the second connecting structure 120, and the other end is connected to the second shielding structure 12 through the fourth connecting structure 140; the side of the second shielding structure 12 away from the first shielding structure 11 is connected to the third shielding structure 16 through the fifth connecting structure 150. The third shielding structure 13 is connected to the fifth shielding structure 15 and the sixth shielding structure 16 through the sixth connecting structure 160; the fourth shielding structure 14 is connected to the third shielding structure 13 through the seventh connecting structure 170; one end of the seventh shielding structure 17 is connected to the fifth shielding structure 15 and the sixth shielding structure 16 through the sixth connecting structure 160, and the other end is connected to the shielding layer of the adjacent row through the third connecting structure 130; in the first direction X, the third shielding structures 13 in two adjacent shielding layers can be connected through the first connecting structure 110.

[0171] In an exemplary embodiment, as shown in FIG8a , the display substrate may further include a first power signal supply line VDD0. The first power signal supply line VDD0 may be disposed in the border region 300 and located at the periphery of the display region 100. In a direction perpendicular to the plane of the display substrate, the first power signal supply line VDD0 is located on a side of the shielding layer BSM away from the substrate. The shielding layer BSM of a plurality of sub-pixels located on a side of the display region 100 near the border region 300 is electrically connected to the first power signal supply line VDD0 via vias. Providing a first power signal to the shielding layer BSM via the first power signal supply line VDD0 prevents the charge in the PI layer of the substrate from affecting the transistors, thereby improving the stability of the shielded transistors.

[0172] In an exemplary embodiment, as shown in Figures 8a and 8b, Figure 8b is a schematic structural diagram of the shielding layer in Figure 8a, and the display substrate may further include a shielding transfer line BSML, which is located at least on both sides of a set of opposite sides of the display area 100. On a plane parallel to the display substrate, the shielding transfer line BSML may be located between the second power line VSS and the display area 100, and the shielding layer BSM of a plurality of sub-pixels located on the side of the display area 100 close to the frame area 300 is connected to the shielding transfer line BSML. The first power signal supply line VDD0 and the shielding transfer line BSML may be electrically connected through a via, and the orthographic projection of the first power signal supply line VDD0 on the substrate at least partially overlaps with the orthographic projection of the shielding transfer line BSML on the substrate. In an exemplary embodiment, the shielding transition line BSML can be set in the first frame B1 to the fourth frame B4, or in the first frame B1 and the second frame B2, or in the third frame B3 and the fourth frame B4. The embodiments of the present disclosure are not limited to this. For example, the shielding transition line BSML can be set in the first frame B1 and the third frame, or in the second frame B2 and the third frame B3.

[0173] As shown in Figure 8c, it is a schematic diagram of a cross-sectional structure of the adjacent position of the display substrate border area 300 and the display area 100. For example, it can be a schematic diagram of a cross-sectional structure of the adjacent position of the first border area B1 and the display area 100. In the structure shown in Figure 8c, 101 is a substrate, BSM is a blocking layer, P-Si can be an active layer, Gate1 is a first conductive layer (which can be called a first gate metal layer), Gate1 is a second conductive layer (which can be called a second gate metal layer), SD1 is a third conductive layer (which can be called a first source-drain metal layer), SD2 is a fourth conductive layer (which can be called a second source-drain metal layer), An is an anode conductive layer, EM is an organic light-emitting layer, Ca is a cathode layer, c1 is a first insulating layer, c2 is a second insulating layer, c3 is a third insulating layer, c4 is a fourth insulating layer, c5 is a fifth insulating layer (which can be called a PVX layer) and a first flat layer, c6 is a second flat layer, and c7 is a pixel definition layer. The elements corresponding to other numbers in Figure 8c can be referred to as described above and will not be repeated here.

[0174] In an exemplary embodiment, the organic light-emitting layer EM may adopt a tandem OLED device. The tandem OLED device structure, i.e., the sub-pixel includes multiple light-emitting layers. Compared with a single-light-emitting-layer OLED device, a smaller current is required to achieve the same brightness. The smaller current can effectively reduce the power consumption of the tandem OLED device and extend the service life of the tandem OLED device.

[0175] The following is an illustrative explanation through the preparation process of the display substrate. The "patterning process" mentioned in the present disclosure includes processes such as coating photoresist, mask exposure, development, etching, and stripping photoresist for metal materials, inorganic materials or transparent conductive materials, and includes processes such as coating organic materials, mask exposure and development for organic materials. Deposition can be carried out by any one or more of sputtering, evaporation, and chemical vapor deposition, coating can be carried out by any one or more of spraying, spin coating and inkjet printing, and etching can be carried out by any one or more of dry etching and wet etching, and the present disclosure does not limit this. "Thin film" refers to a layer of thin film made by deposition, coating or other processes on a substrate (or base substrate). If the "thin film" does not require a patterning process during the entire production process, the "thin film" can also be called a "layer". If the "thin film" requires a patterning process during the entire production process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern". As used in this disclosure, "A and B are disposed in the same layer" means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer refers to the dimension of the film layer in a direction perpendicular to the display substrate. In exemplary embodiments of this disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A contains the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or that the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0176] In an exemplary embodiment, taking three sub-pixels (one sub-pixel row and three sub-pixel columns) in a display area (AA) as an example, a preparation process of a display substrate may include the following operations.

[0177] (101) Prepare a substrate on a glass carrier. In an exemplary embodiment, the substrate may be a flexible substrate or a rigid substrate. The rigid substrate may include, but is not limited to, one or more of glass and quartz, and the flexible substrate may be, but is not limited to, one or more of polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fiber. In an exemplary embodiment, the flexible substrate may include a first flexible material layer, a first inorganic material layer, an adhesive layer, a second flexible material layer, and a second inorganic material layer stacked together. The first and second flexible material layers may be made of polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer soft film, and the first and second inorganic material layers may be made of silicon nitride (SiNx) or silicon oxide (SiOx), etc., to improve the substrate's resistance to water and oxygen. The first and second inorganic material layers are also referred to as barrier layers, and the adhesive layer may be made of amorphous silicon (a-Si). In an exemplary embodiment, taking the stacked structure PI1 / Barrier1 / a-si / PI2 / Barrier2 as an example, its preparation process may include: first coating a layer of polyimide on a glass carrier, and forming a first flexible material (PI1) layer after curing; then depositing a barrier film on the first flexible layer to form a first barrier (Barrier1) layer covering the first flexible material layer; then depositing a layer of amorphous silicon film on the first barrier layer to form an amorphous silicon (a-si) layer covering the first barrier layer; then coating the amorphous silicon layer with another layer of polyimide, and forming a second flexible material (PI2) layer after curing; then depositing a barrier film on the second flexible layer to form a second barrier (Barrier2) layer covering the second flexible layer, thereby completing the preparation of the substrate.

[0178] (102) Forming a blocking layer pattern. In an exemplary embodiment, forming the blocking layer pattern may include: depositing a conductive film of the blocking layer on a substrate, patterning the conductive film of the blocking layer through a patterning process, and forming a blocking layer pattern on the substrate, as shown in FIG9 , which is a planar structural diagram of the blocking layer pattern in three sub-pixels.

[0179] In an exemplary embodiment, the blocking layer pattern of each sub-pixel may include a first connection structure 110, a second connection structure 120, a third connection structure 130, a fourth connection structure 140, a fifth connection structure 150, a sixth connection structure 160, a seventh connection structure 170, a first blocking structure, a second blocking structure 12, a third blocking structure 13, a fourth blocking structure 14, and a seventh blocking structure 17.

[0180] In an exemplary embodiment, the first to fourth shielding structures 11, 14, and seventh shielding structure 17 may be rectangular in shape, and the corners of the rectangles may be chamfered. In the second direction Y, the first shielding structure 11 and the seventh shielding structure 17 may be located on either side of the third shielding structure 13. The first shielding structure 11 may be located on a side of the second shielding structure 12 away from the third shielding structure 13, and the seventh shielding structure 17 may be located on a side of the third shielding structure 13 along the second direction Y. In an exemplary embodiment, in the second direction Y, the first shielding structure 11 is connected to the second connecting structure 120 at one end and to the fourth connecting structure 140 at the other end; the second shielding structure 12 is connected to the fourth connecting structure 140 at one end and to the fifth connecting structure 150 at the other end; the third shielding structure 13 is connected to the fifth connecting structure 150 at one end and to the sixth connecting structure 160 at the other end; the fourth shielding structure 14 is connected to the third shielding structure 13 via the seventh connecting structure 170; and the seventh shielding structure 17 is connected to the sixth connecting structure 160 at one end and to the third connecting structure 130 at the other end. In an exemplary embodiment, in the first direction X, the fourth shielding structure 140 may be connected to the second shielding structure 12 in an adjacent row.

[0181] In an exemplary embodiment, the first connecting structure 110 may be in the shape of a strip extending along the first direction X. The first connecting structure 110 is disposed on one side of the third shielding structure 13 in the first direction X and is connected to the third shielding structure 13. The second connecting structure 120 may be in the shape of a zigzag extending along the second direction Y. The second connecting structure 120 is disposed on a side of the first shielding structure 11 opposite to the second direction Y and is connected to the first shielding structure 11. The third connecting structure 130 may be in the shape of a strip extending along the second direction Y. The third connecting structure 130 is disposed on one side of the seventh shielding structure 17 in the second direction Y and is connected to the seventh shielding structure 17. The fourth connecting structure 140 may be in the shape of a zigzag extending along the second direction Y. In the second direction Y, one end of the fourth connecting structure 140 is connected to the first shielding structure 11 and the other end is connected to the second shielding structure 12. The fifth connecting structure 150 may be in the shape of a strip extending along the second direction Y. In the second direction Y, one end of the fifth connecting structure 150 is connected to the third shielding structure 13 and the other end is connected to the second shielding structure 12. The sixth connecting structure 160 may be in the shape of a zigzag extending along the second direction Y. In the second direction Y, one end of the sixth connecting structure 160 is connected to the third shielding structure 13, and the other end is connected to the seventh shielding structure 17. The seventh connecting structure 170 may be in the shape of a zigzag extending along the second direction Y. In the second direction Y, one end of the seventh connecting structure 170 is connected to the third shielding structure 13, and the other end is connected to the fourth shielding structure 14.

[0182] In an exemplary embodiment, the first connection structure 110 of each sub-pixel is connected to the third shielding structure 13 of the adjacent sub-pixel in the first direction X, so that the shielding layers in one sub-pixel row are connected as one, forming an interconnected integrated structure.

[0183] In an exemplary embodiment, the second connection structure 120 of each sub-pixel is connected to the third connection structure 130 of the adjacent sub-pixel in the second direction Y, so that the shielding layers in one sub-pixel column are connected as a whole to form an interconnected integral structure.

[0184] In an exemplary embodiment, the blocking layers in the sub-pixel rows and sub-pixel columns are connected as one, which can ensure that the blocking layers in the display substrate have the same potential, which is beneficial to improving the uniformity of the panel, avoiding poor display of the display substrate, and ensuring the display effect of the display substrate.

[0185] In an exemplary embodiment, the shapes of the shielding layers in a plurality of sub-pixel rows may be the same, and the shapes of the shielding layers in a plurality of sub-pixel columns may be the same.

[0186] In an exemplary embodiment, the shielding layer may further include a shielding transition line BSML as shown in FIG. 8 a to FIG. 8 c . The shielding transition line BSML may be provided in the frame area 300 located around the display area 100 .

[0187] In an exemplary embodiment, the blocking layer pattern can be formed after preparing the second flexible material (PI2) layer, that is, the blocking layer pattern can be arranged on the second flexible material (PI2) layer, and after the blocking layer pattern is prepared, the second barrier (Barrier2) layer is prepared; or, the blocking layer pattern can be formed after preparing the first flexible material (PI1) layer, that is, the blocking layer pattern can be arranged on the first flexible material (PI1) layer, and after the blocking layer pattern is prepared, the second flexible material (PI2) layer is prepared. The embodiments of the present disclosure are not limited to this.

[0188] (103) Forming a semiconductor layer pattern. In an exemplary embodiment, forming a semiconductor layer pattern may include: depositing a first insulating film and a first semiconductor film in sequence on a substrate having the aforementioned pattern formed thereon, patterning the first semiconductor film through a patterning process to form a first insulating layer covering the blocking layer pattern, and a semiconductor layer pattern disposed on the first insulating layer, as shown in FIG10a to FIG10c. FIG10a is a planar structural diagram of three columns of sub-pixels (i.e., three sub-pixels) from the Q1 column to the Q3 column in a row of sub-pixels, and FIG10b is a planar schematic diagram of the semiconductor layer in FIG10a; FIG10c is a structural diagram of the semiconductor layer of three columns of sub-pixels from the N1 column to the N3 column in a row of sub-pixels.

[0189] In an exemplary embodiment, the semiconductor layer pattern of each sub-pixel may include the active layer 21 of the first transistor T1 to the active layer 27 of the seventh transistor T7, the first initial signal line Vinit1, and the second initial signal line Vinit2, and the active layer 21 of the first transistor T1 to the active layer 27 of the seventh transistor T7 and the first initial signal line Vinit1 and the second initial signal line Vinit2 may be an integrated structure connected to each other.

[0190] In an exemplary embodiment, in the first direction X, the active layer 24 of the fourth transistor T4 and the active layer 25 of the fifth transistor T5 are located on the same side of the active layer 23 of the third transistor T3, and the active layer 22 of the second transistor T2, the active layer 26 of the sixth transistor T6, and the active layer 27 of the seventh transistor T7 are located on the other side of the active layer 23 of the third transistor T3; in the second direction Y, the active layer 24 of the fourth transistor T4 and the active layer 25 of the fifth transistor T5 are located on both sides of the active layer 23 of the third transistor T3, and the active layer 25 of the fifth transistor T5 and the active layer 27 of the seventh transistor T7 are located on the other side of the active layer 23 of the third transistor T3. The active layer 26 of the sixth transistor T6 and the active layer 27 of the seventh transistor T7 are located on the same side of the active layer 23 of the third transistor T3. The active layer 27 of the seventh transistor T7 is located on a side of the active layer 26 of the sixth transistor T6 away from the active layer 23 of the third transistor T3. The active layer 24 of the fourth transistor T4, the active layer 22 of the second transistor T2, and the active layer 21 of the first transistor T1 are located on the same side of the third transistor T3, and the active layer 21 of the first transistor T1 is located on a side of the active layer 22 of the second transistor T2 away from the active layer 23 of the third transistor T3. The first initial signal line Vinit1 is located on a side of the active layer of the first transistor T1 away from the active layer 21 of the second transistor T2, and is connected to the active layer 21 of the first transistor T1 in one row of sub-pixels; the second initial signal line Vinit2 is located on a side of the active layer 27 of the seventh transistor T7 away from the active layer 26 of the sixth transistor T6, and is connected to the active layer 27 of the seventh transistor T7 in one row of sub-pixels.

[0191] In an exemplary embodiment, the sub-pixel in the Mth row and the Q2th column is used as an example for description: in the first direction X, the active layer 24 of the fourth transistor T4 and the active layer 25 of the fifth transistor T5 are located on the side of the active layer 23 of the third transistor T3 away from the sub-pixel in the Q1th column, and the active layer 22 of the second transistor T2, the active layer 26 of the sixth transistor T6, and the active layer 27 of the seventh transistor T7 are located on the side of the active layer 23 of the third transistor T3 away from the sub-pixel in the Q3th column; in the second direction Y, the active layer 21 of the first transistor T1, the active layer 22 of the second transistor T2, and the active layer 27 of the fourth transistor T7 are located on the side of the active layer 23 of the third transistor T3 away from the sub-pixel in the Q3th column. The active layer 24 of the transistor T4 is located on a side of the active layer 23 of the third transistor T3 away from the sub-pixels in the M+1th row, the active layer 25 of the fifth transistor T5, the active layer 26 of the sixth transistor T6, and the active layer 27 of the seventh transistor T7 are located on a side of the active layer 23 of the third transistor T3 away from the sub-pixels in the M-1th row, the active layer 27 of the seventh transistor T7 is located on a side of the active layer 26 of the sixth transistor T6 away from the active layer 23 of the third transistor T3, and the active layer 21 of the first transistor T1 is located on a side of the active layer 22 of the second transistor T2 away from the active layer 23 of the third transistor T3. The first initial signal line Vinit1 is located on a side of the active layer 21 of the first transistor T1 away from the active layer 21 of the second transistor T2 (located on a side of the active layer 21 of the first transistor T1 close to the sub-pixels in the M-1th row), and the second initial signal line Vinit2 is located on a side of the active layer 27 of the seventh transistor T7 away from the active layer 26 of the sixth transistor T6 (located on a side of the active layer 27 of the seventh transistor T7 close to the sub-pixels in the M+1th row).

[0192] In an exemplary embodiment, the active layer 23 of the third transistor T3 may have an Ω shape or an X shape, the active layer 24 of the fourth transistor T4, the active layer 26 of the sixth transistor T6, and the active layer 27 of the seventh transistor T7 may have an I shape, and the active layer 21 of the first transistor T1, the active layer 21 of the second transistor T2, and the active layer 25 of the fifth transistor T5 may have an L shape.

[0193] In an exemplary embodiment, the active layer of each transistor may include a first region, a second region, and a channel region located between the first region and the second region. In an exemplary embodiment, the first region 21-1 of the active layer 21 of the first transistor T1 is aligned with the first initial signal line Vinit1, the second region 21-2 of the active layer 21 of the first transistor T1 may serve as the first region 22-1 of the second transistor T2, the first region 23-1 of the active layer 23 of the third transistor T3 may serve as the second region 24-2 of the active layer 24 of the fourth transistor T4, the second region 25-2 of the active layer 25 of the fifth transistor T5, and the second region 23-2 of the active layer 23 of the third transistor T3 may serve as The first area 26-1 of the active layer 26 of the sixth transistor T6, the second area 22-2 of the active layer 22 of the second transistor T2, and the second area 26-2 of the active layer 26 of the sixth transistor T6 can serve as the second area 27-2 of the active layer 27 of the seventh transistor T7, the first area 27-1 of the active layer 27 of the seventh transistor T7 can be connected to the second initial signal line Vinit2, and the first area 24-1 of the active layer 24 of the fourth transistor T4 and the first area 25-1 of the active layer 25 of the fifth transistor T5 can be set separately.

[0194] In an exemplary embodiment, the orthographic projection of the active layer 21 of the first transistor T1 on the substrate at least partially overlaps with the orthographic projection of the first blocking structure 11 on the substrate, the orthographic projection of the active layer 22 of the second transistor T2 on the substrate at least partially overlaps with the orthographic projection of the second blocking structure 12 on the substrate, the orthographic projection of the active layer 23 of the third transistor T3 on the substrate at least partially overlaps with the orthographic projection of the third blocking structure 13 on the substrate, the orthographic projection of the active layer 24 of the fourth transistor T4 on the substrate at least partially overlaps with the orthographic projection of the fourth blocking structure 14 on the substrate, and the orthographic projection of the active layer 27 of the seventh transistor T7 on the substrate at least partially overlaps with the orthographic projection of the seventh blocking structure 17 on the substrate. In an exemplary embodiment, the orthographic projection of the channel region of the active layer 21 of the first transistor T1 on the substrate is located within the range of the orthographic projection of the first blocking structure 11 on the substrate, the orthographic projection of the channel region of the active layer 22 of the second transistor T2 on the substrate is located within the range of the orthographic projection of the second blocking structure 12 on the substrate, the orthographic projection of the channel region of the active layer 23 of the third transistor T3 on the substrate is located within the range of the orthographic projection of the blocking block 14 on the substrate, the orthographic projection of the channel region of the active layer 24 of the fourth transistor T4 on the substrate is located within the range of the orthographic projection of the fourth blocking structure 14 on the substrate, and the orthographic projection of the channel region of the active layer 27 of the seventh transistor T7 on the substrate is located within the range of the orthographic projection of the seventh blocking structure 17 on the substrate, thereby improving the stability of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, and the seventh transistor T7.

[0195] In an exemplary embodiment, the first initial signal line Vinit1 may be in the shape of a zigzag line extending along a first direction X. A plurality of first transfer electrodes Vinit10 are provided on the first initial signal line Vinit1. The first transfer electrodes Vinit10 are configured to electrically connect the first initial signal line Vinit1 to a subsequently formed first initial signal connection line. The plurality of first initial signal lines Vinit1 are electrically connected to one another via the first initial signal connection line. The first initial signal line Vinit1 is configured to connect to the first region 21-1 of the active layer 21 of the plurality of first transistors T1 in a row of sub-pixels. The connection of the first region 21-1 of the active layer 21 of the plurality of first transistors T1 in the same row of sub-pixels to the first initial signal line Vinit1 and the electrical connection of the plurality of rows of first initial signal lines Vinit1 via the subsequently formed first initial signal connection line ensure that the first electrodes of the first transistors T1 in adjacent sub-pixels have the same potential, thereby improving the uniformity of the panel display, preventing display defects on the display substrate, and ensuring the display quality of the display substrate.

[0196] In an exemplary embodiment, the second initial signal line Vinit2 may be in the shape of a zigzag line extending along the first direction X. A plurality of second transfer electrodes Vinit20 are provided on the second initial signal line Vinit2. The second transfer electrodes Vinit20 are configured to electrically connect the second initial signal line Vinit2 to a subsequently formed second initial signal connection line. The plurality of second initial signal lines Vinit2 are electrically connected to one another via the second initial signal connection line. The second initial signal line Vinit2 is configured to connect to the first region 27-1 of the active layer 27 of the plurality of seventh transistors T7 in a row of sub-pixels. The connection of the first region 27-1 of the active layer 27 of the plurality of seventh transistors T7 in the same row of sub-pixels to the second initial signal line Vinit2 and the electrical connection of the plurality of second initial signal lines Vinit2 to one another via the subsequently formed second initial signal connection line ensure that the first electrodes of the seventh transistors T7 in adjacent sub-pixels have the same potential, thereby improving the uniformity of the panel display, preventing display defects on the display substrate, and ensuring the display quality of the display substrate.

[0197] In an exemplary embodiment, the first transition electrodes Vinit10 and the second transition electrodes Vinit20 may be alternately arranged along the first direction X. The first transition electrodes Vinit10 and the second transition electrodes Vinit20 may be disposed between two adjacent columns of sub-pixels. In the same row of sub-pixels, not all adjacent sub-pixels are provided with the first transition electrodes Vinit10 and the second transition electrodes Vinit20. For example, in the same row of sub-pixels, adjacent first transition electrodes Vinit10 and second transition electrodes Vinit20 may be separated by one or more sub-pixels. For example, adjacent first transition electrodes Vinit10 and second transition electrodes Vinit20 may be separated by three sub-pixels. This is not limited in the present disclosure. In an exemplary embodiment, adjacent first transition electrodes Vinit10 and second transition electrodes Vinit20 may be separated by one pixel unit. A pixel unit may include three or four sub-pixels arranged along the first direction X. That is, in the first direction X, the first transition electrode Vinit10 and the second transition electrode Vinit20 may be located between two adjacent pixel units.

[0198] In an exemplary embodiment, FIG10c is a schematic planar structure diagram of the semiconductor layer of three columns of sub-pixels (columns N1, N2, and N3) located on the side of the Q1 column of sub-pixels away from the Q2 column of sub-pixels in the first direction X. The shielding layer structure of the sub-pixels in columns N1 through N is identical to that of the sub-pixels in columns Q1 through Q3. In this exemplary embodiment, FIG10c differs from FIG10b in that the first initial signal line Vinit1 is not provided with the first transfer electrode Vinit10, and the second initial signal line Vinit2 is not provided with the second transfer electrode Vinit20.

[0199] In an exemplary embodiment, the shapes of the semiconductor layers in the plurality of sub-pixel rows may be the same, and the shapes of the active layers of the first to seventh transistors T1 to T7 in the plurality of sub-pixel columns may be the same.

[0200] In an exemplary embodiment, the semiconductor layer may be made of polycrystalline silicon (p-Si), meaning that the first transistor T1 to the seventh transistor T7 may be LTPS thin-film transistors. In an exemplary embodiment, patterning the first semiconductor thin film through a patterning process may include: first forming an amorphous silicon (a-Si) thin film on a first insulating film, performing a dehydrogenation treatment on the amorphous silicon thin film, and then crystallizing the dehydrogenated amorphous silicon thin film to form a polycrystalline silicon thin film. Subsequently, patterning the polycrystalline silicon thin film to form a semiconductor layer pattern.

[0201] (104) Forming a first conductive layer pattern. In an exemplary embodiment, forming the first conductive layer pattern may include: sequentially depositing a second insulating film and a first conductive film on the substrate having the aforementioned pattern formed thereon, patterning the first conductive film through a patterning process to form a second insulating layer covering the semiconductor layer pattern, and a first conductive layer pattern disposed on the second insulating layer, as shown in FIG11a and FIG11b , where FIG11b is a plan view schematically illustrating the first conductive layer in FIG11a . In an exemplary embodiment, the first conductive layer may be referred to as a first gate metal (GATE1) layer.

[0202] In an exemplary embodiment, the first conductive layer pattern may include at least: a control electrode 31 of a first transistor T1, a control electrode 32 of a second transistor T2, a first plate 33 of a storage capacitor (which may serve as a control electrode of a third transistor T3), a control electrode 34 of a fourth transistor T4, a light-emitting control line E, and a control electrode 37 of a seventh transistor T7. The main portion of the light-emitting control line E may extend along a first direction X. In the same sub-pixel, the control electrode 31 of the first transistor T1, the control electrode 32 of the second transistor T2, the first plate 33 of the storage capacitor, and the light-emitting control line E may be arranged along a second direction Y.

[0203] In an exemplary embodiment, in the second direction Y, the control electrode 31 of the first transistor T1 can be located on a side of the control electrode 32 of the second transistor T2 away from the first electrode plate 33 of the storage capacitor, the control electrode 32 of the second transistor T2 and the light-emitting control line E are located on both sides of the first electrode plate 33 of the storage capacitor, and the control electrode 37 of the seventh transistor T7 can be located on a side of the light-emitting control line E away from the first electrode plate 33 of the storage capacitor.

[0204] Take the Mth row and Q2th column sub-pixel as an example: in the second direction Y, in the same sub-pixel, the control electrode 31 of the first transistor T1 can be located on the side of the control electrode 32 of the second transistor T2 close to the M-1th row sub-pixel, the control electrode 32 of the second transistor T2 can be located between the control electrode 31 of the first transistor T1 and the first electrode plate 33 of the storage capacitor, the light-emitting control line E can be located on the side of the first electrode plate 33 of the storage capacitor close to the M+1th row sub-pixel, and the control electrode 37 of the seventh transistor T7 can be located on the side of the light-emitting control line E close to the M+1th row sub-pixel; in the first direction X, the control electrode 34 of the fourth transistor T4 can be located on the side of the control electrode 32 of the second transistor T2 close to the Q3th column sub-pixel, and can be integrally formed with the control electrode 32 of the second transistor T2 in the Q3th column sub-pixel.

[0205] In an exemplary embodiment, the shape of the control electrode 31 of the first transistor T1 can be substantially U-shaped (for example, a U-shape rotated 90° clockwise), and the area where the control electrode 31 of the first transistor T1 and the two channel regions of the active layer 21 of the first transistor T1 overlap on the substrate can form a double-gate structure of the first transistor T1; the shape of the control electrode 32 of the second transistor T2 can be L-shaped, and the area where the control electrode 32 of the second transistor T2 and the two channel regions of the active layer 22 of the second transistor T2 overlap on the substrate can form a double-gate structure of the second transistor T2. 2; the control electrode 34 of the fourth transistor T4 and the control electrode 37 of the seventh transistor T7 can be in the shape of a strip extending along the first direction X, the control electrode 34 of the fourth transistor T4 can be integrally formed with the control electrode 32 of the second transistor T2 located in the adjacent sub-pixel column in the same row of sub-pixels, the control electrode 34 of the fourth transistor T4 and the orthographic projection of the channel region of the active layer 24 of the fourth transistor T4 on the substrate have an overlapping area, and the control electrode 37 of the seventh transistor T7 and the orthographic projection of the channel region of the active layer 27 of the seventh transistor T7 on the substrate have an overlapping area.

[0206] In an exemplary embodiment, the first electrode plate 33 may be located between the light-emission control line E and the control electrode 32 of the second transistor T2. The first electrode plate 33 may be rectangular, and the corners of the rectangle may be chamfered. The orthographic projection of the first electrode plate 33 on the substrate overlaps with the orthographic projection of the active layer of the third transistor T3 on the substrate. In an exemplary embodiment, the first electrode plate 33 may serve as both a plate of the storage capacitor and the control electrode of the third transistor T3.

[0207] In an exemplary embodiment, the region where the emission control line E overlaps with the active layer of the fifth transistor T5 serves as the control electrode of the fifth transistor T5 , and the region where the emission control line E overlaps with the active layer of the sixth transistor T6 serves as the control electrode of the sixth transistor T6 .

[0208] In an exemplary embodiment, the shapes of the first conductive layers in a plurality of sub-pixel rows may be the same, and the shapes of the first conductive layers in a plurality of sub-pixel columns may be the same.

[0209] In an exemplary embodiment, the light emission control lines E may be designed with equal widths or unequal widths, which not only facilitates the layout of the pixel structure but also reduces the parasitic capacitance between the signal lines.

[0210] In an exemplary embodiment, after forming the first conductive layer pattern, the semiconductor layer can be conductively processed using the first conductive layer as a shield. The semiconductor layer in the area shielded by the first conductive layer forms the channel region of the first transistor T1 to the seventh transistor T7, and the semiconductor layer in the area not shielded by the first conductive layer is conductively processed, that is, the first region and the second region of the active layer 21 of the first transistor T1 to the active layer 27 of the seventh transistor T7 are both conductively processed.

[0211] (105) Forming a second conductive layer pattern. In an exemplary embodiment, forming the second conductive layer pattern may include: depositing a third insulating film and a second conductive film in sequence on the substrate on which the aforementioned pattern is formed, patterning the second conductive film using a patterning process to form a third insulating layer covering the first conductive layer, and a second conductive layer pattern disposed on the third insulating layer, as shown in Figures 12a and 12b. Figure 12a is a planar structural diagram of three columns of sub-pixels (i.e., three sub-pixels) from the Q1 column to the Q3 column in a row of sub-pixels, and Figure 12b is a planar schematic diagram of the second conductive layer in Figure 12a. In an exemplary embodiment, the second conductive layer may be referred to as a second gate metal (GATE2) layer.

[0212] In an exemplary embodiment, the second conductive layer pattern includes at least: a second plate 41 of the storage capacitor and a first shielding electrode 42. The second plate 41 of the storage capacitor serves as the other plate of the storage capacitor. In the second direction Y, in the same sub-pixel, the first connecting electrode 42 is located on one side of the second plate 41. For example, in the same sub-pixel, the first connecting electrode 42 and the second plate 41 of the storage capacitor are arranged sequentially along the second direction Y.

[0213] In an exemplary embodiment, the outline of the second electrode plate 41 can be rectangular, and the corners of the rectangle can be chamfered. The orthographic projection of the second electrode plate 41 on the substrate overlaps with the orthographic projection of the first electrode plate 33 on the substrate. The first electrode plate 33 and the second electrode plate 41 constitute a storage capacitor of the pixel driving circuit. An opening 43 is provided on the second electrode plate 41, and the opening 43 can be located in the middle of the second electrode plate 41. The opening 43 can be rectangular, so that the second electrode plate 41 forms a ring structure. The opening 43 exposes the third insulating layer covering the first electrode plate 33, and the orthographic projection of the first electrode plate 33 on the substrate includes the orthographic projection of the opening 43 on the substrate. In an exemplary embodiment, the opening 43 is configured to accommodate a ninth via hole formed subsequently. The ninth via hole is located in the opening 43 and exposes the first electrode plate 33, so that the second electrode of the first transistor T1 formed subsequently is connected to the first electrode plate 33.

[0214] In an exemplary embodiment, the shape of the first shielding electrode 42 can be L-shaped. In the same sub-pixel, the first shielding electrode 42 can be integrally formed with the second electrode plate 41. The orthographic projection of the first shielding electrode 42 on the substrate does not overlap with the orthographic projections of the control electrode 31 of the first transistor T1, the control electrode 32 of the second transistor T2, and the control electrode 34 of the fourth transistor T4 on the substrate. In an exemplary embodiment, the shape of the control electrode 31 of the first transistor T1 can be roughly U-shaped and rotated 90° clockwise, the shape of the control electrode 32 of the second transistor T2 can be L-shaped and rotated 90° counterclockwise, and the shape of the first shielding electrode 42 can be L-shaped and rotated 180° counterclockwise. The first shielding electrode 42 can include a first portion 42-1, a second portion 42-2, and a third portion 42-3 that are interconnected. In the same sub-pixel, in the first direction X, the orthographic projection of the first portion 42-1 on the substrate can be located at the control electrode of the second transistor T2. The third portion 42-3 may be located on a side of the second portion 42-2 away from the first portion 42-1. At least a portion of the orthographic projection of the control electrode 32 of the second transistor T2 on the substrate is located between the orthographic projection of the first portion 42-1 and the orthographic projection of the third portion 42-3 on the substrate. In the second embodiment Y, the orthographic projection of the second portion 42-2 on the substrate may be located between the orthographic projection of the control electrode 31 of the first transistor T1 and the orthographic projection of the control electrode 32 of the second transistor T2 on the substrate. The orthographic projection of the third portion 42-3 on the substrate at least partially overlaps with the orthographic projection of the active layer 22 of the second transistor T2 on the substrate, thereby shielding the active layer 22 of the second transistor T2 and improving the stability of the second transistor T2.

[0215] In an exemplary embodiment, in the same sub-pixel row, two adjacent second plates 41 are connected to each other, so that multiple second plates 41 located in the same sub-pixel row have approximately the same potential, which can ensure that the second plates of the storage capacitors of adjacent sub-pixels have the same potential, which is beneficial to improving the uniformity of the panel display, avoiding poor display of the display substrate, and ensuring the display effect of the display substrate.

[0216] In an exemplary embodiment, the shapes of the second conductive layers in a plurality of sub-pixel rows may be the same, and the shapes of the second conductive layers in a plurality of sub-pixel columns may be the same.

[0217] (106) Forming a fourth insulating layer pattern. In an exemplary embodiment, forming the fourth insulating layer pattern may include: depositing a fourth insulating film on the substrate on which the aforementioned pattern is formed, patterning the fourth insulating film using a patterning process to form a fourth insulating layer covering the second conductive layer, wherein a plurality of vias are provided on the fourth insulating layer, as shown in FIG13 , which is a planar structural diagram of three sub-pixels.

[0218] In an exemplary embodiment, the multiple via holes in each sub-pixel include at least a first via hole V1, a second via hole V2, a third via hole V3, a fourth via hole V4, a fifth via hole V5, a sixth via hole V6, a seventh via hole V7, an eighth via hole V8, a ninth via hole V9, a tenth via hole V10, and an eleventh via hole V11.

[0219] In an exemplary embodiment, the orthographic projection of the first via hole V1 on the substrate is located within the range of the orthographic projection of the first initial signal line Vinit1 on the substrate (for example, the orthographic projection of the first via hole V1 on the substrate may be located within the range of the orthographic projection of the first transfer electrode Vinit10 on the first initial signal line Vinit1 on the substrate). The fourth insulating layer, the third insulating layer, and the second insulating layer within the first via hole V1 are etched away, exposing the surface of the first initial signal line Vinit1 (for example, exposing the surface of the first transfer electrode Vinit10 on the first initial signal line Vinit1). The first via hole V1 is configured to electrically connect a subsequently formed first initial signal connection line to the first initial signal line Vinit1 through the via hole.

[0220] In an exemplary embodiment, the orthographic projection of the second via V2 on the substrate is located within the range of the orthographic projection of the second initial signal line Vinit2 on the substrate (for example, the orthographic projection of the second via V2 on the substrate may be located within the range of the orthographic projection of the second transfer electrode Vinit20 on the second initial signal line Vinit2 on the substrate). The fourth insulating layer, the third insulating layer, and the second insulating layer within the second via V2 are etched away, exposing the surface of the second initial signal line Vinit2 (for example, exposing the surface of the second transfer electrode Vinit20 on the second initial signal line Vinit2). The second via V2 is configured to electrically connect a subsequently formed second initial signal connection line to the second initial signal line Vinit2 through the via.

[0221] In an exemplary embodiment, the orthographic projection of the third via V3 on the substrate is located within the orthographic projection of the active layer 22 of the second transistor T2 on the substrate. The fourth insulating layer, the third insulating layer, and the second insulating layer within the third via V3 are etched away, exposing the surface of the first region 22-1 of the active layer 22 of the second transistor T2 (also the second region 21-2 of the active layer 21 of the first transistor T1). The third via V3 is configured to connect the second electrode of the subsequently formed first transistor T1 to the active layer 21 of the first transistor T1 through the via, and to connect the first electrode of the subsequently formed second transistor T2 to the active layer 22 of the second transistor T2 through the via.

[0222] In the exemplary embodiment, the orthographic projection of the fourth via hole V4 on the substrate is located within the orthographic projection of the active layer 24 of the fourth transistor T4 on the substrate. The fourth insulating layer, the third insulating layer, and the second insulating layer within the fourth via hole V4 are etched away, exposing the first region 24-1 of the active layer 24 of the fourth transistor T4. The fourth via hole V4 is configured to connect the first electrode of the subsequently formed fourth transistor T4 to the active layer 24 of the fourth transistor T4 through the via hole.

[0223] In an exemplary embodiment, the orthographic projection of the fifth via hole V5 on the substrate is located within the orthographic projection of the active layer 25 of the fifth transistor T5 on the substrate. The fourth insulating layer, the third insulating layer, and the second insulating layer within the fifth via hole V5 are etched away, exposing the surface of the first region 25-1 of the active layer 25 of the fifth transistor T5. The fifth via hole V5 is configured to connect the first electrode of the subsequently formed fifth transistor T5 to the active layer 25 of the fifth transistor T5 through the via hole.

[0224] In an exemplary embodiment, the orthographic projection of the sixth via V6 on the substrate is located within the orthographic projection of the active layer 26 of the sixth transistor T6 on the substrate. The fourth insulating layer, the third insulating layer, and the second insulating layer within the sixth via V6 are etched away, exposing the surface of the second region 26-2 of the active layer 26 of the sixth transistor T6 (also the second region 27-2 of the active layer 27 of the seventh transistor T7). The sixth via V6 is configured to connect the second electrode of a subsequently formed sixth transistor T6 to the active layer 26 of the sixth transistor T6 through the via, and to connect the second electrode of a subsequently formed seventh transistor T7 to the active layer 27 of the seventh transistor T7 through the via.

[0225] In an exemplary embodiment, the orthographic projection of the seventh via V7 on the substrate is located within the orthographic projection of the control electrode 31 of the first transistor T1 on the substrate. The fourth insulating layer and the third insulating layer within the seventh via V7 are etched away, exposing the surface of the control electrode 31 of the first transistor T1. The seventh via V7 is configured to connect a subsequently formed first reset control line to the control electrode 31 of the first transistor T1 through the via.

[0226] In an exemplary embodiment, the orthographic projection of the eighth via V8 on the substrate is located within the orthographic projection of the control electrode 32 of the second transistor T2 on the substrate. The fourth insulating layer and the third insulating layer within the eighth via V8 are etched away, exposing the surface of the control electrode 32 of the second transistor T2. The eighth via V8 is configured to connect a subsequently formed scan signal line to the control electrode 32 of the second transistor T2 through the via.

[0227] In an exemplary embodiment, the orthographic projection of the ninth via V9 on the substrate is located within the orthographic projection of the control electrode 37 of the seventh transistor T7 on the substrate. The fourth insulating layer and the third insulating layer within the ninth via V9 are etched away, exposing the surface of the control electrode 37 of the seventh transistor T7. The ninth via V9 is configured to connect a subsequently formed first reset control line to the control electrode 37 of the seventh transistor T7 through the via.

[0228] In the exemplary embodiment, the orthographic projection of the tenth via hole V10 on the substrate is within the range of the orthographic projection of the opening 44 on the substrate. The fourth insulating layer and the third insulating layer within the tenth via hole V10 are etched away, exposing the surface of the first electrode plate 33. The tenth via hole V10 is configured to connect the second electrode of the subsequently formed first transistor T1 (which is also the first electrode of the second transistor T2) to the first electrode plate 33 through the via hole.

[0229] In an exemplary embodiment, the eleventh via hole V11 is located within the orthographic projection of the second electrode plate 41 on the substrate. The fourth insulating layer within the eleventh via hole V11 is etched away, exposing the surface of the second electrode plate 41. The eleventh via hole V11 is configured to connect a subsequently formed first power connection line to the second electrode plate 41 through the via hole. In an exemplary embodiment, a plurality of eleventh via holes V11 serving as power via holes may be included, and the plurality of eleventh via holes V11 may be arranged sequentially along the second direction Y or the first direction X to increase the reliability of the connection between the first power connection line and the second electrode plate 41.

[0230] In an exemplary embodiment, the fourth insulation layer pattern may further include a power transfer via located in the border area 300. As shown in FIG8c, the first power signal supply line VDD0 (formed subsequently) located in the border area 300 can be electrically connected to the shielding transfer line BSML located in the border area 300 in the shielding layer BSM through the power transfer via.

[0231] (107) Forming a third conductive layer pattern. In an exemplary embodiment, forming the third conductive layer pattern may include: depositing a third conductive film on the substrate on which the aforementioned pattern is formed, patterning the third conductive film using a patterning process, and forming a third conductive layer pattern disposed on the fourth insulating layer, as shown in Figures 14a to 14c. Figure 14a is a planar structural diagram of three columns of sub-pixels (i.e., three sub-pixels) from the Q1 column to the Q3 column in a row of sub-pixels, Figure 14b is a planar schematic diagram of the third conductive layer in Figure 14a, and Figure 14c is a planar structural diagram of three columns of sub-pixels (i.e., three sub-pixels) from the N1 column to the N3 column in a row of sub-pixels. In an exemplary embodiment, the third conductive layer may be referred to as a first source / drain metal (SD1) layer.

[0232] In an exemplary embodiment, the third conductive layer pattern includes at least: a first reset control line Reset1, a scan signal line Gate, a second reset control line Reset2, a first power connection line VDDL, a first connection electrode 51, a second connection electrode 52, a third connection electrode 54, a fourth connection electrode 54, a fifth connection electrode 55, a first power signal supply line VDD0, and a second power line VSS. The main portions of the scan signal line Gate, the first reset control line Reset1, the second reset control line Reset2, and the first power connection line VDDL may extend along the first direction X. In the same row of sub-pixels, the first reset control line Reset1, the scan signal line Gate, the first power connection line VDDL, and the second reset control line Reset2 may be arranged sequentially along the second direction Y.

[0233] In an exemplary embodiment, the first reset control line Reset1 can be configured to be electrically connected to the control electrodes 31 of the multiple first transistors T1 in a row of sub-pixels through multiple seventh vias V7, so that a first reset control signal can be provided to the multiple first transistors T1 in a row of sub-pixels; the scan signal line Gate can be configured to be electrically connected to the control electrodes 32 of the multiple second transistors T2 in a row of sub-pixels through the eighth via V8. Since the control electrodes 32 of the second transistors T2 and the control electrodes 34 of the fourth transistors T4 are interconnected, the scan signal line Gate can provide scan signals to the multiple second transistors T2 and the multiple fourth transistors T4 in a row of sub-pixels; the second reset control line Reset2 can be configured to be electrically connected to the control electrodes 37 of the multiple seventh transistors T7 in a row of sub-pixels through the multiple ninth vias V9, so that a second reset control signal can be provided to the multiple seventh transistors T7 in a row of sub-pixels.

[0234] In an exemplary embodiment, a plurality of power connection electrodes 56 may be provided on the first power connection line VDDL. In the second direction Y, the plurality of power connection electrodes 56 may be provided on a side of the first power connection line VDDL away from the scanning signal line Gate. The shape of the power connection electrode 56 may be roughly a zigzag line extending along the second direction Y. The power connection electrode 56 may be configured to be electrically connected to the active layer 25 of the plurality of fifth transistors T5 in a row of sub-pixels through a plurality of sixth vias V6, and to be electrically connected to the plurality of second electrodes 41 in a row of sub-pixels through a plurality of eleventh vias V11, so that the first power connection line VDDL may provide a first power signal to the plurality of fifth transistors T5 and the plurality of second electrodes 41 in a row of sub-pixels, so that the second electrodes 41 and the first electrodes of the fifth transistors T1 have substantially the same potential.

[0235] In an exemplary embodiment, the shapes of the first connecting electrode 51 and the second connecting electrode 52 can be roughly rectangular, the first connecting electrode 51 can be connected to the first initial signal line Vinit1 through the first via V1 (for example, connected to the first switching electrode Vinit10 provided on the first initial signal line Vinit1), and the second connecting electrode 52 can be connected to the second initial signal line Vinit2 through the second via V2 (for example, connected to the second switching electrode Vinit20 provided on the second initial signal line Vinit2).

[0236] In an exemplary embodiment, the third connection electrode 53 may be shaped like a zigzag extending substantially along the second direction Y. One end of the third connection electrode 53 is connected to the first region 22-1 of the active layer 22 of the second transistor T2 (also the second region 21-2 of the active layer 21 of the first transistor T1) via a third via V3, and the other end is connected to the first electrode plate 33 of the storage capacitor via a tenth via V10. This allows the first electrode plate 33, the second electrode of the first transistor T1, and the first electrode of the second transistor T2 to have the same potential. In an exemplary embodiment, the third connection electrode 53 may serve as the second electrode of the first transistor T1 and the first electrode of the second transistor T2. In the same sub-pixel row, multiple third connection electrodes 53 may be located between the first power connection line VDDL and the scan signal line Gate in the second direction Y.

[0237] In an exemplary embodiment, the fourth connection electrode 54 may be shaped like a zigzag line extending substantially along the second direction Y. The fourth connection electrode 54 may be connected to the first region 24-1 of the active layer 24 of the fourth transistor T4 via a fourth via hole V4. In an exemplary embodiment, the fourth connection electrode 54 may serve as the first electrode of the fourth transistor T4. In the same sub-pixel row, multiple fourth connection electrodes 54 may be located between the first reset control line Reset1 and the scan signal line Gate in the second direction Y.

[0238] In an exemplary embodiment, the fifth connection electrode 55 may be substantially rectangular in shape and may be connected to the second region 26-2 of the active layer 26 of the sixth transistor T6 (also the second region 27-2 of the active layer 27 of the seventh transistor T7) via a fourth fifth via hole V5. In an exemplary embodiment, the fifth connection electrode 55 may serve as the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7. In an exemplary embodiment, within a row of sub-pixels, the fifth connection electrode 55 may be located between the main portion of the first power connection line VDDL and the second reset control line Reset2 in the second direction Y. A plurality of fifth connection electrodes 55 and a plurality of power connection electrodes 56 may be arranged alternately along the first direction X.

[0239] In an exemplary embodiment, as shown in FIG14c , it is a schematic diagram of the planar structure of three columns of sub-pixels (the N1 column, the N2 column, and the N3 column) located on the side of the Q1 column of sub-pixels away from the Q2 column of sub-pixels in the first direction X. In an exemplary embodiment, FIG14c differs from FIG14a in that the first connecting electrode 51 and the second connecting electrode 52 are not provided in the third conductive layer.

[0240] In an exemplary embodiment, as shown in FIG5a and FIG8a, the first power signal supply line VDD0 may be located in the bezel area 300 and disposed around the display area 100. The first power signal supply line VDD0 may be integrally formed with the first power connection line VDDL located in the display area 100. In a plane parallel to the display substrate, the second power line VSS is located on a side of the first power signal supply line VDD0 away from the display area 100.

[0241] (108) Forming a fifth insulating layer and a first planar layer pattern. In an exemplary embodiment, forming the fifth insulating layer pattern and the first planar layer pattern may include: depositing a fifth insulating film on the substrate on which the aforementioned pattern is formed, then coating the first planar film, patterning the first planar film and the first planar film using a patterning process to form a fifth insulating layer covering the third conductive layer and a first planar layer disposed on the fifth insulating layer, wherein a plurality of vias are disposed on the fifth insulating layer and the first planar layer, as shown in FIG15 , which is a planar structural diagram of three sub-pixels.

[0242] In an exemplary embodiment, the plurality of via holes in each sub-pixel include at least a twelfth via hole V12 , a thirteenth via hole V13 , a fourteenth via hole V14 , a forty-fifth via hole V15 , a sixteenth via hole V16 , and a seventeenth via hole V17 .

[0243] In an exemplary embodiment, the orthographic projection of the twelfth via hole V12 on the substrate is located within the range of the orthographic projection of the first connection electrode 51 on the substrate. The fifth insulating layer and the first planar layer within the twelfth via hole V12 are etched away, exposing the surface of the first connection electrode 51. The twelfth via hole V12 is configured to allow a subsequently formed first initial signal connection line to be connected to the first connection electrode 51 through the via hole.

[0244] In an exemplary embodiment, the orthographic projection of the thirteenth via hole V13 on the substrate is located within the range of the orthographic projection of the second connection electrode 52 on the substrate. The fifth insulating layer and the first planar layer within the thirteenth via hole V13 are etched away, exposing the surface of the second connection electrode 52. The thirteenth via hole V13 is configured to allow a subsequently formed second initial signal connection line to be connected to the second connection electrode 52 through the via hole.

[0245] In an exemplary embodiment, the orthographic projection of the fourteenth via V14 on the substrate is within the range of the orthographic projection of the fourth connection electrode 54 on the substrate. The fifth insulating layer and the first planar layer within the fourteenth via V14 are etched away, exposing the surface of the fourth connection electrode 54. The fourteenth via V14 is configured to allow a subsequently formed data signal line to be connected to the fourth connection electrode 54 through the via. In an exemplary embodiment, the orthographic projection of the fifteenth via V15 on the substrate is within the range of the orthographic projection of the first power connection line VDDL (e.g., the first power connection electrode 56 on the first power connection line VDDL) on the substrate. The fifth insulating layer and the first planar layer within the fifteenth via V15 are etched away, exposing the surface of the first power connection line VDDL. The fifteenth via V15 is configured to allow a subsequently formed first power line to be connected to the first power connection line VDDL through the via.

[0246] In an exemplary embodiment, the orthographic projection of the sixteenth via hole V16 on the substrate is located within the range of the orthographic projection of the fifth connection electrode 55 on the substrate. The fifth insulating layer and the first planar layer within the sixteenth via hole V16 are etched away, exposing the surface of the fifth connection electrode 55. The sixteenth via hole V16 is configured to connect a subsequently formed anode connection electrode to the fifth connection electrode 55 through the via hole.

[0247] (109) Forming a fourth conductive layer pattern. In an exemplary embodiment, forming the fourth conductive layer may include: depositing a fourth conductive film on the substrate on which the aforementioned pattern is formed, patterning the fourth conductive film using a patterning process, and forming a fourth conductive layer disposed on the sixth insulating layer, as shown in Figures 16a to 16d, Figure 16a is a planar structural diagram of three columns of sub-pixels (i.e., three sub-pixels) from the Q1 column to the Q3 column in a row of sub-pixels, Figure 16b is a planar schematic diagram of the fourth conductive layer in Figure 16a, Figure 16c is a planar structural diagram of three columns of sub-pixels (i.e., three sub-pixels) from the N1 column to the N3 column in a row of sub-pixels, and Figure 16d is a planar schematic diagram of the fourth conductive layer in Figure 16c. In an exemplary embodiment, the fourth conductive layer may be referred to as a second source / drain metal (SD2) layer.

[0248] In an exemplary embodiment, the fourth conductive layer includes at least: a first power line VDD, a data signal line D, a first initial signal connection line 61, a second initial signal connection line 62, an anode connection electrode 63, a second power connection line VSSL, a second power line VSS, a second power adapter line VSSZ1, and a drive signal connection line GOAL. In an exemplary embodiment, anode connection electrode 63 is an anode connection electrode for a light-emitting element.

[0249] In an exemplary embodiment, the data signal line D may be in a zigzag or bar shape, with a main portion extending along the second direction Y. The data signal line D is connected to the fourth connection electrode 54 through a fourteenth via hole V14. Since the fourth connection electrode 54 is connected to the first region 24-1 of the active layer 24 of the fourth transistor T4 through the via hole, the data signal line D is connected to the first electrode of the fourth transistor T4, thereby writing the data signal into the fourth transistor T4.

[0250] In an exemplary embodiment, the first power line VDD may be in the shape of a zigzag line with a main portion extending along the second direction Y. The first power line VDD may be connected to the first power connection line VDDL via a fifteenth via hole V15. Since the first power connection line VDD is connected to the second electrode plate 41 via the via hole, the first power line VDD is connected to the second electrode plate 41, and the power signal is written to the second electrode plate 41. Since the first power connection line VDDL is connected to the first region 25-1 of the active layer 25 of the fifth transistor T5 via the via hole, the first power line VDD is connected to the first electrode of the fifth transistor T5, and the power signal is written to the fifth transistor T5.

[0251] In an exemplary embodiment, the first initial signal connection line 61 may be in the shape of a zigzag line with a main portion extending along the second direction Y. The first initial signal connection line 61 may be connected to the first connection electrode 51 through a twelfth via hole V12. Since the first connection electrode 51 is connected to the first initial signal line Vinit1 through the via hole, the first initial signal connection line 61 is connected to the first initial signal line Vinit1. Since the first initial signal connection line 61 can be electrically connected to multiple first initial signal lines Vinit1 arranged along the second direction Y, the initial signals provided by the multiple first initial signal lines Vinit1 can be substantially the same. Since the first initial signal line Vinit1 is connected to the first region 21-1 of the first transistor T1, the initial signals obtained by the first transistor T1 in multiple rows of sub-pixels can be substantially consistent, which is beneficial for improving display uniformity of the display substrate.

[0252] In an exemplary embodiment, the second initial signal connection line 62 may be in the shape of a zigzag line with a main portion extending along the second direction Y. The second initial signal connection line 62 may be connected to the second connection electrode 52 via a thirteenth via hole V13. Since the second connection electrode 52 is connected to the second initial signal line Vinit2 via the via hole, the second initial signal connection line 62 is connected to the second initial signal line Vinit2. Since the second initial signal connection line 62 can be electrically connected to multiple second initial signal lines Vinit2 arranged along the second direction Y, the initial signals provided by the multiple second initial signal lines Vinit2 can be substantially the same. Since the second initial signal line Vinit2 is connected to the first region 27-1 of the seventh transistor T7, the initial signals obtained by the seventh transistor T7 in multiple rows of sub-pixels can be substantially consistent, which is beneficial for improving display uniformity of the display substrate.

[0253] In an exemplary embodiment, the anode connection electrode 63 may be connected to the fifth connection electrode 55 through a sixteenth via hole V16. Since the fifth connection electrode 55 is connected to the second region 26-2 of the active layer 26 of the sixth transistor T6 (also the second region 27-2 of the active layer 27 of the seventh transistor T7) through the via hole, the anode connection electrode 63 is connected to the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7.

[0254] In an exemplary embodiment, as shown in Figures 16c to 16e, the second power connection line VSSL may be in the shape of a zigzag line extending along the second direction Y. In an exemplary embodiment, the second power connection line VSSL, the first initial signal connection line 61, and the second initial signal connection line 62 may be arranged in a periodic pattern along the first direction X. Within one period, one column of pixel units may be spaced between the second power connection line VSSL and the first initial signal connection line 61, and one column of pixel units may be spaced between the first initial signal connection line 61 and the second initial signal connection line 62. In the first direction X, the second power connection line VSSL may be located between two adjacent columns of pixel units, the first initial signal connection line 61 may be located between two adjacent columns of pixel units, and the second initial signal connection line 62 may be located between two adjacent columns of pixel units. The embodiments of the present disclosure are not limited to this arrangement. For example, the second power connection line VSSL, the first initial signal line 61, and the second initial signal line 62 may be located between two adjacent columns of sub-pixels, such as between two adjacent columns of sub-pixels in a pixel unit column.

[0255] In an exemplary embodiment, as shown in FIG6e , within one cycle, three pixel units may be spaced between two adjacent second power connection lines VSSL, three pixel units may be spaced between two adjacent first initial signal connection lines 61, and three pixel units may be spaced between two adjacent second initial signal connection lines 62. That is, within one cycle, the number of second power connection lines VSSL: the number of first initial signal connection lines 61: the number of second initial signal connection lines 62 is 1:1:1, and the second power connection lines VSSL, the first initial signal connection lines 61, and the second initial signal connection lines 62 may be arranged sequentially along the first direction X. In an exemplary embodiment, in the first direction X, the periodic distance between the second power connection lines VSSL, the first initial signal connection lines 61, and the second initial signal connection lines 62 is not limited to three pixel units, and may be more than three pixel units. For example, the periodic distance may be four pixel units or 3.5 pixel units, but this disclosure is not limited thereto.

[0256] In an exemplary embodiment, within one cycle, the number of the second power connection lines VSSL: the number of the first initial signal connection lines 61: the second initial signal connection lines 62 is 2:2:1. Within one cycle, the first initial signal connection line 61, the second initial signal connection line 62, the second power connection line VSSL, the first initial signal connection line 61, and the second initial signal connection line 62 can be arranged in sequence along the first direction X. The distance of one cycle can be, but is not limited to, five pixel units.

[0257] In an exemplary embodiment, the second power line VSS located in the fourth conductive layer can be electrically connected to the second power line VSS located in the third conductive layer through a via to form a double-layer structure, or the second power line VSS located in the fourth conductive layer can be directly electrically connected to the second power line VSS located in the third conductive layer to form a double-layer structure, and the orthographic projections of the second power line VSS located in the fourth conductive layer and the second power line VSS located in the third conductive layer on the substrate at least partially overlap; as shown in Figures 5a and 5b, in a direction parallel to the plane where the display substrate is located, the second power adapter line VSSZ1 can be located between the second power line VSS and the first power signal supply line VDD0, and the drive signal connection line GOAL can be located between the first power signal supply line VDD0 and the second power adapter line VSSZ1. In an exemplary embodiment, as shown in Figures 5a and 5b, the driving signal connection line GOAL can be set in the second border B2, the first conductive layer or the second conductive layer can also be provided with a driving signal line GOAL0, the driving signal line GOAL0 can be set in the third border area B3 and the fourth border area B4, and the driving signal connection line GOAL can electrically connect the same driving signal lines GOAL0 located in the third border area B3 and the fourth border area B4 through vias to improve display uniformity.

[0258] (110) Forming a second planar layer pattern. In an exemplary embodiment, forming the second planar layer pattern may include: coating a second planar film on the substrate on which the aforementioned pattern is formed, patterning the second planar film using a patterning process to form a second planar layer covering the fourth conductive layer pattern, wherein a plurality of via holes are provided on the second planar layer, as shown in FIG17 , which is a planar structural diagram of three sub-pixels.

[0259] In an exemplary embodiment, the plurality of via holes in each sub-pixel includes at least a seventeenth via hole V17 , a second power first transfer via hole, and a second power second transfer via hole.

[0260] In an exemplary embodiment, the orthographic projection of the seventeenth via hole V17 on the substrate is within the range of the orthographic projection of the anode connection electrode 63 on the substrate. The second planar layer within the seventeenth via hole V17 is etched away, exposing the surface of the anode connection electrode 63. The seventeenth via hole V17 is configured to connect a subsequently formed anode to the anode connection electrode 63 through the via hole.

[0261] In an exemplary embodiment, as shown in FIG8c , the orthographic projection of the second power first transfer via on the substrate at least partially overlaps with the orthographic projection of the second power line VSS on the substrate, and the orthographic projection of the second power second transfer via on the substrate at least partially overlaps with the orthographic projection of the second power transfer wire VSSZ1 on the substrate, so that the subsequently formed second power transfer electrode VSSZ2 can be electrically connected to the second power line VSS and the second power transfer wire VSSZ1 through the second power first transfer via and the second power second transfer via, respectively.

[0262] At this point, the circuit structure layer can be prepared. In an exemplary embodiment, after the circuit structure layer is prepared, a light-emitting structure layer is prepared on the circuit structure layer. The preparation process of the light-emitting structure layer may include the following operations: forming an anode pattern (i.e., an anode conductive layer), the anode is connected to the anode connection electrode through an anode via (which may be the above-mentioned seventeenth via V17); forming a pixel definition layer, the pixel definition layer is provided with a pixel opening, and the pixel opening exposes the anode; forming an organic light-emitting layer by evaporation or inkjet printing process, the organic light-emitting layer is connected to the anode through the pixel opening, and a cathode is formed on the organic light-emitting layer; forming an encapsulation layer, the encapsulation layer may include a stacked first encapsulation layer, a second encapsulation layer and a third encapsulation layer, the first encapsulation layer and the third encapsulation layer may be made of inorganic materials, the second encapsulation layer may be made of organic materials, and the second encapsulation layer is provided between the first encapsulation layer and the third encapsulation layer, which can ensure that external water vapor cannot enter the light-emitting structure layer. The steps for forming the anode conductive layer and the pixel definition layer are as follows:

[0263] (111) Forming an anode conductive layer pattern. In an exemplary embodiment, forming the anode conductive layer may include: depositing an anode conductive film on the substrate having the aforementioned pattern formed thereon, and patterning the anode conductive film using a patterning process to form an anode conductive layer disposed on the second flat layer, as shown in FIG18 , which is a planar structural diagram of three sub-pixels.

[0264] In an exemplary embodiment, the anode conductive layer includes at least: anodes 71 of a plurality of light emitting elements and a second power switching electrode VSSZ2 .

[0265] In an exemplary embodiment, the anode 71 can be a roughly rectangular structure, and the anode 71 is connected to the anode connecting electrode 63 through the seventeenth via V17. Since the anode connecting electrode 63 is connected to the second area 26-2 of the active layer 26 of the sixth transistor T6 (also the second area 27-2 of the active layer 27 of the seventh transistor T7) through the via, the anode 71 can be connected to the second area 26-2 of the active layer 26 of the sixth transistor T6 (also the second area 27-2 of the active layer 27 of the seventh transistor T7).

[0266] In an exemplary embodiment, as shown in Figure 8c, the orthographic projection of the second power supply switching electrode VSSZ2 on the substrate at least partially overlaps with the orthographic projection of the second power supply line VSS and the second power supply switching line VSSZ1 on the substrate, and the second power supply switching electrode VSSZ2 can be electrically connected to the second power supply line VSS and the second power supply switching line VSSZ1 through the second power supply first switching via and the second power supply second switching via, respectively.

[0267] (112) Forming a pixel definition layer pattern. In some examples, a pixel definition layer film is coated on the substrate having the aforementioned pattern, and a mask, exposure, and development process are performed to form the pixel definition layer. The pixel definition layer may be formed with a plurality of pixel openings 81 exposing the anode layer and cathode transfer vias.

[0268] Figure 19 is a schematic diagram after forming the pixel definition layer. The orthographic projection of the pixel opening 81 on the substrate is located within the orthographic projection of the corresponding anode 71 on the substrate. In an exemplary embodiment, the first pixel opening 811 can be deposited with a luminescent material that emits red light, the second pixel opening 812 can be deposited with a luminescent material that emits green light, and the third pixel opening 813 can be deposited with a luminescent material that emits blue light. In other words, the first pixel opening 811 corresponds to a light-emitting element that emits red light, the second pixel opening 812 corresponds to a light-emitting element that emits green light, and the third pixel opening 813 corresponds to a light-emitting element that emits blue light.

[0269] In an exemplary embodiment, the first initial signal line Vinit1 and the second initial signal line Vinit2 are not limited to being set in the semiconductor layer. For example, as shown in Figure 20, the first initial signal line Vinit1 and the second initial signal line Vinit2 can be set in the third conductive layer; as shown in Figure 21, the first initial signal line Vinit1 and the second initial signal line Vinit2 can be set in the second conductive layer.

[0270] In an exemplary embodiment, as shown in FIG8c , the positive projection of the cathode switching via on the substrate at least partially overlaps with the positive projection of the cathode layer and the second power switching electrode VSSZ2 on the substrate, so that the subsequently formed cathode layer is electrically connected to the second power switching electrode VSSZ2 through the cathode switching via.

[0271] In an exemplary embodiment, taking three sub-pixels (one sub-pixel row and three sub-pixel columns) in the display area (AA) as an example, another preparation process of a display substrate may include the following operations.

[0272] (201) Prepare a substrate on a glass carrier. The preparation method is the same as that of (101) above and will not be repeated here.

[0273] (202) A shielding layer pattern is formed. The preparation method is the same as that of (102) above and will not be repeated here. The shielding layer pattern formed is shown in FIG22. The difference between FIG22 and FIG9 is that the second connecting structure 120 and the third connecting structure 130 can be in the shape of a broken line extending along the second direction Y; the fourth shielding structure 14 can be formed without being integrally formed with the second shielding structure 12.

[0274] (203) Forming a semiconductor layer pattern. The preparation method is the same as that of (103) above and will not be repeated here. The formed semiconductor layer is shown in Figures 23a and 23b. Figure 23a is a schematic diagram of the structure after the layered semiconductor layer, and Figure 23b is a schematic diagram of the semiconductor layer in Figure 23a. The difference between Figures 23a and 23b and Figures 10a and 10b is that the semiconductor layer is not provided with the first initial signal line Vinit1 and the second initial signal line Vinit2; the active layer 23 of the third transistor T3 is provided with a strip structure extending along the first direction X.

[0275] (204) A first conductive layer pattern is formed. The preparation method is the same as that of (104) above and will not be repeated here. The formed semiconductor layer is shown in Figures 24a and 24b.

[0276] (205) A second conductive layer pattern is formed. The preparation method is the same as that of (105) above and will not be repeated here. The formed second conductive layer pattern is shown in Figures 25a and 25b. Figure 25a shows a planar structure diagram of three sub-pixels, and Figure 25b is a structural diagram of the second conductive layer in Figure 25a. The difference between Figures 25a and 25b and Figures 12a and 12b is that: a first initial signal line Vinit1 and a second initial signal line Vinit2 are newly added. In the second direction Y, the first initial signal line Vinit1 and the second initial signal line Vinit2 are located on both sides of the second electrode 41. For example, in the same sub-pixel, the first initial signal line Vinit1, the second electrode 41, and the second initial signal line Vinit2 can be arranged in sequence along the second direction Y, and the first initial signal line Vinit1 and the second initial signal line Vinit2 can extend along the first direction X.

[0277] (206) A fourth insulating layer pattern is formed. The preparation method is the same as that of (106) above and will not be repeated here. The fourth insulating layer pattern formed is shown in FIG26 , which is a planar structural diagram of three sub-pixels. The difference between FIG26 and FIG13 is that the first connecting via VL1 to the fourth connecting via VL2 are newly added. The orthographic projection of the first connecting via VL1 on the substrate at least partially overlaps with the orthographic projection of the active layer 21 of the first transistor T1 on the substrate, the orthographic projection of the second connecting via VL2 on the substrate at least partially overlaps with the orthographic projection of the first initial signal line Vinit1 on the substrate, the orthographic projection of the third connecting via VL3 on the substrate at least partially overlaps with the orthographic projection of the active layer 27 of the seventh transistor T7 on the substrate, and the orthographic projection of the fourth connecting via VL4 on the substrate at least partially overlaps with the orthographic projection of the second initial signal line Vinit2 on the substrate.

[0278] (207) A third conductive layer pattern is formed. The preparation method is the same as that of (107) above and will not be repeated here. The formed third conductive layer pattern is shown in Figures 27a and 27b. Figure 27a shows a planar structure diagram of three sub-pixels, and Figure 27b is a structural diagram of the third conductive layer in Figure 27a. The difference between Figures 27a and 27b and Figures 14a and 14b is that the first connecting electrode 51 and the second connecting electrode 52 are not provided; and the seventh connecting electrode 57 and the eighth connecting electrode 58 are added. Among them, the seventh connection electrode 57 can be a zigzag structure extending along the first direction X, one end of which is connected to the first area 21-1 of the active layer 21 of the first transistor T1 through the first connection via VL1, and the other end is connected to the first initial signal line Vinit1 through the second connection via VL2; the eighth connection electrode 58 can be roughly a zigzag structure extending along the second direction Y, one end of which is connected to the first area 27-1 of the active layer 27 of the seventh transistor T7 through the third connection via VL3, and the other end is connected to the second initial signal line Vinit2 through the fourth connection via VL4.

[0279] (208) Forming a fifth insulating layer and a first flat layer pattern. The preparation method is the same as that of the above (108) and will not be repeated here. The formed fifth insulating layer and first flat layer pattern are shown in FIG28, which is a planar structure diagram of three sub-pixels. The difference between FIG28 and FIG15 is that the orthographic projection of the twelfth via hole V12 on the substrate at least partially overlaps with the orthographic projection of the seventh connecting electrode 57 on the substrate, and the orthographic projection of the thirteenth via hole V13 (not shown in FIG28) on the substrate at least partially overlaps with the orthographic projection of the eighth connecting electrode 58 on the substrate.

[0280] (209) A fourth conductive layer pattern is formed. The preparation method is the same as that of (108) above and will not be repeated here. The formed third conductive layer pattern is shown in Figures 29a and 29b. Figure 29a shows a planar structure diagram of three sub-pixels, and Figure 29b shows a structural diagram of the third conductive layer in Figure 29a.

[0281] In an exemplary embodiment, after the driving circuit layer is prepared, a light-emitting structure layer is prepared on the driving circuit layer, and the preparation process of the light-emitting structure layer may include the following operations. A second flat layer pattern is formed, and at least an anode via is provided on the second flat layer. An anode pattern is formed, and the anode is connected to the anode connection electrode through the anode via. An anode pixel definition layer is formed, and a pixel opening is provided on the pixel definition layer, and the pixel opening exposes the anode. An organic light-emitting layer is formed by an evaporation or inkjet printing process, and a cathode is formed on the organic light-emitting layer. An encapsulation layer is formed, and the encapsulation layer may include a first encapsulation layer, a second encapsulation layer and a third encapsulation layer stacked together. The first encapsulation layer and the third encapsulation layer may be made of inorganic materials, and the second encapsulation layer may be made of organic materials. The second encapsulation layer is arranged between the first encapsulation layer and the third encapsulation layer to ensure that external water vapor cannot enter the light-emitting structure layer.

[0282] In an exemplary embodiment, the subsequent operations of forming a second flat layer pattern, forming an anode conductive layer pattern, and forming a pixel definition layer pattern can be the same as the above-mentioned step (110), step (111), and step (112), respectively, and the embodiments of the present disclosure will not be repeated here.

[0283] The structure and preparation process shown above in the embodiment of the present disclosure are merely exemplary descriptions. In exemplary implementations, the corresponding structure can be changed and the patterning process can be increased or decreased according to actual needs. The display substrate of the embodiment of the present disclosure can be applied to other display devices with pixel driving circuits, such as quantum dot displays, etc., and the present disclosure does not limit this.

[0284] The present disclosure also provides a display device comprising the display substrate of any of the aforementioned embodiments. The display device can be any product or component with a display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigation system, or a vehicle-mounted display.

[0285] In the display substrate and display device provided by the embodiments of the present disclosure, at least one second power connection line in the display substrate is located in the display area and extends to two opposite sides of the display area, and is electrically connected to a second power line located on at least one side of the display area. This can reduce the voltage drop of the second power line, making the second power signals at different positions on the second power line as consistent as possible, thereby improving display uniformity.

[0286] The drawings of the embodiments of the present disclosure only involve the structures involved in the embodiments of the present disclosure, and other structures may refer to general designs.

[0287] In the absence of conflict, the embodiments of the present disclosure, i.e., features in the embodiments, can be combined with each other to form new embodiments.

[0288] Although the embodiments disclosed in the present disclosure are as described above, the contents are only embodiments adopted to facilitate understanding of the embodiments of the present disclosure and are not intended to limit the embodiments of the present disclosure. Any person skilled in the art in the field to which the embodiments of the present disclosure belong may make any modifications and changes in the form and details of implementation without departing from the spirit and scope disclosed in the embodiments of the present disclosure, but the scope of patent protection of the embodiments of the present disclosure shall still be based on the scope defined by the attached claims.

Claims

1. A display substrate, comprising a substrate, a second power line and at least one second power connection line arranged on one side of the substrate, wherein the substrate comprises a display area and a frame area, and on a plane parallel to the display substrate, the frame area is located around the display area, the second power line is arranged in the frame area and is at least located on two opposite sides of the display area; the at least one second power connection line is located in the display area and extends to two opposite sides of the display area, and is electrically connected to the second power line located on at least one side of the display area.

2. The display substrate according to claim 1 further includes a second power transfer electrode and a second power transfer line located in the border area, and on a plane parallel to the display substrate, the second power transfer line is located between the display area and the second power line, and the second power connection line is connected to the second power transfer line. In a direction perpendicular to the plane where the display substrate is located, the second power transfer electrode is located on the side of the second power connection line and the second power line away from the substrate, and the second power line and the second power transfer line are electrically connected through the second power transfer electrode.

3. The display substrate according to claim 2, wherein: The orthographic projection of the second power switching electrode on the substrate at least partially overlaps with the orthographic projections of the second power switching line and the second power line on the substrate, and the second power switching electrode is electrically connected to the second power line and the second power switching line through vias, respectively.

4. The display substrate according to claim 2, wherein: The frame area includes a first frame area and a second frame area located on both sides of the display area along the second direction, and a third frame area and a fourth frame area located on both sides of the display area along the first direction, the second frame area is provided with at least one driving signal connection line, the third frame area and the fourth frame area are respectively provided with at least one driving signal line, the same driving signal lines located in the third frame area and the fourth frame area are electrically connected through one of the driving signal connection lines, on a plane parallel to the display substrate, the driving signal connection line is located between the second power line and the second power adapter line, the driving signal line is located between the second power line and the display area, and the first direction intersects with the second direction.

5. The display substrate according to claim 4, wherein: The border area also includes a binding area, and on a plane parallel to the display substrate, the binding area is located on one side of the display area, the second power line is located at least in the binding area and on a side of the display area away from the binding area, and the at least one second power connection line extends from the binding area to the display area; the binding area is located in the first border area, and the second power transfer electrode and the second power transfer line are located in the first border area and the second border area.

6. The display substrate according to claim 4 further includes a first power signal supply line, and in a direction parallel to the plane where the display substrate is located, the first power signal supply line is arranged in the border area and is located at the periphery of the display area, in the first border area or the second border area, the first power signal supply line is located between the second power adapter line and the display area, and in the third border area or the fourth border area, the first power signal supply line is located between the drive signal line and the display area.

7. The display substrate according to claim 6, further comprising a plurality of first power connection lines and a plurality of first power lines located in the display area, the display area further comprising a plurality of sub-pixels arranged in an array, the plurality of first power connection lines extending along the first direction and arranged at intervals along the second direction, the plurality of first power lines extending along the second direction and arranged at intervals along the first direction; The two ends of the first power connection line are electrically connected to the first power signal supply lines located at the third frame and the fourth frame, respectively, and the middle part of the first power connection line is electrically connected to at least one row of sub-pixels; in a direction perpendicular to the plane where the display substrate is located, the first power line is located on the side of the first power connection line and the first power signal supply line away from the substrate, the middle part of the first power line is electrically connected to the multiple first power lines, and the two ends are electrically connected to the first power signal supply lines located in the first frame area and the second frame area, respectively.

8. The display substrate according to claim 6, wherein: In the second direction, the sizes of the first power signal supply line and the second power line are both larger than the size of the second power adapter line.

9. The display substrate according to any one of claims 4 to 8, further comprising an anode conductive layer and a cathode layer, wherein in a direction perpendicular to the plane where the display substrate is located, the cathode layer is located on a side of the anode conductive layer away from the substrate; the second power switching electrode is located on the anode conductive layer, and its orthographic projection on the substrate at least partially overlaps with the orthographic projection of the cathode layer on the substrate, and the second power switching electrode is electrically connected to the cathode layer.

10. The display substrate according to claim 1, wherein: The number of the second power connection lines is multiple, the display area includes multiple sub-pixels arranged in an array, the multiple second power connection lines are arranged along the row direction and extend along the column direction, at least one second power connection line is arranged between two adjacent columns of sub-pixels, and on a plane parallel to the display substrate, the row direction intersects with the column direction.

11. The display substrate according to claim 10, wherein: The display area also includes multiple initial signal lines and multiple initial signal connecting lines, the multiple initial signal lines are configured to be electrically connected to multiple rows of sub-pixels respectively, and the initial signal connecting lines are configured to be electrically connected to at least some of the initial signal lines; in a direction parallel to the plane where the display substrate is located, the multiple initial signal lines extend along the row direction and are arranged at intervals along the column direction, the multiple initial signal connecting lines extend along the column direction and are arranged at intervals along the row direction, and in a direction perpendicular to the plane where the display substrate is located, the multiple initial signal connecting lines and the multiple initial signal lines are located in different conductive layers.

12. The display substrate according to claim 11, wherein: The plurality of initial signal lines include a plurality of first initial signal lines and a plurality of second initial signal lines, at least some of the sub-pixels include a plurality of transistors, the plurality of transistors include at least a first transistor and a seventh transistor; the plurality of first initial signal lines are configured to be electrically connected to the first transistors in the plurality of rows of sub-pixels, respectively, and the plurality of second initial signal lines are configured to be electrically connected to the seventh transistors in the plurality of rows of sub-pixels, respectively; The multiple initial signal connection lines include multiple first initial signal connection lines and multiple second initial signal connection lines; the first initial signal connection line is configured to be electrically connected to the multiple first initial signal lines, and the second initial signal connection line is configured to be electrically connected to the multiple second initial signal lines.

13. The display substrate according to claim 12, wherein: In a direction perpendicular to the plane where the display substrate is located, the display substrate includes a semiconductor layer, a second conductive layer, a third conductive layer, and a fourth conductive layer sequentially arranged on the base, and the multiple initial signal lines are arranged in one of the film layers among the semiconductor layer, the second conductive layer, and the third conductive layer; the multiple initial signal connection lines are arranged in the fourth conductive layer.

14. The display substrate according to claim 12, wherein: The multiple sub-pixels form a plurality of pixel units arranged in an array, at least some of the pixel units include at least three sub-pixels arranged in sequence along the row direction, and the second power connection line, the first initial signal connection line, and the second initial signal connection line are arranged between two adjacent columns of pixel units.

15. The display substrate according to any one of claims 2 to 8 and 11 to 14, further comprising a shielding layer and a circuit structure layer arranged on the base, wherein the shielding layer is located between the base and the circuit structure layer in a direction perpendicular to the plane where the display substrate is located.

16. The display substrate according to claim 15, wherein: The display area is provided with a plurality of sub-pixels, at least some of the sub-pixels include first to seventh transistors located in the circuit structure layer and at least one shielding structure located in the shielding layer, and in the same sub-pixel, each of the shielding structures is configured to shield the channel region of at least one transistor among the first to seventh transistors.

17. The display substrate according to claim 16, wherein: In the same sub-pixel, the blocking layer includes one or more of the first blocking structure to the seventh blocking structure, wherein the orthographic projection of the first blocking structure on the substrate at least partially overlaps with the orthographic projection of the first transistor on the substrate; the orthographic projection of the second blocking structure on the substrate at least partially overlaps with the orthographic projection of the second transistor on the substrate; the orthographic projection of the third blocking structure on the substrate at least partially overlaps with the orthographic projection of the third transistor on the substrate; the orthographic projection of the fourth blocking structure on the substrate at least partially overlaps with the orthographic projection of the fourth transistor on the substrate; the orthographic projection of the fifth blocking structure on the substrate at least partially overlaps with the orthographic projection of the fifth transistor on the substrate; the orthographic projection of the sixth blocking structure on the substrate at least partially overlaps with the orthographic projection of the sixth transistor on the substrate; the orthographic projection of the seventh blocking structure on the substrate at least partially overlaps with the orthographic projection of the seventh transistor on the substrate.

18. The display substrate according to claim 17, wherein: The multiple sub-pixels form multiple sub-pixel rows, the blocking layer includes a second blocking structure and a fourth blocking structure, and in the same sub-pixel row, the second blocking structure located in one of the sub-pixels and the fourth blocking structure located in an adjacent sub-pixel are an integrated structure.

19. The display substrate according to claim 17, wherein: The multiple sub-pixels form multiple sub-pixel rows, the blocking layer includes a third blocking structure, and in the same sub-pixel row, in the row direction, the distance between two third blocking structures located in two adjacent sub-pixels is greater than the size of the channel region of the fourth transistor.

20. The display substrate according to claim 16 further includes a first power signal supply line, which is arranged in the border area and located at the periphery of the display area. In a direction perpendicular to the plane where the display substrate is located, the first power signal supply line is located on the side of the shielding layer away from the substrate, and the shielding layer of multiple sub-pixels located on the side of the display area close to the border area is electrically connected to the first power signal supply line.

21. The display substrate according to claim 20 further includes a shielding transfer line, wherein the shielding transfer line is located at least on both sides of a group of opposite sides of the display area, and on a plane parallel to the display substrate, the shielding transfer line is located between the second power line and the display area, and a plurality of sub-pixel shielding layers located on the side of the display area close to the border area are connected to the shielding transfer line, and the first power signal supply line is electrically connected to the shielding transfer line through a via, and the orthographic projection of the first power signal supply line on the substrate at least partially overlaps with the orthographic projection of the shielding transfer line on the substrate.

22. A display device comprising the display substrate according to any one of claims 1 to 21.

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