Interface circuit capable of automatically generating auxiliary power supply under multi-level standard

Abstract

The invention discloses an interface circuit capable of automatically generating an auxiliary power supply under a multi-level standard, and relates to the technical field of integrated circuits, the interface circuit comprises an auxiliary power supply unit, a control unit and a signal transmission unit, the control unit and the signal transmission unit are both adaptively connected with the auxiliary power supply unit; the auxiliary power supply unit, the control unit and the signal transmission unit are all connected to a power supply voltage VCCO, the control unit is used for controlling the auxiliary power supply unit to generate an auxiliary voltage group required by the signal transmission unit according to the power supply voltage VCCO, and the auxiliary voltage group comprises a selection signal SEL configured and loaded to the control unit according to the provided power supply voltage VCCO. The control unit generates a control signal group according to the selection signal SEL; and the control signal group controls the auxiliary power supply unit to provide an auxiliary voltage group required by work for the signal transmission unit under the power supply voltage VCCO. The interface circuit can automatically generate an auxiliary voltage group required by work, so that the dependence on an external power supply is reduced, and the reliability of the interface circuit is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and particularly to an interface circuit capable of self-generating an auxiliary power supply under a multi-level standard. Background Art

[0002] A chip generally includes a core circuit and an input / output interface circuit. The input / output interface circuit is an interface for the chip core circuit to communicate with external devices and is usually located at the outermost periphery of the chip layout. In the input / output interface circuit, signals are generally transmitted to and from external devices through input / output buffers (I / O Buffers) and input / output ports (I / O PADs).

[0003] Due to the wide variety of external devices and different interface standards, in practical applications, the input / output interface circuit of the chip needs to be able to operate within a relatively wide range of power supply voltages (VCCO) for the input / output interface circuit, such as 0V to 3.3V, to match the level standards of external devices.

[0004] However, since the devices used in the input / output buffers are usually designed for specific operating voltages, when VCCO cannot provide the required operating voltage for the input / output buffers, the input / output interface circuit often needs to be externally connected to an auxiliary power supply for power supply, which affects the simplicity and reliability of chip applications. Summary of the Invention

[0005] In view of the above problems and technical requirements, the inventor of the present invention proposes an interface circuit capable of self-generating an auxiliary power supply under a multi-level standard. The technical solution of the present invention is as follows:

[0006] An interface circuit capable of self-generating an auxiliary power supply under a multi-level standard, comprising an auxiliary power supply unit, a control unit, and a signal transmission unit, wherein the control unit and the signal transmission unit are both adaptively connected to the auxiliary power supply unit;

[0007] The auxiliary power supply unit, the control unit, and the signal transmission unit are all connected to the power supply voltage VCCO. The control unit is configured to control the auxiliary power supply unit to self-generate an auxiliary voltage group required for the operation of the signal transmission unit, wherein the power supply voltage VCCO matches the level standard used when the signal transmission unit transmits signals;

[0008] When the control unit controls the auxiliary power supply unit to self-generate the auxiliary voltage group, it includes:

[0009] Configuring a selection signal SEL loaded to the control unit according to the provided power supply voltage VCCO, and the control unit generates a control signal group according to the selection signal SEL;

[0010] The control signal group controls the auxiliary power supply unit to provide the auxiliary voltage group required for the operation of the signal transmission unit at the power supply voltage VCCO.

[0011] A further technical solution thereof is that the auxiliary voltage group includes a first auxiliary voltage VAUX and a second auxiliary voltage VAUXL;

[0012] When configuring the selection signal SEL according to the provided power supply voltage VCCO, it includes:

[0013] When the power supply voltage VCCO is equal to the target first auxiliary voltage VAUXT, the selection signal SEL is configured as a first-level signal; when the power supply voltage VCCO is not equal to the target first auxiliary voltage VAUXT, the selection signal SEL is configured as a second-level signal;

[0014] The auxiliary power supply unit includes a first auxiliary power supply circuit and a second auxiliary power supply circuit. The first auxiliary power supply circuit is used to generate a first auxiliary voltage VAUX equal to the target first auxiliary voltage VAUXT, and the second auxiliary power supply circuit is used to generate a second auxiliary voltage VAUXL.

[0015] A further technical solution thereof is that the first auxiliary power supply circuit includes a feedback voltage stabilizing circuit and an output circuit;

[0016] When the selection signal SEL is a first-level signal, the first auxiliary power supply circuit generates the first auxiliary voltage VAUX through the output circuit; when the selection signal SEL is a second-level signal, the first auxiliary power supply circuit generates the first auxiliary voltage VAUX through the feedback voltage stabilizing circuit;

[0017] The second auxiliary power supply circuit generates the second auxiliary voltage VAUXL based on the first auxiliary voltage VAUX.

[0018] A further technical solution thereof is that the output circuit includes power transistors M6, M7, M11, M12, M13, and M14, where

[0019] The first electrodes of the power transistors M11, M13, and M6 are connected to the power supply voltage VCCO. The second electrode of the power transistor M11 is connected to the second electrode of the power transistor M12. The third electrode of the power transistor M11 is connected to the third electrode of the power transistor M12, the second electrode of the power transistor M13, and the second electrode of the power transistor M14;

[0020] The third electrode of the power transistor M13 and the third electrode of the power transistor M14 are connected to the second electrode of the power transistor M6. The second electrode of the power transistor M6 is connected to the second electrode of the power transistor M7. The third electrode of the power transistor M6 is connected to the first electrode of the power transistor M7. The third electrode of the power transistor M7 is connected to the output terminal of the first auxiliary power supply circuit, and the output terminal of the first auxiliary power supply circuit is connected to the signal transmission unit.

[0021] A further technical solution thereof is that the feedback voltage stabilizing circuit includes an error amplifying circuit, a reference circuit, a feedback circuit, and an output adjustment circuit. The reference circuit generates a reference voltage VIN1 based on the power supply voltage VCCO. The feedback circuit generates a feedback voltage VFB based on the first auxiliary voltage VAUX. The error amplifying circuit generates a control voltage Vo based on the reference voltage VIN1 and the feedback voltage VFB. The output adjustment circuit adjusts the first auxiliary voltage VAUX according to the control voltage Vo.

[0022] A further technical solution thereof is that the error amplifying circuit includes an operational amplifier U1. The reference circuit includes a power transistor M10, a resistor R5, a resistor R6, and a resistor R7. The feedback circuit includes a power transistor M1, a power transistor M3, a power transistor M4, a resistor R2, and a resistor R3. The output adjustment circuit includes a power transistor M2, wherein,

[0023] One end of the resistor R5 is connected to the power supply voltage VCCO. The other end of the resistor R5 is connected to one end of the resistor R6 to form a first connection point. The other end of the resistor R6 is connected to one end of the resistor R7 to form a second connection point. The other end of the resistor R7 is connected to the third electrode of the power transistor M10. The first electrode of the power transistor M10 is grounded. The first connection point is connected to the non-inverting input terminal of the operational amplifier U1 to provide the reference voltage VIN1 to the non-inverting input terminal of the operational amplifier U1;

[0024] The output terminal of the operational amplifier U1 is connected to the second electrode of the power transistor M2. The first electrode of the power transistor M2 is connected to the third electrode of the power transistor M1. The first electrode of the power transistor M1 is connected to the power supply voltage VCCO;

[0025] The third electrode of the power transistor M2 is connected to the output terminal of the first auxiliary power supply circuit, the first electrode of the power transistor M4, and the third electrode of the power transistor M3. The third electrode of the power transistor M4 and the first electrode of the power transistor M3 are connected to one end of the resistor R2. The other end of the resistor R2 is connected to one end of the resistor R3 to form a third connection point. The other end of the resistor R3 is grounded; The third connection point is connected to the inverting input terminal of the operational amplifier U1 to provide the feedback voltage VFB to the inverting input terminal of the operational amplifier U1.

[0026] A further technical solution thereof is that the second auxiliary power supply circuit includes a voltage comparator, a power transistor M19, a power transistor M20, and a power transistor M21, wherein,

[0027] The non-inverting input terminal of the voltage comparator is connected to the second connection point to access the reference voltage VIN2, the inverting input terminal of the voltage comparator accesses the feedback voltage VFB, the positive power supply terminal of the voltage comparator is connected to the output terminal of the first auxiliary power supply circuit, and the negative power supply terminal of the voltage comparator is grounded;

[0028] The output terminal of the voltage comparator is connected to the second electrode of the power transistor M21, the third electrode of the power transistor M21 is connected to the third electrodes of the power transistor M19 and the power transistor M20 and forms the output terminal of the second auxiliary power supply circuit, the output terminal of the second auxiliary power supply circuit is connected to the second electrode of the power transistor M1, the first electrode of the power transistor M19 is connected to the output terminal of the first auxiliary power supply circuit, and the first electrodes of the power transistor M20 and the power transistor M21 are grounded.

[0029] A further technical solution thereof is that the control signal group includes a control signal SEL0, a control signal MS18, a control signal MS18C, a control signal MS18A, and a control signal MS33;

[0030] The control signal MS18 is loaded to the second electrodes of the power transistor M19 and the power transistor M20, the control signal MS18C is loaded to the second electrodes of the power transistor M10 and the power transistor M3, the control signal MS18A is loaded to the second electrodes of the power transistor M4, the power transistor M8, and the power transistor M9, and the control signal MS33 is loaded to the second electrodes of the power transistor M11 and the power transistor M12.

[0031] A further technical solution thereof is that the control unit includes a level shifter LS1, a level shifter LS2, an inverter INV1, an inverter INV2, an inverter INV3, an inverter INV4, an inverter INV5, and an inverter INV6, wherein,

[0032] The selection signal SEL accesses the input terminal of the level shifter LS1, the output terminal of the level shifter LS1 outputs the control signal SEL0 and is connected to the input terminal of the inverter INV1, the output terminal of the inverter INV1 outputs the control signal MS18 and is connected to the input terminal of the inverter INV2, the output terminal of the inverter INV2 outputs the control signal MS18C and is connected to the input terminal of the inverter INV3, and the output terminal of the inverter INV3 outputs the control signal MS18A;

[0033] The output terminal of the level shifter LS1 is connected to the input terminal of the inverter INV4. The output terminal of the inverter INV4 is connected to the input terminal of the inverter INV5. The output terminal of the inverter INV5 is connected to the input terminal of the level shifter LS2. The output terminal of the level shifter LS2 is connected to the input terminal of the inverter INV6. The output terminal of the inverter INV6 outputs a control signal MS33;

[0034] The positive power supply terminals of the level shifter LS1, the inverter INV1, the inverter INV2, the inverter INV3, the inverter INV4, and the inverter INV5 are connected to the output terminal of the first auxiliary power supply circuit. The negative power supply terminals of the level shifter LS1, the inverter INV1, the inverter INV2, the inverter INV3, the inverter INV4, and the inverter INV5 are grounded;

[0035] The positive power supply terminals of the level shifter LS2 and the inverter INV6 are connected to the power supply voltage VCCO. The negative power supply terminals of the level shifter LS2 and the inverter INV6 are connected to the output terminal of the second auxiliary power supply circuit.

[0036] A further technical solution thereof is that it further includes a substrate bias unit, and the substrate bias unit is used to provide a substrate bias voltage Vbb for the control unit, the auxiliary power supply unit, and the signal transmission unit according to the power supply voltage VCCO;

[0037] The substrate bias unit includes a power transistor M15, a power transistor M16, and a power transistor M17. The first electrode of the power transistor M15 is connected to the first auxiliary voltage VAUX. The third electrode of the power transistor M15 is connected to the third electrode of the power transistor M16. The first electrode of the power transistor M16 is connected to the second auxiliary voltage VAUXL;

[0038] The first electrode of the power transistor M17 is connected to the power supply voltage VCCO. The third electrode of the power transistor M17 forms the output terminal of the substrate bias unit. The substrates of the power transistor M15 and the power transistor M17 are connected to the third electrode of the power transistor M17. The second electrode of the power transistor M17 is connected to the enable voltage ENB. The second electrodes of the power transistor M15 and the power transistor M16 are connected to the enable voltage EN.

[0039] The beneficial technical effects of the present invention are:

[0040] The input / output interface circuit provided by the present invention can generate, by means of an auxiliary power supply unit, an auxiliary voltage group required for the operation of a signal transmission unit under multiple level standards. The circuit design of self-generating an auxiliary power supply reduces the dependence on an external power supply and improves the reliability of the input / output interface circuit. Among them, when the power supply voltage VCCO is equal to or not equal to the target first auxiliary voltage VAUXT, the path for generating the first auxiliary voltage VAUX is different. When VCCO is equal to the target first auxiliary voltage VAUXT, the path for generating the first auxiliary voltage VAUX can be simpler and faster, reducing the overall power consumption of the circuit.

[0041] In addition, a substrate bias unit is provided to provide a substrate bias voltage Vbb for a control unit, an auxiliary power supply unit, and a signal transmission unit according to the power supply voltage VCCO, further improving the overall reliability of the circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] Figure 1 is a circuit structure block diagram of an embodiment of the interface circuit provided by the present invention.

[0043] Figure 2 is a circuit schematic diagram of an embodiment of the control unit provided by the present invention.

[0044] Figure 3 is a circuit schematic diagram of an embodiment of the first auxiliary power supply circuit provided by the present invention.

[0045] Figure 4 is a circuit schematic diagram of an embodiment of the second auxiliary power supply circuit provided by the present invention.

[0046] Figure 5 is a circuit schematic diagram of an embodiment of the substrate bias unit provided by the present invention.

[0047] Figure 6 is a structure block diagram of the differential output buffer provided by the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0048] The following further describes the specific embodiments of the present invention with reference to the accompanying drawings.

[0049] The present invention provides an interface circuit capable of self-generating an auxiliary power supply under multiple level standards. As Figure 1 shown, it includes an auxiliary power supply unit, a control unit, and a signal transmission unit. The control unit and the signal transmission unit are both adaptively connected to the auxiliary power supply unit;

[0050] The auxiliary power supply unit, the control unit, and the signal transmission unit are all connected to the power supply voltage VCCO. The control unit is used to control the auxiliary power supply unit to generate the auxiliary voltage group required for the operation of the signal transmission unit according to the power supply voltage VCCO. Among them, the power supply voltage VCCO matches the level standard adopted when the signal transmission unit performs signal transmission;

[0051] When the control unit controls the auxiliary power supply unit to generate the auxiliary voltage group by itself, it includes:

[0052] Configuring the selection signal SEL loaded to the control unit according to the provided power supply voltage VCCO, and the control unit generates a control signal group according to the selection signal SEL;

[0053] The control signal group controls the auxiliary power supply unit to provide the auxiliary voltage group required for the operation to the signal transmission unit under the power supply voltage VCCO.

[0054] Specifically, the interface circuit can be used as both an output interface for the chip core circuit to output signals to external devices and an input interface for external devices to input signals to the chip core circuit. The signal transmission unit is connected between the chip core circuit and the external device to convert the chip core circuit signals into signals that can be received by the external device, or convert the external device signals into signals that can be processed by the chip core circuit. The level standard adopted by the signal transmission unit when performing signal transmission is consistent with the level standard of the external device interface connected to the signal transmission unit. When performing signal transmission, the power supply voltage VCCO will be loaded to the external device interface. The required power supply voltage VCCO of the external device interface is different under different level standards. Therefore, it is necessary to make the power supply voltage VCCO match the level standard adopted by the signal transmission unit, that is, the level standard of the external device interface.

[0055] Configuring the selection signal SEL according to the provided power supply voltage VCCO, the control unit generates a control signal group according to the selection signal SEL, and uses the control signal group to control the auxiliary power supply unit to generate the auxiliary voltage group, so that the signal transmission unit can use the auxiliary voltage group to work normally under different power supply voltages VCCO, that is, when adopting multiple different level standards, reducing the dependence on external power supplies and improving the reliability and application simplicity of the input / output interface circuit. The specific structures and working principles of the auxiliary power supply unit, the control unit, and the signal transmission unit can be referred to the following description.

[0056] Further, the auxiliary voltage group includes a first auxiliary voltage VAUX and a second auxiliary voltage VAUXL; when configuring the selection signal SEL according to the provided power supply voltage VCCO, it includes:

[0057] When the power supply voltage VCCO is equal to the target first auxiliary voltage VAUXT, configure the selection signal SEL as a first-level signal; when the power supply voltage VCCO is not equal to the target first auxiliary voltage VAUXT, configure the selection signal SEL as a second-level signal;

[0058] The auxiliary power supply unit includes a first auxiliary power supply circuit and a second auxiliary power supply circuit. The first auxiliary power supply circuit is used to generate a first auxiliary voltage VAUX equal to the target first auxiliary voltage VAUXT, and the second auxiliary power supply circuit is used to generate a second auxiliary voltage VAUXL.

[0059] Specifically, when the power supply voltage VCCO changes, the first auxiliary voltage VAUX required by the signal transmission unit is a fixed value, that is, equal to the target first auxiliary voltage VAUXT, and the second auxiliary voltage VAUXL required by the signal transmission unit changes with the power supply voltage VCCO. In an embodiment of the present invention, the target first auxiliary voltage VAUXT = 1.8V, and the level standards adopted by the signal transmission unit include LVCMOS18 and LVCMOS33. When the signal transmission unit adopts the LVCMOS18 level standard, the power supply voltage VCCO = 1.8V; when the signal transmission unit adopts the LVCMOS33 level standard, the power supply voltage VCCO = 3.3V.

[0060] The above-mentioned second auxiliary voltage VAUXL required by the signal transmission unit changes with the power supply voltage VCCO. Specifically, it means that when VCCO = 1.8V, the second auxiliary voltage VAUXL required by the signal transmission unit = 0V; when VCCO = 3.3V, the second auxiliary voltage VAUXL required by the signal transmission unit = 1.8V.

[0061] Further, the control signal group generated by the control unit according to the selection signal SEL includes: control signal SEL0, control signal MS18, control signal MS18C, control signal MS18A, and control signal MS33;

[0062] The control unit includes a level converter LS1, a level converter LS2, an inverter INV1, an inverter INV2, an inverter INV3, an inverter INV4, an inverter INV5, and an inverter INV6;

[0063] Such as Figure 2As shown, the selection signal SEL is connected to the input end of the level shifter LS1. The output end of the level shifter LS1 outputs a control signal SEL0 and is connected to the input end of the inverter INV1. The output end of the inverter INV1 outputs a control signal MS18 and is connected to the input end of the inverter INV2. The output end of the inverter INV2 outputs a control signal MS18C and is connected to the input end of the inverter INV3. The output end of the inverter INV3 outputs a control signal MS18A;

[0064] The output end of the level shifter LS1 is connected to the input end of the inverter INV4. The output end of the inverter INV4 is connected to the input end of the inverter INV5. The output end of the inverter INV5 is connected to the input end of the level shifter LS2. The output end of the level shifter LS2 is connected to the input end of the inverter INV6. The output end of the inverter INV6 outputs a control signal MS33;

[0065] The positive power supply terminals of the level shifter LS1, the inverter INV1, the inverter INV2, the inverter INV3, the inverter INV4, and the inverter INV5 are connected to the output end of the first auxiliary power supply circuit. The negative power supply terminals of the level shifter LS1, the inverter INV1, the inverter INV2, the inverter INV3, the inverter INV4, and the inverter INV5 are grounded;

[0066] The positive power supply terminals of the level shifter LS2 and the inverter INV6 are connected to the power supply voltage VCCO. The negative power supply terminals of the level shifter LS2 and the inverter INV6 are connected to the output end of the second auxiliary power supply circuit.

[0067] In this embodiment, the first level signal is a high-level signal and the second level signal is a low-level signal. The level standard of the selection signal SEL adopts the level standard of the chip core circuit. When the signal transmission unit adopts the LVCMOS18 level standard, VCCO = VAUXT = 1.8V, and the selection signal SEL is configured as a high-level signal. At this time, the level of the selection signal SEL is 0.85V. When the signal transmission unit adopts the LVCMOS33 level standard, VCCO = 3.3V > VAUXT, and the selection signal SEL is configured as a low-level signal. At this time, the level of the selection signal SEL is 0V.

[0068] Table 1 shows the levels of each control signal in the control signal group when the selection signal SEL is at a high level (0.85V) and a low level (0V). Specifically, when the level of the selection signal SEL is 0.85V, the level of the control signal SEL0 output through the level converter LS1 is GND, the level of the control signal MS18 output through the inverter INV1 is VAUX, the level of the control signal MS18C output through the inverter INV2 is complementary to the level of MS18 and is GND, the level of the control signal MS18A is the same as the level of MS18 and is VAUX, and the level of the control signal MS33 is VAUXL.

[0069] When the level of the selection signal SEL is 0V, the level of the control signal SEL0 obtained through the level converter LS1 is VAUX, the level of the control signal MS18 output through the inverter INV1 is GND, the level of the control signal MS18C output through the inverter INV2 is complementary to the level of MS18 and is VAUX, the level of the control signal MS18A output through the inverter INV3 is GND; the level output by the inverter INV5 is the same as the control signal SEL0, and the level of the control signal MS33 is VCCO, i.e., 3.3V, after the inverting output of the level converter LS2 and the inverter INV6.

[0070] Table 1 Control signal group levels corresponding to high / low levels of the selection signal SEL

[0071] SEL SEL0 MS18 MS18C MS18A MS33 0.85V GND VAUX GND VAUX VAUXL 0V VAUX GND VAUX GND VCCO

[0072] Furthermore, when the selection signal SEL is a high-level signal and a low-level signal, the generation paths of the first auxiliary voltage VAUX are different, but the generated first auxiliary voltage VAUX is equal to the target first auxiliary voltage VAUXT.

[0073] Specifically, the first auxiliary power supply circuit includes a feedback voltage stabilizing circuit and an output circuit. When the selection signal SEL is a high-level signal, the first auxiliary power supply circuit generates the first auxiliary voltage VAUX through the output circuit. As Figure 3 shown, the output circuit includes power transistors M6, M7, M11, M12, M13, and M14, where

[0074] the first electrodes of the power transistors M11, M13, and M6 are connected to the power supply voltage VCCO, the second electrode of the power transistor M11 is connected to the second electrode of the power transistor M12, and the third electrode of the power transistor M11 is connected to the third electrode of the power transistor M12, the second electrode of the power transistor M13, and the second electrode of the power transistor M14;

[0075] The third electrode of the power transistor M13 and the third electrode of the power transistor M14 are connected to the second electrode of the power transistor M6. The second electrode of the power transistor M6 is connected to the second electrode of the power transistor M7. The third electrode of the power transistor M6 is connected to the first electrode of the power transistor M7. The third electrode of the power transistor M7 is connected to the output terminal of the first auxiliary power supply circuit. The output terminal of the first auxiliary power supply circuit is connected to the signal transmission unit.

[0076] The output circuit further includes a power transistor M5, a power transistor M8, and a power transistor M9. The third electrode of the power transistor M2 is connected to the second electrode of the power transistor M5. The third electrode of the power transistor M5 is connected to the second electrodes of the power transistor M6 and the power transistor M7. The first electrode of the power transistor M5 is connected to the third electrodes of the power transistor M8 and the power transistor M9. The first electrode of the power transistor M8 is connected to the output terminal of the first auxiliary power supply circuit. The first electrode of the power transistor M9 is grounded.

[0077] Further, when the selection signal SEL is a low-level signal, the first auxiliary power supply circuit generates a first auxiliary voltage VAUX through a feedback voltage stabilization circuit. The feedback voltage stabilization circuit includes an error amplification circuit, a reference circuit, a feedback circuit, and an output adjustment circuit. The reference circuit generates a reference voltage VIN1 based on the power supply voltage VCCO. The feedback circuit generates a feedback voltage VFB based on the first auxiliary voltage VAUX. The error amplification circuit generates a control voltage Vo based on the reference voltage VIN1 and the feedback voltage VFB. The output adjustment circuit adjusts the first auxiliary voltage VAUX according to the control voltage Vo to keep the first auxiliary voltage VAUX stable and equal to the target first auxiliary voltage VAUXT.

[0078] Specifically, as Figure 3 shown, the error amplification circuit includes an operational amplifier U1. The reference circuit includes a power transistor M10, a resistor R5, a resistor R6, and a resistor R7. The feedback circuit includes a power transistor M1, a power transistor M3, a power transistor M4, a resistor R2, and a resistor R3. The output adjustment circuit includes a power transistor M2;

[0079] One end of the resistor R5 is connected to the power supply voltage VCCO. The other end of the resistor R5 is connected to one end of the resistor R6 to form a first connection point. The other end of the resistor R6 is connected to one end of the resistor R7 to form a second connection point. The other end of the resistor R7 is connected to the third electrode of the power transistor M10. The first electrode of the power transistor M10 is grounded. The first connection point is connected to the non-inverting input terminal of the operational amplifier U1 to provide the reference voltage VIN1 to the non-inverting input terminal of the operational amplifier U1;

[0080] The output terminal of the operational amplifier U1 is connected to the second electrode of the power transistor M2. The first electrode of the power transistor M2 is connected to the third electrode of the power transistor M1. The first electrode of the power transistor M1 is connected to the power supply voltage VCCO.

[0081] The third electrode of the power transistor M2 is connected to the output terminal of the first auxiliary power supply circuit, the first electrode of the power transistor M4, and the third electrode of the power transistor M3. The third electrode of the power transistor M4 and the first electrode of the power transistor M3 are connected to one end of the resistor R2. The other end of the resistor R2 is connected to one end of the resistor R3 to form a third connection point. The other end of the resistor R3 is grounded. The third connection point is connected to the inverting input terminal of the operational amplifier U1 to provide a feedback voltage VFB to the inverting input terminal of the operational amplifier U1.

[0082] Among the above control signals, the control signal MS18C is loaded onto the second electrodes of the power transistors M10 and M3. The control signal MS18A is loaded onto the second electrodes of the power transistors M4, M8, and M9. The control signal MS33 is loaded onto the second electrodes of the power transistors M11 and M12.

[0083] In this embodiment, the above power transistors M1-M14 are all MOS transistors. The power transistors M1, M2, M4, M6, M7, M8, M11, and M13 are PMOS transistors, and the power transistors M3, M5, M9, M10, M12, and M14 are NMOS transistors. For MOS transistors, the above first electrode is the source electrode, the second electrode is the gate electrode, and the third electrode is the drain electrode. Specifically, when implemented, the power transistors M1-M14 can also use other power devices with switching functions.

[0084] When the signal transmission unit adopts the LVCMOS18 level standard, the working principle of the first auxiliary power supply circuit generating the first auxiliary voltage VAUX is as follows: When the signal transmission unit adopts the LVCMOS18 level standard, VCCO = VAUXT = 1.8V. The selection signal SEL is a high-level signal. As can be seen from Table 1, the level of the control signal MS18C is GND, the gate-source voltage difference of the power transistor M10 is less than the threshold voltage, and the power transistor M10 is turned off. At this time, the reference voltage VIN1 follows the power supply voltage VCCO through the resistor R5, and the reference voltage VIN2 follows the power supply voltage VCCO through the resistor R5 and the resistor R6. At the same time, the level of the control signal MS18A is VAUX at this time, both the power transistors M3 and M4 are turned off, the feedback loop in the feedback voltage stabilizing circuit is disconnected, the power transistor M2 is turned off, and the feedback voltage VFB follows GND through the resistor R3.

[0085] Meanwhile, the level of the control signal MS33 is VAUXL. After passing through the inverters formed by the power transistors M11 and M12, and the power transistors M13 and M14, the driving ability of the control signal MS33 is enhanced, controlling the conduction of the power transistors M6 and M7, so that the voltage at the output terminal of the first auxiliary power supply circuit follows the power supply voltage VCCO, that is, the first auxiliary voltage VAUX output at this time is VAUX = VCCO = 1.8V. When the output circuit includes the power transistors M5, M8, and M9, since the level of the control signal MS18A is VAUX, the power transistor M8 is turned off and the power transistor M9 is turned on, pulling the source of the power transistor M5 to the ground potential. The power transistor M5 is turned on, pulling the gates of the power transistors M6 and M7 to the ground potential, enabling the power transistors M6 and M7 to conduct faster.

[0086] When the signal transmission unit adopts the LVCMOS33 level standard, the working principle of the first auxiliary power supply circuit generating the first auxiliary voltage VAUX is as follows: When the signal transmission unit adopts the LVCMOS33 level standard, VCCO = 3.3V, and the selection signal SEL is a low-level signal. As can be seen from Table 1, the level of the control signal MS18C is VAUX, controlling the conduction of the power transistor M10. At this time, the reference voltage VIN1 is VCCO*(R6 + R7) / (R5 + R6 + R7). Meanwhile, the level of the control signal MS18A is GND, and both the power transistors M3 and M4 are turned on. The level of the control signal MS33 is VCCO, controlling the power transistors M6 and M7 to turn off, and the output circuit is disconnected from the output terminal of the first auxiliary power supply circuit. When the output circuit includes the power transistors M5, M8, and M9, since the level of the control signal MS18A is GND at this time, both the power transistors M9 and M5 are turned off.

[0087] At this time, in the feedback voltage regulation circuit, VFB = VAUX*R3 / (R2 + R3). The operational amplifier U1 compares the feedback voltage VFB with the reference voltage VIN1 and generates an error signal and amplifies it to generate the control voltage Vo. At this time, the power transistor M2 serves as the output adjustment circuit. The control voltage Vo controls the output current of the power transistor M2 by controlling the gate voltage of the power transistor M2 to adjust the output first auxiliary voltage VAUX to keep VAUX stably output. In an embodiment of the present invention, in the stable output state, VAUX = VFB*(1 + R2 / R3) = VIN1*(1 + R2 / R3) = VAUXT = 1.8V. As can be seen from the above description, when the power supply voltage VCCO is equal to or not equal to the target first auxiliary voltage VAUXT, the paths for generating the first auxiliary voltage VAUX are different. When VCCO is equal to the target first auxiliary voltage VAUXT, the path for generating the first auxiliary voltage VAUX is simpler and faster, reducing the overall power consumption of the circuit.

[0088] Further, as Figure 4 shown, the second auxiliary power supply circuit includes a voltage comparator, a power transistor M19, a power transistor M20, and a power transistor M21. Among them,

[0089] the positive input terminal of the voltage comparator is connected to the second connection point to access the reference voltage VIN2, the negative input terminal of the voltage comparator accesses the feedback voltage VFB, the positive power supply terminal of the voltage comparator is connected to the output terminal of the first auxiliary power supply circuit, and the negative power supply terminal of the voltage comparator is grounded;

[0090] the output terminal of the voltage comparator is connected to the second electrode of the power transistor M21, the third electrode of the power transistor M21 is connected to the third electrodes of the power transistor M19 and the power transistor M20 and forms the output terminal of the second auxiliary power supply circuit, the output terminal of the second auxiliary power supply circuit is connected to the second electrode of the power transistor M1, the first electrode of the power transistor M19 is connected to the output terminal of the first auxiliary power supply circuit, the first electrodes of the power transistor M20 and the power transistor M21 are grounded, and the second electrodes of the power transistor M19 and the power transistor M20 access the control signal MS18.

[0091] The power transistors M19 - M21 can be MOS transistors. In this embodiment, the power transistors M20 and M21 are NMOS transistors, and the power transistor M19 is a PMOS transistor. When the power transistors M19 - M21 are MOS transistors, the definitions of the first electrode, the second electrode, and the third electrode of the power transistors M19 - M21 are consistent with the definitions of the first electrode, the second electrode, and the third electrode of the MOS transistor above, and will not be elaborated here.

[0092] The working principle of the second auxiliary power supply circuit for generating the second auxiliary voltage VAUXL is specifically as follows:

[0093] When the signal transmission unit adopts the LVCMOS18 level standard, VCCO = VAUXT = 1.8V, the selection signal SEL is a high - level signal. As can be seen from Table 1, at this time, the level of the control signal MS18 is VAUX. After being inverted by the inverter composed of the power transistors M19 and M20, the output second auxiliary voltage VAUXL = 0V. At the same time, as described above, at this time, the feedback voltage VFB follows the ground potential, the reference voltage VIN2 follows the power supply voltage VCCO, the voltage at the positive input terminal of the voltage comparator is greater than the voltage at the negative input terminal, and the output voltage Vo1 of the voltage comparator = VAUX, controlling the power transistor M21 to conduct.

[0094] When the signal transmission unit adopts the LVCMOS33 level standard, VCCO = 3.3V, and the selection signal SEL is a low-level signal. It can be seen from Table 1 that at this time, the level of the control signal MS18 is GND. After being inverted by the inverter composed of the power transistor M19 and the power transistor M20, VAUX is loaded to the output terminal of the second auxiliary power supply circuit. At the same time, a feedback voltage stabilizing circuit in the first auxiliary power supply circuit forms a path. When the first auxiliary voltage VAUX is stably output, the reference voltage VIN2 is less than the reference voltage VIN1, that is, the reference voltage VIN2 is less than the feedback voltage VFB. The voltage at the positive input terminal of the voltage comparator is less than the voltage at the negative input terminal, and the output voltage Vo1 of the voltage comparator = GND, thereby turning off the power transistor M21. At this time, VAUXL = VAUX = 1.8V. Controlling the on-off state of the power transistor M21 by using the voltage comparator can control the output of VAUXL when the LVCMOS33 level standard is adopted, and improve the consistency of the outputs of VAUX and VAUXL.

[0095] Further, the interface circuit further includes a substrate bias unit, and the substrate bias unit is used to provide a substrate bias voltage Vbb for the control unit, the auxiliary power supply unit and the signal transmission unit according to the power supply voltage VCCO to improve the reliability of the circuit;

[0096] The substrate bias unit includes a power transistor M15, a power transistor M16 and a power transistor M17. The first electrode of the power transistor M15 is connected to the first auxiliary voltage VAUX, the third electrode of the power transistor M15 is connected to the third electrode of the power transistor M16, and the first electrode of the power transistor M16 is connected to the second auxiliary voltage VAUXL;

[0097] The first electrode of the power transistor M17 is connected to the power supply voltage VCCO, the third electrode of the power transistor M17 forms the output terminal of the substrate bias unit, the second electrode of the power transistor M17 is connected to the enable voltage ENB, and the second electrodes of the power transistor M15 and the power transistor M16 are connected to the enable voltage EN. The substrates of the power transistor M15 and the power transistor M17 are connected to the third electrode of the power transistor M17.

[0098] Specifically, the power transistors M15 - M17 can be MOS transistors. In this embodiment, the power transistors M15 and M17 are PMOS transistors, and the power transistor M16 is an NMOS transistor. When the power transistors M15 - M17 are MOS transistors, the definitions of the first electrode, the second electrode, and the third electrode of the power transistors M15 - M17 are consistent with the definitions of the first electrode, the second electrode, and the third electrode of the MOS transistor described above, and will not be elaborated here. The enable signal ENB is the inverted signal of the enable signal EN. In this embodiment, the enable signal EN is constantly in a high - level state, and the enable signal ENB is constantly in a low - level state. The power transistor M16 is turned on, the power transistor M15 is turned off, and the power transistor M17 is turned on. The substrate bias voltage Vbb equal to the power supply voltage VCCO is output by the drain of the power transistor M17. Specifically in implementation, according to actual needs, the enable signal EN can also be controlled to be in a low - level state, and the enable signal ENB can be controlled to be in a high - level state, so as to control the power transistor M15 to be turned on and the power transistor M17 to be turned off, making the substrate bias voltage Vbb follow the first auxiliary voltage VAUX to flexibly control the substrate bias voltage Vbb. At the same time, when the substrate bias unit does not need to work, the enable signal EN and the enable signal ENB can also be turned off to reduce the circuit power consumption.

[0099] In this embodiment, the substrate bias voltage Vbb is provided to the control unit, specifically referring to that the substrate bias voltage Vbb is loaded onto the substrates of the level shifters LS1 and LS2 in the control unit. The substrate bias voltage Vbb is provided to the auxiliary power supply unit, specifically referring to that the substrate bias voltage Vbb is loaded onto the substrates of the power transistors M1, M2, M4, M6, M7, M8, M11, M13, and M19, providing a stable substrate potential for the MOS transistors to ensure the normal operation of the MOS transistors.

[0100] The signal transmission unit generally includes an input / output buffer (I / O Buffer) and an input / output port (I / O PAD). The first auxiliary voltage VAUX and the second auxiliary voltage VAUXL are loaded onto the input / output buffer to provide a working voltage for the input / output buffer.

[0101] Figure 6 Taking the differential output buffer as an example, a possible implementation form when the first auxiliary voltage VAUX and the second auxiliary voltage VAUXL provide a working voltage for the input / output buffer is shown. Figure 5 A typical structural block diagram of the differential output buffer is shown, such as Figure 6As shown, the signal DATA_O output by the core circuit is level-converted by the level converter LS3 and the level converter LS4 respectively. The output signal of the level converter LS3 passes through the pre-driving circuit PREDRIVER_P and the slew rate control circuit SLEWRATE_P in turn, and then is output to the I / O PAD through the PMOS tube array P_ARRAY. The output signal of the level converter LS4 passes through the pre-driving circuit PREDRIVER_N and the slew rate control circuit SLEWRATE_N, and then is output to the I / O PAD through the NMOS tube array N_ARRAY, realizing differential output.

[0102] The first auxiliary voltage VAUX and the second auxiliary voltage VAUXL provide working voltage for the output buffer, that is, the first auxiliary voltage VAUX is loaded to the above-mentioned level converter LS3, level converter LS4, pre-drive circuit PREDRIVER_N and slew rate control circuit SLEWRATE_N; the second auxiliary voltage VAUXL is loaded to the pre-drive circuit PREDRIVER_P and the slew rate control circuit SLEWRATE_P, so that the differential output buffer can work normally without the need for an external power supply voltage.

[0103] In addition, the substrate bias unit provides a substrate bias voltage Vbb to the signal transmission unit, specifically, to the device in the internal circuit of the input / output buffer in the signal transmission unit. Figure 6 In the slew rate control circuit SLEWRATE_P shown, the substrate bias voltage Vbb is applied to the substrate of the PMOS transistor M54. The specific form of the input / output buffer in the signal transmission unit can be set according to actual needs.

[0104] It should be noted that the words "first" and "second" used in the above description are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. The above is only a preferred embodiment of the present invention, and the present invention is not limited to the above embodiments. It is understood that other improvements and changes directly derived or associated by those skilled in the art without departing from the spirit and concept of the present invention should be considered to be included in the scope of protection of the present invention.

Claims

1. An interface circuit capable of self-generating auxiliary power under a multi-level standard, characterized in that: It includes an auxiliary power supply unit, a control unit and a signal transmission unit, wherein the control unit and the signal transmission unit are both adapted and connected to the auxiliary power supply unit; The auxiliary power supply unit, the control unit and the signal transmission unit are all connected to the power supply voltage VCCO, and the control unit is used to control the auxiliary power supply unit to self-generate an auxiliary voltage group required for the signal transmission unit to work according to the power supply voltage VCCO, wherein the power supply voltage VCCO matches the level standard adopted by the signal transmission unit when performing signal transmission; The control unit controls the auxiliary power supply unit to self-generate the auxiliary voltage group, including: A selection signal SEL loaded into a control unit is configured according to the provided power supply voltage VCCO, and the control unit generates a control signal group according to the selection signal SEL; The control signal group controls the auxiliary power supply unit to provide the signal transmission unit with an auxiliary voltage group required for operation under the power supply voltage VCCO.

2. The interface circuit capable of self-generating auxiliary power under the multi-level standard according to claim 1, characterized in that: The auxiliary voltage group includes a first auxiliary voltage VAUX and a second auxiliary voltage VAUXL; When configuring the selection signal SEL according to the provided power supply voltage VCCO, it includes: When the power supply voltage VCCO is equal to the target first auxiliary voltage VAUXT, the selection signal SEL is configured as a first level signal; when the power supply voltage VCCO is not equal to the target first auxiliary voltage VAUXT, the selection signal SEL is configured as a second level signal; The auxiliary power supply unit includes a first auxiliary power supply circuit and a second auxiliary power supply circuit. The first auxiliary power supply circuit is used to generate a first auxiliary voltage VAUX equal to a target first auxiliary voltage VAUXT, and the second auxiliary power supply circuit is used to generate a second auxiliary voltage VAUXL.

3. The interface circuit capable of self-generating auxiliary power under the multi-level standard according to claim 2, characterized in that: The first auxiliary power supply circuit includes a feedback voltage stabilization circuit and an output circuit; When the selection signal SEL is a first level signal, the first auxiliary power supply circuit generates a first auxiliary voltage VAUX through an output circuit; when the selection signal SEL is a second level signal, the first auxiliary power supply circuit generates a first auxiliary voltage VAUX through a feedback voltage stabilization circuit; The second auxiliary power supply circuit generates a second auxiliary voltage VAUXL based on the first auxiliary voltage VAUX.

4. The interface circuit capable of self-generating auxiliary power under the multi-level standard according to claim 3, characterized in that: The output circuit includes a power tube M6, a power tube M7, a power tube M11, a power tube M12, a power tube M13 and a power tube M14, wherein: The first electrodes of the power tubes M11, M13 and M6 are connected to the power supply voltage VCCO, the second electrode of the power tube M11 is connected to the second electrode of the power tube M12, and the third electrode of the power tube M11 is connected to the third electrode of the power tube M12, the second electrode of the power tube M13 and the second electrode of the power tube M14; The third electrode of the power tube M13 and the third electrode of the power tube M14 are connected to the second electrode of the power tube M6, the second electrode of the power tube M6 is connected to the second electrode of the power tube M7, the third electrode of the power tube M6 is connected to the first electrode of the power tube M7, the third electrode of the power tube M7 is connected to the output end of the first auxiliary power supply circuit, and the output end of the first auxiliary power supply circuit is connected to the signal transmission unit.

5. The interface circuit capable of self-generating auxiliary power under the multi-level standard according to claim 4, characterized in that: The feedback voltage stabilization circuit includes an error amplifier circuit, a reference circuit, a feedback circuit and an output adjustment circuit. The reference circuit generates a reference voltage VIN1 based on a power supply voltage VCCO, the feedback circuit generates a feedback voltage VFB based on a first auxiliary voltage VAUX, the error amplifier circuit generates a control voltage Vo based on the reference voltage VIN1 and the feedback voltage VFB, and the output adjustment circuit adjusts the first auxiliary voltage VAUX according to the control voltage Vo.

6. The interface circuit capable of self-generating auxiliary power under the multi-level standard according to claim 5, characterized in that: The error amplifier circuit includes an operational amplifier U1, the reference circuit includes a power tube M10, a resistor R5, a resistor R6 and a resistor R7, the feedback circuit includes a power tube M1, a power tube M3, a power tube M4, a resistor R2 and a resistor R3, and the output adjustment circuit includes a power tube M2, wherein: One end of the resistor R5 is connected to the power supply voltage VCCO, the other end of the resistor R5 is connected to one end of the resistor R6 to form a first connection point, the other end of the resistor R6 is connected to one end of the resistor R7 to form a second connection point, the other end of the resistor R7 is connected to the third electrode of the power tube M10, the first electrode of the power tube M10 is grounded, and the first connection point is connected to the non-inverting input terminal of the operational amplifier U1 to provide a reference voltage VIN1 to the non-inverting input terminal of the operational amplifier U1; The output end of the operational amplifier U1 is connected to the second electrode of the power tube M2, the first electrode of the power tube M2 is connected to the third electrode of the power tube M1, and the first electrode of the power tube M1 is connected to the power supply voltage VCCO; The third electrode of the power tube M2 is connected to the output end of the first auxiliary power supply circuit, the first electrode of the power tube M4 and the third electrode of the power tube M3, the third electrode of the power tube M4 and the first electrode of the power tube M3 are connected to one end of the resistor R2, the other end of the resistor R2 is connected to one end of the resistor R3 to form a third connection point, and the other end of the resistor R3 is grounded; the third connection point is connected to the inverting input end of the operational amplifier U1 to provide a feedback voltage VFB to the inverting input end of the operational amplifier U1.

7. The interface circuit capable of self-generating auxiliary power under the multi-level standard according to claim 6, characterized in that: The second auxiliary power supply circuit includes a voltage comparator, a power tube M19, a power tube M20 and a power tube M21, wherein: The non-inverting input terminal of the voltage comparator is connected to the second connection point to access the reference voltage VIN2, the inverting input terminal of the voltage comparator is connected to the feedback voltage VFB, the positive power supply terminal of the voltage comparator is connected to the output terminal of the first auxiliary power supply circuit, and the negative power supply terminal of the voltage comparator is grounded; The output end of the voltage comparator is connected to the second electrode of the power tube M21, the third electrode of the power tube M21 is connected to the third electrode of the power tube M19 and the third electrode of the power tube M20 to form the output end of the second auxiliary power supply circuit, the output end of the second auxiliary power supply circuit is connected to the second electrode of the power tube M1, the first electrode of the power tube M19 is connected to the output end of the first auxiliary power supply circuit, and the first electrodes of the power tubes M20 and M21 are grounded.

8. The interface circuit capable of self-generating auxiliary power under the multi-level standard according to claim 7, characterized in that: The control signal group includes a control signal SEL0, a control signal MS18, a control signal MS18C, a control signal MS18A and a control signal MS33; The control signal MS18 is loaded onto the second electrodes of the power tubes M19 and M20, the control signal MS18C is loaded onto the second electrodes of the power tubes M10 and M3, the control signal MS18A is loaded onto the second electrodes of the power tubes M4, M8 and M9, and the control signal MS33 is loaded onto the second electrodes of the power tubes M11 and M12.

9. The interface circuit capable of self-generating auxiliary power under the multi-level standard according to claim 8, characterized in that: The control unit includes a level converter LS1, a level converter LS2, an inverter INV1, an inverter INV2, an inverter INV3, an inverter INV4, an inverter INV5 and an inverter INV6, wherein: The selection signal SEL is connected to the input end of the level converter LS1, the output end of the level converter LS1 outputs the control signal SEL0 and is connected to the input end of the inverter INV1, the output end of the inverter INV1 outputs the control signal MS18 and is connected to the input end of the inverter INV2, the output end of the inverter INV2 outputs the control signal MS18C and is connected to the input end of the inverter INV3, and the output end of the inverter INV3 outputs the control signal MS18A; The output end of the level converter LS1 is connected to the input end of the inverter INV4, the output end of the inverter INV4 is connected to the input end of the inverter INV5, the output end of the inverter INV5 is connected to the input end of the level converter LS2, the output end of the level converter LS2 is connected to the input end of the inverter INV6, and the output end of the inverter INV6 outputs the control signal MS33; The positive power supply terminals of the level converter LS1, the inverter INV1, the inverter INV2, the inverter INV3, the inverter INV4 and the inverter INV5 are connected to the output terminal of the first auxiliary power supply circuit, and the negative power supply terminals of the level converter LS1, the inverter INV1, the inverter INV2, the inverter INV3, the inverter INV4 and the inverter INV5 are grounded; The positive power supply terminals of the level converter LS2 and the inverter INV6 are connected to the power supply voltage VCCO, and the negative power supply terminals of the level converter LS2 and the inverter INV6 are connected to the output terminal of the second auxiliary power supply circuit.

10. The interface circuit capable of self-generating auxiliary power under multi-level standards according to claim 2, characterized in that: It also includes a substrate bias unit, which is used to provide a substrate bias voltage Vbb for the control unit, the auxiliary power supply unit and the signal transmission unit according to the power supply voltage VCCO; The substrate bias unit includes a power tube M15, a power tube M16 and a power tube M17, a first electrode of the power tube M15 is connected to a first auxiliary voltage VAUX, a third electrode of the power tube M15 is connected to a third electrode of the power tube M16, and a first electrode of the power tube M16 is connected to a second auxiliary voltage VAUXL; The first electrode of the power tube M17 is connected to the power supply voltage VCCO, the third electrode of the power tube M17 forms the output end of the substrate bias unit, the second electrode of the power tube M17 is connected to the enable voltage ENB, the substrates of the power tubes M15 and M17 are connected to the third electrode of the power tube M17, and the second electrodes of the power tubes M15 and M16 are connected to the enable voltage EN.

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