A memory access method, processor and related device

Abstract

The application discloses a memory access method, a processor and related equipment, comprising: receiving a memory access request sent by a processor core, the memory access request carrying a virtual address of data to be accessed; in response to the memory access request, searching for a physical address corresponding to the virtual address of the data from a page table cache; if the physical address cannot be searched from the page table cache, searching for a page table entry of a non-last-level page table corresponding to the virtual address of the data from a page table entry cache, the page table entry cache storing the page table entry of the non-last-level page table corresponding to at least part of the virtual addresses of the data to be accessed by the processor core; if the page table entry of the non-last-level page table can be searched from the page table entry cache, searching for the corresponding physical address from a page table in which the non-last-level page table is located based on the searched page table entry of the non-last-level page table, and accessing the data based on the searched physical address, so as to reduce the number of times of accessing the memory for searching the page table, reduce the searching time of the physical address, and improve the memory access speed.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of computer, in particular to a memory access method, a processor and related equipment. BACKGROUND

[0002] When a processor core needs to access data in a memory, a memory management unit (MMU) will convert a virtual address in a memory access request sent by the processor core into a corresponding physical address, and access data in the memory based on the physical address. Although in the process of converting the virtual address into the physical address, the memory management unit will reduce the lookup time of the physical address by means of a translation lookaside buffer (TLB) to improve the memory access speed, because the translation lookaside buffer only stores the mapping relationship between the virtual address and the physical address of the data recently accessed by the processor core, and does not store the mapping relationship between the virtual address and the physical address of all data accessed by the processor core, the memory access of part of the data cannot reduce the lookup time of the physical address by means of the translation lookaside buffer, resulting in that the memory access speed of part of the data is still low. SUMMARY

[0003] The present application discloses a memory access method, a processor and related equipment to further improve the memory access speed.

[0004] In a first aspect, the present application discloses a memory access method, comprising: receiving a memory access request sent by a processor core; the memory access request carrying a virtual address of data to be accessed; in response to the memory access request, finding a physical address corresponding to the virtual address of the data from a translation lookaside buffer; the translation lookaside buffer storing a mapping relationship between a virtual address and a physical address of data recently accessed by the processor core; if the physical address cannot be found in the translation lookaside buffer, finding a page table entry of a non-last level page table corresponding to the virtual address of the data from a page table entry cache; the page table entry cache storing a page table entry of a non-last level page table corresponding to a virtual address of at least part of data accessed by the processor core; if the page table entry of the non-last level page table can be found in the page table entry cache, finding the physical address from a page table where the non-last level page table is located based on the found page table entry of the non-last level page table, and accessing the data based on the found physical address.

[0005] In some embodiments of the present application, the page table entry cache comprises a first page table entry cache, the at least part of data comprises non-code data, and the step of searching the page table entry cache for the non-ultimate level page table entry corresponding to the virtual address of the data comprises: searching the first page table entry cache for the non-ultimate level page table entry corresponding to the virtual address of the non-code data; and the first page table entry cache storing at least the non-ultimate level page table entry corresponding to the virtual address of at least part of the non-code data of the first page table. The first page table is used to store the mapping relationship between the virtual address of the data of any process running on the processor core and the physical address of the original version thereof.

[0006] In some embodiments of the present application, the page table entry cache comprises a second page table entry cache, the at least part of data comprises code data, and the step of searching the page table entry cache for the non-ultimate level page table entry corresponding to the virtual address of the data comprises: searching the second page table entry cache for the non-ultimate level page table entry corresponding to the virtual address of the code data; and the second page table entry cache storing at least the non-ultimate level page table entry corresponding to the virtual address of at least part of the code data of the second page table. The second page table is used to store the mapping relationship between the virtual address of at least part of the code data of any process running on the processor core or the kernel code data of the processor core and the physical address of the copy thereof. The copy of the at least part of the code data or the kernel code data is stored in the memory in the same NUMA node as the processor core.

[0007] In some embodiments of the present application, the method further comprises: storing the copy of at least part of the code data of any process running on the processor core or the kernel code data of the processor core in the memory in the same NUMA node as the processor core; creating a second page table and causing the second page table to store the mapping relationship between the virtual address of the at least part of the code data or the kernel code data and the physical address of the copy thereof; or, controlling the processor core to create a child process of any process running thereon and causing the process page table of the child process to store the mapping relationship between the virtual address of at least part of the code data of the process and the physical address of the copy thereof, and taking the process page table of the child process as the second page table.

[0008] In some embodiments of the present application, the method further comprises: loading the non-ultimate level page table entry corresponding to the virtual address of at least part of the data required to be accessed by the processor core into the page table entry cache.

[0009] In some embodiments of the present application, if the at least part of the data comprises the kernel code data of the processor core, the loading of the page table entry of the non-ultimate level page table corresponding to the virtual address of the at least part of the data required to be accessed by the processor core into the page table entry cache comprises: turning off the interrupt function of the processor core; loading the page table entry of the non-ultimate level page table of the second page table into the page table entry cache, the second page table being used to store the mapping relationship between the virtual address of the kernel code data of the processor core and the physical address of the copy thereof; turning on the interrupt function of the processor core; if the at least part of the data comprises at least part of the code data of any process running on the processor core, the loading of the page table entry of the non-ultimate level page table corresponding to the virtual address of the at least part of the data required to be accessed by the processor core into the page table entry cache comprises: loading the page table entry of the non-ultimate level page table of the second page table into the page table entry cache while the processor core is running the process, the second page table being used to store the mapping relationship between the virtual address of at least part of the code data of any process running on the processor core and the physical address of the copy thereof.

[0010] In some embodiments of the present application, the loading of the page table entry of the non-ultimate level page table of the second page table into the page table entry cache comprises: determining whether the page table entry cache has the page table entry of the non-ultimate level page table and whether the page table entry of the non-ultimate level page table is from the second page table; if the page table entry cache does not have the page table entry of the non-ultimate level page table or the page table entry of the non-ultimate level page table is not from the second page table, loading the page table entry of the non-ultimate level page table of the second page table into the page table entry cache.

[0011] In some embodiments of the present application, the method further comprises: locking the page table entry of the non-ultimate level page table in the page table entry cache; or periodically loading the page table entry of the non-ultimate level page table corresponding to the virtual address of the at least part of the data required to be accessed by the processor core into the page table entry cache.

[0012] In some embodiments of the present application, after the corresponding physical address is found from the page table in which the found page table entry of the non-ultimate level page table is located, the method further comprises: storing the mapping relationship between the virtual address and the physical address of the data into the page table cache.

[0013] In a second aspect, the present application further discloses a processor, the processor comprising any processor of any NUMA node of a NUMA architecture, the processor comprising a processor core and a memory management unit, the memory management unit being configured to perform the memory access method according to any one of the above.

[0014] In a third aspect, the present application also discloses an electronic device, comprising a plurality of NUMA nodes, each of which comprises at least one memory and at least one processor; the memory is configured to store a computer program; and the processor is configured to execute the computer program to implement the memory access method according to any one of the preceding aspects.

[0015] In a fourth aspect, the present application also discloses a computer readable storage medium, which stores a computer program, and the computer program is executed by a processor to implement the memory access method according to any one of the preceding aspects.

[0016] The memory access method, the processor and the related device disclosed by the present application can first find the page table entry of the non-last level page table corresponding to the virtual address of the data from the page table entry cache when the physical address cannot be found in the page table cache, and then find the physical address of the data from the page table in which the page table entry is located based on the found page table entry of the non-last level page table, so that the number of times of accessing the memory for querying the page table can be reduced, and the time for finding the physical address can be further reduced, and the memory access speed can be improved. BRIEF DESCRIPTION OF DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the background art, the drawings needed to be used in the embodiments of the present application or the background art will be described below.

[0018] Figure 1 FIG. 1 is a schematic diagram of a structure of a processor and a memory according to an embodiment of the present application.

[0019] Figure 2 FIG. 2 is a flowchart of a memory access method according to an embodiment of the present application.

[0020] Figure 3 FIG. 3 is a schematic diagram of a structure of a processor and a memory according to an embodiment of the present application.

[0021] Figure 4 FIG. 4 is a schematic diagram of a structure of a multi-level page table according to an embodiment of the present application.

[0022] Figure 5 FIG. 5 is a schematic diagram of a structure of a NUMA architecture according to an embodiment of the present application.

[0023] Figure 6 FIG. 6 is a schematic diagram of another structure of a processor and a memory according to an embodiment of the present application.

[0024] Figure 7 FIG. 7 is a schematic diagram of another structure of a processor and a memory according to an embodiment of the present application. DETAILED DESCRIPTION

[0025] The technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative efforts belong to the scope of the present application.

[0026] As shown in Figure 1 , Figure 1 is a schematic diagram of a current processor and memory structure, the processor includes a processor core 10 and a memory management unit 11, when the processor core 10 needs to access data in the memory 12, the page table lookup unit 110 of the memory management unit 11 will first find the physical address corresponding to the virtual address of the data from the page table cache 111, the page table cache 111 stores the mapping relationship between the virtual address and the physical address of the data recently accessed by the processor core 10.

[0027] If the corresponding physical address can be found from the page table cache 111, the data in the memory 12 is accessed based on the found physical address. If the corresponding physical address cannot be found from the page table cache 111, the physical address corresponding to the virtual address of the data is found from the corresponding page table 120 in the memory 12, the data in the memory 12 is accessed based on the found physical address, and the mapping relationship between the virtual address and the physical address of the data is stored in the page table cache 111, so that the memory management unit 11 can directly find the corresponding physical address from the page table cache 111 when the processor core 10 accesses the data next time.

[0028] Although in the case that the corresponding physical address can be found in the page table cache 111, the physical address lookup time can be reduced and the memory access speed can be improved, the page table cache 111 does not store the mapping relationship between the virtual address and the physical address of all data required to be accessed by the processor core 10, and in the case that the corresponding physical address cannot be found in the page table cache 111, a long lookup time is still required, resulting in a low memory access speed.

[0029] Based on this, the present application discloses a memory access scheme, the page table entry of the non-last level page table of the page table in which the mapping relationship between the virtual address and the physical address of all data required to be accessed by the processor core is stored in the page table entry cache, in the case that the corresponding physical address cannot be found in the page table cache, the page table entry of the non-last level page table corresponding to the virtual address of the data is first found from the page table entry cache, and then the physical address of the data is found from the page table based on the found page table entry of the non-last level page table, so as to further improve the memory access speed.

[0030] As an optional implementation of the disclosure of the present application, the embodiment of the present application discloses a memory access method, as shown in Figure 2 Figure 2 ​A flowchart of a memory access method disclosed by embodiments of the present application, the method comprising:

[0031] S101: receiving a memory access request sent by a processor core, the memory access request carrying a virtual address of data to be accessed.

[0032] As shown in Figure 3 , Figure 3 A structural schematic diagram of a processor and a memory disclosed by embodiments of the present application. When any processor core 10 needs to access data in the memory 12, the processor core 10 sends a memory access request to the memory management unit 11, the memory access request carrying a virtual address of data to be accessed by the processor core 10. The data includes code data or non-code data, and the code data can also be referred to as instructions.

[0033] S102: in response to the memory access request, finding a physical address corresponding to the virtual address of the data from the page table cache.

[0034] As shown in Figure 3 , after the memory management unit 11 receives the memory access request sent by any processor core 10, the page table lookup unit 110 of the memory management unit 11 will respond to the memory access request and find a physical address corresponding to the virtual address of the data from the page table cache 111. The page table cache 111 stores the mapping relationship between the virtual address and the physical address of the data recently accessed by the processor core 10.

[0035] S103: if the physical address cannot be found in the page table cache, finding a page table entry of a non-last level page table corresponding to the virtual address of the data from the page table entry cache.

[0036] If the page table lookup unit 110 can find the physical address corresponding to the virtual address of the data from the page table cache 111, the data in the memory 12 is accessed based on the found physical address. If the page table lookup unit 110 cannot find the physical address corresponding to the virtual address of the data from the page table cache 111, a page table entry of a non-last level page table corresponding to the virtual address of the data is found from the page table entry cache (TLB walk cache) 112. The page table entry cache 112 stores at least part of the data to be accessed by the processor core 10, and the at least part of the data includes non-code data and code data.

[0037] S104: if the page table entry of the non-last level page table can be found from the page table entry cache, the physical address of the data is found from the page table in which the page table entry is located based on the found page table entry of the non-last level page table, and the data is accessed based on the found physical address.

[0038] Generally, the page table is a multi-level page table. As shown inFigure 4 As shown, Figure 4 A structure diagram of a multi-level page table disclosed in an embodiment of the present application is shown in FIG. 1. The multi-level page table includes a first-level page table to a fourth-level page table, which are respectively a PGD (Page Global Directory) page table, a PUD (Page Upper Directory) page table, a PMD (Page Middle Directory) page table, and a PTE (Page Table Entry) page table. The non-last-level page table is the PGD page table, the PUD page table, or the PMD page table, and the last-level page table is the PTE page table.

[0039] Each level of the page table can include at least one page table page, and each page table page can include at least one page table entry. As shown in FIG. 1, Figure 4 As shown in FIG. 1, the first-level page table, i.e., the PGD page table, includes a PGD1 page table page, the second-level page table, i.e., the PUD page table, includes a PUD1 page table page and a PUD2 page table page, the third-level page table, i.e., the PMD page table, includes a PMD1 page table page and a PMD2 page table page, and the fourth-level page table, i.e., the PTE page table, includes a PTE1 page table page and a PTE2 page table page. The mapping relationship stored in the page table entry of the higher-level page table can be used to obtain the page table entry of the lower-level page table, and the mapping relationship stored in the page table entry of the last-level page table can be used to obtain the physical address. Currently, when searching for the physical address in the multi-level page table shown in FIG. 1, Figure 4 As shown in FIG. 1, when searching for the physical address in the multi-level page table, the page table entries of the PGD page table, the PUD page table, the PMD page table, and the PTE page table in the memory 12 need to be searched in sequence, which results in a long search time for the physical address and a low memory access speed.

[0040] In an embodiment of the present application, the page table entries of the non-last-level page table corresponding to the virtual address of at least part of the data required to be accessed by the processor core 10 are stored in the page table entry cache 112, for example, the page table entries of the PGD page table, the PUD page table, and the PMD page table are stored in the page table entry cache 112. If the page table searching unit 110 cannot find the physical address corresponding to the virtual address of the data from the page table cache 111, the page table entry of the non-last-level page table corresponding to the virtual address of the data is searched from the page table entry cache 112. If the page table searching unit 110 can find the page table entry of the non-last-level page table from the page table entry cache 112, the corresponding physical address is searched from the page table in which the page table entry is located, for example, the page table 120 in the memory 12, based on the found page table entry of the non-last-level page table, and the data is accessed based on the found physical address, so that the number of times of accessing the memory 12 for searching the page table can be reduced, and the search time for the physical address can be reduced, and the memory access speed can be improved.

[0041] Of course, if the page table lookup unit 110 cannot find the page table entry of the non-ultimate level page table from the page table entry cache 112, the physical address is found from the page table in which the page table entry is located, such as the page table 120 in the memory 12, and the data is accessed based on the found physical address.

[0042] It should be noted that only a four-level page table is taken as an example for illustration in the embodiments of the present application, but the present application is not limited thereto, and in other embodiments, the page table can also be a two-level page table, a three-level page table, or even a five-level page table, etc.

[0043] In some embodiments of the present application, all the page table entries of the non-ultimate level page tables, such as the PGD page table, the PUD page table, and the PMD page table, except the ultimate level page table, such as the PTE page table, can be stored in the page table entry cache 112, but the present application is not limited thereto, and in other embodiments, only part of the page table entries of the non-ultimate level page tables, such as the PGD page table and the PUD page table, can be stored in the page table entry cache 112.

[0044] In some embodiments of the present application, the memory management unit 11 can store the page table entries of the non-ultimate level page tables corresponding to the virtual addresses of all the data required to be accessed by the processor core 10 into the page table entry cache 112, but because the resource of the page table entry cache 112 is precious and limited, in other embodiments, the memory management unit 11 can store the page table entries of the non-ultimate level page tables corresponding to the virtual addresses of part of the data required to be accessed by the processor core 10 into the page table entry cache 112.

[0045] For example, when the processor core 10 runs one process, the memory management unit 11 stores the page table entries of the non-ultimate level page tables corresponding to the virtual addresses of the data of the one process into the page table entry cache 112. When the processor core 10 runs another process, the memory management unit 11 empties the page table entry cache 112 and stores the page table entries of the non-ultimate level page tables corresponding to the virtual addresses of the data of the another process into the page table entry cache 112.

[0046] In some embodiments of the present application, after the physical address of the data is found from the page table in which the page table entry of the non-ultimate level page table is located based on the page table entry, the mapping relationship between the virtual address and the physical address of the data can also be stored in the page table cache 111, so that the physical address can be directly found from the page table cache 111 when the processor core 10 accesses the data next time.

[0047] In some embodiments of the present application, the processor core 10 is a processor core of any NUMA node of a Non-Uniform Memory Access (NUMA) architecture. As shown in FIG. 1, the memory management unit 11 is a memory management unit of the NUMA architecture. Figure 5 Figure 5 ​A structure diagram of a NUMA architecture disclosed by an embodiment of the present application includes at least two NUMA nodes, for example, NUMA node 1 and NUMA node 2, each of which includes a processor and a memory, and each of the processors includes at least one processor core 10 and a memory management unit 11.

[0048] Because the processor core 10 in the NUMA architecture accesses data in the memory of the local node at a faster speed and accesses data in the memory of the non-local node at a slower speed, in the case where a process has multiple threads and the multiple threads run on the processor cores 10 of different nodes respectively, in order to improve the running speed of the thread whose code data is not in the local node, a copy of the code data of the thread can be stored in the memory of the local node, and the processor core 10 can access the copy of the code data in the memory of the local node according to the mapping relationship between the virtual address of the code data and the physical address of the copy of the code data stored in the node page table of the local node. The node page table is used to store the mapping relationship between the virtual address of the code data and the physical address of the copy of the code data of any thread or process, the copy of the code data is stored in the memory of the local node, and the original version of the code data is stored in the memory of the non-local node.

[0049] Although the mapping relationship between the virtual address and the physical address of the code data in the node page table of different nodes is different, the processor core 10 of different nodes can all access the copy of the code data in the memory of the local node through the node page table of the local node, but the mapping relationship between the virtual address and the physical address of the non-code data in the node page table of different nodes needs to be the same, so that the processor core 10 of different nodes can all access the original version of the non-code data through the node page table of the local node, to ensure that all nodes have a consistent view of the system state. However, this will cause the updated mapping relationship between the virtual address and the physical address of any non-code data to be synchronized to the node page table of all nodes after being updated, resulting in a complex update process and a large update overhead of the non-code data.

[0050] Based on this, in some embodiments of the present application, as shown in Figure 6 Figure 6 Another structure diagram of a processor and a memory disclosed by an embodiment of the present application, the page table entry cache can include a first page table entry cache 113, and the page table lookup unit 110 can first find the page table entry of the non-ultimate level page table corresponding to the virtual address of the non-code data from the first page table entry cache 113, then find the physical address of the non-code data from the page table, for example, the first page table 121, based on the found page table entry of the non-ultimate level page table, and access the non-code data based on the found physical address.

[0051] ​The first page table cache 113 stores page table entries of non-last-level page tables corresponding to the virtual addresses of at least a portion of the non-code data of the first page table. The first page table 121 stores the mapping relationship between the virtual addresses of data of any process running on the processor core 10 and the physical addresses of its original version. This data includes non-code data and code data. The first page table 121 can be the process page table of any process running on the processor core 10.

[0052] After the mapping between the virtual and physical addresses of non-code data in any process is updated, the mapping between the virtual and physical addresses of that data in the process's page table will also be updated. When processor core 10 needs to access this non-code data, it can access the non-code data based on the updated physical address in the process's page table. This eliminates the need to synchronize the updated mapping to the node page tables of all nodes, thus simplifying the non-code data update process and reducing the overhead of updating non-code data. In essence, the node page tables no longer need to store the mapping between the virtual and physical addresses of non-code data.

[0053] Based on this, in some embodiments of this application, such as Figure 6 As shown, the page table entry cache may also include a second page table entry cache 114. The page table lookup unit 110 may first look up the page table entry of the non-last-level page table corresponding to the virtual address of the code data in the second page table entry cache 114, and then look up the physical address of the code data in the page table in which it is located, such as the second page table 122, based on the found page table entry of the non-last-level page table, and access the code data based on the found physical address.

[0054] The second page table cache 114 stores at least the page table entries of the non-last-level page table corresponding to the virtual addresses of at least a portion of the code data of the second page table 122. The second page table 122 is used to store the mapping relationship between the virtual addresses of at least a portion of the code data of any process running on the processor core 10 or the kernel code data of the processor core 10 and the physical addresses of their copies. The at least a portion of the code data or the copy of the kernel code data of the processor core 10 is stored in memory 12 on the same NUMA node as the processor core 10, while the original version of the at least a portion of the code data or the kernel code data of the processor core 10 is stored in memory 12 on a different NUMA node than the processor core 10.

[0055] It should be noted that the at least part of the code data refers to the code data of the process that the processor core 10 needs to access when running the process. For example, if the process has multiple threads and the multiple threads run on processor core 10 of different NUMA nodes, the at least part of the code data is the code data of the thread running on the processor core 10 in the process.

[0056] It is also to be noted that in the case where the page table lookup unit 110 finds the page table entry of the non-leaf page table of the at least part of the code data from the second page table entry cache 114, even if the first page table 121 is registered on the processor core 10, the page table lookup unit 110 will only find the physical address of the copy of the at least part of the code data from the second page table 122 where the page table entry of the non-leaf page table of the at least part of the code data is located, and will not find the physical address of the original version of the at least part of the code data from the first page table 121.

[0057] It can be understood that if part of the code data of any process running on the processor core 10 is not stored in the memory 12 of the local node in the form of a copy, in the case where the physical address of the part of the code data cannot be found in the page table cache 111, the physical address of the part of the code data can be directly found from the first page table. Of course, in other embodiments, the page table entry of the non-leaf page table corresponding to the virtual address of at least part of the code data of the first page table can also be stored in the second page table entry cache 114, so that after the page table entry of the corresponding non-leaf page table is found from the second page table entry cache 114, the corresponding physical address is found from the first page table based on the found page table entry of the non-leaf page table.

[0058] As shown in FIG. 1, Figure 7 As shown in FIG. 1, Figure 7 As shown in FIG. 1, the page table cache can also include a first page table cache 115 and a second page table cache 116. The first page table cache 115 is used to store the mapping relationship between the virtual address and the physical address of the non-code data recently accessed by the processor core 10, and the second page table cache 116 is used to store the mapping relationship between the virtual address and the physical address of the code data recently accessed by the processor core 10.

[0059] In the case where the data to be accessed by the processor core 10 is non-code data, the page table lookup unit 110 will find the physical address corresponding to the virtual address of the non-code data from the first page table cache 115. In the case where the data to be accessed by the processor core 10 is code data, the page table lookup unit 110 will find the physical address corresponding to the virtual address of the code data from the second page table cache 116.

[0060] In some embodiments of the present application, a page of the local node memory 12 can be allocated in advance for storing a copy of the code data of each processor core 10 of the NUMA node, the copy of the code data can be stored in the page of the local node memory 12, and a node page table, i.e., a second page table, can be created for each NUMA node, and the node page table, i.e., the second page table, can store the mapping relationship between the virtual address of the code data and the physical address of the copy of the code data. In addition, in order to further reduce the query time of the physical address, the second page table can also be stored in the local node memory 12. The local node memory 12 refers to the memory 12 in the same NUMA node as the processor core 10.

[0061] In some embodiments, the second page table can be created, and the second page table can store the mapping relationship between the virtual address of at least part of the code data of any process running on the processor core 10 or the kernel code data of the processor core 10 and the physical address of the copy of the code data. However, the present application is not limited thereto, and in another embodiment, the processor core 10 can be controlled to create a child process of any process running thereon, and the process page table of the child process can store the mapping relationship between the virtual address of at least part of the code data of the process and the physical address of the copy of the code data, and the process page table of the child process can be used as the second page table to simplify the creation process of the second page table.

[0062] In some embodiments of the present application, before searching for the page table entry of the non-last level page table corresponding to the virtual address of the data from the page table entry cache 112, the page table entry of the non-last level page table corresponding to the virtual address of at least part of the data required to be accessed by the processor core 10 needs to be loaded into the page table entry cache 112. For example, when the processor core 10 runs any process, the page table entry of the non-last level page table of the second page table needs to be loaded into the second page table entry cache 114, and the page table entry of the non-last level page table of the first page table needs to be loaded into the first page table entry cache 113.

[0063] In some embodiments of the present application, if at least part of the data includes the kernel code data of the processor core 10, loading the page table entry of the non-last level page table corresponding to the virtual address of at least part of the data required to be accessed by the processor core 10 into the page table entry cache includes: turning off the interrupt function of the processor core 10; loading the page table entry of the non-last level page table corresponding to the virtual address of the kernel code data of the processor core 10 in the second page table into the page table entry cache, and the second page table is used to store the mapping relationship between the virtual address of the kernel code data of the processor core 10 and the physical address of the copy of the kernel code data; and turning on the interrupt function of the processor core 10.

[0064] It should be noted that, because the created second page table does not contain the mapping relationship of the code data other than the code data with the copy, or the created second page table cannot guarantee that the mapping relationship of the code data with the copy is completely consistent with the mapping relationship of the original page table, if the processor core 10 accesses the code data due to an interruption in the process of loading the page table entry of the non-last level page table in the second page table into the page table entry cache, an access error problem can occur.

[0065] In some embodiments, loading the page table entry of the non-last level page table corresponding to the virtual address of the kernel code data of the processor core 10 in the second page table into the page table entry cache comprises: loading the second page table for the processor core 10; emptying the cache of the second page table entry cache 114; loading the page table entry of the non-last level page table corresponding to the virtual address of the kernel code data of the processor core 10 in the second page table into the page table entry cache; and loading the first page table for the processor core 10.

[0066] In some embodiments of the present application, if the at least part of the data includes at least part of the code data of any process running on the processor core 10, loading the page table entry of the non-last level page table corresponding to the virtual address of the at least part of the data required to be accessed by the processor core 10 into the page table entry cache comprises: loading the page table entry of the non-last level page table corresponding to the virtual address of the at least part of the code data in the second page table into the page table entry cache when the processor core 10 runs the process, and the second page table is used to store the mapping relationship between the virtual address of at least part of the code data of any process running on the processor core 10 and the physical address of the copy thereof.

[0067] In some embodiments, loading the page table entry of the non-last level page table corresponding to the virtual address of the at least part of the code data in the second page table into the page table entry cache comprises: loading the second page table for the processor core 10; emptying the cache of the second page table entry cache 114; loading the page table entry of the non-last level page table corresponding to the virtual address of the kernel code data of the processor core 10 in the second page table into the page table entry cache; and loading the first page table for the processor core 10.

[0068] It should be noted that the page table entry of the non-last level page table corresponding to the virtual address of the kernel code data of the processor core 10 in the second page table can be loaded into the page table entry cache using a prefetch instruction. It should also be noted that, after the loading of the page table entry of the non-last level page table is completed, the page table loaded by the processor core 10 is switched to the first page table, so that when the second page table entry cache 114 cannot provide the information required for the current virtual address and physical address conversion, the physical address of the code data required to be accessed can be found from the first page table.

[0069] In some embodiments of the present application, loading the page table entry of the non-last level page table of the second page table into the page table entry cache comprises: determining whether the page table entry cache has the page table entry of the non-last level page table and whether the page table entry of the non-last level page table is from the second page table; if the page table entry cache does not have the page table entry of the non-last level page table or the page table entry of the non-last level page table is not from the second page table, then loading the page table entry of the non-last level page table of the second page table into the page table entry cache, otherwise, not loading the page table entry of the non-last level page table of the second page table into the page table entry cache.

[0070] It should be noted that when the processor core 10 has the function of obtaining address translation information, for example, when the processor core 10 has an AT (Attention) instruction, then the AT instruction can be used to know whether the page table entry of the non-last level page table in the second page table entry cache is from the second page table.

[0071] In some embodiments of the present application, if the processor core 10 has a cache locking function, then the page table entry of the non-last level page table corresponding to at least part of the data whose virtual address needs to be accessed by the processor core 10 can be loaded into the page table entry cache 112, and then the page table entry of the non-last level page table in the page table entry cache 112 can be locked.

[0072] For example, after loading the page table entry of the non-last level page table corresponding to at least part of the code data of any process running on the processor core 10 into the second page table entry cache 114, during the process of the processor core 10 running the process, the page table entry of the non-last level page table corresponding to the code data of the process in the second page table entry cache 114 can be locked to prevent it from being replaced by the page table entry cache eviction algorithm and affecting the actual effect of the memory access method disclosed in the present application.

[0073] In some embodiments, the second page table can be loaded for the processor core 10 first, the page table entry of the non-last level page table corresponding to the code data of the process in the second page table entry cache 114 can be locked using the locking mechanism supported by the processor core 10, and then the first page table can be loaded for the processor core 10.

[0074] It can be understood that when the processor core 10 runs one process, the page table entry of the non-last level page table corresponding to the data of the one process can be locked in the page table entry cache 112, but when the processor core 10 runs another process, the page table entry of the non-last level page table in the page table entry cache 112 can be emptied, and the page table entry of the non-last level page table corresponding to the data of the another process can be locked in the page table entry cache 112.

[0075] Of course, the present application is not limited to this, in other embodiments, if the processor core 10 does not have the cache locking function, the page table entry of the non-last level page table corresponding to the virtual address of at least part of the data required to be accessed by the processor core 10 can be loaded into the page table entry cache periodically.

[0076] In some embodiments, during the process of running any process by the processor core 10, the page table entry of the non-last level page table corresponding to the virtual address of the data of the process can be loaded into the page table entry cache 112 periodically using the timer interrupt.

[0077] It should be noted that because the resource of the page table entry cache 112 is precious and limited, in order to avoid the page table entry locking to cause the available resource of the page table entry cache 112 to be less, only part of the page table entries can be locked. For example, if the mapping relationship of the virtual address of a data is completely defined by a page table entry of the second level page table, the page table entry of the second level page table can be locked. However, if the mapping relationship of the virtual address of a data is defined by two adjacent page table entries of the second level page table, the first level page table can be locked to reduce the number of locked page table entries.

[0078] Based on this, in the embodiments of the present application, the multiple threads of the same process running on different processor cores can share the data space, but each uses the code data with the affinity to the current processor core.

[0079] For example, assuming that the virtual address of [100M, 200M] in the virtual address space of the process is used to store code data, and other virtual addresses are used to store non-code data, the multiple threads of the process run on two processor cores respectively, the two processor cores each have a large enough local memory, and the page table of the process is a 4-level page table, the page size of the page table is 4K bytes, and each page table entry occupies 8 bytes, then the page table entry of the second level page table describing the [0, 1G] virtual address will describe how to find the third level page table, 50 page table entries in the third level page table will describe how to find the fourth level page table, i.e., the last level page table, and these last level page tables will describe how to find the physical memory page storing the 100M code data.

[0080] To use the memory access method provided by the embodiments of the present application, the software first makes a copy of the 100M code data on the local memory of each processor core affinity, and respectively makes a page table for mapping the [100M, 200M] virtual address to the corresponding copy, which is called a copy page table or a node page table. For the processor core supporting the second page table entry cache 114 lock, the second level page table entry of the copy page table [0, 1G] is locked into the second page table entry cache 114, and it is ensured that the second page table entry cache 114 does not contain other page table entries of the copy page table, for example, it does not contain the mapping relationship of the virtual address outside [100M, 200M] which is not described by the copy page table, or it can be invalidated after locking the page table entry of [0, 1G] to describe the mapping relationship of the virtual address outside [100M, 200M], and then the standard page table of the process, i.e., the process page table, is installed on the processor core.

[0081] When the thread running on the processor core performs virtual address and physical address conversion due to accessing code data, if it is found that the cache corresponding to the last level page table entry does not exist, it will find the third level page table entry; if it is found that the cache corresponding to the third level page table entry does not exist, it will find the second level page table entry, because the second level page table entry corresponding to [0, 1G] already exists in the second page table entry cache 114, so the cache of the second level page table entry will hit, and the page corresponding to this page table entry, i.e., the page of the copy page table, will be found, so as to obtain the physical memory page affinity to the processor core.

[0082] When the thread running on the processor core performs virtual address and physical address conversion due to accessing non-code data, for example, the accessed virtual address is 99M, when the last level page table entry cache does not exist, it will find the third page table, the second level page table, and the first level page table entry cache. Because the second level page table entry of [0, 1G] is declared to be applicable only to code data, it will be ignored. Assuming that all cached page table entries do not hit, the required virtual address and physical address mapping relationship will be obtained according to the currently installed page table, i.e., the process page table. Because the process page table defines the global virtual address and physical address mapping relationship of non-code data, all threads of the process can obtain consistent data through the process page table.

[0083] As another optional implementation of the disclosure of the present application, the embodiments of the present application also disclose a processor, which includes any processor of any NUMA node of a NUMA architecture, as shown in Figure 3 or Figure 5 The processor includes a processor core 10 and a memory management unit 11, and the memory management unit is configured to perform the memory access method disclosed in any of the above embodiments.

[0084] As another optional implementation of the disclosure, the embodiment of the present application further discloses an electronic device, which comprises a plurality of NUMA nodes, each of which comprises at least one memory and at least one processor; the memory is used for storing a computer program; and the processor is used for executing the computer program to implement the memory access method disclosed in any one of the above embodiments.

[0085] As another optional implementation of the disclosure, the embodiment of the present application further discloses a computer readable storage medium, which stores a computer program, and the computer program is executed by a processor to implement the memory access method disclosed in any one of the above embodiments.

[0086] The technical features of the above embodiments can be combined in any manner. To make the description concise, all possible combinations of the technical features in the above embodiments are not described, however, as long as the combinations of the technical features do not exist contradictions, they should be considered as the scope of the disclosure.

[0087] The above embodiments only express several implementation manners of the present disclosure, and the description is specific and detailed, but it should not be understood as a limitation on the patent scope of the application. It should be pointed out that for ordinary skilled persons in the art, some modifications and improvements can be made without departing from the concept of the present disclosure, and these all belong to the protection scope of the present disclosure. Therefore, the patent protection scope of the present disclosure should be subject to the appended claims.

Claims

1. A memory access method, characterized in that, include: Load the page table entries of the non-last-level page table corresponding to the virtual address of at least part of the data that the processor core needs to access into the page table entry cache, and lock the page table entries of the non-last-level page table in the page table entry cache. Alternatively, page table entries of non-last-level page tables corresponding to the virtual addresses of at least some of the data that the processor core needs to access can be periodically loaded into the page table entry cache; Receive memory access requests sent by the processor core; The memory access request carries the virtual address of the data to be accessed; In response to the memory access request, the physical address corresponding to the virtual address of the data is retrieved from the page table cache; the page table cache stores the mapping relationship between the virtual addresses and physical addresses of the data recently accessed by the processor core. If the physical address cannot be found in the page table cache, then the page table entry corresponding to the virtual address of the data (not the last-level page table) is searched in the page table entry cache. If a page table entry that is not the last-level page table can be found in the page table entry cache, then the corresponding physical address is found in the page table where the found page table entry is located, and the data is accessed based on the found physical address.

2. The method according to claim 1, characterized in that, The page table entry cache includes a first page table entry cache, the at least part of the data includes non-code data, and the step of retrieving the page table entry corresponding to the virtual address of the data from the page table entry cache (excluding the last-level page table) includes: The first page table cache retrieves the page table entry of the non-last-level page table corresponding to the virtual address of the non-code data from the first page table cache; the first page table cache stores at least a portion of the page table entries of the non-last-level page table corresponding to the virtual addresses of the non-code data of the first page table; the first page table is used to store the mapping relationship between the virtual address of the data of any process running on the processor core and the physical address of its original version.

3. The method according to claim 1, characterized in that, The page table entry cache includes a second page table entry cache, the at least part of the data includes code data, and the step of retrieving the page table entry corresponding to the virtual address of the data from the page table entry cache (excluding the last-level page table) includes: The second page table cache retrieves the page table entry of the non-last-level page table corresponding to the virtual address of the code data from the second page table cache; the second page table cache stores at least the page table entries of the non-last-level page table corresponding to the virtual addresses of at least a portion of the code data of the second page table; the second page table is used to store the mapping relationship between the virtual address and the physical address of the copy of at least a portion of the code data of any process running on the processor core or the kernel code data of the processor core; the at least a portion of the code data or the copy of the kernel code data is stored in memory on the same NUMA node as the processor core.

4. The method according to claim 3, characterized in that, Also includes: At least a portion of the code data of any process running on the processor core or a copy of the kernel code data of the processor core is stored in memory on the same NUMA node as the processor core; Create a second page table, and make the second page table store the mapping relationship between the virtual address of at least part of the code data or the kernel code data and the physical address of its copy; or, The processor core is controlled to create a child process of any process running on it, and the process page table of the child process stores the mapping relationship between the virtual address of at least a portion of the code data of the process and the physical address of its copy, and the process page table of the child process is used as the second page table.

5. The method according to claim 1, characterized in that, If the at least part of the data includes the kernel code data of the processor core, then loading the page table entry of the non-last-level page table corresponding to the virtual address of the at least part of the data that the processor core needs to access into the page table entry cache includes: disabling the interrupt function of the processor core; loading the page table entry of the non-last-level page table of the second page table into the page table entry cache, wherein the second page table is used to store the mapping relationship between the virtual address of the kernel code data of the processor core and the physical address of its copy; and enabling the interrupt function of the processor core. If the at least part of the data includes at least part of the code data of any process running on the processor core, then loading the page table entry of the non-last-level page table corresponding to the virtual address of the at least part of the data that the processor core needs to access into the page table entry cache includes: when the processor core is running the process, loading the page table entry of the non-last-level page table of the second page table into the page table entry cache, wherein the second page table is used to store the mapping relationship between the virtual address of at least part of the code data of any process running on the processor core and the physical address of its copy.

6. The method according to claim 5, characterized in that, The step of loading page table entries from the non-last-level page table of the second page table into the page table entry cache includes: Determine whether the page table entry cache contains a page table entry that is not the last level page table, and whether the page table entry that is not the last level page table comes from the second page table; If the page table entry cache does not contain page table entries that are not from the last-level page table, or if the page table entries that are not from the last-level page table do not originate from the second page table, then the page table entries of the second page table that are not from the last-level page table are loaded into the page table entry cache.

7. The method according to claim 1, characterized in that, After finding the corresponding physical address in the page table based on the page table entry found in the non-last-level page table, the process further includes: The mapping relationship between the virtual address and physical address of the data is stored in the page table cache.

8. A processor, characterized in that, The processor includes any processor of any NUMA node in a NUMA architecture, the processor includes a processor core and a memory management unit, the memory management unit being configured to execute the memory access method according to any one of claims 1 to 7.

9. An electronic device, characterized in that, It includes multiple NUMA nodes, each of which includes at least one memory and at least one processor; The memory is used to store computer programs; When the processor executes the computer program, it implements the memory access method according to any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, implements the memory access method according to any one of claims 1 to 7.

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